Semiconductor memory device

Abstract

A semiconductor memory device capable of performing a suitable write operation is provided. The device performs a write operation including a plurality of first write cycles each including a first programming operation of supplying a first programming voltage to a first conductive layer and supplying a first write path voltage smaller than the first programming voltage to a second conductive layer, the first programming voltage being increased by a first offset voltage as the number of the first write cycles increases, and an erase operation including a programming voltage control operation including a plurality of second write cycles each including a second programming operation of supplying a second programming voltage to a third conductive layer and supplying a second write path voltage smaller than the second programming voltage to a fourth conductive layer, the second programming voltage being increased by a second offset voltage as the number of the second write cycles increases, the magnitude of the first programming voltage being adjusted according to the magnitude of the second programming voltage, and an erase voltage supply operation of supplying an erase voltage to the first wiring after the control operation is performed.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2022-044981 (filed on March 22, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known, comprising: a substrate; a plurality of first conductive layers arranged along a first direction intersecting the surface of the substrate; and a semiconductor layer extending along the first direction and facing the plurality of first conductive layers. Summary of the Invention

[0005] A semiconductor memory device capable of performing suitable write operations is provided.

[0006] One embodiment of a semiconductor memory device includes: a substrate; a plurality of conductive layers arranged along a first direction intersecting a surface of the substrate; a first semiconductor layer extending along the first direction and facing the plurality of conductive layers; a charge storage layer disposed between the plurality of conductive layers and the first semiconductor layer; a first wiring electrically connected to one end of the first semiconductor layer in the first direction; and a control circuit electrically connected to the plurality of conductive layers and the first wiring; the control circuit is configured to perform a write operation and an erase operation, the write operation including a plurality of first write cycles, each of the plurality of first write cycles including a first programming operation, the first programming operation being to supply a first programming voltage to a first conductive layer, which is one of the plurality of conductive layers, and to supply a first programming voltage smaller than the first programming voltage to a second conductive layer, which is one of the plurality of conductive layers. The write path voltage; the first programming voltage increases with each execution of the first write cycle, and the first offset voltage increases with each execution of the first write cycle. The erase action includes: a programming voltage control action; and an erase voltage supply action. After executing the programming voltage control action, an erase voltage is supplied to the first wiring. The programming voltage control action includes multiple second write cycles, each of which includes a second programming action. The second programming action supplies a second programming voltage to a third conductive layer, which is one of the multiple conductive layers, and supplies a second write path voltage smaller than the second programming voltage to a fourth conductive layer, which is one of the multiple conductive layers. The second programming voltage increases with each execution of the second write cycle, and the magnitude of the first programming voltage is adjusted according to the magnitude of the second programming voltage. Attached Figure Description

[0007] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10.

[0008] Figure 2 This is a schematic block diagram showing the configuration of the memory die MD in the first embodiment.

[0009] Figure 3 This is a schematic circuit diagram representing a portion of a memory die (MD).

[0010] Figure 4 This is a schematic block diagram showing the configuration of the sense amplifier module (SAM).

[0011] Figure 5 This is a schematic 3D diagram representing a portion of a memory die (MD).

[0012] Figure 6 It means Figure 5 A schematic enlarged diagram consisting of a portion of it.

[0013] Figure 7 (a) to (c) are schematic bar charts used to illustrate the threshold voltage of the storage unit MC that records 3 bits of data.

[0014] Figure 8 This is a flowchart used to explain the writing operation of the first embodiment.

[0015] Figure 9 It is used for the number of loops n W With programming voltage V PGM1 A diagram illustrating the relationship.

[0016] Figure 10 It is a timing diagram used to illustrate the first programming action and the first verification action.

[0017] Figure 11 It is a schematic cross-sectional view used to illustrate the first programming action.

[0018] Figure 12 This is a schematic cross-sectional view used to illustrate the first verification action.

[0019] Figure 13 This is a flowchart used to explain the erasure operation of the first embodiment.

[0020] Figure 14 This is a flowchart used to explain the erasure operation of the first embodiment.

[0021] Figure 15 It is a timing diagram used to explain the pre-read action.

[0022] Figure 16 It is a schematic cross-sectional view used to illustrate the pre-reading action.

[0023] Figure 17 It is used for the number of loops n E1 With programming voltage V PGM2 A diagram illustrating the relationship.

[0024] Figure 18 It is a timing diagram used to illustrate the second programming action and the second verification action.

[0025] Figure 19 This is a schematic cross-sectional view used to illustrate the second programming action.

[0026] Figure 20 This is a schematic cross-sectional view used to illustrate the second verification action.

[0027] Figure 21 This is a diagram used to illustrate the second programming action for writing word lines.

[0028] Figure 22 This is a diagram used to illustrate the second programming action for erasing word lines.

[0029] Figure 23 It is a timing diagram used to explain the erase voltage supply operation and the erase verification operation.

[0030] Figure 24 It is a schematic cross-sectional view used to illustrate the operation of erasing voltage supply.

[0031] Figure 25 It is a schematic cross-sectional view used to illustrate the erasure verification action.

[0032] Figure 26 This is a flowchart used to explain the erasure operation in the second embodiment.

[0033] Figure 27 This is a flowchart used to explain the writing operation of the third embodiment.

[0034] Figure 28 This is a flowchart used to explain the writing operation of the fourth embodiment.

[0035] Figure 29 It is a timing diagram used to illustrate the pre-charge operation. Detailed Implementation

[0036] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention.

[0037] Furthermore, in this specification, when we say "semiconductor memory device," it refers to both memory dies (memory chips) and memory systems that include controller dies, such as memory cards and SSDs (Solid State Drives). It also refers to devices that include a host computer, such as smartphones, tablets, and personal computers.

[0038] Furthermore, in this specification, when we say that the first component is "electrically connected" to the second component, it can mean that the first component is directly connected to the second component, or that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in an off state, the first transistor is "electrically connected" to the third transistor.

[0039] Additionally, in this specification, when we say that the first component is “connected” between the second and third components, it sometimes means that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0040] Furthermore, in this specification, when we say that a circuit or the like "connects" two wirings, for example, it sometimes means that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings and is in a switched-on state.

[0041] In addition, in this specification, the specified direction parallel to the upper surface of the substrate is called the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the upper surface of the substrate is called the Z direction.

[0042] In addition, in this specification, the direction along a specified surface is sometimes referred to as the first direction, the direction along the specified surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the specified surface is referred to as the third direction. The first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to each other.

[0043] Furthermore, in this specification, expressions such as "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Additionally, when we say the lower surface or lower end of a configuration, we mean the surface or end of that configuration on the substrate side; when we say the upper surface or upper end, we mean the surface or end of that configuration on the opposite side from the substrate. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, etc.

[0044] Additionally, in this specification, when we refer to the “width,” “length,” or “thickness” of a component or part in a specified direction, we sometimes mean the width, length, or thickness of a cross-section or the like as observed using SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy).

[0045] [First Implementation]

[0046] [Memory System 10]

[0047] Figure 1 This is a schematic block diagram showing the configuration of the memory system 10.

[0048] The memory system 10 performs tasks such as reading, writing, and erasing user data based on signals sent from the host 20. The memory system 10 may be, for example, a memory chip, a memory card, an SSD, or other system capable of storing user data. The memory system 10 includes multiple memory dies (MDs) for storing user data, and a controller die (CD) connected to the multiple memory dies and the host 20. The controller die (CD) may include, for example, a processor, RAM (Random Access Memory), ROM (Read Only Memory), and ECC (Error Checking and Correcting) circuitry, performing processes such as logical address to physical address conversion, bit error detection / correction, and wear leveling.

[0049] [The structure of a memory die (MD)]

[0050] Figure 2 This is a schematic block diagram showing the configuration of the memory die MD in the first embodiment. Figure 3 This is a schematic circuit diagram representing a portion of a memory die (MD). Figure 4 This is a schematic block diagram showing the configuration of the sense amplifier module (SAM).

[0051] In addition, Figure 2 The diagram shows multiple control terminals. These control terminals may be shown as corresponding to a high-state active signal (positive logic signal), a low-state active signal (negative logic signal), or both a high-state active signal and a low-state active signal. Figure 2 In the diagram, the symbol for the control terminal corresponding to the active low-state signal includes an overline (hyperb). In this specification, the symbol for the control terminal corresponding to the active low-state signal includes a forward slash (" / ").

[0052] also, Figure 2 The specific configuration can be adjusted as shown in the example. For instance, it is possible to make some or all of the high-state active signals low-state active signals, or to make some or all of the low-state active signals high-state active signals. Additionally, the following terminals RY / ( / BY) are for outputting a ready signal as a high-state active signal and a busy signal as a low-state active signal. The forward slash (" / ") between RY and ( / BY) indicates the separation between the ready signal and the busy signal.

[0053] like Figure 2 As shown, the memory die MD has a memory cell array MCA for storing data and peripheral circuitry PC connected to the memory cell array MCA.

[0054] [Circuit configuration of a memory cell array (MCA)]

[0055] like Figure 3 As shown, the memory cell array (MCA) has multiple memory blocks (BLK). Each memory block (BLK) has multiple string components (SU). Each string component (SU) has multiple memory strings (MS). One end of each memory string (MS) is connected to the peripheral circuitry (PC) via a bit line (BL). The other end of each memory string (MS) is connected to the peripheral circuitry (PC) via a common source line (SL).

[0056] The memory string (MS) has a drain-side selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MCs) (memory cell transistors), and a source-side selection transistor (STS). Hereinafter, the drain-side selection transistor (STD) and the source-side selection transistor (STS) are sometimes referred to simply as selection transistors (STD, STS).

[0057] A memory cell (MC) is a field-effect transistor (memory transistor) that includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge storage film. The threshold voltage of the memory cell (MC) varies depending on the amount of charge in the charge storage film. A memory cell (MC) typically stores one or more bits of data. Furthermore, the gate electrodes of multiple memory cells (MCs) corresponding to a memory string (MS) are connected to word lines (WL). These word lines (WL) are collectively connected to all memory strings (MS) within a memory block (BLK).

[0058] A selection transistor (STD, STS) is a field-effect transistor comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrode of the selection transistor (STD, STS) is connected to both the drain-side selection gate line SGD and the source-side selection gate line SGS. The drain-side selection gate line SGD is provided for a string assembly SU and is commonly connected to all memory strings MS in one string assembly SU. The source-side selection gate line SGS is commonly connected to all memory strings MS in the memory block BLK. Hereinafter, the drain-side selection gate line SGD and the source-side selection gate line SGS are sometimes simply referred to as the selection gate line (SGD, SGS).

[0059] [Circuit configuration of the peripheral circuit PC]

[0060] like Figure 2 As shown, the peripheral circuit PC includes a line decoder RD, a sense amplifier module SAM, a cache memory CM, a counter CNT, a voltage generation circuit VG, and a sequencer SQC. Additionally, the peripheral circuit PC includes an address register ADR, an instruction register CMR, and a status register STR. Furthermore, the peripheral circuit PC includes input / output control circuitry (I / O) and logic circuitry CTR.

[0061] [The structure of the line decoder RD]

[0062] For example, like Figure 3 As shown, the line decoder RD( Figure 2 ) has address data D ADD ( Figure 2 Address decoder 22 performs decoding. Additionally, line decoder RD( Figure 2 It has a block selection circuit 23 and a voltage selection circuit 24 that transmit the operating voltage to the memory cell array MCA according to the output signal of the address decoder 22.

[0063] Address decoder 22 is connected to multiple block select lines BLKSEL and multiple voltage select lines 33. Address decoder 22, for example, refers sequentially to address register ADR according to control signals from sequencer SQC. Figure 2 The row address RA of ).

[0064] The block select circuit 23 has multiple block select circuits 34 corresponding to the memory block BLK. Each block select circuit 34 has multiple block select transistors 35 corresponding to the word line WL and the select gate line (SGD, SGS).

[0065] The block select transistor 35 is, for example, a field-effect transistor. The drain electrode of the block select transistor 35 is electrically connected to the corresponding word line WL or select gate line (SGD, SGS). The source electrode of the block select transistor 35 is electrically connected to the voltage supply line 31 via wiring CG and voltage selection circuit 24. The gate electrode of the block select transistor 35 is commonly connected to the corresponding block select line BLKSEL.

[0066] The voltage selection circuit 24 includes multiple voltage selection sections 36 corresponding to word lines WL and select gate lines (SGD, SGS). Each of the multiple voltage selection sections 36 includes multiple voltage selection transistors 37. The voltage selection transistors 37 are, for example, field-effect transistors. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS) via wiring CG and block selection circuit 23. The source terminals are electrically connected to the corresponding voltage supply lines 31. The gate electrodes are connected to the corresponding voltage selection lines 33.

[0067] [Composition of Sensing Amplifier Module (SAM) and Buffer Memory (CM)]

[0068] like Figure 4 As shown, the sense amplifier module SAM has multiple sense amplifier components SAU0 to SAU15 corresponding to multiple bit lines BL (e.g., 16 bit lines BL). Each sense amplifier component SAU0 to SAU15 has a sense amplifier SA connected to the bit line BL, a wiring LBUS connected to the sense amplifier SA, and latch circuits SDL, DL0 to DL10 connected to the wiring LBUS. i is an integer greater than or equal to 1.

[0069] The sensing amplifier SA senses the data read from the storage cell MC. The latch circuits SDL, DL0 to DL1 temporarily store the data sensed by the sensing amplifier SA. The wiring LBUS is connected to the wiring DBUS via the switching transistor DSW.

[0070] like Figure 4 As shown, the cache memory CM (data register) is connected to the DBUS wiring. The cache memory CM has multiple latch circuits XDL0 to XDL15 corresponding to multiple sense amplifier components SAU0 to SAU15. Data written to or read from the memory cell MC is stored in the multiple latch circuits XDL0 to XDL15 respectively.

[0071] Furthermore, during the write operation, the data DAT contained in the plurality of latch circuits XDL0 to XDL15 is sequentially transmitted to the latch circuit (e.g., latch circuit SDL) within the sense amplifier module SAM. Additionally, during the read and verification operations, the data contained in the latch circuits SDL and DL0 to DL15 within the sense amplifier module SAM is sequentially transmitted to the latch circuits XDL0 to XDL15. Furthermore, during the data output operation, the data DAT contained in the latch circuits XDL0 to XDL15 is sequentially transmitted to the input / output control circuit (I / O).

[0072] [Composition of the counter CNT]

[0073] Counter CNT( Figure 2 It receives data sequentially transmitted from the latch circuits XDL0 to XDL15 of the cache memory CM. Additionally, it counts the number of bits representing "0" or "1" in the bits included here.

[0074] [Construction of the voltage generation circuit VG]

[0075] For example, like Figure 3 As shown, the voltage generation circuit VG( Figure 2 The voltage generation circuit VG is connected to multiple voltage supply lines 31. It includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit 32. These step-down and step-up circuits are respectively connected to the power supply voltage V. CC and grounding voltage V SS ( Figure 2 The voltage supply lines are as follows. The voltage generation circuit VG, for example, generates various operating voltages applied to the bit line BL, source line SL, word line WL, and select gate lines (SGD, SGS) during read, write, and erase operations on the memory cell array MCA, based on control signals from the sequencer SQC, and simultaneously outputs these voltages to multiple voltage supply lines 31. The operating voltages output from the voltage supply lines 31 are appropriately adjusted according to the control signals from the sequencer SQC.

[0076] [Structure of Sequencer SQC]

[0077] Sequencer SQC ( Figure 2 According to the instruction data D stored in the instruction register CMR CMD The internal control signals are output to the line decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG. Additionally, the sequencer SQC outputs the status data D representing the state of the memory die MD. ST Output the appropriate value to the status register STR.

[0078] Additionally, the sequencer SQC generates a ready / busy signal and outputs it to the RY / ( / BY) terminal. During the period when the RY / ( / BY) terminal is in the "L" (Low) state (busy period), access to the memory die MD is essentially disabled. Conversely, during the period when the RY / ( / BY) terminal is in the "H" (High) state (ready period), access to the memory die MD is permitted.

[0079] [Structure of the Address Register (ADR)]

[0080] like Figure 2 As shown, the address register ADR is connected to the input / output control circuit I / O and stores the address data D input from the input / output control circuit I / O. ADD The Address Register (ADR) may have multiple 8-bit register columns. These register columns, for example, store the address data D corresponding to the currently executing internal action, such as read, write, or erase operations. ADD .

[0081] In addition, address data D ADD For example, it contains the column address CA ( Figure 2 ) and row address RA ( Figure 2 The row address RA, for example, contains a specific outgoing memory block BLK. Figure 3 The block address of the specific output string element (SU) and the page address of the word line (WL), the memory plane address of the specific output memory cell array (MCA) (memory plane), and the chip address of the specific output memory die (MD).

[0082] [Structure of the Instruction Register (CMR)]

[0083] The instruction register (CMR) is connected to the input / output control circuit (I / O) and stores the instruction data (D) input from the I / O. CMD The instruction register (CMR) has, for example, at least one set of 8-bit register columns. The instruction data (D) is then transferred. CMD When stored in the instruction register CMR, a control signal is sent to the sequencer SQC.

[0084] [The structure of the status register STR]

[0085] The status register STR is connected to the input / output control circuit I / O and stores the status data D output to the input / output control circuit I / O. ST The status register STR, for example, has multiple 8-bit register columns. These register columns, for example, store status data D related to the internal action being performed, such as read, write, or erase operations. ST Additionally, register columns store, for example, the readiness / busy information of the memory cell array (MCA).

[0086] [Composition of Input / Output Control Circuit (I / O)]

[0087] Input / output control circuit I / O ( Figure 2 It has data signal input / output terminals DQ0~DQ7, data strobe signal input / output terminals DQS, / DQS, shift register, and buffer circuit.

[0088] Data input via data signal input / output terminals DQ0 to DQ7 is input from the buffer circuit to the cache memory CM, address register ADR, or instruction register CMR according to the internal control signals from the logic circuit CTR. Conversely, data output via data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or status register STR to the buffer circuit according to the internal control signals from the logic circuit CTR.

[0089] Signals input via data strobe input / output terminals DQS and / DQS (e.g., data strobe signals and their complementary signals) are used when data is input via data signal input / output terminals DQ0 to DQ7. Data input via data signal input / output terminals DQ0 to DQ7 is loaded into a shift register within the input / output control circuit I / O at the rising edge of the voltage at data strobe input / output terminal DQS (input signal switching) and the falling edge of the voltage at data strobe input / output terminal / DQS (input signal switching), and at the falling edge of the voltage at data strobe input / output terminal DQS (input signal switching) and the rising edge of the voltage at data strobe input / output terminal / DQS (input signal switching).

[0090] [The structure of the logic circuit CTR]

[0091] Logic circuit CTR ( Figure 2 It has multiple external control terminals / CE, CLE, ALE, / WE, / RE, RE, and logic circuits connected to these external control terminals. The logic circuit CTR receives external control signals from the controller die CD via the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and outputs internal control signals to the input / output control circuit (I / O) accordingly.

[0092] [Structure of memory die MD]

[0093] Figure 5 This is a schematic 3D diagram representing a portion of a memory die (MD). Figure 6 It means Figure 5 A schematic enlarged view comprising a portion of it. Furthermore, Figure 5 and Figure 6 This indicates an illustrative composition; the specific composition can be appropriately modified. Furthermore, in Figure 5 and Figure 6 The text omits a portion of its components.

[0094] like Figure 5 As shown, the memory die MD includes a semiconductor substrate 100 and a transistor layer L disposed on the semiconductor substrate 100. TR and set in transistor layer L TR The upper storage cell array layer L MCA .

[0095] [Structure of semiconductor substrate 100]

[0096] The semiconductor substrate 100 is, for example, a single-crystal silicon (Si) semiconductor substrate containing P-type impurities. An N-type well containing N-type impurities such as phosphorus (P) is formed on a portion of the surface of the semiconductor substrate 100. Additionally, a P-type well containing P-type impurities such as boron (B) is formed on a portion of the surface of the N-type well. Furthermore, an insulating region 100I is formed on a portion of the surface of the semiconductor substrate 100.

[0097] [Transistor layer L] TR [Structure]

[0098] In transistor layer L TR Multiple transistors Tr are provided to form the peripheral circuit PC. The source region, drain region, and channel region of transistor Tr are disposed on the surface of semiconductor substrate 100. The gate electrode gc of transistor Tr is disposed on transistor layer L. TR In the plurality of transistors Tr, a contact CS is provided in the source region, drain region, and gate electrode gc. The plurality of contacts CS are connected via transistor layer L. TR The wiring D0, D1, and D2 in the circuit are connected to other transistors Tr and memory cell array layer L. MCA The composition, etc.

[0099] [Storage cell array layer L] MCA [Structure]

[0100] Storage cell array layer L MCA The device comprises multiple memory blocks BLK arranged alternately along the Y direction and multiple inter-block structures ST. Each memory block BLK comprises multiple conductive layers 110 and multiple insulating layers 101 arranged alternately along the Z direction, multiple semiconductor pillars 120 extending along the Z direction, and multiple gate insulating films 130 respectively disposed between the multiple conductive layers 110 and the multiple semiconductor pillars 120.

[0101] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction, and multiple layers are arranged in the Z direction. The conductive layer 110 may, for example, contain a multilayer film of titanium nitride (TiN) and tungsten (W), or it may contain polycrystalline silicon containing impurities such as phosphorus or boron.

[0102] Of the multiple conductive layers 110, one or more conductive layers 110 located at the bottom layer serve as the source-side selected gate line (SGS). Figure 3 The conductive layer 110 and its connected source-side selection transistors (STS) function as gate electrodes. Additionally, the multiple conductive layers 110 located above the conductive layer 110 serve as word lines (WL). Figure 3 ) and multiple storage units MC connected to it Figure 3 The gate electrode of the transistor functions as a gate electrode. Additionally, one or more conductive layers 110 located above the conductive layer 110 serve as the drain-side selected gate line SGD and a plurality of drain-side selected transistors STD connected thereto. Figure 3 The gate electrode of the ) performs its function.

[0103] A conductive layer 112 is disposed below the conductive layer 110. The conductive layer 112 includes a semiconductor layer 113 connected to the lower end of the semiconductor pillar 120 and a conductive layer 114 connected to the lower surface of the semiconductor layer 113. The semiconductor layer 113 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 114 may, for example, contain a conductive layer of a metal such as tungsten (W), tungsten silicide, or other conductive layers. In addition, an insulating layer 101 such as silicon oxide (SiO2) is disposed between the conductive layer 112 and the conductive layer 110.

[0104] Conductive layer 112 serves as the source line SL ( Figure 3 ) to perform its function. Source line SL, for example, for memory cell arrays (MCA) Figure 3 All storage blocks (BLKs) contained in the ) have common settings.

[0105] Multiple semiconductor pillars 120 are arranged in the X and Y directions. The semiconductor pillars 120 are, for example, semiconductor films such as undoped polycrystalline silicon (Si). Each semiconductor pillar 120 has a generally cylindrical shape, with an insulating film 125, such as silicon oxide, disposed in its central portion. Furthermore, the outer peripheral surfaces of each semiconductor pillar 120 are surrounded by conductive layers 110. The lower end of each semiconductor pillar 120 is connected to the semiconductor layer 113 of the conductive layer 112. The upper end of each semiconductor pillar 120 is connected to the bit line BL via an impurity region 121 containing N-type impurities such as phosphorus (P) and contacts Ch and Cb. Each semiconductor pillar 120 serves as a memory string MS ( Figure 3 The multiple memory cells MC and the channel regions of the selection transistors STD and STS contained in the ) function.

[0106] For example, like Figure 6 As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a barrier insulating film 133 deposited between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 are insulating films such as silicon oxide. The charge storage film 132 is a film capable of storing charge, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120.

[0107] In addition, Figure 6 The example shown is a gate insulating film 130 having a charge storage film 132 such as silicon nitride, but the gate insulating film 130 may also have a floating gate such as polysilicon containing N-type or P-type impurities.

[0108] For example, like Figure 5 As shown, the inter-block structure ST extends along the X and Z directions. The inter-block structure ST may include, for example, an insulating layer such as silicon oxide (SiO2). Alternatively, the inter-block structure ST may also include, for example, a conductive layer extending along the X and Z directions and connected to the conductive layer 112, and an insulating layer such as silicon oxide (SiO2) disposed on both sides of the conductive layer in the Y direction.

[0109] [Record the threshold voltage of the multi-bit memory cell MC]

[0110] Next, refer to Figure 7 The threshold voltage of the storage unit MC, which records multi-bit data, is explained. Figure 7 As an example, the threshold voltage of the storage cell MC that records 3 bits of data is shown.

[0111] Figure 7 (a) is a schematic bar chart illustrating the threshold voltage of the memory cell MC that records 3 bits of data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC. Figure 7 (b) is a table showing an example of the relationship between the threshold voltage of the storage unit MC that records 3 bits of data and the recorded data. Figure 7 (c) is another example of the relationship between the threshold voltage of the storage unit MC that records 3 bits of data and the recorded data.

[0112] exist Figure 7 In example (a), the threshold voltage of the memory cell MC is controlled to have 8 states. The threshold voltage of the memory cell MC controlled to the Er state is less than the erase verification voltage V. VFYEr Additionally, for example, the threshold voltage of the memory cell MC controlled in state A is greater than the verification voltage V. VFYA And less than the verification voltage VVFYB Additionally, for example, the threshold voltage of the memory cell MC controlled in state B is greater than the verification voltage V. VFYB And less than the verification voltage V VFYC Similarly, the threshold voltage of the memory cell MC controlled in states C to F is greater than the verification voltage V. VFYC ~Verification voltage V VFYF And less than the verification voltage V VFYD ~Verification voltage V VFYG Additionally, for example, the threshold voltage of the memory cell MC controlled in state G is greater than the verification voltage V. VFYG And less than the readout path voltage V READ Read the path voltage V READ For example, a voltage of around 9V.

[0113] In addition, Figure 7 In example (a), a readout voltage V is set between the threshold distribution corresponding to the Er state and the threshold distribution corresponding to the A state. CGAR Additionally, a readout voltage V is set between the threshold distribution corresponding to state A and the threshold distribution corresponding to state B. CGBR Similarly, readout voltages V are set between the threshold distribution corresponding to state B and the threshold distribution corresponding to state C, and between the threshold distribution corresponding to state F and the threshold distribution corresponding to state G. CGBR ~Read the voltage V CGGR .

[0114] For example, the Er state corresponds to the lowest threshold voltage. The memory cell MC in the Er state is, for example, the memory cell MC in the erase state. The memory cell MC in the Er state is, for example, assigned the data "111".

[0115] Furthermore, state A corresponds to a threshold voltage that is higher than the threshold voltage corresponding to state Er. For example, data "101" is allocated to the storage cell MC in state A.

[0116] Furthermore, state B corresponds to a threshold voltage that is higher than the threshold voltage corresponding to state A. For example, data "001" is allocated to the storage cell MC in state B.

[0117] Similarly, in the diagram, states C through G correspond to threshold voltages that are higher than the threshold voltages of states B through F. The storage cells MC for these states are, for example, assigned the data “011”, “010”, “110”, “100”, and “000”.

[0118] In addition, in such Figure 7 (b) In the illustrated allocation case, the data of the lower bit can be read through one read voltage V. CGDRTo determine the median bit data, it can be obtained through three readout voltages V. CGAR V CGCR V CGFR To determine this, the data in the higher-order bit can be read through three readout voltages V. CGBR V CGER V CGGR This is used to make a judgment. Sometimes, such data allocation is called 1-3-3 encoding.

[0119] Furthermore, the number of bits, the number of states, and the data allocation for each state recorded in the storage unit MC can be appropriately changed.

[0120] For example, in such Figure 7 (c) In the illustrated allocation case, the data of the lower bit can be read through one read voltage V. CGDR To determine the median bit data, it can be obtained through two readout voltages V. CGBR V CGFR To determine this, the data in the upper-level bit can be read through four readout voltages V. CGAR V CGCR V CGER V CGGR This is used to make a judgment. Sometimes, such data allocation is called 1-2-4 encoding.

[0121] [Write action]

[0122] Next, the write operation of the semiconductor memory device in this embodiment will be described.

[0123] Figure 8 This is a flowchart used to explain the writing operation of the first embodiment. Figure 9 It is used for the number of loops n W With programming voltage V PGM1 A diagram illustrating the relationship. Figure 10 It is a timing diagram used to illustrate the first programming action and the first verification action. Figure 11 It is a schematic cross-sectional view used to illustrate the first programming action. Figure 12 This is a schematic cross-sectional view used to illustrate the first verification action.

[0124] Furthermore, in the following explanation, the word line WL that will sometimes become the object of the action is referred to as the selection word line WL. S The word lines WL other than these are called non-selective word lines WL. U Additionally, in the following description, the multiple storage units MC contained in the string component SU, which will sometimes become the action object, are connected to the select word line WL. SThe memory cell MC is called the "selection memory cell MC". Additionally, in the following description, this configuration containing multiple selection memory cells MCs is sometimes referred to as a selection page PG.

[0125] Furthermore, the following description will illustrate an example of performing a write operation on multiple selected memory cells (MCs) corresponding to the selected page (PG).

[0126] The write operation comprises multiple first write cycles. Each first write cycle includes an action that increases the threshold voltage of the memory cell MC (hereinafter referred to as...). Figure 8 Step S202, etc.), and the action of confirming the threshold voltage of the memory cell MC (hereinafter referred to as...) Figure 8 (Step S203, etc.). The first write loop in the write operation of the third and fourth embodiments is also the same.

[0127] In step S200, the initial programming voltage V is set. PGMS ( Figure 9 Initial programming voltage V PGMS The programming voltage V in the first programming action (step S202) PGM1 The initial value of the voltage. Initial programming voltage V PGMS In the following programmed voltage control operation ( Figure 13 In steps S101 to S109, obtain ( Figure 13 Step S106).

[0128] In step S201, the number of iterations n is... W Set to 1. Number of loops n W This is a variable representing the number of times the first write cycle is performed. Additionally, in step S201, for example, the data written to the storage unit MC is latched into the sense amplifier assembly SAU (…). Figure 4 In the latching circuit DL0~DLi. The actions of steps S200 and S201 are, for example, in... Figure 10 The execution time is t300.

[0129] In step S202, the first programming action is performed. The first programming action is to select the word line WL. S Supply programming voltage V PGM1 This action increases the threshold voltage of the memory cell MC. Figure 10 In the example, the action is performed during the period from time t312 to time t316 and during the period from time t328 to time t332.

[0130] In the first programming action, for example, like Figure 10 and Figure 11 As shown, the bit line BL of the selection memory cell MC, which is connected to multiple selection memory cells MC for threshold voltage adjustment, is...W Supply voltage V SRC Additionally, the bit lines BL of the select memory cells MCs connected among multiple select memory cells MCs that do not undergo threshold voltage adjustment are also addressed. P Supply voltage V DD Hereinafter, the memory cell MC that adjusts the threshold voltage among multiple select memory cells MCs is sometimes referred to as the "write memory cell MC," while the select memory cell MC that does not adjust the threshold voltage is referred to as the "disable memory cell MC." Voltage V SRC It can be greater than the ground voltage V SS It can also be related to the ground voltage V SS Equal. Voltage V DD Greater than voltage V SRC .

[0131] Additionally, in the first programming action, for example, like Figure 10 and Figure 11 As shown, the gate line SGD is supplied with voltage V to the drain side. SGD .

[0132] Voltage V SGD Greater than voltage V SRC Additionally, voltage V SGD With voltage V SRC The voltage difference is greater than the threshold voltage required for the drain-side select transistor STD to function as an NMOS (N-channel Metal Oxide Semiconductor) transistor. Therefore, when connected to bit line BL... W In the drain-side selective transistor STD, an electron channel is formed in the channel region, thereby transmitting voltage V. SRC .

[0133] On the other hand, voltage V SGD With voltage V DD The voltage difference is less than the threshold voltage required for the drain-side selection transistor STD to function as an NMOS transistor. Therefore, the voltage difference connected to bit line BL is less than the threshold voltage required for the drain-side selection transistor STD to function as an NMOS transistor. P The drain-side selection transistor STD is in the off state.

[0134] Additionally, in the first programming action, for example, like Figure 11 As shown, a voltage V is supplied to the source line SL. SRC The source side selects to supply ground voltage V to the gate lines SGS and SGSb. SS Therefore, the source-side selection transistors STS and STSb are turned off.

[0135] Additionally, in the first programming action, for example, like Figure 10 and Figure 11As shown, for the non-select word line WL U Supply write path voltage V PASS Write path voltage V PASS Greater than reference Figure 7 The described readout path voltage V READ Write path voltage V PASS For example, a voltage of around 10V. Additionally, the write path voltage V... PASS With voltage V SRC The voltage difference, regardless of the data recorded in the memory cell MC, is greater than the threshold voltage required for the memory cell MC to function as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC, transmitting the voltage V to the written memory cell MC. SRC .

[0136] Additionally, in the first programming action, for example, like Figure 10 and Figure 11 As shown, for the selection word line WL S Supply programming voltage V PGM1 Programming voltage V PGM1 Greater than the write path voltage V PASS .

[0137] Figure 9 This illustrates an example of performing the first programming action in a loop that executes the first write twice. In the first write loop (loop number n)... W =1) The first programming action ( Figure 10 During the time Tpgm from time t314 to time t315, select word line WL S Supply initial programming voltage V PGMS As mentioned above, the initial programming voltage V PGMS In step S200, the programming voltage V is set. PGM1 The initial voltage value. Additionally, in the second write operation of the first loop (loop number n)... W =2) The first programming action ( Figure 10 During the time Tpgm from time t330 to time t331, select word line WL S The supply will be the initial programming voltage V PGMS Add offset voltage ΔV PGM The obtained voltage (V) PGMS +ΔV PGM ) as programming voltage V PGM1 .

[0138] Here, for the connection to bit line BL W The channel supply voltage V of the semiconductor pillar 120 SRC In this semiconductor pillar 120 and select word line WLS A relatively large electric field is generated between them. As a result, electrons in the channels of semiconductor pillar 120 pass through tunnel insulating film 131 ( Figure 6 ) tunneling to the charge storage membrane 132 ( Figure 6 This leads to an increase in the threshold voltage for writing to the memory cell MC.

[0139] Additionally, connected to bit line BL P The channel of the semiconductor pillar 120 becomes electrically floating, and the potential of this channel is controlled by the non-select word line WL. U The voltage rises to the write path voltage V due to capacitive coupling. PASS Left and right. In this semiconductor pillar 120 and select word line WL S Only a smaller electric field than the electric field is generated between them. Therefore, electrons in the channels of semiconductor pillar 120 do not tunnel to charge storage film 132. Figure 6 Therefore, the threshold voltage of the memory cell MC will not increase.

[0140] In step S203 ( Figure 8 In the first verification step, the first verification action is performed. The first verification action is as follows: it is used to select the word line WL. S Supply verification voltage V VFY It detects the on / off state of the memory cell MC and checks whether the threshold voltage of the memory cell MC has reached the target value. Figure 10 In the example, the action is performed during the period from time t317 to time t327 and during the period from time t333 to time t343.

[0141] In the first verification action, for example, like Figure 10 and Figure 12 As shown, during the period from time t318 to time t321, based on the data in the latch circuits DL0 to DL1, the latch is connected to a specific state ( Figure 10 and Figure 12 In the example, state A) corresponds to the bit line BL of the memory cell MC. Figure 10 and Figure 12 In the example, it is the bit line BL A Supply voltage V DD Supply voltage V to other bit lines BL SRC Additionally, a voltage V is supplied to the source line SL. SRC Additionally, during the first verification operation, from time t321 to time t324, the bit line BL connected to the memory cell MC corresponding to state B is... B Supply voltage V DD During the period from time t324 to time t327, the bit line BL connected to the memory cell MC corresponding to state C is... CSupply voltage V DD .

[0142] Additionally, in the first verification action, for example, like Figure 10 and Figure 12 As shown, the gate line SGD is supplied with voltage V to the drain side. SG Voltage V SG Greater than voltage V DD Additionally, voltage V SG With voltage V DD The voltage difference is greater than the threshold voltage required for the drain-side select transistor STD to function as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the drain-side select transistor STD, thereby transferring voltage V. DD .

[0143] Additionally, in the first verification action, for example, like Figure 12 As shown, a voltage V is supplied to the source-side gate lines SGS and SGSb. SG Voltage V SG Greater than voltage V SRC Additionally, voltage V SG With voltage V SRC The voltage difference is greater than the threshold voltage required for the source-side select transistors STS and STSb to function as NMOS transistors. Therefore, electron channels are formed in the channel regions of the source-side select transistors STS and STSb, thereby transferring voltage V. SRC .

[0144] Additionally, in the first verification action, for example, like Figure 10 and Figure 12 As shown, for the non-select word line WL U Supply readout path voltage V READ Read the path voltage V READ Greater than voltage V DD V SRC Additionally, read the path voltage V. READ With voltage V DD V SRC The voltage difference, regardless of the data recorded in the memory cell MC, is greater than the threshold voltage required for the memory cell MC to function as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC, transmitting voltage V to the selected memory cell MC. DD V SRC .

[0145] Additionally, in the first verification action, for example, like Figure 10 and Figure 12 As shown, during the period from time t317 to time t318, the selection word line WL is...S Supply readout path voltage V READ Then, select the word line WL. S Supply verification voltage V VFY Verify voltage V VFY Less than the readout path voltage V READ Verify voltage V VFY It is a reference Figure 7 The verification voltage V described VFYA ~V VFYG Any one of them. In Figure 10 In the example, during the period from time t318 to time t321, the voltage V is verified. VFY It is the verification voltage V corresponding to state A. VFYA Additionally, during the period from time t321 to time t324, the voltage V was verified. VFY It is the verification voltage V corresponding to state B. VFYB Additionally, during the period from time t324 to time t327, the voltage V was verified. VFY It is the verification voltage V corresponding to state C. VFYC .

[0146] Therefore, as Figure 12 As shown, the threshold voltage is the verification voltage V. VFYA The following memory cell MC is turned on, and the threshold voltage is greater than the verification voltage V. VFYA The memory cell MC is switched off. Similarly, the threshold voltage is the verification voltage V. VFYB V VFYC The following memory cell MC is turned on, and the threshold voltage is greater than the verification voltage V. VFYB V VFYC The storage unit MC is in an off state. This is achieved by the sensing amplifier module SAM ( Figure 4 ) via bitline BL A BL B BL C The on / off state of these memory cells (MCs) is detected to obtain data representing the state of the memory cell (MC). This action is called a "sensing action".

[0147] In sensing operations, for example, a voltage V is supplied to the alignment line BL. DD In the state of, make the sensing amplifier SA ( Figure 4 The sensing node is connected to the bit line BL. After the sensing action is performed, the sensing node is electrically disconnected from the bit line BL. Additionally, the charge on the wiring LBUS is discharged or maintained depending on the state of the sensing node. Furthermore, any latch circuit within the sensing amplifier assembly SAU is connected to the wiring LBUS, and the data on the wiring LBUS is latched by this latch circuit.

[0148] exist Figure 10 In the example, during the period from time t319 to time t320, the sensing amplifier SA causes the bit line BL to... A It is connected to the sensing node. Additionally, during the period from time t322 to time t323, the sensing amplifier SA enables the bit line BL to... B It is connected to the sensing node. Additionally, during the period from time t325 to time t326, the sensing amplifier SA enables the bit line BL to... C The period during which the bit line BL is connected to the sensing node is sometimes referred to as the sensing time Ts1, such as the period from time t319 to time t320, the period from time t322 to time t323, and the period from time t325 to time t326.

[0149] Data indicating the on / off state of the storage unit MC is transmitted via wiring LBUS, switching transistor DSW, and wiring DBUS ( Figure 4 The latch circuits XDL0 to XDL15 transmit data to the high-speed cache memory CM. Figure 4 The cache memory CM stores data representing the on / off state of the memory cell MC corresponding to the multiple bit lines BL in multiple latch circuits XDL0 to XDL15.

[0150] For example, when the select memory cell MC corresponding to one bit line BL is in the ON state, the data "1" is stored in the latch circuit XDL corresponding to the bit line BL. The data "1" indicates that the data was not written correctly to the select memory cell MC corresponding to one bit line BL (that is, the threshold voltage of the select memory cell MC did not reach the target value). Hereinafter, the bit of the data "1" is sometimes referred to as the verification failure bit.

[0151] Additionally, for example, when the select memory cell MC corresponding to one bit line BL is in the off state, a "0" data is stored in the latch circuit XDL corresponding to the bit line BL. The "0" data indicates that the data has been successfully written to the select memory cell MC corresponding to the bit line BL (that is, the threshold voltage of the select memory cell MC has reached the target value). Hereinafter, the bit with the "0" data is sometimes referred to as the verification success bit.

[0152] In step S204 ( Figure 8 In step S203, the result of the first verification action is determined. For example, the data obtained through the first verification action in step S203 (hereinafter, sometimes referred to as the first verification data) is sequentially transferred from latch circuits XDL0 to XDL15 to counter CNT. Figure 2The counter CNT counts the number of failed verification bits (the number of "1" bits) in the first verification data. This counting of failed verification bits is performed, for example, at the end of step S203. The sequencer SQC determines whether the number of failed verification bits in the first verification data is less than the first reference value Cr1.

[0153] If the sequencer SQC determines that the verification is successful when the number of failed verification bits in the first verification data is less than the first reference value Cr1, it proceeds to step S207. On the other hand, if the sequencer SQC determines that the verification is failed when the number of failed verification bits in the first verification data is greater than or equal to the first reference value Cr1, it proceeds to step S205.

[0154] In addition, Figure 9 In the example, the loop is written for the first time (loop count n). W =1), indicating a verification failure, the loop (loop count n) is written in the second and first iteration. W =2), and the verification is considered successful.

[0155] In step S205 ( Figure 8 In the loop, determine the number of iterations n. W Has the specified number of attempts (N) been reached? W If the condition is not met, proceed to step S206. If the condition is met, proceed to step S208.

[0156] In step S206 ( Figure 8 In the loop, the number of iterations n W Add 1, and proceed to step S202. Additionally, in step S206, for example, the programming voltage V is... PGM1 Add the specified offset voltage ΔV PGM Therefore, the programming voltage V PGM1 As the number of loops n W The offset voltage ΔV is gradually increased by increasing the voltage. PGM .

[0157] In step S207 ( Figure 8 In the file, the content will be the status data D indicating that the write operation has been completed normally. ST Stored in the status register STR( Figure 2 The write operation is completed within the specified range. Additionally, the status data D... ST The status read action is output to the controller's bare CD (CD). Figure 1 ).

[0158] In step S208 ( Figure 8 In the file, the content will be the status data D indicating that the write operation did not end normally. ST Stored in the status register STR( Figure 2In ), and end the writing action.

[0159] [Erase action]

[0160] Next, the erasure operation of the semiconductor memory device in this embodiment will be described.

[0161] Figure 13 and Figure 14 This is a flowchart illustrating the erasure operation of the first embodiment. The erasure operation includes a programming voltage control operation (…). Figure 13 Steps S101 to S109) and normal erasure action ( Figure 14 Steps S111 to S118).

[0162] The programming voltage control action adjusts the initial programming voltage V based on the degradation level of the memory cell MC. PGMS The erase operation is the process of erasing data stored in the memory cell (MC).

[0163] Furthermore, the following description will illustrate an example of performing an erase operation on the storage block BLK that becomes the action object.

[0164] [Programmable voltage control action]

[0165] In the programmed voltage control operation, by controlling the select word line WL S Supply programming voltage V PGM2 This causes the threshold voltage of the memory cell MC in the Er state to gradually increase to the threshold voltage corresponding to a specific state (state A in this embodiment). The programming voltage V required to increase to the threshold voltage corresponding to the specific state is then determined. PGM2 As the first programming action ( Figure 8 The initial programming voltage V in (202) PGMS .

[0166] The programming voltage control action includes a pre-read action (step S101), a second programming action (step S103, etc.), a second verification action (step S104, etc.), and an initial programming voltage V. PGMS The acquisition action (step S106). For example... Figure 13 and Figure 14 As shown, the programmed voltage control action is performed before the normal erase action.

[0167] In addition, the programming voltage control operation includes multiple second write cycles. Each second write cycle includes a second programming operation (step S103, etc.) and a second verification operation (step S104, etc.).

[0168] Figure 15 It is a timing diagram used to explain the pre-read action. Figure 16It is a schematic cross-sectional view used to illustrate the pre-reading action. Figure 17 It is used for the number of loops n E1 With programming voltage V PGM2 A diagram illustrating the relationship. Figure 18 It is a timing diagram used to illustrate the second programming action and the second verification action. Figure 19 This is a schematic cross-sectional view used to illustrate the second programming action. Figure 20 This is a schematic cross-sectional view used to illustrate the second verification action.

[0169] Figure 21 This is a diagram used to illustrate the second programming action for writing word lines. Figure 22 This is a diagram used to illustrate the second programming action for erasing word lines.

[0170] In step S101 ( Figure 13 In the process of selecting a page (PG), a prefetch operation is performed. This prefetch operation involves reading data from multiple selection memory units (MCs) corresponding to the PG to identify whether the PG is a page with data written to it (i.e., a page in the programmed state) or a page without data written to it (i.e., a page in the erased state). Furthermore, the selection word line WL connected to the PG... S Select any word line WL from the multiple word lines WL contained in the memory block BLK that will be the target of the erase operation. Select word line WL S It can be a predefined word line (WL). For example, selecting word line WL. S This could be a word line WL at a specific layer, counted from the source line SL. Prefetching actions, for example, in... Figure 15 The moment t11 ​​begins.

[0171] In pre-reading actions, such as... Figure 16 As shown, a voltage V is supplied to the multiple bit lines BL contained in the string component SU, which becomes the object of the action. DD Additionally, a voltage V is supplied to the source line SL. SRC .

[0172] Additionally, in pre-reading actions, such as... Figure 15 and Figure 16 As shown, during the period from time t12 to time t16, a voltage V is supplied to the drain-side gate line SGD. SG As described above, an electron channel is formed in the channel region of the drain-side selective transistor STD, thereby transmitting voltage V. DD .

[0173] Additionally, in pre-reading actions, such as... Figure 16 As shown, a voltage V is supplied to the source-side gate lines SGS and SGSb. SGAs described above, electron channels are formed in the channel regions of the selective transistors STS and STSb on the source side, thereby transmitting voltage V. SRC .

[0174] Additionally, in pre-reading actions, such as... Figure 15 and Figure 16 As shown, during the period from time t12 to time t16, the non-selection word line WL... U Supply readout path voltage V READ Read the path voltage V READ Greater than voltage V DD V SRC Additionally, read the path voltage V. READ With voltage V DD V SRC The voltage difference, regardless of the data recorded in the memory cell MC, is greater than the threshold voltage required for the memory cell MC to function as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC, transmitting voltage V to the selected memory cell MC. DD V SRC .

[0175] Additionally, in pre-reading actions, such as... Figure 15 and Figure 16 As shown, during the period from time t13 to time t16, the selection word line WL is... S Supply readout voltage V CGR Read the voltage V CGR Less than the readout path voltage V READ In this embodiment, as Figure 16 and Figure 17 As shown, the voltage V will be read. CGR Let V be the readout voltage corresponding to state A. CGAR Read the voltage V CGAR With voltage V SRC The voltage difference is greater than the threshold voltage of the memory cell MC in the Er state. Therefore, the memory cell MC in the Er state becomes ON. Consequently, current flows in the bit line BL connected to this memory cell MC. On the other hand, the read voltage V... CGAR With voltage V SRC The voltage difference is less than the threshold voltage of the memory cell MC in states A through G. Therefore, the memory cell MC in states A through G is in an off state. Consequently, no current flows in the bit line BL connected to this memory cell MC.

[0176] Additionally, during the pre-read operation, the sensor amplifier module SAM ( Figure 4 The system detects whether the current flows to the line BL, thereby detecting the on / off state of the memory cell MC.

[0177] exist Figure 15 In the example, the sensing amplifier SA performs sensing operation on the bit line BL during the period from time t14 to time t15.

[0178] Data indicating the on / off state of the storage unit MC is verified by the first verification action ( Figure 8 The same method as step S203) is used to transfer data to the latch circuits XDL0 to XDL15 of the cache memory CM. Figure 4 ).

[0179] For example, when the selection memory cell MC corresponding to one bit line BL is in the ON state, the data "1" is stored in the latch circuit XDL corresponding to the bit line BL. The data "1" indicates that data is recorded in the selection memory cell MC corresponding to one bit line BL. Hereinafter, the bit of the data "1" is sometimes referred to as the bit of the ON state.

[0180] Additionally, for example, when the selection memory cell MC corresponding to one bit line BL is in an off state, data of "0" is stored in the latch circuit XDL corresponding to the bit line BL. The data of "0" indicates that no data is recorded in the selection memory cell MC corresponding to the bit line BL. Hereinafter, the bit of data of "0" is sometimes referred to as the bit of the off state.

[0181] In addition, the data acquired through the pre-read operation (hereinafter sometimes referred to as read data) is sequentially transferred from the latch circuits XDL0 to XDL15 to the counter CNT ( Figure 2 The counter CNT counts the number of bits in the ON state (the number of "1" bits) in the read data. The number of ON state bits is transmitted to the sequencer SQC. The sequencer SQC determines whether the number of ON state bits is less than the reference value Crr.

[0182] When the number of bits in the ON state is less than the reference value Crr, the sequencer SQC selects page PG as the programming state page. On the other hand, when the number of bits in the ON state is greater than or equal to the reference value Crr, the sequencer SQC selects page PG as the erase state page.

[0183] The sequencer SQC stores the result of determining whether the selected page PG is a page in the programming state or a page in the erasure state in a designated register.

[0184] In step S102 ( Figure 13 In the loop, the number of iterations n E1 Set to 1. Number of loops n E1 This is a variable representing the number of times the second write is executed in the loop. This action, for example, occurs in... Figure 18 The execution time is t100.

[0185] In step S103 ( Figure 13 In the process, the second programming action is executed. The second programming action is the selection word line WL. S Supply programming voltage V PGM2 This action increases the threshold voltage of the memory cell MC. Figure 18 In the example, the action is performed during the period from time t110 to time t114 and during the period from time t120 to time t124.

[0186] In the second programming action, for example, like Figure 19 As shown, for all bit lines BL W Supply voltage V SRC .

[0187] Additionally, in the second programming action, for example, like Figure 18 and Figure 19 As shown, during the period from time t111 to time t114, a voltage V is supplied to the drain-side gate line SGD. SGD In this case, as described above, when connected to bit line BL... W In the drain-side selective transistor STD, an electron channel is formed in the channel region, thereby transmitting voltage V. SRC .

[0188] Additionally, in the second programming action, for example, like Figure 19 As shown, a voltage V is supplied to the source line SL. SRC The source side selects to supply ground voltage V to the gate lines SGS and SGSb. SS Therefore, the source-side selection transistors STS and STSb are turned off.

[0189] Additionally, in the second programming action, for example, like Figure 18 and Figure 19 As shown, during the period from time t111 to time t114, the non-selection word line WL... U Supply write path voltage V PASS Therefore, as described above, an electron channel is formed in the channel region of the non-selected memory cell MC, transmitting the voltage V to the write memory cell MC. SRC .

[0190] Additionally, in the second programming action, for example, like Figure 18 and Figure 19 As shown, during the period from time t112 to time t113, the selection word line WL is... S Supply programming voltage V PGM2 Programming voltage V PGM2 Greater than the write path voltage V PASS .

[0191] Figure 17 This represents an example of executing the second programming action in a loop that performs the second write operation 6 times. In the first second write operation (loop number n)... E1 =1) The second programming action ( Figure 18 During the period from time t112 to time t113, select word line WL S Supply initial programming voltage V PGM0 Initial programming voltage V PGM0 It is the programming voltage V PGM2 The initial value. Additionally, the second loop (loop count n) is written in the second iteration. E1 =2) The second programming action ( Figure 18 During the period from time t122 ​​to time t123, select word line WL S The supply will be the initial programming voltage V PGM0 The voltage obtained by adding the offset voltage ΔV (V) PGM0 +ΔV) is used as the programming voltage V PGM2 Write the loop (loop count n) from the 3rd to the 6th iteration. E1 In the second programming action of (=3~6), select word line WL respectively. S Supply voltage (V) PGM0 +2ΔV), voltage (V) PGM0 +3ΔV), voltage (V) PGM0 +4ΔV), voltage (V) PGM0 +5ΔV) as the programming voltage V PGM2 .

[0192] In the second programming action as described above, it will be as follows: Figure 18 and Figure 19 The operating voltage shown is supplied to the bit line BL, source line SL, word line WL, and select gate line (SGD, SGS), thereby increasing the threshold voltage of the selected memory cell MC in stages.

[0193] For example, when selecting a page where page PG is in programming mode, such as Figure 21 As shown, in the initial state, the threshold voltages of the multiple memory cells MC corresponding to the selected page PG are distributed between the Er state and the G state. Figure 17 As shown, the programming voltage V in the second programming action PGM2 As the second write loop executes (loop count n) E1 The offset voltage ΔV increases sequentially with the number of write cycles (n). Therefore, the threshold voltage of the memory cell MC corresponding to the Er state also increases with the number of executions in the second write cycle (cycle number n). E1 It increases in stages and gradually. For example, such as Figure 21 As shown, compared to the initial state, when the number of loops nE1 When the value is 3, the threshold voltage of the memory cell MC corresponding to the Er state is larger. Additionally, the threshold voltage is related to the number of cycles n. E1 Compared to when the number of iterations is 3, when the number of iterations n E1 When the threshold voltage is 5, the threshold voltage of the memory cell MC corresponding to the Er state is larger. In this way, the threshold distribution corresponding to the Er state gradually approaches the threshold distribution corresponding to the A state.

[0194] Furthermore, the increase in threshold voltage is smaller for memory cells MC corresponding to states A through G compared to memory cells MC corresponding to state Er.

[0195] Additionally, for example, when selecting a page where page PG is in an erased state, such as Figure 22 As shown, in the initial state, the threshold voltages of multiple memory cells MC corresponding to the selected page PG are included in the threshold distribution corresponding to the Er state. The threshold voltage of the memory cell MC corresponding to the Er state increases with the number of executions of the second write loop (loop number n). E1 It increases in stages.

[0196] In step S104 ( Figure 13 In the process of selecting the word line WL, the second verification action is performed. The second verification action is as follows: S Supply verification voltage (e.g., the same as the readout voltage V) CGAR (Using the same voltage), it detects the on / off state of the memory cell MC and whether the threshold voltage of the memory cell MC has reached the target value. Figure 18 In the example, the action is performed during the period from time t115 to time t119 and during the period from time t125 to time t127.

[0197] In the second verification action, for example, like Figure 20 As shown, a voltage V is supplied to all bit lines BL corresponding to the selected page PG. DD Additionally, a voltage V is supplied to the source line SL. SRC .

[0198] Additionally, in the second verification action, for example, like Figure 18 and Figure 20 As shown, during the period from time t115 to time t119, a voltage V is supplied to the drain-side gate line SGD. SG In this case, as described above, an electron channel is formed in the channel region of the selected transistor STD on the drain side, thereby transmitting voltage V. DD .

[0199] Additionally, in the second verification action, for example, like Figure 20As shown, a voltage V is supplied to the source-side gate lines SGS and SGSb. SG In this case, as described above, electron channels are formed in the channel regions of the source-side selective transistors STS and STSb, thereby transmitting voltage V. SRC .

[0200] Additionally, in the second verification action, for example, like Figure 18 and Figure 20 As shown, during the period from time t115 to time t119, the non-selection word line WL... U Supply readout path voltage V READ In this case, as described above, an electron channel is formed in the channel region of the non-selected memory cell MC, transmitting voltage V to the selected memory cell MC. DD V SRC .

[0201] Additionally, in the second verification action, for example, like Figure 18 and Figure 20 As shown, during the period from time t116 to time t119, the selection word line WL is... S Supply verification voltage. Figure 18 and Figure 20 In the example, the verification voltage is set to the readout voltage V corresponding to state A. CGAR The same voltage. Therefore, as... Figure 20 As shown, the threshold voltage is the verification voltage (readout voltage V). CGAR The memory cell MC below the threshold voltage becomes the ON state, and the threshold voltage is greater than the verification voltage (read voltage V). CGAR The storage unit MC of the sensor amplifier module (SAM) becomes disconnected. Figure 4 The on / off state of these memory cells (MCs) is detected via the bit line BL to obtain data representing the state of the memory cell (MC).

[0202] exist Figure 18 In the example, the sensing amplifier SA performs sensing operation on the bit line BL during the period from time t117 to time t118.

[0203] Data indicating the on / off state of the storage unit MC is verified by the first verification action ( Figure 8 The same method as step S203) is used to transfer data to the latch circuits XDL0 to XDL15 of the cache memory CM. Figure 4 ).

[0204] When the selected memory cell MC is in the ON state, a "1" is stored in the latch circuit XDL. Conversely, when the selected memory cell MC is in the OFF state, a "0" is stored in the latch circuit XDL. As described above, the bit containing the "1" is sometimes referred to as the verification failure bit, and the bit containing the "0" is referred to as the verification success bit.

[0205] In step S105 ( Figure 13 In step S104, the result of the second verification action is determined. For example, the data obtained through the second verification action (hereinafter, sometimes referred to as the second verification data) is sequentially transferred from the latch circuits XDL0 to XDL15 to the counter CNT. Figure 2 The counter CNT counts the bits that failed verification (the number of "1" bits) in the second verification data. The counting of the bits that failed verification is performed at the end of step S104. The bits that failed verification are transmitted to the sequencer SQC.

[0206] The sequencer SQC determines whether the selected page PG is in a programming state or an erased state during the pre-read operation (step S101). Next, if the selected page PG is in a programming state, the sequencer SQC determines whether the number of failed verification bits in the second verification data is less than the second reference value Cr21 used for pages in a programming state. Conversely, if the selected page PG is in an erased state, the sequencer SQC determines whether the number of failed verification bits in the second verification data is less than the second reference value Cr22 used for pages in an erased state.

[0207] As described above, in the initial state, the number of selected memory cells MC corresponding to the threshold distribution of the Er state is greater than that of the selected page PG in the erase state compared to the selected page PG in the programming state. That is, the number of selected memory cells MC of the determination object in step S105 is greater. Therefore, the second reference value Cr22 used for the page in the erase state is set to a value larger than the second reference value Cr21 used for the page in the programming state.

[0208] If the number of failed verification bits in the second verification data is less than the second reference value (Cr21 or Cr22), the sequencer SQC determines that the verification is successful and proceeds to step S106. On the other hand, if the number of failed verification bits in the second verification data is greater than or equal to the second reference value (Cr21 or Cr22), the sequencer SQC determines that the verification has failed and proceeds to step S107.

[0209] In addition, Figure 17 In the example, the loop is written 2nd time from the 1st to the 5th time (loop count n). E1 =1~5), which is considered a verification failure. The loop (loop count n) is written in the 6th iteration, 2nd iteration. E1=6), and the verification is considered successful.

[0210] In step S107 ( Figure 13 In the loop, determine the number of iterations n. E1 Has the specified number of attempts (N) been reached? E1 If the condition is not met, proceed to step S108. If the condition is met, proceed to step S109.

[0211] In step S108 ( Figure 13 In the loop, the number of iterations n E1 Add 1, and proceed to step S103. Additionally, in step S108, for example, the programming voltage V is... PGM2 Add the specified offset voltage ΔV. Therefore, the programming voltage V PGM2 As the number of loops n E1 The offset voltage ΔV is increased successively by adding more voltages.

[0212] In step S109 ( Figure 13 In the data, the content will be the state data D, which indicates that the erasure action did not end properly. ST Stored in the status register STR( Figure 2 In the process of erasing, the erasure action ends.

[0213] In step S106 ( Figure 13 In the process, obtain the programming voltage V at the time point when the verification is successful. PGM2 The value is used as the first programming action in the write operation ( Figure 8 Step S202) Initial programming voltage V PGMS Then, enter Figure 14 Step S111.

[0214] Furthermore, erase operations are performed on a block-by-block (BLK) basis, while write operations are performed on a page-by-page (PG) basis. The initial programming voltage V obtained in step S106... PGMS The programming voltage V in all pages PG contained in the memory block BLK that is the object of the erase operation is set to be... PGM1 The initial value.

[0215] In addition, it means Figure 13 The initial programming voltage V obtained in step S106 PGMS The data is transmitted to the controller die CD via the input / output control circuit I / O. The controller die CD will display the initial programming voltage V. PGMS The data is stored in the designated storage section, and the initial programming voltage V during the write operation is measured in units of storage blocks BLK. PGMS Management is performed. Therefore, even if the period between the erase operation and the write operation becomes longer, the initial programming voltage V can be appropriately managed. PGMSFurthermore, in this case, Figure 8 In step S200, the initial programming voltage V, representing the voltage transferred from the controller's bare CD, is set. PGMS The data.

[0216] Furthermore, in the first embodiment, Figure 13 The initial programming voltage V obtained in step S106 PGMS and Figure 8 The initial programming voltage V used in step S202 PGMS Set to the same voltage value. However, Figure 13 The initial programming voltage V obtained in step S106 PGMS and Figure 8 The initial programming voltage V used in step S202 PGMS It can also be set to different voltage values. For example, Figure 8 The initial programming voltage used in step S202 only needs to be the same as... Figure 13 The initial programming voltage V obtained in step S106 PGMS The corresponding voltage can be greater than the initial programming voltage V. PGMS The voltage can also be less than the initial programming voltage V. PGMS The voltage.

[0217] Furthermore, the characteristics (ease of writing) of the memory cells (MCs) contained in a single memory block (BLK) vary depending on their position in the Z-direction. For example, like... Figure 5 and Figure 6 As shown, semiconductor pillars 120 and gate insulating film 130 are formed inside a memory hole that extends along the Z direction and has a generally cylindrical shape. Here, the diameter of the memory hole is generally smaller on the side near the source line SL (conductive layer 112) (-Z direction side) than on the side near the bit line BL (+Z direction side). Furthermore, the smaller the diameter of the memory hole, the stronger the electric field. Therefore, the smaller the diameter of the memory hole, the easier it is for electrons to be injected (written) into the charge storage film 132.

[0218] Initial programming voltage V PGMS ( Figure 9 , Figure 10 This characteristic (ease of writing) can also be considered and corrected accordingly. For example, [the following can be done] Figure 13 The memory cell MC selected in steps S103 and S104 is called the reference memory cell MC. For example, when a write operation is performed on a memory cell MC located at a position where the diameter of the memory hole is smaller than that of the reference memory cell MC, the initial programming voltage V PGMS It can also be less than the initial programming voltage V obtained in step S106. PGMSSimilarly, when a write operation is performed on a memory cell MC whose diameter is larger than that of the reference memory cell MC, the initial programming voltage V... PGMS It can also be greater than the initial programming voltage V obtained in step S106. PGMS .

[0219] [Normal erasure action]

[0220] Figure 23 It is a timing diagram used to illustrate the normal erasure operation. Figure 24 It is a schematic cross-sectional view used to illustrate the erase voltage supply operation included in the normal erase operation. Figure 25 It is a schematic cross-sectional view used to illustrate the erasure verification action included in the normal erasure operation.

[0221] A normal erase operation consists of multiple erase cycles. Each erase cycle includes an action that reduces the threshold voltage of the memory cell MC (described below). Figure 14 Steps S112, etc.), and the action of confirming the threshold voltage of the memory cell MC (hereinafter referred to as...) Figure 14 (Step S113, etc.). The erasure cycle in the normal erasure operation of the second embodiment is also the same.

[0222] In step S111 ( Figure 14 In the loop, the number of iterations n E2 Set to 1. Number of loops n E2 This is a variable representing the number of times the erase loop is executed. This action, for example, occurs in... Figure 23 The execution time is t201.

[0223] In step S112 ( Figure 14 In this process, the erase voltage supply operation is performed. The erase voltage supply operation is as follows: a ground voltage V is supplied to the word line WL. SS An erase voltage V is supplied to the source line SL and the bit line BL. ERA This reduces the threshold voltage of the memory cell MC. Figure 23 In the example, the action is performed during the period from time t202 to time t203 and during the period from time t208 to time t209.

[0224] In the process of erasing the voltage supply, for example, like Figure 23 and Figure 24 As shown, an erase voltage V is supplied to the bit line BL and the source line SL. ERA ( Figure 23 The value in the middle is the initial erase voltage V. ERA0 Erasure voltage V ERA For example, a voltage of around 17V to 25V.

[0225] Additionally, in the process of erasing the voltage supply, for example, like Figure 24 As shown, the gate line SGD is supplied with voltage V to the drain side. SG Voltage V SG Less than the erasure voltage V ERA This generates GIDL (Gate-Induced Drain Leakage) in the drain-side select transistor STD, producing electron-hole pairs. Additionally, electrons move to the bit line BL, and holes move to the memory cell MC.

[0226] Additionally, in the process of erasing the voltage supply, for example, like Figure 24 As shown, a voltage V is supplied to the source-side gate lines SGS and SGSb. SG Voltage V SG "Less than the erase voltage V" ERA Therefore, GIDL is also generated in the source-side selective transistors STS and STSb, producing electron-hole pairs. Furthermore, electrons move to the source line SL side, and holes move to the memory cell MC side.

[0227] Additionally, in the process of erasing the voltage supply, for example, like Figure 23 and Figure 24 As shown, a ground voltage V is supplied to the word line WL. SS Therefore, holes in the channels of semiconductor pillar 120 pass through tunnel insulating film 131 ( Figure 6 ) tunneling to the charge storage membrane 132 ( Figure 6 This reduces the threshold voltage of the memory cell (MC).

[0228] In step S113 ( Figure 14 In the process of selecting the word line WL, an erasure verification action is performed. The erasure verification action is as follows: it is used to verify the selection of the word line WL. S Supply erase verification voltage V VFYEr ( Figure 7 It detects the on / off state of the memory cell MC and checks whether the threshold voltage of the memory cell MC has reached the target value. Figure 23 In the example, the action is performed during the period from time t204 to time t207 and during the period from time t210 to time t213.

[0229] In the erase verification action, for example like Figure 25 As shown, a voltage V is supplied to the bit line BL. DD Additionally, a voltage V is supplied to the source line SL. SRC .

[0230] Additionally, in the erase verification process, such as... Figure 25As shown, the gate line SGD is supplied with voltage V to the drain side. SG As described above, an electron channel is formed in the channel region of the drain-side selective transistor STD, thereby transmitting voltage V. DD .

[0231] Additionally, in the erase verification process, such as... Figure 25 As shown, a voltage V is supplied to the source-side gate lines SGS and SGSb. SG As described above, electron channels are formed in the channel regions of the selective transistors STS and STSb on the source side, thereby transmitting voltage V. SRC .

[0232] Additionally, in the erase verification process, such as... Figure 25 As shown, the erase verification voltage V is supplied to the word line WL. VFYEr Erasure verification voltage V VFYEr Less than the readout path voltage V READ ( Figure 7 Therefore, as Figure 25 As shown, the threshold voltage is the erase verification voltage V. VFYEr The following memory cell MC becomes active when the threshold voltage is greater than the erase verification voltage V. VFYEr The memory cell MC is in an off state. The signal is transmitted via the bit line BL through the sense amplifier module SAM (…). Figure 4 ) Detect the on / off status of these storage units (MCs) and obtain data representing the status of the storage unit (MC).

[0233] exist Figure 23 In the example, the sensing amplifier SA senses the bit line BL during the period from time t205 to time t206. Sometimes, the period from time t205 to time t206 is called the sensing time Ts2.

[0234] Data indicating the on / off state of the storage unit MC is verified by the first verification action ( Figure 8 The same method as step S203) is used to transfer data to the latch circuits XDL0 to XDL15 of the cache memory CM. Figure 4 ).

[0235] When the memory cell MC is in the ON state, a "1" is stored in the latch circuit XDL. Conversely, when the memory cell MC is in the OFF state, a "0" is stored in the latch circuit XDL. As described above, the bits containing "1" are sometimes referred to as the bits indicating successful erasure verification, and the bits containing "0" are referred to as the bits indicating failed erasure verification.

[0236] In step S114 ( Figure 14In the process of erasure verification, the result of the erasure verification action is determined. For example, the data obtained through the erasure verification action in step S113 (hereinafter, sometimes referred to as erasure verification data) is sequentially transferred from latch circuits XDL0 to XDL15 to counter CNT. Figure 2 The counter CNT counts the bits that failed to erase verification in the erase verification data (the number of bits of "0" data). The counting of the bits that failed to erase verification is performed at the end of step S113. The bits that failed to erase verification are transmitted to the sequencer SQC.

[0237] The sequencer SQC determines whether the number of bits in the erase verification data that failed is less than the baseline value Cre. If the number of bits in the erase verification data that failed is greater than or equal to the baseline value Cre, the erase verification is deemed to have failed, and the process proceeds to step S115. On the other hand, if the number of bits in the erase verification data that failed is less than the baseline value Cre, the erase verification is deemed to have succeeded, and the process proceeds to step S117.

[0238] In step S115 ( Figure 14 In the loop, determine the number of iterations n. E2 Has the specified number of attempts (N) been reached? E2 If the condition is not met, proceed to step S116. If the condition is met, proceed to step S118.

[0239] In step S116 ( Figure 14 In the loop, the number of iterations n E2 Add 1, and proceed to step S112. Additionally, in step S116, for example, the erase voltage V is... ERA Add the specified offset voltage ΔV ERA Therefore, the voltage V is erased. ERA As the number of loops n E2 The offset voltage ΔV is increased successively. ERA .

[0240] In step S117 ( Figure 14 In the data, the content will be the status data D indicating that the erasure operation has been completed normally. ST Stored in the status register STR( Figure 2 In the process, the erasure operation ends. Additionally, the state data D... ST The status read action is output to the controller's bare CD (CD). Figure 1 ).

[0241] In step S118 ( Figure 14 In the data, the content will be the state data D, which indicates that the erasure action did not end properly. ST Stored in the status register STR( Figure 2 In the process of erasing, the erasure action ends.

[0242] [Effect]

[0243] As the number of write and erase operations increases, the memory cell MC deteriorates, making it easier for electrons to tunnel into the charge storage film 132. In this state, the threshold voltage tends to increase during the first programming operation. Therefore, if the initial value of the programming voltage is not adjusted regardless of the degree of degradation of the memory cell MC, the threshold voltage of the memory cell MC may become excessively high during the first programming operation. Therefore, in this embodiment, a programming voltage control operation is performed to adjust the initial value of the programming voltage based on the degree of degradation of the memory cell MC.

[0244] Furthermore, the programming voltage control operation is also considered to be performed during the write operation, for example. However, in this case, performing the programming voltage control operation takes time, thus increasing the write operation time. In addition, compared with the erase operation, the write operation requires shorter operation time and higher speed. Therefore, in the first embodiment, by performing the programming voltage control operation during the erase operation, the optimal initial programming voltage corresponding to the degradation degree of the memory cell MC is obtained, and the increase in the write operation time is suppressed.

[0245] [Second Implementation]

[0246] In the first embodiment, during the programming voltage control operation of the erase operation, the initial programming voltage V corresponding to the degradation degree of the memory cell MC is acquired. PGMS Using the obtained initial programming voltage V PGMS The first programming operation in the write operation is performed. In the second embodiment, in addition to the configuration of the first embodiment, the parameters used in the normal erase operation (erase parameters) are changed according to the degree of degradation of the storage cell MC.

[0247] Figure 26 This is a flowchart used to explain the erasure operation in the second embodiment.

[0248] In step S120, the erasure parameters used in the normal erasure operation are set. The erasure parameters are, for example, (1) the erasure voltage V. ERA (2) Voltage value (V) ERA Supply time ( Figure 23 (3) Sensing time of sensing amplifier SA (Tep), (3) Sensing time of sensing amplifier SA Figure 23 (Ts2).

[0249] Furthermore, in the normal erasure operation of the second embodiment, the same procedure as in the normal erasure operation of the first embodiment is performed. Figure 14 Steps S111 to S118. Therefore, detailed descriptions of these processes are omitted.

[0250] If the memory cell MC deteriorates, the data stored in the memory cell MC may be difficult to erase. In addition, if the memory cell MC deteriorates, current may be difficult to flow in the bit line BL, etc., thereby reducing the accuracy of the sensing action in the erase verification operation. Therefore, in the second embodiment, the erase parameters of (1) to (3) are adjusted according to the degree of deterioration of the memory cell MC obtained in the programming voltage control operation.

[0251] For example, based on the initial programming voltage V obtained in step S106 PGMS Or the initial programming voltage V has been obtained. PGMS Number of loops n at each time point E1 To change the erase parameters mentioned in (1) to (3). For example, the more severe the degradation of the memory cell MC, the higher the erase voltage V will be. ERA The higher the voltage value, the more severe the degradation of the memory cell MC, the lower the erase voltage V. ERA The longer the supply time Tep, the longer the sensing time Ts2 becomes. Furthermore, the more severe the degradation of the memory cell MC, the longer the sensing time Ts2 becomes. However, the relationship between the degree of degradation of the memory cell MC and the erase parameters (1) to (3) may vary depending on the configuration of the semiconductor memory device. Therefore, the increase or decrease of the erase parameters (1) to (3) corresponding to the degree of degradation of the memory cell MC may be the opposite of the example described.

[0252] Based on this configuration, erase voltage supply and erase verification operations can be performed using erase parameters corresponding to the degradation level of the memory cell MC. As a result, data erasure of the memory cell MC can be performed appropriately during normal erase operations.

[0253] In addition, in step S120, all the erasure parameters of (1) to (3) can be set, or any one or two of the erasure parameters of (1) to (3) can be set.

[0254] [Third Implementation]

[0255] In the third embodiment, in addition to the configurations of the first and second embodiments, the parameters (verification parameters) used in the first verification operation of the write operation are changed according to the degradation degree of the storage cell MC.

[0256] Figure 27 This is a flowchart used to explain the writing operation of the third embodiment.

[0257] In step S220, the verification parameters used in the first verification action of the write operation are set. The verification parameters are, for example, (1) the sensing time of the sensing amplifier SA. Figure 10 The voltage V of bit line BL of Ts1), (2) DD(3) The conditions for successful verification in the first verification action, and (4) The conditions for skipping the verification action for any state in the first verification action.

[0258] Regarding the verification parameters in (4), in order to reduce unnecessary verification actions, a verification skip action is performed for any state (one or more of states A to G). For example, the number of times the verification skip action is skipped is the "condition for the verification skip action for any state" in the verification parameters in (4).

[0259] Furthermore, in the write operation of the third embodiment, the same process as in the write operation of the first embodiment is performed. Figure 8 Steps S200 and S201 to S208 are described below. Therefore, detailed descriptions of these processes are omitted.

[0260] As described above, if the memory cell MC deteriorates, current will have difficulty flowing in the bit line BL and the like. In this case, the accuracy of the sensing action in the first verification operation may sometimes decrease. Therefore, in the third embodiment, the verification parameters (1) to (4) are adjusted according to the degree of deterioration of the memory cell MC obtained in the programming voltage control operation.

[0261] For example, based on the initial programming voltage V obtained in step S106 PGMS Or the initial programming voltage V has been obtained. PGMS Number of loops n at each time point E1 To change the verification parameters mentioned in (1) to (4). For example, the more severe the degradation of the memory cell MC, the longer the sensing time Ts1 becomes. In addition, the more severe the degradation of the memory cell MC, the longer the voltage V supplied to the bit line BL becomes. DD The higher the voltage value, the greater the degradation of the memory cell MC, resulting in a larger first reference value Cr1 in step S204. Furthermore, the greater the degradation of the memory cell MC, the fewer the number of skips required for verification skipping actions in any state. However, the relationship between the degradation degree of the memory cell MC and the verification parameters in (1) to (4) may vary depending on the configuration of the semiconductor memory device. Therefore, the increase or decrease of the verification parameters in (1) to (4) corresponding to the degradation degree of the memory cell MC can also be the opposite of the example described above.

[0262] Based on this configuration, the first verification operation can be performed using verification parameters corresponding to the degradation degree of the storage cell MC. As a result, the data writing verification of the storage cell MC can be appropriately performed in the first verification operation.

[0263] In addition, in step S220, all the verification parameters of (1) to (4) can be set, or any one, two or three of the verification parameters of (1) to (4) can be set.

[0264] [Fourth Implementation]

[0265] In the fourth embodiment, in addition to the configuration of the first to third embodiments, the parameters (programming parameters) used in the first programming operation of the write operation are changed according to the degradation degree of the storage cell MC.

[0266] Figure 28 This is a flowchart used to explain the writing operation of the fourth embodiment. Figure 29 It is a timing diagram used to illustrate the pre-charge operation.

[0267] In step S230, the programming parameters used in the first programming action of the write operation are set. The programming parameters are, for example, (1) the programming voltage V. PGM1 Supply time ( Figure 10 (Tpgm), (2) the time of the pre-charge action ( Figure 29 (3) The voltage supplied to each word line WL during the pre-charge operation (Tpch), (3) Figure 29 V PCH ).

[0268] The pre-charge action is the process of drawing out electrons remaining in the channels of the semiconductor pillar 120. This pre-charge action is a preparatory action performed before the first programming action.

[0269] In the pre-charging action, for example like Figure 29 As shown, during the period from time t301 to time t303, a voltage V is supplied to the drain-side gate line SGD. SG_PROG The voltage V supplied to the word line WL is... PCH Additionally, during the pre-charge operation, a voltage V is supplied to the bit line BL between time t302 and time t304. BLL_PROG The time from time t301 to time t304 is the pre-charge operation time Tpch. By supplying voltage to each wiring in this way, electrons remaining in the channels of semiconductor pillar 120 are drawn out.

[0270] Furthermore, the write operation in the fourth embodiment is performed in the same manner as the write operation in the third embodiment. Figure 27 Steps S200, S220, and S201 to S208 are described. Therefore, detailed descriptions of these processes are omitted.

[0271] As described above, if the memory cell MC deteriorates, data will be easily written during the first programming operation. Furthermore, if the memory cell MC deteriorates, current will have difficulty flowing in the bit line BL, etc. Therefore, in the fourth embodiment, the programming parameters (1) to (3) are adjusted based on the degree of deterioration of the memory cell MC obtained during the programming voltage control operation.

[0272] For example, based on the initial programming voltage V obtained in step S106 PGMS Or the initial programming voltage V has been obtained. PGMS Number of loops n at each time point E1 To change the programming parameters mentioned in (1) to (3). For example, the more severe the degradation of the memory cell MC, the more the programming voltage V will be changed. PGM1 The shorter the supply time Tpgm, the longer the precharge operation time Tpch. Furthermore, the more severe the degradation of the memory cell MC, the longer the precharge operation time Tpch. Additionally, the more severe the degradation of the memory cell MC, the longer the voltage V supplied to each word line WL during the precharge operation. PCH The larger.

[0273] Based on this configuration, the first programming operation can be performed using programming parameters corresponding to the degradation level of the memory cell MC. As a result, data can be appropriately written to the memory cell MC during the first programming operation.

[0274] In addition, in step S230, all programming parameters of (1) to (3) can be set, or any one or two of the programming parameters of (1) to (3) can be set.

[0275] [Other Implementation Methods]

[0276] The semiconductor memory device according to the embodiments has been described above. However, the above description is merely illustrative, and the configuration or method can be appropriately adjusted.

[0277] For example, the following example is shown: when the erase voltage supply operation in embodiments 1 to 4 is performed, an erase voltage V is supplied to both the bit line BL and the source line SL. ERA However, when performing the erase voltage supply operation, the supply of erase voltage V to either the bit line BL or the source line SL can be omitted. ERA .

[0278] Additionally, during the erase operation, only one word line WL is set as the selected word line WL. S The programming voltage control action is used to obtain the initial programming voltage V by using the result of the first programming voltage control action. PGMSHowever, the programming voltage control action can be performed multiple times during the erase operation. In this case, a different word line WL can be set as the selected word line WL each time the programming voltage control action is performed. S Alternatively, the initial programming voltage V can be obtained by using the results of multiple programming voltage control actions. PGMS In this case, for example, multiple initial programming voltages V obtained during multiple programming voltage control actions can also be used. PGMS1 The average value, etc., is used to obtain the initial programming voltage V. PGMS .

[0279] Additionally, the offset voltage ΔV used in the first programming action PGM The offset voltage ΔV used in the second programming action can be a different voltage or the same voltage.

[0280] [other]

[0281] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0282] [Explanation of Symbols]

[0283] MC storage unit

[0284] MCA storage cell array

[0285] PC peripheral circuits (control circuits)

[0286] WL lettering (conductive layer, conductive layer 1 to conductive layer 4)

[0287] BL bit line (first wiring)

[0288] SL source line (first wiring)

[0289] 120 Semiconductor Layer

[0290] 130 Charge storage layer.

Claims

1. A semiconductor memory device comprising: Substrate; Multiple conductive layers are arranged along a first direction intersecting the surface of the substrate; The first semiconductor layer extends along the first direction and faces the plurality of conductive layers; A charge storage layer is disposed between the plurality of conductive layers and the first semiconductor layer; The first wiring is electrically connected to one end of the first semiconductor layer in the first direction; and The control circuit is electrically connected to the plurality of conductive layers and the first wiring. The control circuit is configured to perform write and erase operations. The write operation comprises multiple first write loops. Each of the multiple first write loops contains a first programming action. The first programming action involves supplying a first programming voltage to a first conductive layer, which is one of the plurality of conductive layers, and supplying a first write path voltage, smaller than the first programming voltage, to a second conductive layer, which is also one of the plurality of conductive layers. The first programming voltage increases sequentially with the number of executions of the first write loop, and the first offset voltage increases accordingly. The erasure action includes: Programmable voltage control actions; and The erase voltage supply action involves supplying an erase voltage to the first wiring after the programmable voltage control action is executed. The programmed voltage control action includes multiple second write cycles. Each of the multiple second write loops contains a second programming action. The second programming action involves supplying a second programming voltage to a third conductive layer, which is one of the plurality of conductive layers, and supplying a second write path voltage, smaller than the second programming voltage, to a fourth conductive layer, which is also one of the plurality of conductive layers. The second programming voltage increases sequentially with the number of executions of the second write loop, and the second offset voltage increases accordingly. The magnitude of the first programming voltage is adjusted according to the magnitude of the second programming voltage.

2. The semiconductor memory device according to claim 1, wherein Set the first programming voltage in the first write loop executed first in the write operation to the third programming voltage. When the second programming voltage in the last executed second write loop of the programming voltage control action is set to the fourth programming voltage... The magnitude of the third programming voltage is adjusted according to the magnitude of the fourth programming voltage.

3. The semiconductor memory device according to claim 1, wherein... Each of the multiple first write loops contains a first verification action. The first verification action involves supplying a first verification voltage to the first conductive layer and supplying a first readout path voltage to the second conductive layer that is smaller than the first programming voltage. Each of the multiple second write loops contains a second verification action. The second verification action is to supply a second verification voltage to the third conductive layer and a second readout path voltage to the fourth conductive layer that is smaller than the second programming voltage.

4. The semiconductor memory device according to claim 3, wherein The second verification data obtained through the second verification action includes first data corresponding to the bits that were successfully verified, and second data corresponding to the bits that were verified as unsuccessful. Each of the multiple second write loops includes a second decision action. The second determination action determines whether the quantity of the first data or the second data is within the second benchmark value.

5. The semiconductor memory device according to claim 1, wherein... The programmed voltage control action includes a pre-read action. The pre-read action involves supplying a readout voltage to the third conductive layer and supplying a third readout path voltage, which is smaller than the first programming voltage, to the fourth conductive layer before performing the second programming action.

6. The semiconductor memory device according to claim 4, wherein The programmed voltage control action includes a pre-read action. The pre-read action involves supplying a readout voltage to the third conductive layer and the readout path voltage to the fourth conductive layer before executing the second programming action. The read data obtained through the pre-read action includes third data corresponding to the bit in the ON state and fourth data corresponding to the bit in the OFF state, and The second baseline value changes based on the quantity of the third or fourth data.

7. The semiconductor memory device according to claim 1, wherein At least one of the magnitude of the erase voltage and the supply time of the erase voltage is changed according to the magnitude of the second programming voltage.

8. The semiconductor memory device according to claim 1, wherein The control circuit includes a sensing amplifier electrically connected to the first wiring. The erasure action includes erasing the verification action. The erase verification action is performed after the erase voltage supply action, by supplying an erase verification voltage smaller than the erase voltage to the plurality of conductive layers, and then sensing the voltage of the first wiring by the sensing amplifier. The sensing time of the sensing amplifier varies depending on the magnitude of the second programming voltage.

9. The semiconductor memory device according to claim 1, wherein The write operation includes a first verification operation. The first verification action is performed after the first programming action, by supplying a first voltage to the first wiring, supplying a first verification voltage to the first conductive layer that is smaller than the first write path voltage, and supplying a fourth read path voltage to the second conductive layer that is larger than the first verification voltage. At least one of the magnitude of the first voltage and the condition for skipping the first verification action is changed according to the magnitude of the second programming voltage.

10. The semiconductor memory device according to claim 3, wherein The control circuit includes a sensing amplifier electrically connected to the first wiring. In the first verification operation, the sensing amplifier senses the voltage of the first wiring. The sensing time of the sensing amplifier varies depending on the magnitude of the second programming voltage.

11. The semiconductor memory device according to claim 9, wherein The first verification data obtained through the first verification action includes the fifth data corresponding to the successfully verified bit and the sixth data corresponding to the failed verification bit. The write operation includes a first determination operation. The first determination action determines whether the quantity of the fifth or sixth data is within the first benchmark value, and The first reference value is changed according to the magnitude of the second programming voltage.

12. The semiconductor memory device according to claim 1, wherein In the first programming operation, the supply time of the first programming voltage is changed according to the magnitude of the second programming voltage.

13. The semiconductor memory device according to claim 1, wherein The write operation includes a precharge operation. The pre-charging action involves supplying a pre-charging voltage to the first conductive layer and the second conductive layer before executing the first programming action. At least one of the magnitude of the pre-charge voltage and the supply time of the pre-charge voltage is changed according to the magnitude of the second programming voltage.

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