TOF measurement circuit and method based on column-shared tdc

Abstract

The application discloses a TOF measurement circuit and a measurement method based on column-shared TDC, which comprises a pixel array, a time address detection circuit and a readout circuit; the pixel array detects photons and outputs avalanche signals; the time address detection circuit measures the time of flight of the photons and encodes the row address of the pixels responding to the photons; and the readout circuit sequentially reads out the time of flight data and the address data column by column; the time address detection circuit proposed by the application can avoid the problem of inaccurate measurement results caused by photon event collision to the greatest extent while quantizing the time of flight of the photons; on the other hand, the circuit can directly encode the row address and read out the time of flight data and the row address data of the photons through the readout circuit, without additional column address encoding and control logic circuit, thereby effectively reducing the circuit complexity and saving the chip area; in addition, the application has a simple structure and is easy to realize large-scale pixel array expansion integration.

Description

Technical Field

[0001] This invention relates to the field of single-photon detection imaging technology, specifically to a TOF measurement circuit and method based on column-shared TDC. Background Technology

[0002] Time-of-flight (TOF) detectors based on single-photon avalanche diodes (SPADs) obtain target position information by measuring the flight time of light signals between the detector and the target. They offer advantages such as high detection efficiency, large dynamic range, and fast response speed, and have been widely used in 3D imaging, face recognition, AR / VR, and fluorescence lifetime imaging. TOF detectors typically employ an on-chip time-to-digital converter (TDC) to quantize and read out the photon flight time. Depending on whether the TDC is located within the pixel, the TOF measurement circuit architecture can be divided into two types: pixel-wise TDC and shared TDC.

[0003] In the per-pixel TDC architecture, the presence of a TDC circuit in each SPAD results in a low pixel fill factor and a large array area. Furthermore, in some low-light detection applications, the TDCs in the array continue to operate and quantize a large amount of invalid Time-of-Flight (TOF) information even when the SPADs do not detect photon events. The shared TDC architecture places the TDCs on the periphery of the pixel array and allows for configuration of the number of TDCs based on the actual application environment, thus mitigating some of the shortcomings of the per-pixel architecture. However, since multiple pixels share one or more TDCs, photon event collisions are inevitable, especially for signal photons with very similar timing. Additionally, in the shared TDC architecture, all pixels require row and column address encoding, and the address information must be read along with the TOF information to distinguish spatial locations. Moreover, shared architectures mostly use event-driven readout, resulting in highly complex circuit logic control and data post-processing, which is detrimental to pixel scaling. Summary of the Invention

[0004] The purpose of this section is to outline some aspects of embodiments of the present invention and to briefly describe some preferred embodiments. Simplifications or omissions may be made in this section, as well as in the abstract and title of this application, to avoid obscuring the purpose of these documents; however, such simplifications or omissions should not be construed as limiting the scope of the invention.

[0005] In view of the above-mentioned problems, the present invention is proposed.

[0006] Therefore, the technical problem solved by the present invention is the problem of photon event collision, complex address encoding scheme and complex logic control of readout circuit in the existing shared TDC architecture.

[0007] A first aspect of the present invention provides a TOF measurement circuit based on column-shared TDC, including an n×m pixel array, a time address detection circuit, and a readout circuit;

[0008] The n×m pixel array is composed of m columns of pixels. Each column of pixels corresponds to the time address detection circuit and the readout circuit. The input terminal VHH of the pixel column is connected to an external bias voltage. The output terminals P[1]~P[n] of the pixel column are connected to the input terminals L[1]~L[n] of the time address detection circuit.

[0009] The start signal is connected to the input terminal Start of the time address detection circuit. The time information output terminals TOF[1]~TOF[k] of the time address detection circuit are connected to the input terminals B[1]~B[k] of the readout circuit. The address information output terminals AD[1]~AD[k] of the time address detection circuit are connected to the input terminals C[1]~C[k] of the readout circuit.

[0010] The input terminal sel of the readout circuit is connected to an external segment selection signal. The input terminal IN of the readout circuit is connected to the output terminal OUT of the previous column readout circuit. The input terminal IN of the first column readout circuit is grounded, and the output terminal OUT of the last column readout circuit is a data output port.

[0011] As a preferred embodiment of the TOF measurement circuit based on column-shared TDC described in this invention, wherein: the j-th column of the n×m pixel array contains n pixels P<1,j>~P<n,j> The pixel is composed of a single-photon avalanche diode and an analog front-end circuit;

[0012] The cathodes of all single-photon avalanche diodes in each pixel are connected to the input terminal VHH of the pixel column, and the anodes of the single-photon avalanche diodes are connected to the input terminal of the analog front-end circuit.

[0013] The output terminal of the analog front-end circuit is connected to the output terminals P[1] to P[n] of the pixel column. The analog front-end circuit can perform avalanche quenching on the single-photon avalanche diode that senses photons and generate a narrow-pulse avalanche signal, which is then sent to the time address detection circuit for subsequent processing.

[0014] As a preferred embodiment of the TOF measurement circuit based on column-shared TDC described in this invention, the time address detection circuit comprises an anti-collision address encoding circuit, timing generation logic, and GRO_TDC. <1> ~GRO_TDC <k>composition;

[0015] The input terminals I1~In of the anti-collision address encoding circuit are connected to the input terminals L[1]~L[n] of the time address detection circuit, the output terminal Stop of the anti-collision address encoding circuit is connected to the input terminal A of the timing generation logic, and the output terminals H1~Hk of the anti-collision address encoding circuit are connected to the address information output terminals AD[1]~AD[k] of the time address detection circuit.

[0016] The input terminal B of the timing generation logic is connected to the input terminal Start of the time address detection circuit, and the EN1~ENk of the timing generation logic are connected to the GRO_TDC. <1> ~GRO_TDC <k>The input terminal 'in' corresponds to the connection;

[0017] The GRO_TDC <1> ~GRO_TDC <k>The output terminal out is connected to the time information output terminals TOF[1]~TOF[k] of the time address detection circuit. GRO_TDC quantizes the time interval between the rising edges of the Start and Stop signals through the counting clock generated by the internal ring oscillation. The time interval is the photon flight time.

[0018] As a preferred embodiment of the TOF measurement circuit based on column-shared TDC described in this invention, the anti-collision address encoding circuit consists of a judgment circuit, a two-to-one data selector MUX, or a cascaded structure composed of logic gates and address storage and readout logic.

[0019] The cascaded structure has a total of x levels. The first level includes one decision circuit, the second level includes two decision circuits and one 2-to-1 data selector MUX, the third level includes four decision circuits and two 2-to-1 data selector MUX, and so on. The xth level includes n / 2 decision circuits and n / 4 2-to-1 data selector MUX, where n represents the number of pixels.

[0020] In stages 1 to x-1, the input terminals I1 and I2 of each stage's judgment circuit are connected to the output terminals Q of the two adjacent judgment circuits in the next stage. In stage x, the input terminals of the judgment circuit are sequentially connected to the input terminals I1 to In of the anti-collision address encoding circuit. The output terminal Q of the stage 1 judgment circuit is connected to the output terminal Stop of the anti-collision address encoding circuit. The input terminals 0 and 1 of each stage's 2-to-1 data selector MUX are connected to the corresponding address flag output terminals A of the two adjacent judgment circuits in that stage. The output terminal A of the stage 1 judgment circuit outputs address flag A1, and the output terminal of the stage 2 2-to-1 data selector MUX outputs address flag A2. In stages 3 to x, the output terminal of each stage's 2-to-1 data selector MUX is connected to the input terminal of the OR logic gate in that stage, and the address flags A3 to A4 are output through the OR logic gate. x In levels 2 through x, the selection input S of the 2-to-1 data selector MUX in each level is controlled by the address flag bit output from the previous level.

[0021] Address flags A1~A x The parallel input is fed to the address storage and readout logic. The output terminals M1 to Mk of the address storage and readout logic are connected to the output terminals H1 to Hk of the anti-collision address encoding circuit. The address storage and readout logic serially outputs the row address information of the photon pixel.

[0022] As a preferred embodiment of the TOF measurement circuit based on column-shared TDC described in this invention, the judgment circuit includes a first D flip-flop, a second D flip-flop, a first OR gate, a second OR gate, a third OR gate, a fourth OR gate, a delay circuit with dual-ended input and dual-ended output, and an RS flip-flop.

[0023] The input terminals I1 and I2 of the judgment circuit are respectively connected to the input terminals CK of the first D flip-flop and the second D flip-flop. The other input terminal D of the first D flip-flop and the second D flip-flop is simultaneously connected to the high level VDD. The output terminal Q of the first D flip-flop is simultaneously connected to the input terminal A of the second OR gate, the input terminal B of the fourth OR gate, the input terminal S of the RS flip-flop, and the first input terminal of the delay circuit. The output terminal Q of the second D flip-flop is simultaneously connected to the input terminal B of the first OR gate, the input terminal A of the fourth OR gate, the input terminal R of the RS flip-flop, and the second input terminal of the delay circuit. The two output terminals of the delay circuit are respectively connected to the two input terminals A and B of the third OR gate. The output terminal of the third OR gate is simultaneously connected to the input terminal A of the first OR gate and the input terminal B of the second OR gate. The output terminals Y of the first OR gate and the second OR gate are respectively connected to the high-level reset terminals Rst of the first D flip-flop and the second D flip-flop. The output terminal Y of the fourth OR gate is connected to the output terminal Q of the judgment circuit. The output terminal O of the RS flip-flop is connected to the address flag output terminal A of the judgment circuit.

[0024] As a preferred embodiment of the TOF measurement circuit based on column-shared TDC described in this invention, the judgment circuit is used to determine whether two input signals I1 and I2 collide within a time window t. The duration of the time window t is determined by the delay circuit. If the two input signals I1 and I2 collide, only the signal that arrives first is determined to be valid; otherwise, both are determined to be valid.

[0025] The judgment circuit outputs a valid signal I1 or I2 and simultaneously outputs the address flag bit of that signal. The address flag bit of the valid signal I1 is 1, and the address flag bit of the valid signal I2 is 0.

[0026] As a preferred embodiment of the TOF measurement circuit based on column-shared TDC described in this invention, wherein: the timing generation logic is generated by a timing unit. <1> ~Timing Unit <k>It consists of a D flip-flop and a two-input AND gate;

[0027] The timing unit <1> The input terminal I1 is connected to a high level VDD, and the timing unit <1> The output terminal O is connected to the timing unit. <2> The input terminal I1, the timing unit <2> The output terminal O is connected to the timing unit. <3> The input terminal I1, and so on, the timing unit <1> ~Timing Unit <k>The timing unit forms a chain-like structure. <k>The output terminal O of the timing unit is grounded. <1> ~Timing Unit <k>The output terminal EN is sequentially connected to the output terminals EN[1] to EN[k] of the timing generation logic, and the input terminal B of the timing generation logic is simultaneously connected to the timing unit. <1> ~Timing Unit <k>The input terminal I2 and the clock input terminal CK of the D flip-flop are connected, and the input terminal A of the timing generation logic is also connected to the timing unit. <1> ~Timing Unit <k>Input terminal I3;

[0028] The input terminal D of the D flip-flop is connected to a high level VDD, the output terminal Q of the D flip-flop is connected to the input terminal i1 of the two-input AND gate, and the input terminal i2 of the two-input AND gate is connected to the timing unit. <k>The output terminal EN of the two-input AND gate is connected to the timing unit. <1> ~Timing Unit <k>The reset terminal R and the reset terminal Rst of the D flip-flop.

[0029] As a preferred embodiment of the TOF measurement circuit based on column-shared TDC described in this invention, the timing unit consists of a D flip-flop, a first two-input NOR gate, and a second two-input NOR gate.

[0030] The input terminal I1 of the timing unit is connected to the clock input terminal CK of the D flip-flop; the input terminal I2 of the timing unit is connected to the input terminal D of the D flip-flop; the input terminal I3 of the timing unit is connected to the input terminal A of the second two-input NOR gate; the reset terminal R of the timing unit is connected to the reset terminal Rst of the D flip-flop; the output terminal O of the timing unit is simultaneously connected to the output terminal Q of the D flip-flop and the input terminal B of the first two-input NOR gate; and the output terminal EN of the timing unit is simultaneously connected to the output terminal Y of the first two-input NOR gate and the input terminal B of the second two-input NOR gate.

[0031] The input terminal A of the first two-input NOR gate is connected to the output terminal Y of the second two-input NOR gate.

[0032] As a preferred embodiment of the TOF measurement circuit based on column-shared TDC described in this invention, the readout circuit consists of a data selector and a shift register;

[0033] The input terminals T1 to Tk of the data selector are connected to the input terminals B[1] to B[k] of the readout circuit, the input terminals D1 to Dk of the data selector are connected to the input terminals C[1] to C[k] of the readout circuit, the input terminal S of the data selector is connected to the input terminal sel of the readout circuit, and the output terminal O of the data selector is connected to the input terminal I of the shift register.

[0034] The input terminal Data_in of the shift register is connected to the input terminal IN of the readout circuit, and the output terminal Data_out of the shift register is connected to the output terminal OUT of the readout circuit.

[0035] A second aspect of the present invention provides a TOF measurement method based on column-shared TDC, applied to a TOF measurement circuit as described in any embodiment of the present invention, characterized in that the TOF measurement method includes a TOF measurement stage and a readout stage;

[0036] The TOF measurement phase includes the laser emitting a laser at the j-th column pixel under the control of the start signal Start, and simultaneously the output terminals EN1~ENk of the timing generation logic turning high to drive GRO_TDC. <1> ~GRO_TDC <k>Start timing;

[0037] When the first echo photon is detected by the pixel in column j, the operation of the time address detection circuit is carried out in two steps simultaneously. The first step is that the anti-collision address encoding circuit determines the single-photon avalanche diode responding to the echo photon based on the output of the analog front-end circuit in the pixel, and stores the row address data AD[1] of the single-photon avalanche diode. The second step is that the anti-collision address encoding circuit generates a Stop signal to pull down the output terminal EN1 of the timing generation logic and stop GRO_TDC. <1> The time-of-flight data of the echo photon is timed and latched [1];

[0038] When the second echo photon is detected by the pixel in column j, the anti-collision address encoding circuit determines whether it has collided with the first echo photon within the time window t. If a collision occurs, it is ignored. If no collision occurs, the operation of the time address detection circuit is repeated. In the subsequent echo photon detection, the anti-collision address encoding circuit will continue to determine whether the echo photon has collided with the previous echo photon within the time window t. If no collision occurs, the operation of the time address detection circuit is repeated until all GRO_TDCs are responded to. The echo photons detected by the pixel in column j after all GRO_TDCs are responded to are ignored.

[0039] The readout phase includes sequential processing starting from column 1. The flight time data and address data of each column are sent sequentially to the shift register and serially output to the LVDS through the data selector in the order of TOF[1], AD[1], TOF[2], AD[2]...TOF[k], AD[k] under the drive of the external control signal S. When the external control signal S is high, the flight time data is sent; when it is low, the address data is sent. The duration of the high and low levels of the external control signal S is determined by the number of bits of the flight time data and the address data, respectively.

[0040] The beneficial effects of this invention are:

[0041] ① The TOF measurement circuit proposed in this invention adopts a TDC column sharing method. On the one hand, the TDC circuit is placed on the periphery of the pixel array, which can improve the pixel fill factor. On the other hand, the number of TDCs shared by each column of pixels can be configured according to the actual application scenario and the size of the pixel array, which can effectively improve the photon detection efficiency and reduce unnecessary waste of chip area and power consumption.

[0042] ② The anti-collision address encoding circuit proposed in this invention can, on the one hand, prevent the loss of avalanche signals caused by photon event collisions to the greatest extent, and on the other hand, the circuit can directly encode the row address through a two-to-one data selector. The encoding scheme is very simple and reliable.

[0043] ③ The readout circuit proposed in this invention can simultaneously send out row address information and TOF information through a data selector and a shift register without additional control logic circuitry. Furthermore, the column-by-column readout method eliminates the need for column address encoding, further reducing circuit complexity and saving chip area.

[0044] ④ The present invention has a novel structure and is simple to implement. Compared with existing technologies, it is easier to realize ultra-large-scale pixel arrays. Attached Figure Description

[0045] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0046] Figure 1 A schematic diagram of the overall structure of the TOF measurement circuit based on column-shared TDC provided by the present invention;

[0047] Figure 2 A schematic diagram of a single-column circuit structure for a TOF measurement circuit based on column-shared TDC provided by the present invention;

[0048] Figure 3 A schematic diagram of the anti-collision address encoding circuit structure in the time address conversion circuit of the TOF measurement circuit based on column-shared TDC provided by the present invention;

[0049] Figure 4 A schematic diagram of the judgment circuit structure in the anti-collision address encoding circuit of the TOF measurement circuit based on column-shared TDC provided by the present invention;

[0050] Figure 5 A schematic diagram of the timing generation logic structure in the time address conversion circuit of the TOF measurement circuit based on column-shared TDC provided by the present invention;

[0051] Figure 6 Timing diagram of the TOF measurement circuit and method based on column-shared TDC provided by the present invention;

[0052] Figure 7 A schematic diagram of the simulation results of the TOF measurement circuit and measurement method based on column-shared TDC provided by the present invention. Detailed Implementation

[0053] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0054] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0055] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0056] This invention is described in detail with reference to the schematic diagrams. When detailing the embodiments of this invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not be construed as limiting the scope of protection of this invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0057] Furthermore, in the description of this invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used solely for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first," "second," or "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0058] Unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" in this invention should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; similarly, they can refer to mechanical connections, electrical connections, or direct connections, or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0059] Example 1

[0060] Reference Figures 1-6 As one embodiment of the present invention, it includes:

[0061] A first aspect of this invention discloses a Time-of-Flight (TOF) measurement circuit based on column-shared TDC, comprising:

[0062] like Figure 1 As shown, the TOF measurement circuit consists of an n×m pixel array, a time address detection circuit T<1,2...m>, and a readout circuit R<1,2...m>. The measurement circuit is divided into m columns of pixels, and each column of pixels has a corresponding time address detection circuit T. <j>(j = 1, 2, 3…m) and readout circuit R <j>(j = 1, 2, 3…m);

[0063] like Figure 2 As shown, the input terminal VHH of the pixel column is connected to an external bias voltage, and the output terminals P[1]~P[n] of the pixel column are connected to the input terminals L[1]~L[n] of the time address detection circuit. The input terminal Start of the time address detection circuit is connected to an external start signal, and the time information output terminals TOF[1]~TOF[k] of the time address detection circuit are connected to the input terminals B[1]~B[k] of the readout circuit. The address information output terminals AD[1]~AD[k] of the time address detection circuit are connected to the input terminals C[1]~C[k] of the readout circuit. The input terminal sel of the readout circuit is connected to an external segment selection signal, and the input terminal IN of the readout circuit is connected to the output terminal OUT of the previous column readout circuit. The input terminal IN of the first column readout circuit is grounded, and the output terminal OUT of the last column readout circuit is the data output port.

[0064] Specifically, each column of an n×m pixel array contains n pixels P. <1> ~P <n>Each pixel consists of a single-photon avalanche diode (SPAD) and an analog front-end circuit (AFE).

[0065] It should be noted that the cathodes of all single-photon avalanche diodes (SPADs) in each pixel are connected to the input terminal VHH of the pixel column, and the anodes of the single-photon avalanche diodes (SPADs) are connected to the input terminal of the analog front-end circuit (AFE). The output terminal of the analog front-end circuit (AFE) is connected to the output terminals P[1]~P[n] of the pixel column. The analog front-end circuit (AFE) can perform avalanche quenching on the single-photon avalanche diodes (SPADs) that have sensed photons and generate a narrow-pulse avalanche signal, which is then sent to the time address detection circuit for subsequent processing.

[0066] Furthermore, the time address detection circuit consists of an anti-collision address encoding circuit, timing generation logic, and GRO_TDC. <1> ~GRO_TDC <k>composition;

[0067] It should be noted that the input terminals I1 to In of the anti-collision address encoding circuit are connected to the input terminals L[1] to L[n] of the time address detection circuit, the output terminal Stop of the anti-collision address encoding circuit is connected to the input terminal A of the timing generation logic, and the output terminals H1 to Hk of the anti-collision address encoding circuit are connected to the address information output terminals AD[1] to AD[k] of the time address detection circuit; the input terminal B of the timing generation logic is connected to the input terminal Start of the time address detection circuit, and the EN1 to ENk of the timing generation logic are connected to GRO_TDC. <1> ~GRO_TDC <k>The input terminal 'in' corresponds to the connection; GRO_TDC <1> ~GRO_TDC <k>The output terminal out is connected to the time information output terminals TOF[1]~TOF[k] of the time address detection circuit. GRO_TDC quantizes the time interval between the rising edges of the Start and Stop signals through the counting clock generated by the internal ring oscillator. This time interval is the photon flight time.

[0068] Specifically, such as Figure 3 As shown, the anti-collision address encoding circuit consists of a judgment circuit, a two-to-one data selector MUX, a cascaded structure of OR logic gates, and address storage and readout logic.

[0069] It should be noted that the cascaded structure has a total of x stages. Stage 1 includes one decision circuit (decision circuit <1_1>), Stage 2 includes two decision circuits (decision circuits <2_1> and <2_2_1>) and one 2-to-1 data selector (MUX<2_1>), Stage 3 includes four decision circuits (decision circuits <3_1>, <3_2>, <3_3>, and <3_4>) and two 2-to-1 data selectors (MUX<3_1> and <3_2>), and so on, with Stage x including n / 2 decision circuits (decision circuits <1_1> and <2_2_1>).<x_1> 1. Judgment circuit<x_2> …Judgment circuit<x_n / 2> ) and n / 4 two-to-one data selectors (MUX)<x_1> MUX<x_2> …MUX<x_n / 4> ), where n represents the number of pixels;

[0070] In stages 1 through x-1, the inputs I1 and I2 of each stage's decision circuit are connected to the outputs Q of the two adjacent decision circuits in the next stage. In stage x, the inputs of the decision circuit are sequentially connected to the inputs I1 through In of the anti-collision address encoding circuit. The output Q of the stage 1 decision circuit is connected to the output Stop of the anti-collision address encoding circuit. The inputs 0 and 1 of each stage's 2-to-1 data selector MUX are connected to the corresponding address flag outputs A of the two adjacent decision circuits in that stage. The output A of the stage 1 decision circuit outputs address flag A1, and the output of the stage 2 2-to-1 data selector MUX outputs address flag A2. In stages 3 through x, the output of each stage's 2-to-1 data selector MUX is connected to the input of the OR logic gate in that stage, outputting address flags A3 through A4. x In levels 2 through x, the selection input S of the 2-to-1 data selector MUX in each level is controlled by the address flags output from the previous level; address flags A1 to A... x The parallel inputs are fed to the address storage and readout logic. The outputs M1 to Mk of the address storage and readout logic are connected to the corresponding outputs H1 to Hk of the anti-collision address encoding circuit. The address storage and readout logic will respond with the row address information (A1, A2, ... A1) of the photon pixel. x Serial output.

[0071] Specifically, such as Figure 4 As shown, the judgment circuit includes a first D flip-flop (DFF_1), a second D flip-flop (DFF_2), a first OR gate (OR_1), a second OR gate (OR_2), a third OR gate (OR_3), a fourth OR gate (OR_4), a delay circuit with two-terminal input and two-terminal output (Delay), and an RS flip-flop (Latch).

[0072] It should be noted that the input terminals I1 and I2 of the judgment circuit are connected to the input terminals CK of the first D flip-flop (DFF_1) and the second D flip-flop (DFF_2), respectively. The other input terminal D of the first D flip-flop (DFF_1) and the second D flip-flop (DFF_2) is simultaneously connected to the high level VDD. The output terminal Q of the first D flip-flop (DFF_1) is simultaneously connected to the input terminal A of the second OR gate (OR_2), the input terminal B of the fourth OR gate (OR_4), the input terminal S of the RS flip-flop (Latch), and the first input terminal of the delay circuit (Delay). The output terminal Q of the second D flip-flop (DFF_2) is simultaneously connected to the input terminal B of the first OR gate (OR_1), the input terminal A of the fourth OR gate (OR_2), and the RS flip-flop. The input terminal R of the Latch is connected to the second input terminal of the delay circuit. The two output terminals of the delay circuit are connected to the two input terminals A and B of the third OR gate (OR_3), respectively. The output terminal of the third OR gate (OR_3) is connected to the input terminal A of the first OR gate (OR_1) and the input terminal B of the second OR gate (OR_2). The output terminal Y of the first OR gate (OR_1) and the second OR gate (OR_2) are connected to the high-level reset terminal Rst of the first D flip-flop (DFF_1) and the second D flip-flop (DFF_2), respectively. The output terminal Y of the fourth OR gate (OR_4) is connected to the output terminal Q of the judgment circuit. The output terminal O of the RS flip-flop (Latch) is connected to the address flag output terminal A of the judgment circuit.

[0073] It should be noted that the judgment circuit is used to determine whether two input signals I1 and I2 collide within a time window t. The duration of the time window t is determined by the delay circuit. If the two input signals I1 and I2 collide, only the signal that arrives first is considered valid; otherwise, both are considered valid. The judgment circuit outputs a valid signal I1 or I2 and simultaneously outputs the address flag of that signal. The address flag of the valid signal I1 is 1, and the address flag of the valid signal I2 is 0.

[0074] Specifically, such as Figure 5 As shown, the timing generation logic is generated by the timing unit. <1> ~Timing Unit <k>It consists of a D flip-flop (DFF) and a two-input AND gate;

[0075] It should be noted that the timing unit <1> The input terminal I1 is connected to a high level VDD, and its output terminal O is connected to the timing unit. <2> Input terminal I1, timing unit <2> The output terminal O is connected to the timing unit. <3> The input terminal I1, and so on, the timing unit <1> ~Timing Unit <k>Forming a chain-like structure, timing unit <k>The output terminal O is grounded, and the timing unit... <1> ~Timing Unit <k>The output terminal EN is connected in sequence to the output terminals EN[1]~EN[k] of the timing generation logic, and the input terminal B of the timing generation logic is simultaneously connected to the timing unit. <1> ~Timing Unit <k>The input terminal I2 and the clock input terminal CK of the D flip-flop (DFF), and the input terminal A of the timing generation logic are also connected to the timing unit. <1> ~Timing Unit <k>The input terminal I3 of the D flip-flop (DFF) is connected to a high level VDD, and its output terminal Q is connected to the input terminal i1 of the two-input AND gate. The input terminal i2 of the two-input AND gate is connected to the timing unit. <k>The output terminal EN is connected to the timing unit, and its output terminal Y is also connected to the timing unit. <1> ~Timing Unit <k>The reset terminal R and the reset terminal Rst of the D flip-flop (DFF).

[0076] Specifically, the timing unit consists of a D flip-flop (DFF), a first two-input NOR gate (NOR_1), and a second two-input NOR gate (NOR_2);

[0077] It should be noted that the input terminal I1 of the timing unit is connected to the clock input terminal CK of the D flip-flop (DFF), its input terminal I2 is connected to the input terminal D of the D flip-flop (DFF), its input terminal I3 is connected to the input terminal A of the second two-input NOR_2 gate, its reset terminal R is connected to the reset terminal Rst of the D flip-flop (DFF), its output terminal O is connected to both the output terminal Q of the D flip-flop (DFF) and the input terminal B of the first two-input NOR_1 gate, and its output terminal EN is connected to both the output terminal Y of the first two-input NOR_1 gate and the input terminal B of the second two-input NOR_2 gate; the input terminal A of the first two-input NOR_1 gate is connected to the output terminal Y of the second two-input NOR_2 gate.

[0078] Furthermore, the readout circuit consists of a data selector and a shift register;

[0079] It should be noted that the input terminals T1 to Tk of the data selector are connected to the input terminals B[1] to B[k] of the readout circuit, the input terminals D1 to Dk of the data selector are connected to the input terminals C[1] to C[k] of the readout circuit, the input terminal S of the data selector is connected to the input terminal sel of the readout circuit, and the output terminal O of the data selector is connected to the input terminal I of the shift register; the input terminal Data_in of the shift register is connected to the input terminal IN of the readout circuit, and the output terminal Data_out of the shift register is connected to the output terminal OUT of the readout circuit.

[0080] A second aspect of the present invention discloses a TOF measurement method based on column-shared TDC, which is applied to a TOF measurement circuit as described in any embodiment of the present invention;

[0081] Specifically, such as Figure 6 As shown, the TOF measurement method includes a TOF measurement phase and a readout phase;

[0082] It should be noted that the TOF measurement phase includes,

[0083] Under the control of the start signal Start, the laser emits a laser at the j-th column pixel, and simultaneously the output terminals EN1~ENk of the timing generation logic turn high to drive GRO_TDC. <1> ~GRO_TDC <k>Start timing;

[0084] When the first echo photon is detected by the j-th column pixel, the timing address detection circuit operates in two steps simultaneously. The first step is that the anti-collision address encoding circuit determines the single-photon avalanche diode (SPAD) responding to the echo photon based on the output of the analog front-end circuit (AFE) in the pixel, and stores the row address data AD[1] of the single-photon avalanche diode (SPAD). The second step is that the anti-collision address encoding circuit generates a Stop signal to pull low the output terminal EN1 of the timing generation logic and stop GRO_TDC. <1> The time-of-flight data of the echo photon is timed and latched [1];

[0085] When the second echo photon is detected by the pixel in column j, the anti-collision address encoding circuit determines whether it has collided with the first echo photon within the time window t. If a collision occurs, it is ignored. If no collision occurs, the operation of the time address detection circuit is repeated. In the subsequent echo photon detection, the anti-collision address encoding circuit will continue to determine whether the echo photon has collided with the previous echo photon within the time window t. If no collision occurs, the operation of the time address detection circuit is repeated until all GRO_TDCs are responded to. The echo photons detected by the pixel in column j after all GRO_TDCs are responded to are ignored.

[0086] It should be noted that the readout phase includes,

[0087] Starting from column 1, the flight time data and address data of each column are sent sequentially to the shift register and serially output to the LVDS through the data selector in the order of TOF[1], AD[1], TOF[2], AD[2]...TOF[k], AD[k] under the drive of the external control signal S. When the external control signal S is high, the flight time data is sent; when it is low, the address data is sent. The duration of the high and low levels of the external control signal S is determined by the number of bits of the flight time data and the address data, respectively.

[0088] It should be noted that: ① The TOF measurement circuit proposed in this invention adopts a TDC column-sharing method. On the one hand, the TDC circuit is placed on the periphery of the pixel array, which can improve the pixel fill factor. On the other hand, the number of TDCs shared by each column of pixels can be configured according to the actual application scenario and the size of the pixel array, which can effectively improve photon detection efficiency and reduce unnecessary waste of chip area and power consumption. ② The anti-collision address encoding circuit proposed in this invention can prevent the loss of avalanche signals caused by photon collisions to the greatest extent. On the other hand, the circuit can directly encode the row address through a two-to-one data selector. The encoding scheme is very simple and reliable. ③ The readout circuit proposed in this invention can send out the row address information and TOF information simultaneously through a data selector and a shift register without additional control logic circuits. Moreover, the column-by-column readout method does not require column address encoding, further reducing circuit complexity and saving chip area. ④ This invention has a novel structure and is simple to implement. Compared with existing technologies, it is easier to realize ultra-large-scale pixel arrays.

[0089] Example 2

[0090] Reference Figure 7 This is the second embodiment of the present invention. Unlike the first embodiment, this embodiment provides a verification test of the TOF measurement circuit and measurement method based on column-shared TDC, in order to verify and explain the technical solution used in this method.

[0091] This embodiment simulates the TOF measurement circuit based on the standard 0.18μm CMOS process. The specific simulation parameters are as follows: Taking a column of four pixels sharing two GRO_TDCs as an example, the four photon analog signals are set sequentially at 22.6ns, 24.6ns, 50.6ns and 71ns from the rising edge of the Start signal and sent to SPAD2, SPAD1, SPAD0 and SPAD3 respectively. The time window generated by the delay circuit is set to 5ns, and the counting clock period generated by the internal ring oscillator of GRO_TDC is 1ns.

[0092] The simulation results are as follows Figure 7 As shown in the figure: the horizontal axis represents the simulation time, and the vertical axis represents the voltage value at the output terminal.

[0093] Depend on Figure 7 It can be seen that after the rising edge of the Start signal arrives, the output terminals EN1 and EN2 of the timing generation logic become high level. At this time, the two GRO_TDCs start timing. When SPAD2 detects the first photon, the output terminal EN1 of the timing generation logic becomes low level, and GRO_TDC1 stops timing to obtain the time-of-flight data TOF[1] and its corresponding address data AD[1]. When SPAD1 detects the second photon, the anti-collision detection circuit recognizes that it has collided with the first photon and ignores it. When SPAD0 detects the third photon, the output terminal EN2 of the timing generation logic becomes low level, and GRO_TDC2 stops timing to obtain the time-of-flight data TOF[2] and its corresponding address data AD[2]. At this time, GRO_TDC is fully loaded. When SPAD3 detects the fourth photon, it is directly ignored. During the readout stage, TOF[1], AD[1], TOF[2], and AD[2] are read out in sequence.

[0094] Therefore, as can be seen from the above simulation, the time address detection circuit proposed in this invention can, on the one hand, avoid the problem of inaccurate measurement results caused by photon collisions while quantifying photon flight time, and on the other hand, the circuit can directly encode the row address and read out the photon flight time data and row address data through the readout circuit, without the need for additional column address encoding and control logic circuits, effectively reducing circuit complexity and saving chip area.

[0095] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.< / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / n> < / j> < / j> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k>

Claims

1. A TOF measurement circuit based on column-shared TDC, characterized in that, Includes an n×m pixel array, a time address detection circuit, and a readout circuit; The n×m pixel array is composed of m columns of pixels. Each column of pixels corresponds to the time address detection circuit and the readout circuit. The input terminal VHH of the pixel column is connected to an external bias voltage. The output terminals P[1]~P[n] of the pixel column are connected to the input terminals L[1]~L[n] of the time address detection circuit. The Start input terminal of the time address detection circuit is connected to an external start signal. The time information output terminals TOF[1]~TOF[k] of the time address detection circuit are connected to the input terminals B[1]~B[k] of the readout circuit. The address information output terminals AD[1]~AD[k] of the time address detection circuit are connected to the input terminals C[1]~C[k] of the readout circuit. The input terminal sel of the readout circuit is connected to an external segment selection signal. The input terminal IN of the readout circuit is connected to the output terminal OUT of the previous column readout circuit. The input terminal IN of the first column readout circuit is grounded. The output terminal OUT of the last column readout circuit is a data output port. The time address detection circuit consists of an anti-collision address encoding circuit, timing generation logic, and GRO_TDC. <1> ~GRO_TDC <k> composition;< / k> The anti-collision address encoding circuit consists of a judgment circuit, a two-to-one data selector MUX, or a cascaded structure composed of logic gates, as well as address storage and readout logic. The judgment circuit includes a first D flip-flop, a second D flip-flop, a first OR gate, a second OR gate, a third OR gate, a fourth OR gate, a delay circuit with two-terminal input and two-terminal output, and an RS flip-flop. The judgment circuit is used to determine whether two input signals I1 and I2 collide within a time window t. The duration of the time window t is determined by the delay circuit. If the two input signals I1 and I2 collide, only the signal that arrives first is considered valid; otherwise, both are considered valid.

2. The TOF measurement circuit based on column-shared TDC as described in claim 1, characterized in that: The j-th column of the n×m pixel array contains n pixels P<1,j>~Pj.<n,j> The pixel is composed of a single-photon avalanche diode and an analog front-end circuit; The cathodes of all single-photon avalanche diodes in each pixel are connected to the input terminal VHH of the pixel column, and the anodes of the single-photon avalanche diodes are connected to the input terminal of the analog front-end circuit. The output terminal of the analog front-end circuit is connected to the output terminals P[1]~P[n] of the pixel column. The analog front-end circuit can perform avalanche quenching on the single-photon avalanche diode that senses photons and generate a narrow-pulse avalanche signal, which is then sent to the time address detection circuit for subsequent processing.

3. The TOF measurement circuit based on column-shared TDC as described in claim 1, characterized in that: The time address detection circuit consists of an anti-collision address encoding circuit, timing generation logic, and GRO_TDC. <1> ~GRO_TDC <k> composition;< / k> The input terminals I1~In of the anti-collision address encoding circuit are connected to the input terminals L[1]~L[n] of the time address detection circuit, the output terminal Stop of the anti-collision address encoding circuit is connected to the input terminal A of the timing generation logic, and the output terminals H1~Hk of the anti-collision address encoding circuit are connected to the address information output terminals AD[1]~AD[k] of the time address detection circuit. The input terminal B of the timing generation logic is connected to the input terminal Start of the time address detection circuit, and the EN1~ENk of the timing generation logic are connected to the GRO_TDC. <1> ~GRO_TDC <k> The input terminal 'in' corresponds to the connection;< / k> The GRO_TDC <1> ~GRO_TDC <k>The output terminal out is connected to the time information output terminals TOF[1]~TOF[k] of the time address detection circuit. GRO_TDC quantizes the time interval between the rising edges of the Start and Stop signals through the counting clock generated by the internal ring oscillation. The time interval is the photon flight time.< / k> 4. The TOF measurement circuit based on column-shared TDC as described in claim 3, characterized in that: The anti-collision address encoding circuit consists of a judgment circuit, a two-to-one data selector MUX, or a cascaded structure composed of logic gates, as well as address storage and readout logic. The cascaded structure has a total of x levels. The first level includes one decision circuit, the second level includes two decision circuits and one 2-to-1 data selector MUX, the third level includes four decision circuits and two 2-to-1 data selector MUX, and so on. The xth level includes n / 2 decision circuits and n / 4 2-to-1 data selector MUX, where n represents the number of pixels. In stages 1 to x-1, the input terminals I1 and I2 of each stage's judgment circuit are connected to the output terminals Q of the two adjacent judgment circuits in the next stage. In stage x, the input terminals of the judgment circuit are sequentially connected to the input terminals I1 to In of the anti-collision address encoding circuit. The output terminal Q of the stage 1 judgment circuit is connected to the output terminal Stop of the anti-collision address encoding circuit. The input terminals 0 and 1 of each stage's 2-to-1 data selector MUX are connected to the corresponding address flag output terminals A of the two adjacent judgment circuits in that stage. The output terminal A of the stage 1 judgment circuit outputs the address flag A1, and the output terminal of the stage 2 2-to-1 data selector MUX outputs the address flag A2. In stages 3 to x, the output terminal of each stage's 2-to-1 data selector MUX is connected to the input terminal of the OR logic gate in that stage, and the address flags A3 to A4 are output through the OR logic gate. x In levels 2 through x, the selection input S of the 2-to-1 data selector MUX in each level is controlled by the address flag bit output from the previous level. Address flags A1~A x The parallel input is fed to the address storage and readout logic. The output terminals M1~Mk of the address storage and readout logic are connected to the output terminals H1~Hk of the anti-collision address encoding circuit. The address storage and readout logic serially outputs the row address information of the photon pixel.

5. The TOF measurement circuit based on column-shared TDC as described in claim 4, characterized in that: The judgment circuit includes a first D flip-flop, a second D flip-flop, a first OR gate, a second OR gate, a third OR gate, a fourth OR gate, a delay circuit with two-terminal input and two-terminal output, and an RS flip-flop. The input terminals I1 and I2 of the judgment circuit are respectively connected to the input terminals CK of the first D flip-flop and the second D flip-flop. The other input terminal D of the first D flip-flop and the second D flip-flop is simultaneously connected to the high level VDD. The output terminal Q of the first D flip-flop is simultaneously connected to the input terminal A of the second OR gate, the input terminal B of the fourth OR gate, the input terminal S of the RS flip-flop, and the first input terminal of the delay circuit. The output terminal Q of the second D flip-flop is simultaneously connected to the input terminal B of the first OR gate, the input terminal A of the fourth OR gate, the input terminal R of the RS flip-flop, and the second input terminal of the delay circuit. The two output terminals of the delay circuit are respectively connected to the two input terminals A and B of the third OR gate. The output terminal of the third OR gate is simultaneously connected to the input terminal A of the first OR gate and the input terminal B of the second OR gate. The output terminals Y of the first OR gate and the second OR gate are respectively connected to the high-level reset terminals Rst of the first D flip-flop and the second D flip-flop. The output terminal Y of the fourth OR gate is connected to the output terminal Q of the judgment circuit. The output terminal O of the RS flip-flop is connected to the address flag output terminal A of the judgment circuit.

6. The TOF measurement circuit based on column-shared TDC as described in claim 5, characterized in that: The judgment circuit is used to determine whether two input signals I1 and I2 collide within a time window t. The duration of the time window t is determined by the delay circuit. If the two input signals I1 and I2 collide, only the signal that arrives first is considered valid; otherwise, both are considered valid. The judgment circuit outputs a valid signal I1 or I2 and simultaneously outputs the address flag bit of that signal. The address flag bit of the valid signal I1 is 1, and the address flag bit of the valid signal I2 is 0.

7. The TOF measurement circuit based on column-shared TDC as described in claim 3, characterized in that: The timing generation logic is generated by a timing unit. <1> ~Timing Unit <k> It consists of a D flip-flop and a two-input AND gate;< / k> The timing unit <1> The input terminal I1 is connected to a high level VDD, and the timing unit <1> The output terminal O is connected to the timing unit. <2> The input terminal I1, the timing unit <2> The output terminal O is connected to the timing unit. <3> The input terminal I1, and so on, the timing unit <1> ~Timing Unit <k>The timing unit forms a chain-like structure. <k>The output terminal O of the timing unit is grounded. <1> ~Timing Unit <k>The output terminal EN is sequentially connected to the output terminals EN[1]~EN[k] of the timing generation logic, and the input terminal B of the timing generation logic is simultaneously connected to the timing unit. <1> ~Timing Unit <k>The input terminal I2 and the clock input terminal CK of the D flip-flop are connected, and the input terminal A of the timing generation logic is also connected to the timing unit. <1> ~Timing Unit <k> Input terminal I3;< / k> < / k> < / k> < / k> < / k> The input terminal D of the D flip-flop is connected to a high level VDD, the output terminal Q of the D flip-flop is connected to the input terminal i1 of the two-input AND gate, and the input terminal i2 of the two-input AND gate is connected to the timing unit. <k>The output terminal EN of the two-input AND gate is connected to the timing unit. <1> ~Timing Unit <k> The reset terminal R and the reset terminal Rst of the D flip-flop.< / k> < / k> 8. The TOF measurement circuit based on column-shared TDC as described in claim 7, characterized in that: The timing unit consists of a D flip-flop, a first two-input NOR gate, and a second two-input NOR gate; The input terminal I1 of the timing unit is connected to the clock input terminal CK of the D flip-flop; the input terminal I2 of the timing unit is connected to the input terminal D of the D flip-flop; the input terminal I3 of the timing unit is connected to the input terminal A of the second two-input NOR gate; the reset terminal R of the timing unit is connected to the reset terminal Rst of the D flip-flop; the output terminal O of the timing unit is simultaneously connected to the output terminal Q of the D flip-flop and the input terminal B of the first two-input NOR gate; and the output terminal EN of the timing unit is simultaneously connected to the output terminal Y of the first two-input NOR gate and the input terminal B of the second two-input NOR gate. The input terminal A of the first two-input NOR gate is connected to the output terminal Y of the second two-input NOR gate.

9. The TOF measurement circuit based on column-shared TDC as described in claim 1, characterized in that: The readout circuit consists of a data selector and a shift register; The input terminals T1~Tk of the data selector are connected to the input terminals B[1]~B[k] of the readout circuit, the input terminals D1~Dk of the data selector are connected to the input terminals C[1]~C[k] of the readout circuit, the input terminal S of the data selector is connected to the input terminal sel of the readout circuit, and the output terminal O of the data selector is connected to the input terminal I of the shift register. The input terminal Data_in of the shift register is connected to the input terminal IN of the readout circuit, and the output terminal Data_out of the shift register is connected to the output terminal OUT of the readout circuit.

10. A TOF measurement method based on column-shared TDC, applied to the TOF measurement circuit as described in any one of claims 1 to 9, characterized in that, The TOF measurement method includes a TOF measurement phase and a readout phase; The TOF measurement phase includes the laser emitting a laser at the j-th column pixel under the control of the start signal Start, while the output terminals EN1~ENk of the timing generation logic turn high to drive GRO_TDC. <1> ~GRO_TDC <k> Start timing;< / k> When the first echo photon is detected by the pixel in column j, the operation of the time address detection circuit is carried out in two steps simultaneously. The first step is that the anti-collision address encoding circuit determines the single-photon avalanche diode responding to the echo photon based on the output of the analog front-end circuit in the pixel, and stores the row address data AD[1] of the single-photon avalanche diode. The second step is that the anti-collision address encoding circuit generates a Stop signal to pull down the output terminal EN1 of the timing generation logic and stop GRO_TDC. <1> The time-of-flight data of the echo photon is timed and latched [1]; When the second echo photon is detected by the pixel in column j, the anti-collision address encoding circuit determines whether it has collided with the first echo photon within the time window t. If a collision occurs, it is ignored. If no collision occurs, the operation of the time address detection circuit is repeated. In the subsequent echo photon detection, the anti-collision address encoding circuit will continue to determine whether the echo photon has collided with the previous echo photon within the time window t. If no collision occurs, the operation of the time address detection circuit is repeated until all GRO_TDCs are responded to. The echo photons detected by the pixel in column j after all GRO_TDCs are responded to are ignored. The readout stage includes sequential processing starting from column 1. The time-of-flight data and address data of each column are sent sequentially to the shift register of the readout circuit and serially output to the LVDS under the drive of the external control signal S in the order of TOF[1], AD[1], TOF[2], AD[2]...TOF[k], AD[k] through the data selector of the readout circuit. When the external control signal S is high, the time-of-flight data is sent; when it is low, the address data is sent. The duration of the high and low levels of the external control signal S is determined by the number of bits of the time-of-flight data and the address data, respectively.

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