Pixel circuit, pixel driving method and display device

Abstract

The application provides a pixel circuit, a pixel driving method and a display device. The pixel circuit comprises a data voltage writing circuit, a driving circuit, a light emitting control circuit, a first control circuit, a first energy storage circuit and a light emitting element; a first end of the first energy storage circuit is electrically connected with a control end of the driving circuit, a second end of the first energy storage circuit is electrically connected with a first end of the driving circuit, and the first energy storage circuit is used for storing electric energy; a second end of the driving circuit is electrically connected with the light emitting element, and the driving circuit is used for generating a driving current for driving the light emitting element under the control of the potential of the control end thereof; the width of the channel of the transistor included in the light emitting control circuit is greater than the width of the channel of other transistors except the transistor included in the pixel circuit and the transistor included in the driving circuit. The pixel circuit can perform threshold voltage self-compensation, and better brightness uniformity can be achieved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel circuit, a pixel driving method, and a display device. Background Technology

[0002] OLED (Organic Light Emitting Diode) displays are currently a hot topic in flat panel display research, and pixel circuit design is a core technology of OLED displays. However, there is currently no readily available, simple, current-type pixel circuit capable of threshold voltage self-compensation for use in OLED displays. Summary of the Invention

[0003] The main objective of this invention is to provide a pixel circuit, a pixel driving method, and a display device, thereby solving the problem that the prior art cannot provide a current-type pixel circuit with a simple structure capable of threshold voltage self-compensation.

[0004] To achieve the above objectives, embodiments of the present invention provide a pixel circuit, including a data voltage writing circuit, a driving circuit, a light emission control circuit, a first control circuit, a first energy storage circuit, and a light emission element;

[0005] The data voltage writing circuit is electrically connected to the first scanning end, the data line and the data writing end respectively, and is used to control the data line to provide a corresponding voltage signal to the data writing end under the control of the first scanning signal provided by the first scanning end;

[0006] The light-emitting control circuit is electrically connected to the light-emitting control terminal, the first voltage terminal, and the first terminal of the driving circuit, respectively, and is used to control the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0007] The first control circuit is electrically connected to the first control terminal, the second voltage terminal, and the second terminal of the drive circuit, respectively, and is used to control the connection between the second terminal of the drive circuit and the second voltage terminal under the control of the first control signal provided by the first control terminal;

[0008] The first terminal of the first energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the first energy storage circuit is electrically connected to the first terminal of the drive circuit. The first energy storage circuit is used to store electrical energy.

[0009] The second terminal of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of its control terminal.

[0010] The width of the channel of the transistor included in the light-emitting control circuit is greater than the width of the channel of the other transistors included in the pixel circuit besides the transistors included in the driving circuit.

[0011] Optionally, the width of the channel of the transistor included in the light-emitting control circuit is equal to the width of the channel of the transistor included in the driving circuit.

[0012] Optionally, the light-emitting control circuit includes a first transistor;

[0013] The gate of the first transistor is electrically connected to the light-emitting control terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, the second electrode of the first transistor is electrically connected to the first terminal of the driving circuit, and the back gate of the first transistor is electrically connected to the third voltage terminal.

[0014] Optionally, the data writing terminal is electrically connected to the control terminal of the driving circuit.

[0015] Optionally, all transistors included in the pixel circuit are PMOS transistors.

[0016] Optionally, the first control circuit includes a second transistor;

[0017] The gate of the second transistor is electrically connected to the first control terminal, the first terminal of the second transistor is electrically connected to the second voltage terminal, the second terminal of the second transistor is electrically connected to the second terminal of the driving circuit, and the back gate of the second transistor is electrically connected to the third voltage terminal.

[0018] Optionally, the data voltage writing circuit includes a third transistor;

[0019] The gate of the third transistor is electrically connected to the first scan terminal, the first electrode of the third transistor is electrically connected to the data line, the second electrode of the third transistor is electrically connected to the data write terminal, and the back gate of the third transistor is electrically connected to the third voltage terminal.

[0020] Optionally, the first energy storage circuit includes a first capacitor;

[0021] The first terminal of the first capacitor is electrically connected to the control terminal of the driving circuit, and the second terminal of the first capacitor is electrically connected to the first terminal of the driving circuit.

[0022] Optionally, the first energy storage circuit further includes a second capacitor;

[0023] The second capacitor is the capacitance between the second terminal of the transistor included in the light-emitting control circuit and the back gate of the transistor included in the light-emitting control circuit.

[0024] Optionally, the pixel circuit further includes a third capacitor and a fourth capacitor;

[0025] The third capacitor is the capacitance between the second terminal of the transistor included in the first control circuit and the back gate of the transistor included in the first control circuit.

[0026] The fourth capacitor is the capacitance between the second terminal of the transistor included in the data voltage writing circuit and the back gate of the transistor included in the data voltage writing circuit.

[0027] Optionally, the overlap area between the second electrode of the transistor included in the light-emitting control circuit and the back gate of the transistor included in the light-emitting control circuit is greater than the overlap area between the second electrode of the transistor included in the first control circuit and the back gate of the transistor included in the first control circuit.

[0028] The overlap area between the second electrode of the transistor included in the light-emitting control circuit and the back gate of the transistor included in the light-emitting control circuit is greater than the overlap area between the second electrode of the transistor included in the data voltage writing circuit and the back gate of the transistor included in the data voltage writing circuit.

[0029] Optionally, the driving circuit includes a driving transistor;

[0030] The gate of the driving transistor is the control terminal of the driving circuit, the first terminal of the driving transistor is the first terminal of the driving circuit, the second terminal of the driving transistor is the second terminal of the driving circuit, and the back gate of the driving transistor is electrically connected to the third voltage terminal.

[0031] This invention also provides a pixel driving method applied to the aforementioned pixel circuit, the pixel driving method comprising:

[0032] Under the control of the first scan signal, the data voltage writing circuit controls the data line to provide a corresponding voltage signal to the data writing end;

[0033] Under the control of the light emission control signal, the light emission control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit;

[0034] Under the control of the first control signal, the first control circuit controls the connection between the second terminal of the drive circuit and the second voltage terminal;

[0035] The driving circuit generates a driving current to drive the light-emitting element under the control of the potential at its control terminal.

[0036] Optionally, the data writing terminal is electrically connected to the control terminal of the driving circuit, and the display cycle includes an initialization phase, a self-discharge phase, a data writing phase, and a light-emitting phase set sequentially; the pixel driving method includes:

[0037] During the initialization phase, the data line provides a reference voltage Vref. Under the control of the first scan signal, the data voltage writing circuit controls the data line to provide the reference voltage Vref to the control terminal of the driving circuit. Under the control of the light emission control signal, the light emission control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit. Under the control of the first control signal, the first control circuit controls the connection between the second terminal of the driving circuit and the second voltage terminal.

[0038] During the self-discharge phase, the first control circuit, under the control of the first control signal, controls the connection between the second terminal of the driving circuit and the second voltage terminal; the data voltage writing circuit, under the control of the first scan signal, controls the disconnection between the data line and the control terminal of the driving circuit; then, under the control of the light emission control signal, the first voltage terminal is disconnected from the first terminal of the driving circuit.

[0039] At the start of the self-discharge phase, the drive circuit, under the control of the potential at its control terminal, connects the first terminal of the drive circuit with the second terminal of the drive circuit, and discharges through the drive circuit and the first control circuit until the drive circuit disconnects the connection between its first terminal and the second terminal of the drive circuit.

[0040] During the data writing phase, the data line provides a data voltage Vdata. Under the control of the first scan signal, the data voltage writing circuit controls the writing of the data voltage Vdata to the control terminal of the driving circuit. Under the control of the first control signal, the first control circuit controls the connection between the second terminal of the driving circuit and the second voltage terminal.

[0041] During the light-emitting stage, the data voltage writing circuit, under the control of the first scan signal, controls the disconnection between the data line and the control terminal of the driving circuit. Then, under the control of the light-emitting control signal, the light-emitting control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit. Under the control of the first control signal, the first control circuit controls the disconnection between the second terminal of the driving circuit and the second voltage terminal. The driving circuit drives the light-emitting element to emit light.

[0042] This invention also provides a display device including the pixel circuit described above.

[0043] Compared with the prior art, the pixel circuit, pixel driving method, and display device described in the embodiments of the present invention set the width of the channel of the transistor included in the light-emitting control circuit to be greater than the width of the channel of other transistors included in the pixel circuit besides the transistors included in the driving circuit. This makes the capacitance value of the first parasitic capacitance of the transistor included in the light-emitting control circuit greater than the capacitance value of the parasitic capacitance of the other transistors. When the data voltage is written, the voltage is divided by the first parasitic capacitance and the first capacitor included in the first energy storage circuit. By setting the capacitance value of the first parasitic capacitance and the capacitance value of the first capacitor included in the first energy storage circuit, threshold voltage compensation can be achieved. The embodiments of the present invention can provide a current-type pixel circuit with a simple structure that can perform threshold voltage self-compensation. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the gate, channel, and drain of the first transistor in the pixel circuit according to at least one embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of the parasitic capacitances of the first transistor;

[0046] Figure 3 This is a structural diagram of the pixel circuit according to at least one embodiment of the present invention;

[0047] Figure 4 This is a circuit diagram of the pixel circuit according to at least one embodiment of the present invention;

[0048] Figure 5 This is the present invention. Figure 4 The timing diagram of at least one embodiment of the pixel circuit shown;

[0049] Figure 6 This is the present invention. Figure 4 Simulation timing diagram of at least one embodiment of the pixel circuit shown;

[0050] Figure 7 Is Figure 4 A schematic diagram showing the addition of the parasitic capacitance between the back gate and drain of the second transistor P2 and the parasitic capacitance between the back gate and drain of the third transistor P3, based on the existing structure.

[0051] Figure 8 This is a schematic diagram of the gate, channel, and drain of the second transistor P2 in the pixel circuit.

[0052] Figure 9This is a schematic diagram of the gate, channel, and drain of the third transistor P3 in the pixel circuit.

[0053] Figure 10 This is a schematic diagram comparing the channel width W1 of the first transistor P1 and the channel width W2 of the second transistor P2.

[0054] Figure 11 This is a schematic diagram comparing the channel width W1 of the first transistor P1 with the channel width W3 of the third transistor P3. Detailed Implementation

[0055] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two terminals of the transistor (excluding the gate and back gate), one terminal is referred to as the first terminal, and the other as the second terminal. In at least one embodiment of this invention, the first terminal can be the source, and the second terminal can be the drain; alternatively, the first terminal can be the drain, and the second terminal can be the source.

[0057] The pixel circuit described in this embodiment of the invention includes a data voltage writing circuit, a driving circuit, a light emission control circuit, a first control circuit, a first energy storage circuit, and a light emission element;

[0058] The data voltage writing circuit is electrically connected to the first scanning end, the data line and the data writing end respectively, and is used to control the data line to provide a corresponding voltage signal to the data writing end under the control of the first scanning signal provided by the first scanning end;

[0059] The light-emitting control circuit is electrically connected to the light-emitting control terminal, the first voltage terminal, and the first terminal of the driving circuit, respectively, and is used to control the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0060] The first control circuit is electrically connected to the first control terminal, the second voltage terminal, and the second terminal of the drive circuit, respectively, and is used to control the connection between the second terminal of the drive circuit and the second voltage terminal under the control of the first control signal provided by the first control terminal;

[0061] The first terminal of the first energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the first energy storage circuit is electrically connected to the first terminal of the drive circuit. The first energy storage circuit is used to store electrical energy.

[0062] The second terminal of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of its control terminal.

[0063] The width of the channel of the transistor included in the light-emitting control circuit is greater than the width of the channel of the other transistors included in the pixel circuit besides the transistors included in the driving circuit.

[0064] In at least one embodiment of the present invention, the back gate of the transistor included in the light-emitting control circuit can be electrically connected to a third voltage terminal, the first electrode of the transistor included in the light-emitting control circuit can be electrically connected to the first voltage terminal, the second electrode of the transistor included in the light-emitting control circuit can be electrically connected to the first terminal of the driving circuit, and the gate of the transistor included in the light-emitting control circuit can be electrically connected to the light-emitting control terminal.

[0065] In this embodiment of the invention, the width of the channel of the transistor included in the light-emitting control circuit is set to be greater than the width of the channel of the other transistors included in the pixel circuit besides the transistor and the transistor included in the driving circuit, so that the capacitance value of the first parasitic capacitance of the transistor included in the light-emitting control circuit is greater than the capacitance value of the parasitic capacitance of the other transistors.

[0066] The first parasitic capacitance can be the parasitic capacitance between the second electrode of the transistor included in the light-emitting control circuit and the back gate of the transistor included in the light-emitting control circuit.

[0067] In this embodiment of the invention, the width of the channel of the transistor included in the light-emitting control circuit is set to be greater than the width of the channel of the other transistors included in the pixel circuit besides the transistors included in the driving circuit. This makes the capacitance value of the first parasitic capacitance of the transistor included in the light-emitting control circuit greater than the capacitance value of the parasitic capacitance of the other transistors. When data voltage is written, voltage division is performed through the first parasitic capacitance and the first capacitor included in the first energy storage circuit. By setting the capacitance value of the first parasitic capacitance and the capacitance value of the first capacitor included in the first energy storage circuit, threshold voltage compensation can be achieved.

[0068] In at least one embodiment of the present invention, the width of the channel of the transistor included in the light-emitting control circuit is equal to the width of the channel of the transistor included in the driving circuit, in order to facilitate layout, but not limited thereto.

[0069] In actual operation, the width of the channel of the transistor included in the light-emitting control circuit may be equal to or different from the width of the channel of the transistor included in the driving circuit.

[0070] In a specific implementation, the light-emitting control circuit may include a first transistor;

[0071] The gate of the first transistor is electrically connected to the light-emitting control terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, the second electrode of the first transistor is electrically connected to the first terminal of the driving circuit, and the back gate of the first transistor is electrically connected to the third voltage terminal.

[0072] The transistor included in the light-emitting control circuit can be the first transistor.

[0073] In at least one embodiment of the present invention, the first energy storage circuit may include a first capacitor and a second capacitor;

[0074] The first terminal of the first capacitor is electrically connected to the control terminal of the driving circuit, and the second terminal of the first capacitor is electrically connected to the first terminal of the driving circuit.

[0075] The second capacitor can be the capacitance between the second terminal of the first transistor and the back gate of the first transistor, and the second capacitor can be the first parasitic capacitance, but is not limited thereto.

[0076] like Figure 1 As shown, G1 is the gate of P1, D1 is the drain of P1, and CH1 is the channel of P1; the gate G1 of P1 covers the channel CH1 of P1.

[0077] exist Figure 1 In the diagram, W1 represents the width of the channel of P1, L1 represents the length of the channel of P1, L01 represents the length of the second pole of P1 along the first direction, and Xj represents the height of the second pole of P1.

[0078] C2z=Cj×L01×W1+Cjw(2L01+W1);

[0079] Where Cj is the capacitance value per unit area, Cjw is the capacitance value per unit area, and C2z is the capacitance value of the second capacitor; as can be seen from the above formula, the capacitance value C2z of the second capacitor is proportional to the width W1 of the channel of the first transistor. When the width W1 of the channel of the first transistor is large, the capacitance value of the second capacitor is large.

[0080] exist Figure 1In at least one embodiment shown, the first electrode of P1 is the source and the second electrode of P1 is the drain, but this is not a limitation.

[0081] exist Figure 1 In at least one of the embodiments shown, the first direction may be a horizontal direction, but is not limited thereto.

[0082] Figure 2 This is a schematic diagram of the parasitic capacitance of the first transistor. Figure 2 In the diagram, P1 is the first transistor, C2 is the second capacitor, Cgd1 is the parasitic capacitance between the gate and drain of P1, Cgs1 is the parasitic capacitance between the gate and source of P1, Csb1 is the parasitic capacitance between the drain and back gate of P1, and Cgb1 is the parasitic capacitance between the gate and back gate of P1; G1 is the gate of P1, S1 is the source of P1, D1 is the drain of P1, and B1 is the back gate of P1.

[0083] exist Figure 2 In the embodiment shown, the first electrode of P1 is the source, and the second electrode of P1 is the drain.

[0084] The pixel circuit described in this embodiment of the invention is a simple current-type pixel circuit, which can perform threshold voltage self-compensation and achieve good brightness uniformity.

[0085] The pixel circuit described in this embodiment of the invention uses PMOS transistors (P-type metal-oxide-semiconductor transistors) as all transistors, which have a wider anode dynamic range, resist the spot line defects caused by short circuits between the two poles of the light-emitting element, and compensate for the lifespan decay caused by the increased internal resistance of the light-emitting element.

[0086] In at least one embodiment of the present invention, the light-emitting element may be an OLED (organic light-emitting diode), and the pixel circuit described in the embodiments of the present invention may be a current-type pixel circuit applied to silicon-based OLED microdisplays.

[0087] In related technologies, silicon-based OLED microdisplays are widely used in AR (Augmented Reality) and VR (Virtual Reality) fields. With continuous technological development, they demand higher resolution and PPI. The main factors limiting the improvement of PPI in pixel circuits based on CMOS (Complementary Metal-Oxide Semiconductor) technology are the uniformity of circuit output, the width W and length L of the channels of the MOS transistors in the pixel circuit, and the design rules between the MOS transistors in the pixel circuit. Based on this, at least one embodiment of the present invention uses PMOS transistors for the pixel circuit to improve PPI (Pixels Per Inch).

[0088] Optionally, the first voltage terminal V1 can be a power supply voltage terminal, and the second voltage terminal can be a ground terminal or a low voltage terminal, but is not limited thereto.

[0089] Optionally, the light-emitting element may be an organic light-emitting diode, but is not limited thereto.

[0090] In at least one embodiment of the present invention, the data writing terminal may be electrically connected to the control terminal of the driving circuit, but is not limited thereto.

[0091] like Figure 3 As shown, the pixel circuit described in this embodiment of the invention includes a data voltage writing circuit 11, a driving circuit 10, a light emission control circuit 12, a first control circuit 13, a first energy storage circuit 14, and a light emission element EL.

[0092] The data voltage writing circuit 11 is electrically connected to the first scanning terminal WS1, the data line Data, and the data writing terminal N1, respectively, and is used to control the data line Data to provide a corresponding voltage signal to the data writing terminal N1 under the control of the first scanning signal provided by the first scanning terminal WS1.

[0093] The light-emitting control circuit 12 is electrically connected to the light-emitting control terminal EM, the first voltage terminal V1 and the first terminal of the driving circuit 10, respectively, and is used to control the first voltage terminal V1 and the first terminal of the driving circuit 10 to be connected under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0094] The first control circuit 13 is electrically connected to the first control terminal RST, the second voltage terminal V2 and the second terminal of the drive circuit 10, respectively, and is used to control the connection between the second terminal of the drive circuit 10 and the second voltage terminal V2 under the control of the first control signal provided by the first control terminal RST.

[0095] The first end of the first energy storage circuit 14 is electrically connected to the control end of the drive circuit 10, and the second end of the first energy storage circuit 14 is electrically connected to the first end of the drive circuit 10. The first energy storage circuit 14 is used to store electrical energy.

[0096] The second terminal of the driving circuit 10 is electrically connected to the light-emitting element EL. The driving circuit 10 is used to generate a driving current to drive the light-emitting element EL under the control of the potential at its control terminal.

[0097] exist Figure 3 In at least one embodiment of the pixel circuit shown, the data writing terminal N1 is electrically connected to the control terminal of the driving circuit 10.

[0098] The present invention is as follows Figure 3 When at least one embodiment of the pixel circuit shown is in operation, the display cycle may include an initialization phase, a self-discharge phase, a data writing phase, and a light emission phase that are set sequentially.

[0099] During the initialization phase, the first control circuit 13, under the control of the first control signal, controls the second terminal of the driving circuit 10 to connect with the second voltage terminal V2, so as to reset the potential of the second terminal of the driving circuit 10; the data line Data provides a reference voltage Vref, and the data voltage writing circuit 11, under the control of the first scan signal, controls the data line Data to provide a reference voltage Vref to the control terminal of the driving circuit 10; the light emission control circuit 12, under the control of the light emission control signal, controls the first voltage terminal V1 to connect with the first terminal of the driving circuit 10.

[0100] During the initialization phase, the data voltage writing circuit 11 controls the provision of a reference voltage Vref to the control terminal of the drive circuit 10. The purpose of this is to control the potential of the control terminal of the drive circuit 10 so that when the self-discharge phase begins, the drive circuit 10 can control the connection between the first terminal and the second terminal of the drive circuit 10 under the control of the potential of its control terminal.

[0101] During the self-discharge phase, under the control of the first control signal, the first control circuit 13 controls the connection between the second terminal of the driving circuit 10 and the second voltage terminal V2 to reset the potential of the second terminal of the driving circuit 10; under the control of the first scan signal, the data voltage writing circuit 11 controls the disconnection between the data line Data and the control terminal of the driving circuit 10; then, under the control of the light emission control signal, the light emission control circuit 12 controls the disconnection between the first voltage terminal V1 and the first terminal of the driving circuit 10.

[0102] During the self-discharge phase, both the first terminal and the second terminal of the first energy storage circuit 14 are in a floating state, so the difference between the potential of the first terminal and the potential of the second terminal of the first energy storage circuit 14 remains unchanged.

[0103] At the start of the self-discharge phase, under the control of the potential at its control terminal, the drive circuit 10 connects the first terminal and the second terminal of the drive circuit 10, and discharges through the drive circuit 10 and the first control circuit 13 to lower the potential at the first terminal of the drive circuit 10, until the drive circuit 10 disconnects the connection between the first terminal and the second terminal of the drive circuit 10 under the control of the potential at its control terminal.

[0104] During the data writing phase, the data line Data provides a data voltage Vdata. Under the control of the first scan signal, the data voltage writing circuit 11 controls the data line Data to provide the data voltage Vdata to the control terminal of the driving circuit 10. Under the control of the light emission control signal, the light emission control circuit 12 controls the first voltage terminal V1 to disconnect from the first terminal of the driving circuit 10. Under the control of the first control signal, the first control circuit 13 controls the second terminal of the driving circuit 10 to connect with the second voltage terminal V2, so as to reset the potential of the second terminal of the driving circuit 10. The potential of the control terminal of the driving circuit 10 is Vdata.

[0105] During the light-emitting stage, the data voltage writing circuit 11, under the control of the first scan signal, controls the disconnection between the data line Data and the control terminal of the driving circuit 10. Then, under the control of the light-emitting control signal, the light-emitting control circuit 12 controls the connection between the first voltage terminal V1 and the first terminal of the driving circuit 10. Under the control of the first control signal, the first control circuit 13 controls the disconnection between the second terminal of the driving circuit 10 and the second voltage terminal V2. The driving circuit 10 drives the light-emitting element EL to emit light.

[0106] This invention Figure 3 In at least one embodiment of the pixel circuit shown, during operation, in the light-emitting phase, the gate-source voltage of the driving transistor included in the driving circuit 10 is capable of compensating for the threshold voltage of the driving transistor (in the light-emitting phase, the gate-source voltage of the driving transistor is...). Figure 4 (As described in the description of the operation process of at least one embodiment of the pixel circuit shown), the light-emitting current of the light-emitting element is independent of the threshold voltage, thereby improving display uniformity.

[0107] Optionally, the first control circuit includes a second transistor;

[0108] The gate of the second transistor is electrically connected to the first control terminal, the first terminal of the second transistor is electrically connected to the second voltage terminal, the second terminal of the second transistor is electrically connected to the second terminal of the driving circuit, and the back gate of the second transistor is electrically connected to the third voltage terminal.

[0109] Optionally, the data voltage writing circuit includes a third transistor;

[0110] The gate of the third transistor is electrically connected to the first scan terminal, the first electrode of the third transistor is electrically connected to the data line, the second electrode of the third transistor is electrically connected to the data write terminal, and the back gate of the third transistor is electrically connected to the third voltage terminal.

[0111] Optionally, the first energy storage circuit includes a first capacitor;

[0112] The first terminal of the first capacitor is electrically connected to the control terminal of the driving circuit, and the second terminal of the first capacitor is electrically connected to the first terminal of the driving circuit.

[0113] Optionally, the first energy storage circuit further includes a second capacitor;

[0114] The second capacitor is the capacitance between the second terminal of the transistor included in the light-emitting control circuit and the back gate of the transistor included in the light-emitting control circuit.

[0115] Optionally, the reference voltage writing circuit includes a fourth transistor;

[0116] The gate of the fourth transistor is electrically connected to the scanning terminal, the first terminal of the fourth transistor is electrically connected to the reference voltage terminal, the second terminal of the fourth transistor is electrically connected to the control terminal of the driving circuit, and the back gate of the fourth transistor is electrically connected to the third voltage terminal.

[0117] Optionally, the driving circuit includes a driving transistor;

[0118] The gate of the driving transistor is the control terminal of the driving circuit, the first terminal of the driving transistor is the first terminal of the driving circuit, the second terminal of the driving transistor is the second terminal of the driving circuit, and the back gate of the driving transistor is electrically connected to the third voltage terminal.

[0119] In at least one embodiment of the present invention, the third voltage terminal may be a high voltage terminal, but is not limited thereto.

[0120] like Figure 4 As shown, in Figure 3Based on at least one embodiment of the pixel circuit shown, the first control circuit 13 includes a second transistor P2; the driving circuit 10 includes a driving transistor P0; and the light-emitting element is an organic light-emitting diode O1.

[0121] The gate of the second transistor P2 is electrically connected to the first control terminal RST, the source of the second transistor P2 is electrically connected to the ground terminal gnd, and the drain of the second transistor P2 is electrically connected to the drain of the driving transistor P0.

[0122] The data voltage writing circuit 11 includes a third transistor P3;

[0123] The gate of the second transistor P3 is electrically connected to the first scan terminal WS1, the source of the third transistor P3 is electrically connected to the data line Data, and the drain of the third transistor P3 is electrically connected to the gate of the driving transistor P0.

[0124] The first energy storage circuit 14 includes a first capacitor C1 and a second capacitor C2;

[0125] The first terminal of the first capacitor C1 is electrically connected to the gate of the driving transistor P0, and the second terminal of the first capacitor C1 is electrically connected to the source of the driving transistor P0.

[0126] The second capacitor C2 is disposed between the drain of the first transistor P1 and the back gate of the first transistor P1.

[0127] The light-emitting control circuit 12 includes a first transistor P1;

[0128] The gate of the first transistor P1 is electrically connected to the light-emitting control terminal EM, the source of the first transistor P1 is electrically connected to the power supply voltage terminal, and the drain of the first transistor P1 is electrically connected to the source of the driving transistor P0; the power supply voltage terminal is used to provide the power supply voltage ELVDD.

[0129] The drain of the driving transistor P0 is electrically connected to the anode of the organic light-emitting diode O1, and the cathode of the organic light-emitting diode O1 is connected to the common electrode voltage Vcom.

[0130] exist Figure 4 In at least one embodiment of the pixel circuit shown, the gate of P0 is electrically connected to the data writing terminal N1.

[0131] exist Figure 4 In at least one embodiment of the pixel circuit shown, the second capacitor C2 can be a first parasitic capacitor, which can be the parasitic capacitor between the drain of the first transistor P1 and the back gate of the first transistor P1.

[0132] In this invention Figure 4 In at least one embodiment of the pixel circuit shown, all transistors are PMOS transistors (P-type metal-oxide-semiconductor transistors).

[0133] In this invention Figure 4 In at least one embodiment of the pixel circuit shown, the back gates of P1, P2, P0, and P4 are all electrically connected to a high-voltage terminal, which is used to provide a high voltage VDD.

[0134] In at least one embodiment of the present invention, ELVDD may be less than or equal to VDD, but is not limited thereto. For example, VDD may be 6V or 8V.

[0135] exist Figure 4 In at least one embodiment of the pixel circuit shown, the third transistor P3 can transmit the reference voltage Vref to the gate of the driving transistor P0 during the initialization phase, and transmit the data voltage Vdata to the gate of the driving transistor P0 during the data writing phase S3; during the light emission phase S4, RST provides a high voltage signal, P2 is turned off, and P0 is equivalent to a current source controlled by its gate voltage, thereby realizing direct control of the driving current flowing through O1 by the data voltage Vdata. Therefore, the present invention... Figure 4 At least one embodiment of the pixel circuit shown is a current-type pixel circuit.

[0136] This invention Figure 4 At least one embodiment of the pixel circuit shown is a current-mode pixel circuit that uses all PMOS transistors. Compared with a current-mode pixel circuit built with NMOS transistors on the same process platform, it has a wider anode dynamic range for the following reasons:

[0137] For a current-mode pixel circuit built with NMOS transistors, when the voltage of the anode of the organic light-emitting diode O1 is set to a negative voltage, this negative voltage will be connected to the source or drain of the transistor in the pixel circuit. When the transistor is an n-type transistor, there is a forward-biased diode between the back gate and the source of the transistor, which causes a latch-up effect, making the pixel circuit work abnormally. Therefore, the current-mode pixel circuit using PMOS transistors has a wider anode dynamic range. When all the transistors in the current-mode pixel circuit are PMOS transistors, the potential of the anode of the organic light-emitting diode O1 can be a negative voltage.

[0138] The present invention is as follows Figure 4 At least one embodiment of the pixel circuit shown can prevent dot-line defects caused by latch-up, which prevents a short circuit between the anode and cathode of the organic light-emitting diode O1, for the following reasons:

[0139] Due to the present invention as Figure 4 At least one embodiment of the pixel circuit shown is a current-type pixel circuit that uses all PMOS transistors. When a latch-up effect occurs due to a short circuit between the anode and cathode of O1, the dot-line defect will not be caused by latch-up due to the negative voltage of the anode of O1.

[0140] The present invention is as follows Figure 4 At least one embodiment of the pixel circuit shown can prevent the N-type substrate of the third transistor P3, used for transmitting data voltage, from leaking to the drain of the third transistor P3 into the first capacitor C1, thus preventing the occurrence of low grayscale bright spots, for the following reasons:

[0141] The present invention is as follows Figure 4 In at least one embodiment of the pixel circuit shown, the transistors used are all PMOS transistors. Therefore, in the non-light-emitting stage, even if the N-type substrate of the third transistor P3 leaks to the drain of the third transistor P3 to the first capacitor C1, since the driving transistor P0 is also a PMOS transistor, P0 will not drive O1 to emit light, and no bright spot will appear.

[0142] In related technologies, P0 is an NMOS transistor. The higher the gate potential of P0, the brighter the organic light-emitting diode. Therefore, in the non-light-emitting stage, the drain of P3 leaks to the first capacitor C1, which raises the gate potential of P0, causing the organic light-emitting diode to emit light and produce a bright spot. Based on this, at least one embodiment of the present invention sets the transistor as a PMOS transistor to solve the above problem.

[0143] This invention Figure 4 At least one embodiment of the pixel circuit shown is a current-type pixel circuit, which can compensate for the lifespan degradation caused by the increase in the internal resistance of the organic light-emitting diode O1, and, in the present invention Figure 4 In at least one embodiment of the pixel circuit shown, the back gate of each transistor is connected to a high voltage VDD, but not to ELVDD, so that the substrate nwell potential of each transistor is separated from ELVDD, allowing ELVDD to be flexibly configured within a range smaller than VDD.

[0144] The pixel circuit described in at least one embodiment of the present invention can be a current-type pixel circuit applied to silicon-based OLED (organic light-emitting diode) microdisplay chips, but is not limited thereto. At least one embodiment of the present invention is based on a specific semiconductor process platform and uses only PMOS transistors for pixel circuit design, overcoming the space limitations of MOS transistors imposed by design rules in pixel circuits where PMOS and NMOS transistors coexist. This effectively shortens the pixel area and increases PPI (Pixels Per Inch).

[0145] like Figure 5 As shown, the present invention is as follows Figure 4 When at least one embodiment of the pixel circuit shown is in operation, the display cycle may include an initialization phase S1, a self-discharge phase S2, a data writing phase S3, and a light emission phase S4 that are set sequentially.

[0146] During the initialization phase S1, RST, WS1, and EM all provide low voltage signals, and Data provides a reference voltage Vref. At this time, P1, P3, and P2 are all turned on. The source of P0 is connected to the power supply voltage ELVDD, the drain of P0 is connected to ground gnd, and the gate of P0 is connected to the reference voltage Vref, so that P0 can be turned on at the beginning of the self-discharge phase. During the initialization phase S1, the absolute value of the gate-source voltage of P0, |Vgs|, is Vini, and Vini is equal to ELVDD - Vref; where Vini is the initial voltage.

[0147] In the initialization phase S1, ELVDD-Vref is greater than |Vth|, so that P0 can be turned on at the start of the self-discharge phase S2; where Vth is the threshold voltage of P0 without back-gate effect.

[0148] During the self-discharge phase S2, WS1 first provides a high voltage signal, P3 is disconnected first, causing N1 to float. Then, EM provides a high voltage signal, P1 is disconnected again, RST provides a low voltage signal, and P2 is turned on to control the connection between the drain of P0 and ground gnd, thus starting the discharge.

[0149] During the self-discharge stage S2, both the first and second ends of C1 are floating, so the voltage difference across C1 remains unchanged.

[0150] At the start of the self-discharge phase S2, P0 is turned on, and discharge is carried out through P0 and P2 to lower the potential Vs of the source of P0; since N1 is floating, the gate voltage Vg of P0 decreases simultaneously with Vs, and C1 keeps |Vgs| at Vini.

[0151] At the start of the self-discharge stage S2, due to the decrease in Vs, a back-gate effect occurs, and |Vth_ef| equals a×(VDD-Vs)+|Vth|, where Vth_ef is the threshold voltage of P0 with the back-gate effect, and a is the coefficient of the back-gate effect; as Vs decreases, |Vgs| remains at Vini; when |Vth_ef| increases to Vini, P0 is turned off, and the discharge stops; at this time, a×(VDD-Vs)+|Vth|=Vini;

[0152] During the data writing phase S3, WS1 provides a low voltage signal, EM provides a high voltage signal, RST provides a low voltage signal, Data provides a data voltage Vdata, P3 is turned on to write the data voltage Vdata into the gate of P0, P2 is turned on to connect the drain of P0 to ground gnd, and P1 is turned off.

[0153] During the data writing phase S3, the gate potential Vg of P0 is changed from... Let Vdata be the source of P0. Since the source of P0 is floating, ΔVs = (1-b) × ΔVg; where b = C1z / (C1z+C2z), C1z is the capacitance value of C1, and C2z is the capacitance value of C2.

[0154]

[0155]

[0156] The source voltage Vs of P0 becomes

[0157] That is,

[0158] During the light-emitting stage S4, WS1 provides a high voltage signal, P3 is turned on, then EM provides a low voltage signal, P1 is turned on; then RST provides a high voltage signal, P2 is turned off; Vs is pulled up to ELVDD to eliminate the back gate effect, C1 holds |Vgs|, and P0 drives the organic light-emitting diode O1 to emit light.

[0159] In the light-emitting stage S4,

[0160]

[0161] Where K is the current coefficient of P0, and Ioled is the luminous current of O1; from the above equation, it can be seen that when When Ioled equals 1, it is independent of Vth, and Ioled = K × (b × (VDD - Vdata) - b × Vini) 2 .

[0162] As can be seen from the above working process, the present invention Figure 4 In at least one embodiment of the pixel circuit shown, during the light-emitting phase, the gate-source voltage of the driving transistor P0 can compensate for the threshold voltage of the driving transistor P0, so that the light-emitting current of the organic light-emitting diode O1 is independent of the threshold voltage Vth, thereby improving display uniformity.

[0163] Figure 6 This invention is as follows Figure 4The timing simulation diagram of the pixel circuit shown is in... Figure 6 In the diagram, for each voltage signal, the vertical axis is in V (volts), for the current signal, the vertical axis is in nA (nanoamperes), and the horizontal axis represents time.

[0164] exist Figure 6 In the diagram, Vg represents the gate potential of P0, Vs represents the source potential of P0, Va represents the anode potential of O1, and Ioled represents the luminous current of O1.

[0165] In this invention Figure 4 In at least one embodiment of the pixel circuit shown, the width of the channel of P0 may be equal to the width of the channel of P1, but is not limited thereto; in actual operation, the width of the channel of P0 may or may not be equal to the width of the channel of P1, and the width of the channel of P0 and the width of the channel of P1 may be relatively large, and the width of the channel of P0 and the width of the channel of P1 may be greater than the width of the channels of other transistors included in the pixel circuit.

[0166] The pixel circuit described in at least one embodiment of the present invention may further include a third capacitor and a fourth capacitor; the third capacitor is the capacitance between the second terminal of the transistor included in the first control circuit and the back gate of the transistor included in the first control circuit.

[0167] The fourth capacitor is the capacitance between the second terminal of the transistor included in the data voltage writing circuit and the back gate of the transistor included in the data voltage writing circuit.

[0168] In at least one embodiment of the present invention, the overlap area between the second electrode of the transistor included in the light-emitting control circuit and the back gate of the transistor included in the light-emitting control circuit is greater than the overlap area between the second electrode of the transistor included in the first control circuit and the back gate of the transistor included in the first control circuit.

[0169] The overlap area between the second electrode of the transistor included in the light-emitting control circuit and the back gate of the transistor included in the light-emitting control circuit is greater than the overlap area between the second electrode of the transistor included in the data voltage writing circuit and the back gate of the transistor included in the data voltage writing circuit.

[0170] In a specific implementation, the pixel circuit can be disposed on a substrate.

[0171] The overlapping area between the second electrode of the transistor included in the light-emitting control circuit and the back gate of the transistor included in the light-emitting control circuit can refer to the overlapping area between the orthographic projection of the second electrode of the transistor included in the light-emitting control circuit on the substrate and the orthographic projection of the back gate of the transistor included in the light-emitting control circuit on the substrate.

[0172] The overlap area between the second electrode of the transistor included in the first control circuit and the back gate of the transistor included in the first control circuit can refer to the overlap area between the orthographic projection of the second electrode of the transistor included in the first control circuit on the substrate and the orthographic projection of the back gate of the transistor included in the first control circuit on the substrate.

[0173] The overlap area between the second electrode of the transistor included in the data voltage writing circuit and the back gate of the transistor included in the data voltage writing circuit can refer to the overlap area between the orthogonal projection of the second electrode of the transistor included in the data voltage writing circuit on the substrate and the orthogonal projection of the back gate of the transistor included in the data voltage writing circuit on the substrate.

[0174] Optionally, the first control circuit includes a second transistor, and the data voltage writing circuit includes a third transistor; the third capacitor may be the parasitic capacitance between the second terminal of the second transistor and the back gate of the second transistor, and the fourth capacitor may be the parasitic capacitance between the second terminal of the third transistor and the back gate of the third transistor.

[0175] In a specific implementation, the overlap area between the second electrode of the first transistor and the back gate of the first transistor is greater than the overlap area between the second electrode of the second transistor and the back gate of the second transistor.

[0176] The overlap area between the second electrode of the first transistor and the back gate of the first transistor is greater than the overlap area between the second electrode of the three transistors and the back gate of the three transistors.

[0177] In at least one embodiment of the present invention, the pixel circuit may be disposed on a substrate.

[0178] The overlap area between the second electrode of the first transistor and the back gate of the first transistor can refer to the overlap area between the orthographic projection of the second electrode of the first transistor on the substrate and the orthographic projection of the back gate of the first transistor on the substrate.

[0179] The overlapping area between the second electrode of the second transistor and the back gate of the second transistor can refer to the overlapping area between the orthographic projection of the second electrode of the second transistor on the substrate and the orthographic projection of the back gate of the second transistor on the substrate.

[0180] The overlapping area between the second electrode of the third transistor and the back gate of the third transistor can refer to the overlapping area between the orthogonal projection of the second electrode of the third transistor on the substrate and the orthogonal projection of the back gate of the third transistor on the substrate.

[0181] like Figure 7 As shown, C3 is the third capacitor, which can be the parasitic capacitance between the back gate of P2 and the drain of P2. C4 is the fourth capacitor, which can be the parasitic capacitance between the back gate of P3 and the drain of P3.

[0182] The width of the channel of P1 is greater than the width of the channel of P2, the width of the channel of P1 is greater than the width of the channel of P3, the capacitance value of C2 (C2z) can be greater than the capacitance value of C3, and the capacitance value of C2 (C2z) can be greater than the capacitance value of C4.

[0183] Figure 8 This is a schematic diagram of the gate, channel, and drain of P2.

[0184] Figure 9 This is a schematic diagram of the gate, channel, and drain of P3.

[0185] exist Figure 7 , Figure 8 and Figure 9 In the corresponding embodiment, the second electrode is the drain electrode.

[0186] exist Figure 8 In the diagram, D2 is the drain of P2, G2 is the gate of P2, CH2 is the channel of P2, W2 is the width of the channel of P2, and L2 is the length of the channel of P2.

[0187] exist Figure 9 In the diagram, D3 is the drain of P3, G3 is the gate of P3, CH3 is the channel of P3, W3 is the width of the channel of P3, and L3 is the length of the channel of P3.

[0188] Figure 10 This is a comparative diagram showing the width W1 of the channel in P1 and the width W2 of the channel in P2. Figure 11 This is a comparative diagram of the width W1 of the channel in P1 and the width W3 of the channel in P3.

[0189] Depend on Figure 10 It is evident that W2 is less than W1, therefore... Figure 11 It can be seen that W3 is less than W1, the capacitance value of C3 can be less than the capacitance value of C2 (C2z), and the capacitance value of C4 can be less than the capacitance value of C2 (C2z).

[0190] The pixel driving method described in this embodiment of the invention is applied to the pixel circuit described above, and the pixel driving method includes:

[0191] Under the control of the first scan signal, the data voltage writing circuit controls the data line to provide a corresponding voltage signal to the data writing end;

[0192] Under the control of the light emission control signal, the light emission control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit;

[0193] Under the control of the first control signal, the first control circuit controls the connection between the second terminal of the drive circuit and the second voltage terminal;

[0194] The driving circuit generates a driving current to drive the light-emitting element under the control of the potential at its control terminal.

[0195] In at least one embodiment of the present invention, the data writing terminal is electrically connected to the control terminal of the driving circuit, and the display cycle may include an initialization phase, a self-discharge phase, a data writing phase, and a light emission phase set sequentially; the pixel driving method may include:

[0196] During the initialization phase, the data line provides a reference voltage Vref. Under the control of the first scan signal, the data voltage writing circuit controls the data line to provide the reference voltage Vref to the control terminal of the driving circuit. Under the control of the light emission control signal, the light emission control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit. Under the control of the first control signal, the first control circuit controls the connection between the second terminal of the driving circuit and the second voltage terminal.

[0197] During the self-discharge phase, the first control circuit, under the control of the first control signal, controls the connection between the second terminal of the driving circuit and the second voltage terminal; the data voltage writing circuit, under the control of the first scan signal, controls the disconnection between the data line and the control terminal of the driving circuit; then, under the control of the light emission control signal, the first voltage terminal is disconnected from the first terminal of the driving circuit.

[0198] At the start of the self-discharge phase, the drive circuit, under the control of the potential at its control terminal, connects the first terminal of the drive circuit with the second terminal of the drive circuit, and discharges through the drive circuit and the first control circuit until the drive circuit disconnects the connection between its first terminal and the second terminal of the drive circuit.

[0199] During the data writing phase, the data line provides a data voltage Vdata. Under the control of the first scan signal, the data voltage writing circuit controls the writing of the data voltage Vdata to the control terminal of the driving circuit. Under the control of the first control signal, the first control circuit controls the connection between the second terminal of the driving circuit and the second voltage terminal.

[0200] During the light-emitting stage, the data voltage writing circuit, under the control of the first scan signal, controls the disconnection between the data line and the control terminal of the driving circuit. Then, under the control of the light-emitting control signal, the light-emitting control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit. Under the control of the first control signal, the first control circuit controls the disconnection between the second terminal of the driving circuit and the second voltage terminal. The driving circuit drives the light-emitting element to emit light.

[0201] The display device described in this embodiment of the invention includes the pixel circuit described above.

[0202] The display device provided in this embodiment of the invention can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0203] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that, It includes a data voltage writing circuit, a driving circuit, a light-emitting control circuit, a first control circuit, a first energy storage circuit, and a light-emitting element; The data voltage writing circuit is electrically connected to the first scanning end, the data line and the data writing end respectively, and is used to control the data line to provide a corresponding voltage signal to the data writing end under the control of the first scanning signal provided by the first scanning end; The light-emitting control circuit is electrically connected to the light-emitting control terminal, the first voltage terminal, and the first terminal of the driving circuit, respectively, and is used to control the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control terminal. The first control circuit is electrically connected to the first control terminal, the second voltage terminal, and the second terminal of the drive circuit, respectively, and is used to control the connection between the second terminal of the drive circuit and the second voltage terminal under the control of the first control signal provided by the first control terminal; The first terminal of the first energy storage circuit is electrically connected to the control terminal of the drive circuit, and the second terminal of the first energy storage circuit is electrically connected to the first terminal of the drive circuit. The first energy storage circuit is used to store electrical energy. The second terminal of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of its control terminal. The width of the channel of the transistor included in the light-emitting control circuit is greater than the width of the channel of the other transistors included in the pixel circuit besides the transistors included in the driving circuit. The data writing end is electrically connected to the control end of the driving circuit, and the display cycle includes an initialization phase, a self-discharge phase, a data writing phase, and a light emission phase that are set sequentially. During the initialization phase, the data line provides a reference voltage Vref. The data voltage writing circuit is used to control the data line to provide the reference voltage Vref to the control terminal of the driving circuit under the control of the first scan signal during the initialization phase. The light emission control circuit is used to control the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light emission control signal during the initialization phase. The first control circuit is used to control the connection between the second terminal of the driving circuit and the second voltage terminal under the control of the first control signal during the initialization phase. The first control circuit is used to control the connection between the second terminal of the drive circuit and the second voltage terminal under the control of the first control signal during the self-discharge stage. During the self-discharge phase, the data voltage writing circuit, under the control of the first scan signal, controls the disconnection between the data line and the control terminal of the driving circuit. Afterwards, under the control of the light emission control signal, the light emission control circuit controls the disconnection between the first voltage terminal and the first terminal of the driving circuit. At the start of the self-discharge phase, the drive circuit, under the control of the potential at its control terminal, connects the first terminal of the drive circuit with the second terminal of the drive circuit, and discharges through the drive circuit and the first control circuit until the drive circuit disconnects the connection between its first terminal and the second terminal of the drive circuit. During the data writing phase, the data line provides a data voltage Vdata. The data voltage writing circuit is used to control the writing of the data voltage Vdata to the control terminal of the driving circuit under the control of the first scan signal during the data writing phase. The first control circuit is used, during the data writing phase, to control the connection between the second terminal of the drive circuit and the second voltage terminal under the control of the first control signal; During the light emission stage, the data voltage writing circuit, under the control of the first scan signal, controls the disconnection between the data line and the control terminal of the driving circuit. Then, under the control of the light emission control signal, the light emission control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit. Under the control of the first control signal, the first control circuit controls the disconnection between the second terminal of the driving circuit and the second voltage terminal. The driving circuit drives the light-emitting element to emit light.

2. The pixel circuit as described in claim 1, characterized in that, The width of the channel of the transistor included in the light-emitting control circuit is equal to the width of the channel of the transistor included in the driving circuit.

3. The pixel circuit as described in claim 1, characterized in that, The light-emitting control circuit includes a first transistor; The gate of the first transistor is electrically connected to the light-emitting control terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, the second electrode of the first transistor is electrically connected to the first terminal of the driving circuit, and the back gate of the first transistor is electrically connected to the third voltage terminal.

4. The pixel circuit according to any one of claims 1 to 3, characterized in that, All transistors included in the pixel circuit are PMOS transistors.

5. The pixel circuit according to any one of claims 1 to 3, characterized in that, The first control circuit includes a second transistor; The gate of the second transistor is electrically connected to the first control terminal, the first terminal of the second transistor is electrically connected to the second voltage terminal, the second terminal of the second transistor is electrically connected to the second terminal of the driving circuit, and the back gate of the second transistor is electrically connected to the third voltage terminal.

6. The pixel circuit according to any one of claims 1 to 3, characterized in that, The data voltage writing circuit includes a third transistor; The gate of the third transistor is electrically connected to the first scan terminal, the first electrode of the third transistor is electrically connected to the data line, the second electrode of the third transistor is electrically connected to the data write terminal, and the back gate of the third transistor is electrically connected to the third voltage terminal.

7. The pixel circuit according to any one of claims 1 to 3, characterized in that, The first energy storage circuit includes a first capacitor; The first terminal of the first capacitor is electrically connected to the control terminal of the driving circuit, and the second terminal of the first capacitor is electrically connected to the first terminal of the driving circuit.

8. The pixel circuit as described in claim 7, characterized in that, The first energy storage circuit also includes a second capacitor; The second capacitor is the capacitance between the second terminal of the transistor included in the light-emitting control circuit and the back gate of the transistor included in the light-emitting control circuit.

9. The pixel circuit as described in claim 8, characterized in that, The pixel circuit also includes a third capacitor and a fourth capacitor; The third capacitor is the capacitance between the second terminal of the transistor included in the first control circuit and the back gate of the transistor included in the first control circuit. The fourth capacitor is the capacitance between the second terminal of the transistor included in the data voltage writing circuit and the back gate of the transistor included in the data voltage writing circuit.

10. The pixel circuit as described in claim 9, characterized in that, The overlap area between the second electrode of the transistor included in the light-emitting control circuit and the back gate of the transistor included in the light-emitting control circuit is greater than the overlap area between the second electrode of the transistor included in the first control circuit and the back gate of the transistor included in the first control circuit. The overlap area between the second electrode of the transistor included in the light-emitting control circuit and the back gate of the transistor included in the light-emitting control circuit is greater than the overlap area between the second electrode of the transistor included in the data voltage writing circuit and the back gate of the transistor included in the data voltage writing circuit.

11. The pixel circuit according to any one of claims 1 to 3, characterized in that, The driving circuit includes a driving transistor; The gate of the driving transistor is the control terminal of the driving circuit, the first terminal of the driving transistor is the first terminal of the driving circuit, the second terminal of the driving transistor is the second terminal of the driving circuit, and the back gate of the driving transistor is electrically connected to the third voltage terminal.

12. A pixel driving method, applied to a pixel circuit as described in any one of claims 1 to 11, characterized in that, The pixel driving method includes: Under the control of the first scan signal, the data voltage writing circuit controls the data line to provide a corresponding voltage signal to the data writing end; Under the control of the light emission control signal, the light emission control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit; Under the control of the first control signal, the first control circuit controls the connection between the second terminal of the drive circuit and the second voltage terminal; The driving circuit generates a driving current to drive the light-emitting element under the control of the potential at its control terminal; The data writing terminal is electrically connected to the control terminal of the driving circuit, and the display cycle includes an initialization phase, a self-discharge phase, a data writing phase, and a light emission phase set sequentially; the pixel driving method includes: During the initialization phase, the data line provides a reference voltage Vref. Under the control of the first scan signal, the data voltage writing circuit controls the data line to provide the reference voltage Vref to the control terminal of the driving circuit. Under the control of the light emission control signal, the light emission control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit. Under the control of the first control signal, the first control circuit controls the connection between the second terminal of the driving circuit and the second voltage terminal. During the self-discharge phase, the first control circuit, under the control of the first control signal, controls the connection between the second terminal of the driving circuit and the second voltage terminal; the data voltage writing circuit, under the control of the first scan signal, controls the disconnection between the data line and the control terminal of the driving circuit; then, under the control of the light emission control signal, the first voltage terminal is disconnected from the first terminal of the driving circuit. At the start of the self-discharge phase, the drive circuit, under the control of the potential at its control terminal, connects the first terminal of the drive circuit with the second terminal of the drive circuit, and discharges through the drive circuit and the first control circuit until the drive circuit disconnects the connection between its first terminal and the second terminal of the drive circuit. During the data writing phase, the data line provides a data voltage Vdata. Under the control of the first scan signal, the data voltage writing circuit controls the writing of the data voltage Vdata to the control terminal of the driving circuit. Under the control of the first control signal, the first control circuit controls the connection between the second terminal of the driving circuit and the second voltage terminal. During the light-emitting stage, the data voltage writing circuit, under the control of the first scan signal, controls the disconnection between the data line and the control terminal of the driving circuit. Then, under the control of the light-emitting control signal, the light-emitting control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit. Under the control of the first control signal, the first control circuit controls the disconnection between the second terminal of the driving circuit and the second voltage terminal. The driving circuit drives the light-emitting element to emit light.

13. A display device, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 11.

Images