A network card hybrid nucleophilic hardware binding method, device and storage medium

Abstract

This application relates to the field of computer network interface cards (NICs), and discloses a hardware bonding method, apparatus, and storage medium for hybrid NIC-CPU core bonding. The method includes: determining configuration information of a configuration register based on bonding requirements; performing a configuration operation on the configuration register using preset configuration instructions based on the configuration information; and performing a bonding operation between the NIC and a CPU core or between the NIC and a NUMA core based on the configuration register. This approach increases NIC packet forwarding performance while reducing CPU usage, reduces cross-NUMA memory access, simplifies the configuration process, and makes configuration more convenient and faster. It can isolate different NICs, improving NIC forwarding performance; and provides more flexible and convenient configuration, enabling cross-NUMA access and inter-core isolation of the NIC.

Description

Technical Field

[0001] This application relates to the field of computer network interface card (NIC) technology, and in particular to a hardware bonding method, apparatus, storage medium, and electronic device for hybrid NIC bonding. Background Technology

[0002] The purpose of the background description provided herein is to give an overall background to this application. The statements in this section are merely to provide background information relevant to this application and do not necessarily constitute prior art.

[0003] With the development of CPUs, multi-NUMA architectures are increasingly used in CPUs. Taking the Phytium 64C (FT64C) CPU as an example, this CPU contains 64 cores and 8 NUMAs, with each NUMA containing 8 cores (see reference). Figure 1 (Note that the NUMA numbers are not simply arranged in order; this is related to the design architecture of the Phytium processor.)

[0004] During CPU initialization, network interface cards (NICs) are typically bound to all CPU cores. This means that if there are enough NIC queues, each CPU core will be bound to a separate NIC queue. (See reference...) Figure 2 .

[0005] In a multi-NUMA model (using the FT64C processor as an example), when the network interface card (NIC) binds 64 queues to 64 cores, cross-NUMA memory access becomes problematic. Since cross-NUMA memory access is inefficient, it leads to increased packet forwarding latency and poor packet forwarding performance. Please refer to [link / reference needed]. Figure 1 For example:

[0006] When a core on NUMA-0 accesses a message in its own memory, it takes, assuming, only 1ms.

[0007] When a core on NUMA-0 needs to access a packet on NUMA-1, the time required will be longer, possibly up to 1.2ms.

[0008] When a core on NUMA-0 needs to access a packet on NUMA-3, the time required will be longer, possibly up to 1.6ms.

[0009] When a core on NUMA-0 needs to access a packet on NUMA-7, the time required will be longer, possibly up to 1.8ms.

[0010] When a core on NUMA-0 needs to access a packet on NUMA-6, the time required will be longer, possibly up to 3ms. In this case, packet forwarding takes the longest.

[0011] In summary, packet forwarding across NUMAs takes a long time, especially when there are more NUMAs to cross, the longer the packet access time and the lower the packet forwarding efficiency.

[0012] While existing technologies include a solution that limits the total number of NUMAs bound to all queues of a network interface card (NIC), thereby reducing the number of memory accesses across NUMAs, this solution also has the following drawbacks in practical use:

[0013] (1) The operation is complex and requires the configuration of multiple files and data;

[0014] (2) The implementation is relatively rough and it is not easy to achieve precise configuration. The solution can only bind queues according to NUMA and cannot bind them according to cores.

[0015] (3) It is not flexible enough in actual use;

[0016] (4) To meet the different requirements of different customers, it is necessary to modify the code, recompile, and deploy the software and hardware environment. Summary of the Invention

[0017] To address the aforementioned issues, this application proposes a hardware bonding method, apparatus, storage medium, and electronic device for hybrid NIC bonding, which solves the problems of low packet forwarding efficiency and insufficient flexibility in bonding implementation mentioned above.

[0018] The first aspect of this application provides a hardware bonding method for hybrid parent-child network interface cards (NICs), wherein a configuration register is provided in the NIC, and the method includes:

[0019] The configuration information of the configuration register is determined according to the binding requirements;

[0020] Based on the configuration information, a configuration operation is performed on the configuration register using a preset configuration instruction;

[0021] The network interface card (NIC) is bound to the CPU core or the NIC to the NUMA core according to the configuration register.

[0022] Further, the configuration register includes:

[0023] Network card status register, CPU core bound status register, or NUMA bound predefined template register.

[0024] Furthermore, if the configuration register is a network interface card status register,

[0025] The current status of the PORT corresponding to each binary bit is identified by the value of each binary bit in the network card status register.

[0026] Furthermore, in the case where the configuration register is a CPU core bound status register,

[0027] The binding status of the CPU core corresponding to each bit is identified by the value of each bit in the CPU core binding status register.

[0028] Furthermore, if the configuration register is a NUMA-bound predefined template register,

[0029] The NUMA binding status is identified by the value of the predefined template register for NUMA binding.

[0030] Furthermore, the step of identifying the NUMA binding status through the value of the NUMA binding predefined template register includes:

[0031] If the value of the NUMA binding predefined template register is not greater than the first preset threshold, the PORT port of the network card will not be bound to NUMA.

[0032] Furthermore, the step of identifying the NUMA binding status through the value of the NUMA binding predefined template register includes:

[0033] When the value of the NUMA binding predefined template register is within a preset value range, all ports of the network card are bound to one or more NUMAs respectively; wherein, the number of NUMAs is equal to the value of the NUMA binding predefined template register.

[0034] Furthermore, if the configuration register is a NUMA binding predefined template register and the value of the NUMA binding predefined template register is greater than a second preset threshold,

[0035] The NUMA pre-binding strategy is determined based on the value of the NUMA binding predefined template register.

[0036] The binding operation between the network interface card and the NUMA is performed according to the NUMA pre-binding policy.

[0037] A second aspect of this application provides a hardware bonding device for hybrid network interface cards (NICs), the device comprising:

[0038] The determination module is used to determine the configuration information of the configuration register based on the binding requirements;

[0039] The configuration module is used to perform configuration operations on the configuration register according to the configuration information using preset configuration instructions;

[0040] The binding module is used to perform binding operations between the network card and the CPU core or between the network card and NUMA according to the configuration register.

[0041] A third aspect of this application provides a computer-readable storage medium storing a computer program that can be executed by one or more processors to implement the steps of the method described above.

[0042] A fourth aspect of this application provides an electronic device including a memory and one or more processors, wherein a computer program is stored on the memory, and the memory and the one or more processors are communicatively connected to each other, wherein when the computer program is executed by the one or more processors, it implements the steps of the method described above.

[0043] Compared with the prior art, the technical solution of this application has the following advantages or beneficial effects:

[0044] A hardware implementation scheme for hybrid pro-core network interface cards (NICs) is disclosed, which increases NIC packet forwarding performance while reducing CPU usage, reduces memory access across NUMA, and simplifies the configuration process, making configuration more convenient and faster. Different NICs can be isolated, improving NIC forwarding performance. The configuration is more flexible and convenient, enabling cross-NUMA access and inter-core isolation of NICs. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0046] It should also be noted that, for ease of description, only the parts relevant to this disclosure are shown in the accompanying drawings. The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions in this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0047] Figure 1 This is a schematic diagram of the structure of an FT64C processor;

[0048] Figure 2 A schematic diagram of the network structure between a switch, a network interface card (NIC), and a host computer is provided as an embodiment of this application.

[0049] Figure 3 A flowchart illustrating a hardware bonding method for hybrid affinity network interface cards (NICs) provided in this application embodiment;

[0050] Figure 4 A schematic diagram illustrating NUMA binding as provided in an embodiment of this application;

[0051] Figure 5 A schematic diagram illustrating a core-based binding method provided in an embodiment of this application;

[0052] Figure 6 A schematic diagram of a hardware bonding device for hybrid network interface cards (NICs) provided in this application embodiment;

[0053] Figure 7 This is a connection block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0054] The following detailed description of the embodiments of this application, in conjunction with the accompanying drawings, will provide a thorough understanding of how this application uses technical means to solve technical problems and achieve corresponding technical effects, enabling its implementation. The embodiments of this application and the various features within them can be combined with each other without conflict, and all resulting technical solutions are within the protection scope of this application.

[0055] It should be clearly stated that the embodiments described below are merely some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0056] The following explanations will first describe some of the technical terms used in the embodiments of this application and / or the prior art, so that those skilled in the art can understand the technical solutions of this application:

[0057] NUMA: Non-Uniform Memory Access. NUMA describes the shared memory architecture used in modern multiprocessing systems. A NUMA is a computing system composed of multiple nodes, all of which share aggregated memory. Each NUMA has its own local memory, and local NUMAs can access their own memory at a relatively fast rate. NUMAs can also access the memory of other NUMAs, but at a relatively slower rate.

[0058] "Core-friendly" refers to binding a network interface card (NIC) queue to a CPU core, a concept closely related to multi-core CPUs. It's a technical term derived from this concept of binding NIC queues to CPU cores.

[0059] MAC: Media Access Control (MAC) sublayer protocol. In the OSI 7-layer model of computer networks, the PHY module operates at the physical layer, and the MAC module operates at the data link layer. In this application, MAC refers to a separate network interface card (NIC) hardware, including the PHY and MAC processing modules in the usual sense.

[0060] Hybrid affinity: Different MAC network ports can be affinity-connected to the same set of CPU cores, or they can be affinity-connected to different sets of CPU cores. This relationship is called "hybrid affinity".

[0061] N10: A model of a smart network card chip independently developed by the applicant of this application, which can support multiple MAC network ports.

[0062] Example 1

[0063] This embodiment provides a hardware solution for binding NUMA and cores. The network card using the method of this disclosure is equipped with a configuration register, which is used to perform the corresponding binding operation according to the configured information.

[0064] Figure 3 A flowchart of a hardware bonding method for hybrid pro-core network interface cards (NICs) provided in this application embodiment is shown below. Figure 3 As shown, the method includes the following steps:

[0065] Step 310: Determine the configuration information of the configuration register according to the binding requirements;

[0066] Step 320: Perform a configuration operation on the configuration register according to the configuration information using a preset configuration instruction;

[0067] Step 330: Perform the binding operation between the network card and the CPU core or between the network card and NUMA according to the configuration register.

[0068] In some embodiments, the configuration register includes:

[0069] Network card status register, CPU core bound status register, or NUMA bound predefined template register.

[0070] In some embodiments, when the configuration register is a network interface card status register...

[0071] The current status of the PORT corresponding to each binary bit is identified by the value of each binary bit in the network card status register; wherein, the current status includes: an open and available status and a closed and unavailable status.

[0072] As an example, consider the network interface card (NIC) status register (PORT_STATE_REG): This is a 64-bit register. Each bit represents the open or closed state of a NIC's port. For example:

[0073] If the value of bit-x (the xth binary bit) of the current PORT_STATE_REG is 1, it means that PORT-x is currently in an open and available state;

[0074] If the current value of bit-x in PORT_STATE_REG is 0, it means that PORT-x is currently closed and unavailable.

[0075] The value of x ranges from 0 to 63, indicating that the system can store the status of up to 64 network cards.

[0076] In some embodiments, when the configuration register is a CPU core binding status register...

[0077] The binding status of the CPU core corresponding to each binary bit is identified by the value of each binary bit in the CPU core binding status register; wherein, the binding status includes: unbound and bound.

[0078] As an example, for the CPU core binding status registers (PORT_00_BINDING_CORE_REG~PORT_63_BINDING_CORE_REG): this is a set of 64 registers, each with 64 bits.

[0079] The x-th register indicates the core that the x-th port needs to be bound to. The specific core binding status is represented by bits 0-63. For example, a value of 1 for bit-y (the y-th binary bit) indicates that the x-th port is bound to the y-th CPU core; a value of 0 for bit-y indicates that the x-th port is not bound to the y-th CPU core.

[0080] For example:

[0081] If the current value of bit-y in PORT_x_BINDING_CORE_REG is 0, it means that PORT-x is not currently bound to the y-th CPU core.

[0082] If the current value of bit-y in PORT_x_BINDING_CORE_REG is 1, it means that PORT-x is currently bound to the y-th CPU core.

[0083] The values ​​of x and y both range from 0 to 63. This indicates that the system supports a maximum of 64 network cards and 64 CPU cores in a single bonding state.

[0084] In some embodiments, when the configuration register is a NUMA-bound predefined template register...

[0085] The NUMA binding status is identified by the value of the predefined template register for NUMA binding.

[0086] As an example, consider the NUMA binding predefined template register (NUMA_BINDING_MODE_REG): it completes a full NUMA binding scheme by setting each register individually. Templates for complete PORT and NUMA binding schemes can be predefined and stored; then, the selection of which binding scheme is chosen is determined by specifying the value of this register. This is a more efficient configuration method.

[0087] As will be understood by those skilled in the art, in this embodiment, the granularity of NUMA is coarse, while the granularity of CORE is fine. For example, binding NUMA means binding all COREs on the NUMA; while binding CORE means binding only certain cores on the NUMA.

[0088] Here is a configuration example:

[0089] The value of the NUMA_BINDING_MODE_REG register is 0, meaning the PORT is not bound to NUMA.

[0090] In some embodiments, identifying the NUMA binding status through the value of the NUMA binding predefined template register includes:

[0091] When the value of the NUMA binding predefined template register is within a preset value range, all ports of the network card are bound to one or more NUMAs respectively; wherein, the number of NUMAs is equal to the value of the NUMA binding predefined template register.

[0092] For example, here is another configuration example:

[0093] The value of the NUMA_BINDING_MODE_REG register is 1, which binds all PORT ports to one NUMA, i.e., NUMA-0;

[0094] The value of the NUMA_BINDING_MODE_REG register is 2, which binds all PORT ports to two NUMAs, namely NUMA-0 and NUMA-1 respectively;

[0095] The value of the NUMA_BINDING_MODE_REG register is 3, which binds all PORT ports to the three NUMAs, namely NUMA-0, NUMA-1, and NUMA-3 respectively.

[0096] The value of the NUMA_BINDING_MODE_REG register is 4, which binds all PORT ports to the four NUMAs, namely NUMA-0, NUMA-1, NUMA-3, and NUMA-4 respectively.

[0097] In some embodiments, when the configuration register is a NUMA binding predefined template register and the value of the NUMA binding predefined template register is greater than a second preset threshold...

[0098] The NUMA pre-binding strategy is determined based on the value of the NUMA binding predefined template register.

[0099] The binding operation between the network interface card and the NUMA is performed according to the NUMA pre-binding policy.

[0100] The NUMA pre-binding strategy can be configured according to actual needs.

[0101] For example, here is another configuration example:

[0102] If the value of the NUMA_BINDING_MODE_REG register is any value other than 0 to 4, check and verify whether a NUMA pre-binding scheme (NUMA pre-binding strategy) corresponding to the current value of the NUMA_BINDING_MODE_REG register is defined. If the NUMA pre-binding scheme index is valid, then use the pre-binding scheme as the new binding scheme.

[0103] As an illustration, macro definitions can be used to define the address / number values ​​of the three registers for use in the corresponding instructions:

[0104] #define PORT_STATE_REG(0)

[0105] / / Define 64 registers consecutively:

[0106] / / PORT_00_BINDING_CORE_REG~PORT_63_BINDING_CORE_REG

[0107] #define PORT_00_BINDING_CORE_REG(1)

[0108] #define PORT_01_BINDING_CORE_REG(2)

[0109] / / .....

[0110] #define PORT_63_BINDING_CORE_REG(64)

[0111] #define NUMA_BINDING_MODE_REG(65).

[0112] Those skilled in the art will understand that the first preset threshold can be set to 0, the second preset threshold can be set to 4, and the preset value range can be set to [1~4]; the specific values ​​of the first and second preset thresholds and the preset value range can be set according to actual needs.

[0113] As an example, since the hardware implementation scheme disclosed in this embodiment mainly relies on the value of the registers, the following two related configuration instructions are provided for simple register-value-oriented implementation:

[0114] Register read instruction: reg_read reg_id,reg_val.

[0115] As will be understood by those skilled in the art, the first parameter of the read instruction is the address / number of the register, and the second parameter is the actual value read from the register given by the first parameter.

[0116] Write register instruction: reg_write reg_id,new_val.

[0117] As will be understood by those skilled in the art, the first parameter of the write instruction is the address / number of the register, and the second parameter is the actual value to be written to the register.

[0118] It is understandable that the preset configuration commands can be set according to actual needs, and no special restrictions are made here.

[0119] In the above instructions, the value of reg_id can be from 0 to 65, representing all registers used in the hardware implementation. The reg_id number for a specific register can be defined according to actual needs; details will not be elaborated further.

[0120] The hardware implementation scheme disclosed in this embodiment is characterized by the following: it provides dedicated registers in the network card chip, which can achieve the following functions for different network cards:

[0121] (1) Through relevant configuration, the queues of each network card can be bound to the corresponding NUMA and core;

[0122] (2) It can bind only certain cores on certain NUMAs, without requiring binding to all NUMAs and all cores on all NUMAs, making the binding scheme more flexible;

[0123] (3) After the corresponding configuration is completed, simply reload the driver to make the configuration take effect;

[0124] (4) For a single board with multiple MAC interfaces (i.e. network PORT interfaces), it can be bound to different NUMA or cores;

[0125] (5) The network card can be flexibly configured according to different CPU hardware to find the optimal core binding configuration and maximize network card performance.

[0126] Below, we will take a network card with two network ports that integrates the N10 network card chip as an example, and use Phytium's 64-core CPU to illustrate the binding relationship between the network card, the core, and NUMA:

[0127] As an example, the structural relationship based on NUMA binding can be found in [reference]. Figure 4 Network interface card 0 (MAC-0) is bound to two NUMAs, NUMA-0 and NUMA-1. Each of these NUMAs has 8 CPU cores, so network interface card MAC-0 is effectively bound to two NUMAs, which means it has 16 cores. When binding by NUMA, the following configuration is possible:

[0128] reg_write PORT_STATE_REG,0x0000_0000_0000_0003 # The first two network cards are valid;

[0129] reg_write NUMA_BINDING_MODE_REG,2# Bind 2 NUMAs to each network card.

[0130] As another example, CPU core binding is used; for details on the binding structure, please refer to [reference needed]. Figure 5 , Figure 5 The dashed lines in the diagram also represent the binding relationship between the MAC-0 network card and the CPU core. This is simply to distinguish it from the binding of the MAC-1 network card; it has no different meaning from the binding relationship represented by the solid lines. Figure 5 In this configuration, the specific binding relationships are as follows: MAC-0 is bound to NUMA-0 (0-3 cores) and NUMA-1 (12-15 cores); MAC-1 is bound to NUMA-0 (4-7 cores) and NUMA-1 (8-11 cores). When binding by CPU cores, the following configurations can be made:

[0131] Regarding the network interface card status register (PORT_STATE_REG):

[0132] Since only network cards 0 and 1 are valid and bound, only bits -0 and -1 of the PORT_STATE_REG register have a value of 1, meaning the entire register has a value of 0x0000_0000_0000_0003.

[0133] For the CPU core binding status registers (PORT_00_BINDING_CORE_REG~PORT_63_BINDING_CORE_REG):

[0134] Since only two network cards are in use, only one of the 64 CPU core binding status registers is active.

[0135] The PORT_00_BINDING_CORE_REG and PORT_01_BINDING_CORE_REG registers are meaningful, while the values ​​of the remaining 62 registers are all 0 by default;

[0136] Since MAC-0 is bound to cores 0-3 and 12-15, the values ​​of bits -0, -1, -2, -3, -12, -13, -14, and -15 in the corresponding register PORT_00_BINDING_CORE_REG are all 1. Therefore, its final value should be 0x0000_0000_0000_F00F.

[0137] Since MAC-1 is bound to cores 4-7 and 8-11, the values ​​of bits -4, -5, -6, -7, -8, -9, -10, and -11 of the corresponding register PORT_01_BINDING_CORE_REG are 1. Therefore, its final value should be 0x0000_0000_0000_0FF0.

[0138] After determining the register values, the hardware implementation configuration is completed by writing the values ​​of all the registers using `reg_write`. For example (using three instructions to update the values ​​of three registers respectively. The first parameter of the write instruction is the address / number of the register, and the second parameter is the actual value to be written to the register):

[0139] reg_write PORT_STATE_REG,0x0000_0000_0000_0003

[0140] reg_write PORT_00_BINDING_CORE_REG,0x0000_0000_0000_F00F

[0141] reg_write PORT_01_BINDING_CORE_REG,0x0000_0000_FFFF_0FF0.

[0142] It should be noted that for scenarios with high performance requirements, three NUMAs can be bound; if CPU needs to be reserved for other business (such as auditing), one or two NUMAs can be bound.

[0143] The hardware implementation scheme for hybrid network interface cards (NICs) provided in this embodiment increases NIC packet forwarding performance while reducing CPU usage, reduces cross-NUMA memory access, and simplifies the configuration process, making configuration more convenient and faster. It can isolate different NICs, improving NIC forwarding performance; the configuration is more flexible and convenient, and it can realize cross-NUMA port access and inter-core isolation of NICs.

[0144] Example 2

[0145] This embodiment provides a hardware bonding device for hybrid network interface cards (NICs). This device embodiment can be used to execute the method embodiment of this application. For details not disclosed in this device embodiment, please refer to the method embodiment of this application. Figure 6 This application provides a schematic diagram of a hardware bonding device for hybrid network interface cards (NICs) in an embodiment of the present application. Figure 6 As shown, the apparatus 600 disclosed in this embodiment includes:

[0146] The determination module 601 is used to determine the configuration information of the configuration register according to the binding requirements;

[0147] Configuration module 602 is used to perform configuration operations on the configuration register according to the configuration information using preset configuration instructions;

[0148] The binding module 603 is used to perform binding operations between the network card and the CPU core or between the network card and the NUMA according to the configuration register.

[0149] In some embodiments, the configuration register includes:

[0150] Network card status register, CPU core bound status register, or NUMA bound predefined template register.

[0151] In some embodiments, when the configuration register is a network interface card status register...

[0152] The current status of the PORT corresponding to each binary bit is identified by the value of each binary bit in the network card status register.

[0153] In some embodiments, when the configuration register is a CPU core binding status register...

[0154] The binding status of the CPU core corresponding to each bit is identified by the value of each bit in the CPU core binding status register.

[0155] In some embodiments, when the configuration register is a NUMA-bound predefined template register...

[0156] The NUMA binding status is identified by the value of the predefined template register for NUMA binding.

[0157] In some embodiments, identifying the NUMA binding status through the value of the NUMA binding predefined template register includes:

[0158] If the value of the NUMA binding predefined template register is not greater than the first preset threshold, the PORT port of the network card will not be bound to NUMA.

[0159] In some embodiments, identifying the NUMA binding status through the value of the NUMA binding predefined template register includes:

[0160] When the value of the NUMA binding predefined template register is within a preset value range, all ports of the network card are bound to one or more NUMAs respectively; wherein, the number of NUMAs is equal to the value of the NUMA binding predefined template register.

[0161] In some embodiments, when the configuration register is a NUMA binding predefined template register and the value of the NUMA binding predefined template register is greater than a second preset threshold...

[0162] The NUMA pre-binding strategy is determined based on the value of the NUMA binding predefined template register.

[0163] The binding operation between the network interface card and the NUMA is performed according to the NUMA pre-binding policy.

[0164] Those skilled in the field can understand that Figure 6 The structures shown do not constitute a limitation on the apparatus of the embodiments of this application. They may include more or fewer modules / units than shown, or combine certain modules / units, or have different module / unit arrangements.

[0165] Those skilled in the art will understand that the modules or steps described above can be implemented using general-purpose computing devices, either centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby allowing them to be stored in a storage device for execution by a computing device. Furthermore, in some cases, the steps shown or described can be performed in a different order than presented herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module.

[0166] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of each module can be referred to the corresponding process in the aforementioned method embodiments, and will not be repeated here.

[0167] Example 3

[0168] This embodiment provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, can implement the method steps as described in the foregoing method embodiments; these steps will not be repeated here.

[0169] Computer-readable storage media may individually include computer programs, data files, data structures, etc., or combinations thereof. The computer-readable storage media or computer program may be specifically designed and understood by those skilled in the art of computer software, or the computer-readable storage media may be known and available to those skilled in the art of computer software. Examples of computer-readable storage media include: magnetic media, such as hard disks, floppy disks, and magnetic tapes; optical media, such as CD-ROMs and DVDs; magneto-optical media, such as optical discs; and hardware devices specifically configured to store and execute computer programs, such as read-only memory (ROM), random access memory (RAM), flash memory; or servers, application stores, etc. Examples of computer programs include machine code (e.g., code generated by a compiler) and files containing high-level code that can be executed by a computer using an interpreter. The described hardware devices may be configured to function as one or more software modules to perform the operations and methods described above, and vice versa. Furthermore, computer-readable storage media may be distributed across networked computer systems, allowing for the decentralized storage and execution of program code or computer programs.

[0170] Example 4

[0171] This embodiment provides a computer program product. The computer program product includes a computer program or instructions, which, when executed by a processor, implement all or part of the steps of the method as described in the foregoing method embodiments; these will not be repeated here.

[0172] Furthermore, the computer program product may include one or more computer-executable components configured to perform the embodiments when the program is run; the computer program product may also include a computer program tangibly contained on a readable medium thereof, the computer program containing program code for performing any of the methods in the embodiments of this disclosure. In such embodiments, the computer program may be downloaded and installed from a network via a communication component, and / or installed from a removable medium.

[0173] Example 5

[0174] This embodiment provides an electronic device. Figure 7 A connection block diagram of an electronic device provided in an embodiment of this application, such as... Figure 7 As shown, the electronic device 700 may include: one or more processors 701, memory 702, multimedia components 703, input / output (I / O) interface 704, and communication components 705.

[0175] One or more processors 701 are used to execute all or part of the steps as described in the foregoing method embodiments. Memory 702 is used to store various types of data, which may include, for example, instructions for any application or method in the electronic device, as well as application-related data.

[0176] One or more processors 701 may be implemented as an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a controller, a microcontroller, a microprocessor, or other electronic components, for performing the methods as described in the foregoing method embodiments.

[0177] The memory 702 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0178] Multimedia component 703 may include a screen, which may be a touchscreen, and an audio component for outputting and / or inputting audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in memory or transmitted via a communication component. The audio component also includes at least one speaker for outputting audio signals.

[0179] I / O interface 704 provides an interface between one or more processors 701 and other interface modules, such as a keyboard, mouse, buttons, etc. These buttons can be virtual buttons or physical buttons.

[0180] The communication component 705 is used for wired or wireless communication between the electronic device 700 and other devices. Wired communication includes communication via network port, serial port, etc.; wireless communication includes Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, 4G, 5G, or one or more combinations thereof.

[0181] In summary, this application provides a hardware bonding method, apparatus, storage medium, and electronic device for hybrid network interface card (NIC) bonding. The hardware implementation scheme for hybrid NIC bonding disclosed in this application increases NIC packet forwarding performance while reducing CPU usage, reduces cross-NUMA memory access, and simplifies the configuration process, making configuration more convenient and faster. It can isolate different NICs, improving NIC forwarding performance; the configuration is more flexible and convenient, enabling cross-NUMA access and inter-core isolation of NICs.

[0182] It should also be understood that the methods or apparatuses disclosed in the embodiments provided in this application can also be implemented in other ways. The method or apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functions, and operations of possible implementations of methods and apparatuses according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, computer program segment, or part of a computer program, which includes one or more computer programs for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings, and may actually be executed substantially in parallel. They may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer programs.

[0183] In this application, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "including one..." does not exclude the presence of other identical elements in the process, method, apparatus, or device that includes the element; the use of terms such as "first" and "second" is for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly indicating the number or sequence of the indicated technical features; in the description of this application, unless otherwise stated, the terms "multiple" or "many" mean at least two; if a server is described, it should be noted that a server can be an independent physical server or terminal, or a server cluster consisting of multiple physical servers, or a cloud server capable of providing basic cloud computing services such as cloud servers, cloud databases, cloud storage, and CDN; if a smart terminal or mobile device is described in this application, it should be noted that a smart terminal or mobile device can be a mobile phone, tablet computer, smartwatch, netbook, wearable electronic device, personal digital assistant (PDA), augmented reality (AR) device, virtual reality (VR) device, smart TV, smart speaker, personal computer (PC). Computer (PC) etc., but not limited to these, this application does not make any special restrictions on the specific form of smart terminals or mobile devices.

[0184] Finally, it should be noted that in the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "a single example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0185] Although embodiments of this application have been shown and described above, it is to be understood that the above embodiments are exemplary and the content is only for the purpose of facilitating understanding of this application, and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A hardware bonding method for hybrid pro-core network interface cards (NICs), characterized in that, The network interface card (NIC) is equipped with configuration registers, including: a NIC status register, a CPU core binding status register, or a NUMA binding predefined template register; the method includes: The configuration information of the configuration register is determined according to the binding requirements; Based on the configuration information, a configuration operation is performed on the configuration register using a preset configuration instruction; The network interface card (NIC) is bound to the CPU core or the NIC to the NUMA core according to the configuration register.

2. The hardware bonding method for hybrid pro-core network interface cards (NICs) according to claim 1, characterized in that, When the configuration register is the network interface card status register. The current status of the PORT corresponding to each binary bit is identified by the value of each binary bit in the network card status register.

3. The hardware bonding method for hybrid pro-core network interface cards (NICs) according to claim 1, characterized in that, When the configuration register is a CPU core bound status register. The binding status of the CPU core corresponding to each bit is identified by the value of each bit in the CPU core binding status register.

4. The hardware bonding method for hybrid pro-core network interface cards (NICs) according to claim 1, characterized in that, When the configuration register is a NUMA-bound predefined template register. The NUMA binding status is identified by the value of the predefined template register for NUMA binding.

5. The hardware bonding method for hybrid pro-core network interface cards (NICs) according to claim 4, characterized in that, The step of identifying the NUMA binding status by using the value of the predefined template register for NUMA binding includes: If the value of the NUMA binding predefined template register is not greater than the first preset threshold, the PORT port of the network card will not be bound to NUMA.

6. The hardware bonding method for hybrid pro-core network interface cards (NICs) according to claim 4, characterized in that, The step of identifying the NUMA binding status by using the value of the predefined template register for NUMA binding includes: When the value of the NUMA binding predefined template register is within a preset value range, all ports of the network card are bound to one or more NUMAs respectively; wherein, the number of NUMAs is equal to the value of the NUMA binding predefined template register.

7. The hardware bonding method for hybrid pro-core network interface cards (NICs) according to any one of claims 1 to 6, characterized in that, When the configuration register is a NUMA binding predefined template register and the value of the NUMA binding predefined template register is greater than a second preset threshold. The NUMA pre-binding strategy is determined based on the value of the NUMA binding predefined template register. The binding operation between the network interface card and the NUMA is performed according to the NUMA pre-binding policy.

8. A hardware bonding device for hybrid network interface cards (NICs), characterized in that, include: The determination module is used to determine the configuration information of the configuration registers based on the binding requirements; The configuration module is used to perform configuration operations on the configuration register according to the configuration information using preset configuration instructions; The binding module is used to perform binding operations between the network card and the CPU core or between the network card and the NUMA according to the configuration register; The network card is equipped with a configuration register, which includes a network card status register, a CPU core binding status register, or a NUMA binding predefined template register.

9. A computer-readable storage medium, characterized in that, The computer program stored in the computer-readable storage medium, when executed by one or more processors, implements the hardware bonding method for hybrid parent-core network interface cards as described in any one of claims 1 to 7.

10. An electronic device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, it implements the hardware bonding method for hybrid pro-core network cards as described in any one of claims 1 to 7.

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