Display device

Abstract

A display device is provided, comprising a substrate layer, pixels, scan lines, and data lines. The capacitor of each pixel includes a first electrode on a first layer and a second electrode on a second layer. The transistor of each pixel includes a control electrode on a first layer and an input electrode and an output electrode on a third layer. The connection electrode of the pixel is on a fourth layer. The substrate layer includes a first region, a second region, and a third region. The scan lines include a first line portion on the second region and a second line portion on the third region. The data lines include a third line portion on the second region, a fourth line portion on the third region, and a connection portion connecting the third line portion and the fourth line portion. Some first line portions are on the first layer, and others are on the second layer. Some third line portions are on the third layer, and others are on the fourth layer. The connection portion includes a first connection portion and a second connection portion along a first direction. When viewed from the first direction, the first connection portion and the second connection portion are spaced apart from each other along a second direction.

Description

[0001] This application is a divisional application of the patent application filed on November 21, 2019, with application number 201911145436.9 and title "Display Device". Technical Field

[0002] Exemplary embodiments of the invention generally relate to a display device, and more specifically, to a display device having improved display quality and being provided with an electronic module having improved sensitivity. Background Technology

[0003] The display device may be a device that includes a display panel for displaying images, an input sensing component for sensing external input, and various electronic components such as electronic modules. The electronic components may be electrically connected to each other via various arranged signal lines. The display panel includes light-emitting elements that generate images. The input sensing component may include sensing electrodes for sensing external input. The electronic module may include a camera, an infrared sensor, a proximity sensor, etc. The electronic module may be disposed below the display panel.

[0004] The information disclosed above in this background section is only for understanding the background of the inventive concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0005] An apparatus constructed according to an exemplary embodiment of the invention provides a display device, the display device being provided with an electronic module having improved sensitivity and improved display quality.

[0006] Additional features of the inventive concept will be set forth in the description below, and will be apparent in part from the description, or may be learned by practice of the inventive concept.

[0007] According to one or more exemplary embodiments of the invention, a display device includes: a substrate layer including a first region, a second region surrounding the first region, and a third region surrounding the second region; a first signal line portion disposed on the second region and the third region and arranged to be spaced apart from each other in a first direction; a second signal line portion disposed on the second region and the third region and arranged to be spaced apart from each other in a second direction intersecting the first direction; and a pixel disposed on the third region and electrically connected to one of the first signal line portions, wherein each of the first signal line portions includes: a first line; a second line separated from the first line; and a first connection portion configured to connect the first line and the second line, and at least a portion of the first connection portion of the first signal line portion overlaps with at least a portion of the second signal line portion.

[0008] The display device may also include an electronic module configured to be superimposed on the first area when viewed in a plan view.

[0009] The first line and the second line can be set on the same layer, and the first connecting part can be set on a different layer than the first line and the second line.

[0010] The first line and the second line can be set on different layers, and the first connecting part can be set on the same layer as one of the first line and the second line.

[0011] The first connection portion can be divided into an overlay connection portion and a non-overlay connection portion. The overlay connection portion can be overlaid with at least a portion of the second signal line portion, and the non-overlay connection portion can be not overlaid with the second signal line portion.

[0012] The overlapping connection part can be set on the second region, and the non-overlapping connection part can be set on the third region.

[0013] The stacked connection portion may include multiple stacked connection portions, and the non-stacked connection portion may include multiple non-stacked connection portions. The multiple stacked connection portions may be arranged to be separated from each other in a first direction, and the multiple non-stacked connection portions may be arranged to be separated from each other in a first direction.

[0014] The overlapping connection may include multiple overlapping connection portions, and when viewed in a first direction, two adjacent overlapping connection portions among the multiple overlapping connection portions may not overlap each other.

[0015] The overlapping connection may include a plurality of overlapping connection portions, wherein when viewed in a first direction, a portion of each of the two closest overlapping connection portions may not overlap with each other, and the remaining portions of the two closest overlapping connection portions may overlap with each other in the first direction.

[0016] The first line can be set on the second region, a portion of the first line can extend in accordance with the shape of the boundary between the first region and the second region, and the second line can extend in a second direction.

[0017] The first connection portion can be connected to at least one of the first wire and the second wire through a through hole defined in the insulating layer, the insulating layer being configured to cover at least one of the first wire and the second wire.

[0018] Each of the second signal line portions may include: a third line; a fourth line separated from the third line; and a second connecting portion configured to connect the third line and the fourth line, and at least a portion of the second connecting portion of the second signal line portion may overlap with at least a portion of the first signal line portion.

[0019] A third line may be disposed on the second region, at least a portion of the third line may extend in a shape corresponding to the boundary between the first region and the second region, a fourth line may extend in a first direction, and a second connecting portion may be connected to at least one of the third line and the fourth line through a through hole defined in the insulating layer, the insulating layer being configured to cover at least one of the third line and the fourth line.

[0020] The hole can be confined to a first region of the matrix layer, and when viewed in a plan view, the hole can be surrounded by a second region.

[0021] A display module is composed of a substrate layer, a first signal line portion, a second signal line portion, and pixels; a first module region superimposed on a first region, a second module region superimposed on a second region, and a third module region superimposed on a third region can be defined in the display module; and the transmittance of the first module region can be higher than the transmittance of the third module region.

[0022] According to one or more exemplary embodiments of the invention, a display device includes: a display panel defining a non-display area and a display area surrounding the non-display area, wherein the display panel includes: a substrate layer including a first region having a hole corresponding to the non-display area, a second region surrounding the first region, and a third region corresponding to the display area; and first signal line portions disposed on the second region and the third region, the first signal line portions being arranged to be spaced apart from each other in a first direction, and each of the first signal line portions including: a first line; a second line separated from the first line; and a first connecting portion configured to connect the first line and the second line.

[0023] The first connecting part can be configured to overlap with the second region.

[0024] The first connecting portions of the first signal line portion can be arranged to be separated from each other in a first direction.

[0025] Two adjacent first connecting parts may not overlap each other in the first direction.

[0026] The display device may further include second signal line portions arranged to be spaced apart from each other in a second direction intersecting the first direction, wherein each of the second signal line portions may include: a third line; a fourth line separated from the third line; and a second connecting portion configured to connect the third line and the fourth line.

[0027] It will be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0028] The accompanying drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the inventive concept. The drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification.

[0029] Figure 1A This is a perspective view of a display device according to an exemplary embodiment.

[0030] Figure 1B This is an exploded perspective view of a display device according to an exemplary embodiment.

[0031] Figure 2 This is a block diagram of a display device according to an exemplary embodiment.

[0032] Figure 3 This is a plan view of a display panel according to an exemplary embodiment.

[0033] Figure 4 This is a plan view of the input sensing unit according to an exemplary embodiment.

[0034] Figure 5 This is a cross-sectional view of a display panel according to an exemplary embodiment.

[0035] Figure 6 This is a cross-sectional view of a display panel according to an exemplary embodiment.

[0036] Figure 7 This is a cross-sectional view of a display panel according to an exemplary embodiment.

[0037] Figure 8 It is shown Figure 3 The enlarged plan view of region XX' shown in the figure.

[0038] Figure 9 Is with Figure 8 The image shown is a photograph of the region corresponding to area YY'.

[0039] Figure 10 Is with Figure 9 The diagram shows a schematic plan view of the region corresponding to region ZZ'.

[0040] Figure 11 It is along Figure 10 The sectional view taken by section line I-I'.

[0041] Figure 12 It is along Figure 10 The sectional view taken by section line II-II'.

[0042] Figure 13 yes Figure 8 The diagram shows an enlarged schematic plan view of region KK'.

[0043] Figure 14 It is along Figure 13 The sectional view taken by section line III-III'.

[0044] Figure 15 Is with Figure 8 The image shown is a photograph of the region corresponding to area YY'.

[0045] Figure 16 Is with Figure 15 The diagram shows a schematic plan view of the area corresponding to region LL'.

[0046] Figure 17 It is shown Figure 3 The enlarged plan view of region XX' shown in the figure.

[0047] Figure 18 Is with Figure 17 The image shown is of the region corresponding to region MM'.

[0048] Figure 19 Is with Figure 18 The diagram shows a schematic plan view of the region corresponding to region NN'.

[0049] Figure 20 This is an exploded perspective view of a display device according to an exemplary embodiment. Detailed Implementation

[0050] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms as non-limiting examples of apparatuses or methods employing one or more inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but not necessarily exclusive. For example, a particular shape, construction, and characteristic of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0051] Unless otherwise stated, the exemplary embodiments shown are to be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as “elements”) of various embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0052] Crosshairs and / or shading are typically used in accompanying drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, scale, commonalities between the elements shown, or any other characteristics, properties, etc. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. A particular process sequence may be performed differently than the described sequence when exemplary embodiments can be implemented differently. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of the described sequence. Moreover, the same reference numerals denote the same elements.

[0053] When a component or layer is referred to as being "on," "connected to," or "bonded to" another component or layer, the component or layer may be directly on, directly connected to, or directly bonded to the other component or layer, or there may be intermediate components or layers present. However, when a component or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another component or layer, there are no intermediate components or layers present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection, with or without intermediate components. Furthermore, the DR1, DR2, and DR3 axes are not limited to the three axes of a Cartesian coordinate system (such as the x, y, and z axes) but can be interpreted in a broader sense. For example, the DR1, DR2, and DR3 axes can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0054] Although the terms “first,” “second,” etc., may be used here to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element.

[0055] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in a “sidewall”) may be used herein to describe the relationship between one element and another (other) element as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features would then be positioned “above” said other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0056] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and variations thereof and / or “including” and variations thereof are used in this specification, they indicate the presence of stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “basically,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0057] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views, which are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Thus, variations in the shapes illustrated will be expected, for example, due to manufacturing techniques and / or tolerances. Therefore, the exemplary embodiments disclosed herein should not necessarily be interpreted as limited to the specific shapes shown for the regions, but will include deviations in shape due to, for example, manufacturing processes. In this way, the regions shown in the figures can be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, so this is not intended to be limiting.

[0058] In accordance with the conventions of the art, exemplary embodiments of functional blocks, units, and / or modules are described and illustrated in the accompanying drawings. Those skilled in the art will understand that these functional blocks, units, and / or modules are physically implemented using electronic (or optical) circuits (such as logic circuits), discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., formed using semiconductor-based or other manufacturing techniques. When functional blocks, units, and / or modules are implemented using microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be selectively driven by firmware and / or software. It is also contemplated that each functional block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of the inventive concept, each functional block, unit, and / or module of some exemplary embodiments may be physically divided into two or more interactive and discrete functional blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, functional blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex functional blocks, units and / or modules.

[0059] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in general dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formalized sense, unless expressly defined herein.

[0060] In the following description, exemplary embodiments of the inventive concept will be illustrated with reference to the accompanying drawings.

[0061] Figure 1A This is a perspective view of a display device according to an exemplary embodiment. Figure 1B This is an exploded perspective view of a display device according to an exemplary embodiment. Figure 2 This is a block diagram of a display device according to an exemplary embodiment. In the following, reference will be made to... Figure 1A , Figure 1B and Figure 2 To describe an exemplary embodiment.

[0062] The display device EA can be a device that is activated in response to an electrical signal. The display device EA can include various examples. For instance, the display device EA can include a tablet PC, a laptop PC, a television, etc. In this embodiment, the display device EA is exemplarily shown as a smartphone.

[0063] The display device EA can display an image IM on a display surface FS on a third direction DR3, the display surface FS being parallel to each of the first direction DR1 and the second direction DR2. The display surface FS on which the image IM is displayed can correspond to the front surface of the display device EA and can also correspond to the front surface FS of the window 100. Hereinafter, the display surface and front surface of the display device EA, as well as the front surface of the window 100, will be indicated by the same reference numerals. The image IM can include not only moving images but also still images. Figure 1A The example shown is a clock window and an application icon used as an image IM.

[0064] In this embodiment, the front (or upper) and rear (or lower) surfaces of each component are defined relative to the direction along which it displays the image IM. The front and rear surfaces may be opposite each other on a third direction DR3, and the normal direction of each of the front and rear surfaces may be parallel to the third direction DR3. Meanwhile, the directions represented by the first direction DR1, the second direction DR2, and the third direction DR3 are relative and can be converted to other directions. Hereinafter, the first direction, the second direction, and the third direction are the directions represented by the first direction DR1, the second direction DR2, and the third direction DR3, respectively, and are indicated by the same reference numerals.

[0065] The display device EA may include a window 100, a display module 200, a driving circuit section 300, a housing 400, and an electronic module 500. In this embodiment, the window 100 and the housing 400 may be combined to form the appearance of the display device EA.

[0066] Window 100 may include an optically transparent insulating material. For example, window 100 may include glass or plastic. Window 100 may have a multilayer structure or a single-layer structure. For example, window 100 may include multiple plastic films bonded together by an adhesive, or it may include a glass substrate and a plastic film bonded together by an adhesive.

[0067] When viewed in a plan view, window 100 can be divided into a transmission area TA and a border area BZA. In this specification, the term "in a plan view" can refer to the view in a third-party direction DR3. Additionally, "thickness direction" can refer to the third-party direction DR3.

[0068] The transmission region TA can be an optically transparent region. The border region BZA can be a region with a relatively lower transmittance than the transmission region TA. The border region BZA can define the shape of the transmission region TA. The border region BZA can be adjacent to and surround the transmission region TA.

[0069] The border area BZA may have a predetermined color. The border area BZA may cover the peripheral area NAA of the display module 200 and prevent or suppress the peripheral area NAA from being viewed from the outside. However, this is an exemplary illustration; in the window 100 according to the exemplary embodiment, the border area BZA may be omitted.

[0070] In an exemplary embodiment, the sensing area SA may be an area superimposed on the electronic module 500, which will be described later. The display device EA can receive external signals required by the electronic module 500 or provide signals output from the electronic module 500 to the outside through the sensing area SA. According to an exemplary embodiment, the sensing area SA may be defined as superimposed on the transmission area TA. Therefore, the separate area configured to provide the sensing area SA in an area other than the transmission area TA can be omitted. Therefore, the area of ​​the border area BZA can be reduced.

[0071] Figure 1B The example shown illustrates one sensing region SA, but the exemplary embodiment is not limited thereto. For example, two or more sensing regions SA may be defined. Additionally, although... Figure 1B An example is shown where the sensing region SA is defined at the upper left end of the transmission region TA, but the sensing region SA can be defined in various regions, such as at the upper right end of the transmission region TA, at the center of the transmission region TA, at the lower left end of the transmission region TA, or at the lower right end of the transmission region TA.

[0072] The display module 200 may be positioned below the window 100. In this specification, the phrase "below" may refer to the display module 200 in the opposite direction to the direction in which it provides the image. The display module 200 can display an image IM and detect external input TC. The display module 200 includes a front surface (also referred to as a display surface) IS comprising an active area AA and a peripheral area NAA. The active area AA may be an area activated in response to an electrical signal.

[0073] In this embodiment, the effective area AA can be the area on which the image IM is displayed and the external input TC is detected. The transmission area TA is superimposed on the effective area AA at least. For example, the transmission area TA is superimposed on the entire effective area AA or a portion of the effective area AA. Therefore, the user can view the image IM or provide external input TC through the transmission area TA.

[0074] The peripheral region NAA can be the area covered by the border region BZA. The peripheral region NAA is adjacent to the active region AA. The peripheral region NAA can surround the active region AA. Within the peripheral region NAA, drive circuits, drive wiring, etc., for driving the active region AA can be configured.

[0075] In this embodiment, the display module 200 is assembled in a flat state where the effective area AA and the peripheral area NAA face the window 100. However, this is shown exemplary, and a portion of the peripheral area NAA may be bent. In this case, a portion of the peripheral area NAA faces the rear surface of the display device EA, such that the area of ​​the bezel area BZA can be reduced on the front surface of the display device EA. Alternatively, the display module 200 may also be assembled in a state where a portion of the effective area AA is also bent. Alternatively, in the display module 200 according to the exemplary embodiment, the peripheral area NAA may be omitted.

[0076] The display module 200 may include a display panel 210 and an input sensing unit 220.

[0077] The display panel 210 can be the component that actually generates the image IM. The image IM generated by the display panel 210 is displayed on the display surface IS and viewed by an external user through the transmission area TA.

[0078] Input sensing unit 220 detects external input TC applied from the outside. For example, input sensing unit 220 may detect external input TC provided to window 100. External input TC may be input from a user. User input includes various types of external input, such as a part of the user's body, light, heat, pen, or pressure. In this embodiment, external input TC is shown as a user's hand applied to the front surface FS. However, this is an exemplary illustration, and as mentioned above, user input can be provided in various forms. The display device EA may also detect external input TC applied by the user to the side or rear surface of the display device EA, depending on the structure of the display device EA, and the exemplary embodiments are not limited to any one embodiment.

[0079] The driving circuit section 300 can be electrically connected to the display panel 210 and the input sensing unit 220. The driving circuit section 300 may include a main circuit board MB, a first flexible film CF1, and a second flexible film CF2.

[0080] The first flexible film CF1 can be electrically connected to the display panel 210. The first flexible film CF1 can connect the display panel 210 and the main circuit board MB. The first flexible film CF1 can be connected to a pad (also called a "soldering pad") disposed on the peripheral area NAA (display pad) of the display panel 210. The first flexible film CF1 provides electrical signals for driving the display panel 210. These electrical signals can be generated from the first flexible film CF1 or the main circuit board MB.

[0081] The second flexible film CF2 can be electrically connected to the input sensing unit 220. The second flexible film CF2 can connect the input sensing unit 220 and the main circuit board MB. The second flexible film CF2 can be connected to a pad (sensing pad) disposed on the peripheral area NAA of the input sensing unit 220. The second flexible film CF2 provides electrical signals for driving the input sensing unit 220. These electrical signals can be generated from either the second flexible film CF2 or the main circuit board MB.

[0082] The main circuit board MB may include various driving circuits for driving the display module 200, connectors for power supply, etc. The first flexible film CF1 and the second flexible film CF2 may be connected to the main circuit board MB. According to an exemplary embodiment of the inventive concept, the display module 200 can be easily controlled by a single main circuit board MB. However, this is merely an illustrative example; in the display module 200 according to the exemplary embodiment, the display panel 210 and the input sensing unit 220 may also be connected to different main circuit boards, and the first flexible film CF1 or the second flexible film CF2 may not be connected to the main circuit board MB. Furthermore, the exemplary embodiment is not limited to any one of these embodiments.

[0083] In an exemplary embodiment, a region in the display module 200 corresponding to the sensing region SA may have a relatively higher transmittance than an effective region AA not superimposed on the sensing region SA. For example, at least a portion of the components of the display panel 210 and the input sensing unit 220 may be removed. Therefore, the electronic module 500 configured to superimpose on the sensing region SA can easily transmit and / or receive signals through the sensing region SA.

[0084] Figure 1B An exemplary illustration shows a predetermined aperture MH (hereinafter referred to as a module aperture) defined in a region of the display module 200 corresponding to the sensing region SA. The module aperture MH may be defined in the effective region AA and penetrate the display module 200. The display panel 210 and the input sensing unit 220 may be penetrated by the module aperture MH. That is, the module aperture MH may be defined such that all components of the display panel 210 and the input sensing unit 220 that are configured to overlap with the sensing region SA are removed. Since the module aperture MH is defined in the effective region AA, the sensing region SA may be located within the transmission region TA.

[0085] When viewed in a plan view, the electronic module 500 can be stacked with the module aperture MH and the sensing area SA. The electronic module 500 can be positioned below the display module 200, and at least a portion of the electronic module 500 can be housed within the module aperture MH. The electronic module 500 can receive external input transmitted through the sensing area SA or provide output through the sensing area SA.

[0086] The housing 400 is integrated with the window 100. The integration of the housing 400 with the window 100 provides interior space. The display module 200 and the electronic module 500 can be accommodated within the interior space.

[0087] The housing 400 may include a material with relatively high rigidity. For example, the housing 400 may include glass, plastic, or metal, or may include multiple frames and / or panels composed of a combination of glass, plastic, or metal. The housing 400 can stably protect the components of the display device EA housed in the internal space from external impacts.

[0088] Reference Figure 2 The display device EA may include a display module 200, a power module PM, a first electronic module EM1, and a second electronic module EM2. The display module 200, the power module PM, the first electronic module EM1, and the second electronic module EM2 may be electrically connected to each other.

[0089] The power module PM supplies the power required for the overall operation of the display device EA. The power module PM may include a conventional battery module.

[0090] The first electronic module EM1 and the second electronic module EM2 may include various functional modules for operating the display device EA.

[0091] The first electronic module EM1 can be directly mounted on the motherboard that is electrically connected to the display module 200, or mounted on a separate board and electrically connected to the motherboard via connectors, etc.

[0092] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM, and an external interface IF. Some modules may not be mounted on the motherboard, but can be electrically connected to the motherboard via a flexible circuit board.

[0093] The control module CM controls the overall operation of the display device EA. The control module CM can be a microprocessor. For example, the control module CM can activate or deactivate the display module 200. The control module CM can control other modules such as the image input module IIM or the audio input module AIM based on touch signals received from the display module 200.

[0094] The wireless communication module TM can use Bluetooth or Wi-Fi lines to send / receive wireless signals to another terminal. The wireless communication module TM can use general communication lines to send / receive audio signals. The wireless communication module TM may include a transmitting unit TM1 that modulates and transmits the signal to be transmitted, and a receiving unit TM2 that demodulates the received signal.

[0095] The image input module IIM processes image signals and converts them into image data that can be displayed on the display module 200. The audio input module AIM receives external audio signals through a microphone in recording mode, voice recognition mode, etc., and converts the audio signals into electronic voice data.

[0096] The external interface IF can be used as an interface to connect to external chargers, wired / wireless data ports, card (e.g., memory card or SIM / UIM card) slots, etc.

[0097] The second electronic module EM2 may include an audio output module AOM, a light-emitting module LM, a light-receiving module LRM, a camera module CMM, etc. These components can be directly mounted on the motherboard, mounted on a separate board and electrically connected to the display module 200 via connectors, or electrically connected to the first electronic module EM1.

[0098] The audio output module AOM converts audio data received from the wireless communication module TM or stored in the memory MM, and outputs the converted audio data to the outside.

[0099] A light-emitting module (LM) generates and outputs light. The LM can output infrared light. The LM may include LED elements. A light-receiving module (LRM) detects infrared light. The LRM can be activated when at least a predetermined level of infrared light is detected. The LRM may include a CMOS sensor. After the infrared light generated by the LM is output, the infrared light is reflected from an external object (e.g., a user's finger or face), and the reflected infrared light can be incident on the LRM. A camera module (CMM) can capture an image of the external environment.

[0100] The electronic module 500 according to an exemplary embodiment may include at least any one of the components of a first electronic module EM1 and a second electronic module EM2. For example, the electronic module 500 may include at least any one of an audio output module AOM, a light emission module LM, a light receiving module LRM, a camera module CMM, a thermal sensing module, etc. The electronic module 500 can detect external objects received through the sensing area SA, or provide audio signals such as voice or light such as infrared light to the outside. In addition, the electronic module 500 may also include multiple modules, and the exemplary embodiment is not limited to any one embodiment.

[0101] In an exemplary embodiment, the display module 200, the first electronic module EM1, the second electronic module EM2, the power module PM, and / or one or more of its components may be implemented via one or more general-purpose and / or special-purpose components (such as one or more discrete circuits, digital signal processing chips, integrated circuits, application-specific integrated circuits, microprocessors, processors, programmable arrays, field-programmable arrays, instruction set processors, etc.).

[0102] According to one or more exemplary embodiments, the features, functions, processes, etc. described herein may be implemented via software, hardware (e.g., general-purpose processors, digital signal processing (DSP) chips, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), etc.), firmware, or a combination thereof. In this way, the display module 200, the first electronic module EM1, the second electronic module EM2, the power module PM, and / or one or more of its components may include one or more memories or be additionally associated with one or more memories, said one or more memories including code (e.g., instructions) configured to cause the display module 200, the first electronic module EM1, the second electronic module EM2, the power module PM, and / or one or more of its components to execute one or more features, functions, processes, etc. described herein.

[0103] Memory can be any medium that provides code to one or more software, hardware, and / or firmware components for execution. Such memory can be implemented in any suitable form, including but not limited to non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical discs or magnetic disks. Volatile media include dynamic memory. Transmission media include coaxial cables, copper wires, and optical fibers. Transmission media can also take the form of sound waves, light waves, or electromagnetic waves. Common forms of computer-readable media include, for example, floppy disks, floppy disks, hard disks, magnetic tapes, any other magnetic media, optical disc read-only memory (CD-ROM), rewritable optical disc (CD-RW), digital video disc (DVD), rewritable DVD (DVD-RW), any other optical media, punched cards, paper tape, optical marking paper, any other physical media with perforated patterns or other optically identifiable markings, random access memory (RAM), programmable read-only memory (PROM) and erasable programmable read-only memory (EPROM), FLASH-EPROM, any other memory chip or cassette, carrier wave, or any other medium from which information can be read by, for example, a controller / processor.

[0104] Figure 3 This is a plan view of a display panel according to an exemplary embodiment.

[0105] Reference Figure 3The display panel 210 may include a substrate layer BS, multiple pixels PX, multiple signal lines GL, DL and PL, and multiple display pads PDD.

[0106] The effective area AA of the display panel 210 is the area where the image is displayed, and the peripheral area NAA can be the area where the driving circuit, driving line, etc. are installed. Figure 3 The effective area AA and the peripheral area NAA of the display panel 210 are shown. Multiple pixels PX can be set in the effective area AA.

[0107] The substrate layer BS can be a stacked structure including a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or multiple insulating layers.

[0108] The substrate layer BS can include a first region AR1, a second region AR2, and a third region AR3. When viewed in a planar view, the second region AR2 can surround the first region AR1, and the third region AR3 can surround the second region AR2. The first region AR1, the second region AR2, and the third region AR3 can be surrounded by an outer region NAA. Multiple pixels PX can be set on the third region AR3. That is, the third region AR3 can correspond to the effective region AA.

[0109] When viewed in a plan view, at least a portion of the first region AR1 may be an area superimposed on the sensing region SA. The module aperture MH may be defined within at least a portion of the first region AR1. That is, components of the display panel 210 may be removed from the area corresponding to the sensing region SA, or may be configured not to superimpose on the sensing region SA. When viewed in a plan view, the first region AR1 may surround the module aperture MH. Structures such as recesses or dams for blocking the permeation path of external moisture or oxygen may be provided on the first region AR1, which will be described later.

[0110] The pixels PX providing the image may not be located on the first region AR1 and the second region AR2 of the substrate layer BS. Therefore, in the display panel 210, the area including the first region AR1 and the second region AR2 of the substrate layer BS can be defined as a non-display area. Multiple pixels PX can be located on the third region AR3 of the substrate layer BS. Therefore, the area including the third region AR3 of the substrate layer BS can be defined as a display area. That is, the display area of ​​the display panel 210 can correspond to the third region AR3 of the substrate layer BS, and the non-display area of ​​the display panel 210 can correspond to the first region AR1 and the second region AR2 of the substrate layer BS.

[0111] According to an exemplary embodiment, when viewed in a plan view, a non-display area surrounded by the display area can be provided. The non-display area may be adjacent to the electronic module 500 (see...). Figure 1BThe overlapping area. Therefore, the separate area set up to provide a sensing area on the periphery of the display area can be omitted, thus reducing the area of ​​the border area. The border area can represent the area surrounding the display area.

[0112] Multiple signal lines GL, DL, and PL are connected to pixel PX, and electrical signals are transmitted to pixel PX. Among the signal lines included in display panel 210, scan line GL, data line DL, and power line (hereinafter also referred to as power line) PL are exemplarily shown. However, this is exemplary, and signal lines GL, DL, and PL may also include at least any one of initial voltage lines and light-emitting lines, and the exemplary embodiments are not limited to any one embodiment.

[0113] Multiple signal lines GL, DL, and PL can be set on the second area AR2 and the third area AR3. Multiple signal lines GL, DL, and PL do not need to be set on the first area AR1.

[0114] In this embodiment, an enlarged and exemplary equivalent circuit diagram of a single pixel PX among a plurality of pixels PX is shown. Pixel PX may include a first transistor TR1, a capacitor CP, a second transistor TR2, and a light-emitting element ELD. The first transistor TR1 may be a switching element that controls the on-off state of pixel PX. The first transistor TR1 may respond to a scan signal transmitted via scan line GL and transmit or block data signals transmitted via data line DL.

[0115] Capacitor CP is connected to the first transistor TR1 and the power line PL. Capacitor CP is charged with an amount of charge corresponding to the difference between the data signal transmitted from the first transistor TR1 and the first power supply signal applied to the power line PL.

[0116] The second transistor TR2 is connected to the first transistor TR1, the capacitor CP, and the light-emitting element ELD. The second transistor TR2 controls the drive current flowing through the light-emitting element ELD in accordance with the amount of charge stored in the capacitor CP. The on-time of the second transistor TR2 can be determined based on the amount of charge charged into the capacitor CP. During the on-time, the second transistor TR2 provides the light-emitting element ELD with a first power signal transmitted via the power line PL.

[0117] Light-emitting diodes (ELDs) can generate light and control the amount of light in response to electrical signals. For example, ELDs can include organic light-emitting elements or quantum dot light-emitting elements.

[0118] The light-emitting element ELD is connected to the power supply terminal VSS and receives a power signal (hereinafter referred to as the second power signal) that is different from the first power signal provided through the power line PL. A drive current corresponding to the difference between the first power signal and the second power signal provided from the second transistor TR2 flows through the light-emitting element ELD, and the light-emitting element ELD can generate light corresponding to the drive current. Meanwhile, this is illustrated exemplaryly; the pixel PX may include electronic components with various configurations and arrays, and the exemplary embodiments are not limited to any one embodiment.

[0119] A power pattern VDD is disposed in the peripheral area NAA. In this embodiment, the power pattern VDD is connected to multiple power lines PL. Therefore, the display panel 210 includes the power pattern VDD so that it can provide substantially the same first power signal to multiple pixels PX.

[0120] The display pad PDD may include a first pad D1 and a second pad D2. Multiple first pads D1 may be provided and connected to a data line DL. The second pad D2 may be connected to a power pattern VDD and electrically connected to a power line PL. The display panel 210 can provide externally supplied electrical signals to the pixels PX via the display pad PDD. In addition to the first pads D1 and the second pads D2, the display pad PDD may also include pads for receiving other electrical signals, but the exemplary embodiments are not limited to any one embodiment.

[0121] Figure 4 This is a plan view of the input sensing unit according to an exemplary embodiment.

[0122] Reference Figure 4 The input sensing unit 220 can be disposed on the display panel 210. For example, the input sensing unit 220 can be directly disposed on the display panel 210, or it can be attached to the display panel 210 by means of an adhesive component. When forming the display panel 210 (see...) Figure 1B When the input sensing unit 220 is formed through a continuous process, the input sensing unit 220 can be referred to as an input sensing layer. Alternatively, when the input sensing unit 220 is bonded to the display panel 210 by an adhesive member, the input sensing unit 220 can be referred to as an input sensing panel.

[0123] The input sensing unit 220 includes a first sensing electrode TE1, a second sensing electrode TE2, multiple sensing lines TL1, TL2 and TL3, and multiple sensing pads PDT.

[0124] The first sensing electrode TE1 and the second sensing electrode TE2 are disposed in the effective region AA. The input sensing unit 220 can obtain information about the external input TC (see figure) by the change in capacitance between the first sensing electrode TE1 and the second sensing electrode TE2. Figure 1A (information).

[0125] The first sensing electrode TE1 may include a first sensing pattern SP1 and a first connection pattern BP1. At least one first connection pattern BP1 may be connected to two adjacent first sensing patterns SP1. The second sensing electrode TE2 may include a second sensing pattern SP2 and a second connection pattern BP2. At least one second connection pattern BP2 may be connected to two adjacent second sensing patterns SP2.

[0126] Sensing lines TL1, TL2, and TL3 are disposed in the peripheral area NAA. Sensing lines TL1, TL2, and TL3 may include a first sensing line TL1, a second sensing line TL2, and a third sensing line TL3.

[0127] A first sensing line TL1 is connected to a first sensing electrode TE1. A second sensing line TL2 is connected to one end of a second sensing electrode TE2. A third sensing line TL3 is connected to the other end of the second sensing electrode TE2. The other end of the second sensing electrode TE2 may be a portion of the end facing the first end of the second sensing electrode TE2.

[0128] According to an exemplary embodiment, the second sensing electrode TE2 can be connected to the second sensing line TL2 and the third sensing line TL3. Therefore, sensitivity can be maintained uniformly relative to the region of the second sensing electrode TE2, which has a relatively larger length than the first sensing electrode TE1. Meanwhile, this is illustrated exemplaryly, and the third sensing line TL3 can be omitted, and the exemplary embodiment is not limited to any one embodiment.

[0129] A sensing pad PDT is disposed on the peripheral area NAA. The sensing pad PDT may include a first sensing pad T1, a second sensing pad T2, and a third sensing pad T3. The first sensing pad T1 is connected to a first sensing line TL1, thereby being electrically connected to a first sensing electrode TE1. The second sensing pad T2 is connected to a second sensing line TL2, and the third sensing pad T3 is connected to a third sensing line TL3. Therefore, the second sensing pad T2 and the third sensing pad T3 are electrically connected to a second sensing electrode TE2.

[0130] A portion of the input sensing unit 220 can be removed from the area corresponding to the sensing area SA. For example, a portion of the first sensing electrode TE1 and a portion of the second sensing electrode TE2 may not be disposed in the sensing area SA. In this embodiment, the first sensing electrode TE1, which is configured to overlap with the sensing area SA, includes a first sensing pattern that includes a shape with the removed portion, and the second sensing electrode TE2 may include a second sensing pattern that includes a shape with the removed portion.

[0131] According to an exemplary embodiment, portions of the sensing electrodes TE1 and TE2 in the region overlapping with the sensing region SA can be removed, thereby preventing the electronic module 500 (see Figure 1B This addresses the issue of the sensor being blocked by either the first sensing electrode TE1 or the second sensing electrode TE2. Therefore, the sensitivity of the electronic module 500 can be improved.

[0132] Figure 5 This is a cross-sectional view of a display panel according to an exemplary embodiment. Figure 6 This is a cross-sectional view of a display panel according to an exemplary embodiment. Figure 5 This is a cross-sectional view of the display panel 210, including the third region AR3 of the substrate layer BS. Figure 6 It is a cross-sectional view of the display panel 210 including the first region AR1 and the second region AR2 of the substrate layer BS.

[0133] Reference Figure 5 and Figure 6 The first insulating layer 10 is disposed on the substrate layer BS. The first insulating layer 10 may include a barrier layer 11 and a buffer layer 12.

[0134] The barrier layer 11 may include inorganic materials. The barrier layer 11 prevents oxygen or moisture introduced through the substrate layer BS from penetrating into the pixel PX (see...). Figure 3 In the buffer layer 12, inorganic materials may be included. The buffer layer 12 can provide the pixel PX with a lower surface energy than the substrate layer BS, so that the pixel PX can be stably formed on the substrate layer BS. Figure 5 Each of the barrier layer 11 and buffer layer 12 is shown as a single layer. However, this is an exemplary illustration, and the barrier layer 11 and buffer layer 12 according to the exemplary embodiment may be multiple and may also be stacked alternately on top of each other. Alternatively, at least any one of the barrier layer 11 and buffer layer 12 may be multiple, or may be omitted.

[0135] Each pixel PX (see Figure 3 It can include pixel circuits and light-emitting elements (ELDs). Pixel circuits can include transistors (TRs), capacitors, etc. Figure 5 The diagram shows only one transistor TR. The transistor TR can be... Figure 3 The second transistor TR2 is described in the text.

[0136] A transistor TR can be disposed on a first insulating layer 10. The transistor TR includes a semiconductor pattern SP, a control electrode CE, an input electrode IE, and an output electrode OE. The semiconductor pattern SP is disposed on the first insulating layer 10. The semiconductor pattern SP may include a semiconductor material. The control electrode CE is separated from the semiconductor pattern SP, and a second insulating layer 20 is disposed between the control electrode CE and the semiconductor pattern SP. The control electrode CE can be connected to... Figure 3 The first transistor TR1 and one electrode of capacitor CP are described in the figure.

[0137] The input electrode IE and output electrode OE are separated from the control electrode CE, and the third insulating layer 30 and the fourth insulating layer 40 are disposed between the input electrode IE and output electrode OE and the control electrode CE. The input electrode IE and output electrode OE penetrate the second insulating layer 20, the third insulating layer 30 and the fourth insulating layer 40, and are respectively connected to one side and the other side of the semiconductor pattern SP.

[0138] The upper electrode UE can be disposed between the third insulating layer 30 and the fourth insulating layer 40. The upper electrode UE can be connected to Figure 3 The other electrode of the capacitor CP described in the text.

[0139] A fifth insulating layer 50 is disposed on the fourth insulating layer 40 and covers the input electrode IE and the output electrode OE. The fourth insulating layer 40 may include organic and / or inorganic materials and may have a single-layer structure or a multilayer structure.

[0140] The connecting electrode CNE can be disposed on the fifth insulating layer 50. The connecting electrode CNE can be connected to the output electrode OE. The sixth insulating layer 60 can be disposed on the connecting electrode CNE.

[0141] The transistor TR according to the exemplary embodiments can be formed in various structures, and the exemplary embodiments are not limited to... Figure 5 The embodiments shown are illustrated in the figure.

[0142] A light-emitting element (ELD) is disposed on a sixth insulating layer 60. The light-emitting element (ELD) may include a first electrode E1, a light-emitting layer EL, and a second electrode E2. The first electrode E1 can penetrate the sixth insulating layer 60 and is electrically connected to the transistor TR through a connecting electrode CNE.

[0143] A seventh insulating layer 70 may be disposed on the sixth insulating layer 60. An opening is defined in the seventh insulating layer 70, and the opening can expose at least a portion of the first electrode E1. The seventh insulating layer 70 may be a pixel defining film.

[0144] The light-emitting layer EL can be disposed on the first electrode E1 exposed through an opening defined in the seventh insulating layer 70. The light-emitting layer EL can include a light-emitting material. For example, the light-emitting layer can be composed of at least any one of materials that emit red, green, and blue light. The light-emitting layer EL can include a fluorescent or phosphorescent material. The light-emitting layer EL can include an organic or inorganic light-emitting material. The light-emitting layer EL can emit light in response to the potential difference between the first electrode E1 and the second electrode E2.

[0145] The second electrode E2 can be disposed on the light-emitting layer EL. The second electrode E2 can have a region extending from the effective region AA (see...). Figure 3 ) extends to the outer NAA region (see Figure 3 The second electrode E2 can target multiple pixels PX (see...) in a single shape. Figure 3 The light-emitting element ELD on each pixel PX receives a common second power supply voltage through the second electrode E2.

[0146] The second electrode E2 may comprise a transmissive conductive material or a semi-transmissive conductive material. Therefore, light generated from the light-emitting layer EL can be readily emitted onto the third-party DR3 via the second electrode E2. However, this is an exemplary illustration; the light-emitting element ELD according to the exemplary embodiment may be driven in a rear-surface emission mode where the first electrode E1 comprises a transmissive or semi-transmissive material, or in a bi-surface emission mode where light is emitted toward both the front and rear surfaces, and the exemplary embodiment is not limited to any one of these embodiments.

[0147] An eighth insulating layer 80 is disposed on and encapsulates the light-emitting element ELD. In this embodiment, the eighth insulating layer 80 may be an encapsulation layer. The eighth insulating layer 80 may have a layer extending from the effective region AA (see...). Figure 3 ) extends to the outer NAA region (see Figure 3 The shape is integral. At the same time, although not shown, the cover layer covering the second electrode E2 may be further disposed between the second electrode E2 and the eighth insulating layer 80.

[0148] The eighth insulating layer 80 may include a first inorganic layer 81, an organic layer 82, and a second inorganic layer 83 sequentially stacked on the third-direction DR3. In this embodiment, the first inorganic layer 81, the organic layer 82, and the second inorganic layer 83 are all shown as single layers. However, this is an exemplary illustration, and at least any one of the first inorganic layer 81, the organic layer 82, and the second inorganic layer 83 may be multiple or omitted, and the exemplary embodiments are not limited to any one embodiment.

[0149] The first inorganic layer 81 may cover the second electrode E2. The first inorganic layer 81 can prevent external moisture and oxygen from penetrating into the light-emitting element ELD. For example, the first inorganic layer 81 may include silicon nitride, silicon oxide, or a mixture thereof. The first inorganic layer 81 may be formed by a deposition process.

[0150] The organic layer 82 may be disposed on and in contact with the first inorganic layer 81. The organic layer 82 may provide a flat surface on the first inorganic layer 81. Specifically, the organic layer 82 may provide a flat surface for the effective area AA.

[0151] Uneven areas formed on the first inorganic layer 81, particles present on the first inorganic layer 81, etc., can be covered by the organic layer 82, and the influence of the surface state from the upper surface of the first inorganic layer 81 on the components formed on the organic layer 82 can be prevented. Additionally, the organic layer 82 can alleviate stress between contact layers. The organic layer 82 may include organic materials and can be formed by solution processes such as spin coating, slot coating, or inkjet printing.

[0152] A second inorganic layer 83 is disposed on and covers the organic layer 82. The second inorganic layer 83 can be formed more stably on a relatively flat surface than when formed on the first inorganic layer 81. The second inorganic layer 83 encapsulates moisture and the like released from the organic layer 82 and prevents moisture and the like from flowing to the outside. The second inorganic layer 83 may comprise silicon nitride, silicon oxide, or a mixture thereof. The second inorganic layer 83 can be formed by a deposition process.

[0153] Reference Figure 6 The grooves GV1, GV2, and GV3 can be defined in the first region AR1 of the substrate layer BS near the module hole MH. Additionally, the dam section DMP can be disposed on the first region AR1 of the substrate layer BS.

[0154] Each of the recesses GV1, GV2, and GV3 can be defined as being recessed from the upper surface of the substrate layer BS. Each of the recesses GV1, GV2, and GV3 can be formed such that at least a portion of the substrate layer BS is removed. A deposition pattern ELP can be disposed on each of the recesses GV1, GV2, and GV3, and the deposition pattern ELP can be covered by at least any one of the first inorganic layer 81 and the second inorganic layer 83.

[0155] The display panel 210 according to an exemplary embodiment also includes recesses GV1, GV2, and GV3, thereby blocking the continuity between the deposited pattern ELP and the light-emitting element ELD. Therefore, it blocks the penetration path of external moisture or oxygen and prevents damage to the effective area AA (see Figure 3 Damage to components in ().

[0156] Furthermore, the deposited pattern ELP disposed on each of the recesses GV1, GV2, and GV3 is covered by a first inorganic layer 81 or a second inorganic layer 83, thereby preventing the influence of the deposited pattern ELP on other components during the manufacturing of the display panel 210. Therefore, the process reliability of the display panel 210 can be improved. However, this is an exemplary illustration; in the display panel 210 according to the exemplary embodiment, the recesses GV1, GV2, and GV3 may be provided as a single recess or omitted, and the exemplary embodiment is not limited to any one embodiment.

[0157] The recesses GV1, GV2, and GV3 can be defined as being spaced apart from each other. The recesses GV1, GV2, and GV3 are exemplarily shown as a first recess GV1, a second recess GV2, and a third recess GV3 formed sequentially in a direction adjacent to the module aperture MH, separated from the second region AR2. Each of the first recess GV1, the second recess GV2, and the third recess GV3 may have a closed linear shape surrounding the module aperture MH, or it may have a discontinuous linear shape surrounding at least a portion of the periphery of the module aperture MH, and the exemplary embodiments are not limited to any one embodiment.

[0158] A dam section DMP is disposed on the first region AR1, such that the formation area of ​​the organic layer 82 is confined within a predetermined area, and further expansion of the organic layer 82 is prevented. Multiple dam section DMPs can be provided and disposed between the recesses GV1, GV2, and GV3. The dam section DMP is shown as a stacked structure comprising a first layer P11, a second layer P12, and a third layer P13. However, this is merely an example; the dam section DMP can also have a single-layer structure, and the exemplary embodiments are not limited to any one embodiment.

[0159] A cover layer FL may be disposed on the first region AR1. For example, the cover layer FL may cover the non-flat surface formed by the dam portion DMP or the recess portions GV1, GV2 and GV3 to provide a flat surface FL_SH. The flat surface FL_SH defined by the cover layer FL may define a plane that is substantially the same as the flat surface 80_S defined by the eighth insulating layer 80.

[0160] The display panel 210 may also include a metal pattern MTL. The metal pattern MTL may be disposed on the first region AR1. The metal pattern MTL may be disposed along the periphery of the module hole MH and cover at least a portion of the cover layer FL. When the module hole MH is formed, the metal pattern MTL can prevent the cover layer FL from being damaged by lasers or the like. In addition, the metal pattern MTL can press down on the cover layer FL, thereby preventing the cover layer FL from floating up.

[0161] Signal lines SLa, SLb, SLc, and SLd can be disposed on the second region AR2 of the substrate layer BS. Signal lines SLa, SLb, SLc, and SLd can include a first line SLa, a second line SLb, a third line SLc, and a fourth line SLd. Some of the signal lines SLa, SLb, SLc, and SLd can be scan lines GL (see...). Figure 3 Other options could be data cables (DL) (see...) Figure 3 For example, the first line SLa and the second line SLb can be scan lines GL, and the third line SLc and the fourth line SLd can be data lines DL.

[0162] The first wire SLa can be disposed between the second insulating layer 20 and the third insulating layer 30. The first wire SLa can be disposed on the same layer as the control electrode CE. The second wire SLb can be disposed between the third insulating layer 30 and the fourth insulating layer 40. The second wire SLb can be disposed on the same layer as the upper electrode UE. The third wire SLc can be disposed between the fourth insulating layer 40 and the fifth insulating layer 50. The third wire SLc can be disposed on the same layer as the output electrode OE and the input electrode IE. The fourth wire SLd can be disposed between the fifth insulating layer 50 and the sixth insulating layer 60. The fourth wire SLd can be disposed on the same layer as the connection electrode CNE.

[0163] Figure 7 This is a cross-sectional view of a display panel according to an exemplary embodiment. Figure 7 This is a cross-sectional view of the display panel 210-1, including the first region AR1 and the second region AR2 of the substrate layer BS. (In the description...) Figure 7 When, the description will be related to Figure 6 The parts that are different from each other, and Figure 6 The same components described herein are indicated by the same reference numerals and will not be described repeatedly.

[0164] Reference Figure 7 The display panel 210-1 may include a substrate layer BS-1 and an encapsulation substrate 80-1.

[0165] The encapsulation substrate 80-1 can be disposed on the second electrode E2. The encapsulation substrate 80-1 and the second electrode E2 can be separated from each other. The space GAP located between the encapsulation substrate 80-1 and the second electrode E2 can be filled with air or an inert gas. Alternatively, in an exemplary embodiment, the space GAP can also be filled with a filler material such as a silicone polymer, epoxy resin, or acrylic resin.

[0166] The encapsulation substrate 80-1 can be bonded to the substrate layer BS-1 via the sealing member PSL. The encapsulation substrate 80-1 can be disposed on the substrate layer BS-1, while maintaining a predetermined gap via the sealing member PSL.

[0167] The sealing member PSL can be an assembly that defines the inner surface of the module hole MH. The sealing member PSL can include organic materials such as light-curable resins and thermoplastic resins, or inorganic materials such as frit seals, and exemplary embodiments are not limited to any one embodiment.

[0168] Figure 8 It is shown Figure 3 The enlarged plan view of region XX' shown in the figure.

[0169] Reference Figure 8The substrate layer BS may include a first region AR1, a second region AR2, and a third region AR3. The module hole MH may be confined within the first region AR1. Therefore, the first region AR1 may surround the periphery of the module hole MH. The second region AR2 may surround the first region AR1. The third region AR3 may surround the second region AR2.

[0170] A first signal line section SLP1 and a second signal line section SLP2 can be provided on the second region AR2 and the third region AR3. The data line DL that passes through the second region AR2 can be referred to as the first signal line section SLP1, and the scan line GL that passes through the second region AR2 can be referred to as the second signal line section SLP2. That is, each of the first signal line section SLP1 and the second signal line section SLP2 can be provided on the second region AR2 and the third region AR3, respectively.

[0171] The first signal line portion SLP1 can be arranged in the first direction DR1 to be separated from each other, and the second signal line portion SLP2 can be arranged in the second direction DR2 to be separated from each other.

[0172] The boundary BD between the first region AR1 and the second region AR2 can have a circular shape. A portion of each of the first signal line portion SLP1 and the second signal line portion SLP2 (the portion is disposed on the second region AR2) can extend correspondingly to the shape of the boundary BD.

[0173] Each first signal line segment SLP1 may include a first connection segment CEP1, and each second signal line segment SLP2 may include a second connection segment CEP2. The first connection segment CEP1 and the second connection segment CEP2 can reduce the amount of charge accumulated on each of the first signal line segments SLP1 and SLP2. Therefore, during electrostatic discharge testing, the peak current appearing in the first signal line segments SLP1 and SLP2 can be reduced. Therefore, the impact on the display panel 210 (see...) can be reduced. Figure 3 This could cause electrical damage.

[0174] Each of the first connecting portion CEP1 and the second connecting portion CEP2 can be configured as multiple. A portion of the first connecting portion CEP1 can be disposed on the second region AR2, and another portion can be disposed on the third region AR3. Similarly, a portion of the second connecting portion CEP2 can be disposed on the second region AR2, and another portion can be disposed on the third region AR3. According to an exemplary embodiment, since a portion of the first connecting portion CEP1 and a portion of the second connecting portion CEP2 are disposed on the second region AR2, the area of ​​the unused space around the module hole MH can be reduced. The unused space can include a portion of the second region AR2 and the third region AR3. For example, a portion of the third region AR3 can be an area where no pixel PX is disposed.

[0175] Pixels PX can be set to multiple, and can be referred to as pixels PX in the following text.

[0176] One pixel PX can be electrically connected to a scan line GL and a data line DL. Another pixel PX can be electrically connected to one of the first signal lines SLP1 and a scan line GL. Yet another pixel PX can be electrically connected to one of the second signal lines SLP2 and a data line DL. And yet another pixel PX can be electrically connected to one of the first signal lines SLP1 and one of the second signal lines SLP2.

[0177] Figure 9 Is with Figure 8 The image shown is a photograph of the region corresponding to area YY'.

[0178] Reference Figure 3 and Figure 9 The third region AR3 may include a main region MAA and a peripheral region PAA. Pixel PX may be set on the main region MAA, or it may not be set on the peripheral region PAA. The first connecting part CEP1 and the second connecting part CEP2 (see...) Figure 8 The image can be set on the peripheral area PAA. The peripheral area PAA and the area of ​​the display panel 210 corresponding to the second area AR2 are areas where no image is displayed, and can be defined as invalid space.

[0179] According to an exemplary embodiment, since a portion of the first connecting portion CEP1 and a portion of the second connecting portion CEP2 are disposed on the second region AR2, the width of the peripheral region PAA can be reduced. Therefore, the area of ​​the unused space can be reduced.

[0180] Figure 10 It is shown that... Figure 9 A schematic plan view of the area corresponding to region ZZ'. Figure 11 It is along Figure 10 The sectional view taken by section line I-I'. Figure 12 It is along Figure 10 The sectional view taken along section line II-II'. For ease of description, in Figure 10 , Figure 11 and Figure 12 Some components have been omitted.

[0181] Reference Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 The first signal line portion SLP1 can be divided into a first signal line portion SLP1a and a first signal line portion SLP1b. Each of the first signal line portions SLP1a and SLP1b can be configured as multiple, and the first signal line portions SLP1a and SLP1b can be arranged alternately in the first direction DR1.

[0182] The first signal line portion SLP1a may include a first line LN1a, a second line LN2a, and a first connecting portion CEP1a. The first line LN1a and the second line LN2a may be separated from each other. The first line LN1a and the second line LN2a may not be directly connected to each other. The expression "not directly connected" can mean "not in direct contact." The first line LN1a and the second line LN2a may be electrically connected to each other through the first connecting portion CEP1a.

[0183] Figure 11 This corresponds to the cross-sectional view of the first signal line portion SLP1a. The first line LN1a and the second line LN2a can be disposed on the same layer. For example, the first line LN1a and the second line LN2a can be disposed between the fourth insulating layer 40 and the fifth insulating layer 50. That is, the first line LN1a and the second line LN2a can constitute... Figure 6 The third line SLc is shown in the figure.

[0184] The first connecting portion CEP1a may be disposed on the fifth insulating layer 50. The first connecting portion CEP1a may penetrate the fifth insulating layer 50 and be connected to each of the first wire LN1a and the second wire LN2a.

[0185] The first signal line portion SLP1b may include a first line LN1b, a second line LN2b, and a first connection portion CEP1b. The first line LN1b and the second line LN2b may be separated from each other and disposed on different layers. The first line LN1b and the second line LN2b may be electrically connected to each other through the first connection portion CEP1b.

[0186] Figure 12This can correspond to the cross-sectional view of the first signal line portion SLP1b. The first line LN1b can be disposed between the fifth insulating layer 50 and the sixth insulating layer 60, and the second line LN2b can be disposed between the fourth insulating layer 40 and the fifth insulating layer 50. The first line LN1b can be configured as follows: Figure 6 The fourth line SLd and the second line LN2b shown can be constructed Figure 6 The third line SLc is shown in the figure.

[0187] The first connection portion CEP1b may be disposed on the same layer as the first line LN1b and may extend from the first line LN1b. In another exemplary embodiment, the first connection portion CEP1b may be disposed on the same layer as the second line LN2b and may extend from the second line LN2b. The first signal line portion SLP1b may also include a dummy pattern D-LN2b. The dummy pattern D-LN2b may be disposed on the same layer as the second line LN2b. The dummy pattern D-LN2b may be electrically connected to the first connection portion CEP1b. In addition, in another exemplary embodiment, the dummy pattern D-LN2b may be omitted or may be connected to the second line LN2b.

[0188] Refer again Figure 10 The connecting portions CEP1a and CEP1b can be configured to be separated from each other in the first direction DR1. At least three of the closest first connecting portions CEP1a and CEP1b can be stacked on top of each other in the first direction DR1.

[0189] Furthermore, a portion of the first connecting portions CEP1a and CEP1b can be designated as the overlay connecting portion CEP-O, and another portion can be designated as the non-overlay connecting portion CEP-NO. At least a portion of the overlay connecting portion CEP-O can be overlaid with the second region AR2. The overlay connecting portion CEP-O can be overlaid with at least a portion of the second signal line portion SLP2. The non-overlay connecting portion CEP-NO may not be overlaid with the second region AR2. That is, the non-overlay connecting portion CEP-NO can be located on the third region AR3.

[0190] Each of the stacked connection CEP-O and the non-stacked connection CEP-NO can be configured as multiple, and each of the stacked connection CEP-O and the non-stacked connection CEP-NO can be arranged to be separated from each other in the first direction DR1.

[0191] Figure 13 It is shown Figure 8 The enlarged plan view of region KK' shown in the figure. Figure 14 It is along Figure 13 The sectional view taken by section line III-III'.

[0192] Reference Figure 13 and Figure 14 The second signal line section SLP2 can be divided into a second signal line section SLP2a and a second signal line section SLP2b. Each of the second signal line sections SLP2a and SLP2b can be configured as multiple, and can be arranged alternately in the second direction DR2.

[0193] The second signal line section SLP2a may include a third line LN3a, a fourth line LN4a, and a second connecting section CEP2a. The third line LN3a and the fourth line LN4a may be separated from each other. The third line LN3a and the fourth line LN4a may not be directly connected to each other. The second signal line section SLP2b may include a third line LN3b, a fourth line LN4b, and a second connecting section CEP2b. The third line LN3b and the fourth line LN4b may be separated from each other. The third line LN3b and the fourth line LN4b may not be directly connected to each other.

[0194] The third wire LN3a can be disposed between the third insulating layer 30 and the fourth insulating layer 40, and can form a... Figure 6 The second wire SLb is described in the text. The fourth wire LN4a can be disposed between the second insulating layer 20 and the third insulating layer 30, and can form... Figure 6 The first line SLa is described in the diagram. The third line LN3b can constitute the first line SLa, and the fourth line LN4b can constitute the second line SLb. When viewed in a plan view, the second connecting parts CEP2a and CEP2b can be superimposed on the first signal line part SLP1.

[0195] Figure 15 Is with Figure 8 The image shown is a photograph of the region corresponding to area YY'. Figure 16 It is shown that... Figure 15 A schematic plan view of the area corresponding to region LL'.

[0196] Reference Figure 15 and Figure 16 A portion of the first connecting portions CEP1a and CEP1b can be designated as the overlay connecting portion CEP-O, and another portion can be designated as the non-overlay connecting portion CEP-NO. The overlay connecting portion CEP-O can be overlaid with the second region AR2. The overlay connecting portion CEP-O can be overlaid with at least a portion of the second signal line portion SLP2. The non-overlay connecting portion CEP-NO may not be overlaid with the second region AR2. That is, the non-overlay connecting portion CEP-NO can be located on the third region AR3.

[0197] The second signal line portion SLP2 located on the surface where the stacked connection portion CEP-O is provided can cause unevenness. Residue is retained in the unevenness during the formation of the stacked connection portion CEP-O. Adjacent stacked connection portions CEP-O can connect to each other through this residue, which can lead to operational defects in the display panel 210.

[0198] According to an exemplary embodiment, each of the overlapping connection portions CEP-O and the non-overlapping connection portions CEP-NO can be configured as multiple. The non-overlapping connection portions CEP-NO can be arranged in the first direction DR1 while being spaced apart from each other. The overlapping connection portions CEP-O can be arranged in a zigzag pattern relative to the virtual lines extending in the first direction DR1. That is, the overlapping connection portions CEP-O may not be arranged continuously in the predetermined direction. For example, when viewed in the first direction DR1, two adjacent overlapping connection portions CEP-O1 and CEP-O2 may not overlap each other. Therefore, the possibility that two overlapping connection portions CEP-O1 and CEP-O2 are connected to each other by residue can be reduced.

[0199] For example, the widths of the overlapping connection portions CEP-O1 and CEP-O2 are greater than the widths of the first lines LN1a and LN1b and the second lines LN2a and LN2b. The width refers to the width along the first direction DR1. According to an exemplary embodiment, the overlapping connection portions CEP-O1 and CEP-O2 are not continuously arranged along the first direction DR1. Therefore, the distance between adjacent first signal line portions SLP1a and SLP1b can be increased. Therefore, the phenomenon of adjacent first signal line portions SLP1a and SLP1b short-circuiting each other can be prevented.

[0200] In an exemplary embodiment, when viewed in the first direction DR1, at least a portion of each of the two adjacent overlapping connecting portions CEP-O1 and CEP-O2 may not overlap each other. That is, when viewed in the first direction DR1, at least other portions of the two adjacent overlapping connecting portions CEP-O1 and CEP-O2 may overlap each other. In this case, since the centers of the overlapping connecting portions CEP-O are not located on the same line (e.g., on a line extending in the first direction DR1), the possibility of the overlapping connecting portions CEP-O being connected by residue can be reduced.

[0201] Figure 17 It is shown Figure 3 The enlarged plan view of region XX' shown in the figure. Figure 18 It is among them and Figure 17 The image is the region corresponding to region MM' that is imaged. Figure 19 It is shown that... Figure 18A schematic planar diagram of the region corresponding to region NN'.

[0202] Reference Figure 17 , Figure 18 and Figure 19 When with Figure 8 In comparison, the positions of the first connecting part CEP1 and the second connecting part CEP2 are different.

[0203] The first connection portion CEP1 may not be superimposed on the second signal line portion SLP2, and the second connection portion CEP2 may not be superimposed on the first signal line portion SLP1. For example, each of the first connection portion CEP1 and the second connection portion CEP2 may not be provided on the second region AR2, but on the third region AR3. Figure 20 This is an exploded perspective view of a display device according to an exemplary embodiment. In the description Figure 20 When, the description will be related to Figure 1B The parts that are different from each other, and Figure 1B The same components described herein are indicated by the same reference numerals and will not be described repeatedly.

[0204] Reference Figure 20 The display device EA-T may include a window 100, a display module 200-T, a driving circuit section 300-T, a housing 400, and an electronic module 500.

[0205] The driving circuit section 300-T may include a main circuit board MB and a flexible film CF. The display module 200-T may be divided into a first module area MD1, a second module area MD2, and a third module area MD3. The first module area MD1 may be... Figure 3 The first region AR1 of the substrate layer BS shown in the figure corresponds to the region, the second module region MD2 can be the region corresponding to the second region AR2 of the substrate layer BS, and the third module region MD3 can be the region corresponding to the third region AR3 of the substrate layer BS.

[0206] When viewed in a plan view, the first module region MD1 can be an area superimposed on the electronic module 500. The transmittance of the first module region MD1 can be higher than that of the third module region MD3. To improve the transmittance of the first module region MD1, certain components may not be located in the first module region MD1. For example, an avoidance design can be implemented such that signal lines GL, DL, and PL (see...) Figure 3 At least a portion of the components constituting the display module 200-T may not be superimposed on the first module region MD1. Additionally, at least a portion of the components constituting the display module 200-T may not be located in the first module region MD1. For example, the first electrode E1 (see...) Figure 5 ), second electrode E2 (see Figure 5 ), light-emitting element ELD (see Figure 5 ), transistor TR (see Figure 5 ), first sensing electrode TE1 (see Figure 4 ) or the second sensing electrode TE2 (see Figure 4 At least one of them may not be set in the first module area MD1.

[0207] Therefore, the electronic module 500, which is configured to be superimposed on the first module region MD1, can easily view external objects through the first module region MD1, or the output signal generated by the electronic module 500 can be easily transmitted to the outside.

[0208] A display device according to an exemplary embodiment may include a substrate layer, a first signal line portion, and a second signal line portion. The substrate layer may include a first region in which neither the first nor the second signal line portion is disposed, a second region surrounding the first region, and a third region surrounding the second region. The first signal line portion may include a first connecting portion. A portion of the first connecting portion may overlap with a second signal line portion disposed on the second region. Therefore, the area of ​​unused space around the first region can be reduced. Furthermore, the first connecting portion overlapping the second region may be discontinuously disposed in a predetermined direction. Therefore, short-circuiting between adjacent first signal line portions can be prevented.

[0209] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and the various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A display device, the display device comprising: A substrate layer, including a first region in which a hole is defined, a second region surrounding the first region, and a third region surrounding the second region; A pixel is disposed on the third region of the substrate layer; Scan lines are electrically connected to at least some of the pixels and are disposed on the third and second regions of the substrate layer; as well as Data lines, electrically connected to at least some of the pixels and disposed on the third and second regions of the substrate layer, wherein: Each pixel includes a pixel circuit, a light-emitting element, and a connection electrode connecting the pixel circuit and the light-emitting element. The pixel circuit includes a transistor and a capacitor. The capacitor includes a first electrode disposed on a first layer and a second electrode disposed on a second layer above the first layer. The transistor includes a control electrode disposed on the first layer and an input electrode and an output electrode disposed on a third layer above the second layer. The connecting electrode is disposed on the fourth layer above the third layer. The scan line includes a first line portion disposed on the second region of the substrate layer and a second line portion disposed on the third region of the substrate layer. The data line includes a third wire portion disposed on the second region of the substrate layer, a fourth wire portion disposed on the third region of the substrate layer, and a connecting portion connecting the third wire portion and the fourth wire portion respectively. Some of the first line portions are disposed on the first layer, and the other first line portions are disposed on the second layer. Some of the third line portions are disposed on the third layer, and the other third line portions are disposed on the fourth layer. The connecting portion includes a first connecting portion arranged in a first direction and a second connecting portion arranged in the first direction, and When viewed from the first direction, the first connecting portion and the second connecting portion are spaced apart from each other in a second direction that intersects the first direction.

2. The display device according to claim 1, wherein, The connecting part is located on the fourth layer.

3. The display device according to claim 1, wherein, The fourth line is disposed on the third layer.

4. The display device according to claim 1, wherein, Each of the first and third line portions has a shape that surrounds at least a portion of the hole.

5. The display device according to claim 1, wherein, A portion of each of the first and third line portions is a curve.

6. The display device according to claim 1, wherein, Each of the second line portion and the fourth line portion is a straight line.

7. The display device according to claim 1, further comprising: The first dam is disposed on the substrate layer and surrounds at least a portion of the hole; The first groove and the second groove are recessed from the upper surface of the substrate layer and positioned on the substrate layer, such that the first dam is arranged on the substrate layer between the first groove and the second groove. as well as A second dam is disposed on the substrate layer and surrounds at least a portion of the hole, wherein the second dam is spaced apart from the first dam on the substrate layer, and a second groove is disposed between the first dam and the second dam.

8. The display device according to claim 7, wherein, When viewed in a plan view, the first line portion and the third line portion do not overlap with the second dam, and The distance between the first line portion and the third line portion and the hole is greater than the distance between the second dam and the hole.

9. The display device according to claim 7, wherein, The first dam and the second dam are arranged to be spaced apart from each other.

10. The display device according to claim 7, wherein, The first dam has a single-layer structure or a multi-layer structure comprising multiple layers, and wherein the height of the second dam is shorter than the height of the first dam.

11. The display device according to claim 1, wherein, Some of the first connecting portions do not overlap with the first line portion and the third line portion, while other first connecting portions overlap with the first line portion and the third line portion.

12. The display device according to claim 11, wherein, Some of the second connecting portions do not overlap with the first line portion and the third line portion, while other second connecting portions overlap with the first line portion and the third line portion.

13. The display device according to claim 1, wherein, The connecting portion does not overlap with the first line portion and the third line portion.

14. The display device according to claim 11, wherein, The third wire portion disposed on the third layer and the fourth wire portion disposed on the third layer are spaced apart from each other, and the third wire portion and the fourth wire portion are electrically connected through the connecting portion.

15. The display device according to claim 1, wherein, The number of the first connecting parts is greater than the number of the second connecting parts.

16. The display device according to claim 1, wherein, When viewed from the first direction, the second connecting portion is closer to the hole than the first connecting portion.

17. The display device according to claim 1, wherein, Each scan line in the scan line includes a first line portion in the first line portion and a second line portion in the second line portion that is electrically connected to the first line portion, and Each of the data lines includes a third line portion of the third line portion and a fourth line portion of the fourth line portion that is electrically connected to the third line portion.

18. The display device according to claim 1, further comprising: Normal scan lines are positioned on the third region and do not overlap with the second region. The normal data cable is positioned on the third area and does not overlap with the second area.

19. The display device according to claim 1, wherein, The first layer, the second layer, the third layer, and the fourth layer are defined along a direction away from the substrate layer.

20. The display device according to claim 1, wherein, The connecting portion includes an integral connecting portion and an independent connecting portion. The integral connecting portion extends from the third line portion disposed on the fourth layer and has a shape integral with the third line portion. The independent connecting portion contacts the third line portion disposed on the third layer.

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