Packaged electronic device comprising a plurality of power transistors

Abstract

The present application relates to a packaged electronic device comprising a plurality of power transistors. An electronic device comprises at least a first branch and a second branch, each branch comprising a first transistor and a second transistor arranged in series with each other and formed in a respective die of a semiconductor material. The dies are sandwiched between a first substrate element and a second substrate element. The first substrate element and the second substrate element are respectively formed from a multilayer structure comprising a first electrically conductive layer, a second electrically conductive layer and an insulating layer extending between the first electrically conductive layer and the second electrically conductive layer. The first electrically conductive layers of the first substrate element and the second substrate element face an outer side of the electronic device and define a first main face and a second main face of the electronic device. The second electrically conductive layers of the first substrate element and the second substrate element are shaped to form contact areas facing and selectively electrically contacting the plurality of dies.

Description

Technical Field

[0001] This disclosure relates to a packaged electronic device that includes a plurality of power transistors. Background Technology

[0002] For example, the circuit may include power devices that operate under high voltage (even up to 1200V) conditions and have rapidly switchable current, such as silicon carbide devices or silicon devices, such as superjunction MOSFETs, IGBTs and gallium nitride (GaN) devices.

[0003] For such circuits and power electronics, specific packages are required to allow for high heat dissipation. These packages are typically formed from an insulating rigid body (e.g., resin), usually in a parallelepiped shape, embedding one or more electronic components within them. They may include dissipative structures that contact the electronic components, facing the package surface and typically occupying a large portion of the long substrate of the parallelepiped shape. The dissipative structures are sometimes formed from the same metal support (called a "lead frame") that carries one or more dies integrating one or more electronic components and multiple leads for external connections. Typically, in this case, the lead frame has a surface directly facing the outside of the package.

[0004] For example, in the case of a packaged device including a silicon MOSFET transistor, the die of the integrated MOSFET transistor may have a drain pad on its first larger surface and at least two contact pads (a source pad and a gate pad, respectively) on a second larger surface opposite the first larger surface. The transistor contact pad (typically the drain pad) is attached to a leadframe support portion that is in direct contact with one or more leads. Other contact pads (typically the gate pad and source pad) are coupled to other leads via bonding wires or clips. Such standard packages typically have leads arranged on the same side of the dissipation structure and therefore typically allow downward dissipation.

[0005] Other devices (such as those including GaN) have different external arrangements of contacts, but still have a conductive back surface (forming the source contact) and front contact pads for other terminals. Summary of the Invention

[0006] This disclosure relates to a package that allows upward cooling (TSC - top-side cooling) due to a proper configuration of the leads and lead frame support portions. For example, Figure 1An integrated device 1 is shown, comprising two electronic components integrated into corresponding dies 2A and 2B and embedded in a packaged insulating mass 3 having a generally parallelepiped shape, as shown in the attribution. The integrated device 1 includes a leadframe 4 formed of a DBC (Direct Copper Bond) multilayer structure, comprising a first metallic conductive layer, an insulating layer made of ceramic, and a second metallic conductive layer.

[0007] Second metal conductive layer ( Figure 1 (See image) Two conductive portions 5A and 5B are formed, which are electrically separated to form corresponding contact portions for dies 2A and 2B, and are directly coupled to the corresponding drain pads (not visible) of dies 2A and 2B and coupled to leads 6. Other leads 7 are connected to the source and gate pads of dies 2A and 2B and any other contact pads via conductive areas 9 forming part of the lead frame 4 and possible wiring 8.

[0008] Conductive portions 5A, 5B, and 9 are thermally coupled to a heat dissipation region 10 formed by a first metallic conductive layer. Figure 2A The heat dissipation area 10 faces outward and is flush (e.g., coplanar) with the top of the encapsulated insulating mass block 3. However, due to the insulating layer, the conductive portions 5A, 5B, and 9 are electrically isolated relative to the heat dissipation area 10.

[0009] Using this type of package, different circuit and component topologies can be formed, such as Figures 3A to 3I As shown.

[0010] Integrated device 1 dissipates on one side and can be attached to a dissipation structure, such as... Figure 4 As schematically shown. Here, integrated device 1 is located in its junction with heat dissipation area 10 ( Figure 2A ) At the opposite surfaces through its leads 6, 7 (in Figure 4 The heat dissipation area 10 is attached to the support 15 (not visible in the image) such as a printed circuit board (PCB). Additionally, the heat dissipation area 10 is attached to the heat sink 16, for example, by a screw (17) to the support 15. In use, cooling fluid (air or liquid 18) flows in contact with the heat sink 16.

[0011] While allowing for effective cooling on one side, this solution is not optimal for electronics consisting of large components, such as MOSFET transistors with high power and high switching current and / or different topologies. In fact, in such cases, the packaged device will have a large, unsuitable overall size and still not adequate dissipation.

[0012] To overcome this problem, in Italian patent application 102019000013743 (corresponding to EP 3 780 100), this disclosure relates to a packaged power electronic device in which at least two power components are attached to corresponding electrically insulating and thermally conductive elements, such as DBC (directly bonded copper) substrates, and a thermal conductor (e.g., a third DBC) is interposed between the power components.

[0013] In this way, power electronic devices can be cooled on both sides, forming DSC (dual-sided cooling) devices that allow for high power consumption.

[0014] This solution is particularly well-suited for full-bridge circuits, where power components can be arranged in space such that some metal layers of the DBC form contact areas between the power components, and the outer metal layers can be exposed to the action of cooling fluid.

[0015] However, it is not easily applicable to other circuit topologies, such as inverters, and its thickness is not always acceptable in any case.

[0016] This disclosure aims to provide a packaging solution that overcomes the shortcomings discussed above.

[0017] At least one embodiment of the electronic device disclosed herein can be summarized as including at least a first branch and a second branch, each branch including a first transistor and a second transistor arranged in series with each other, the electronic device including a first substrate element, a second substrate element and a plurality of dies of semiconductor material, each die integrating a corresponding transistor between the first transistor and the second transistor, the dies being arranged side by side with each other and between the first substrate element and the second substrate element, wherein the first substrate element and the second substrate element each include a multilayer structure including a first conductive layer, a second conductive layer and an insulating layer, the insulating layer being disposed between the first conductive layer and the second conductive layer, the first conductive layer of the first substrate element and the second substrate element facing outwards of the electronic device and defining a first main surface and a second main surface of the electronic device, and the second conductive layer of the first substrate element and the second substrate element being shaped to form a contact region facing the plurality of dies and selectively electrically contacting the plurality of dies. Attached Figure Description

[0018] To better understand this disclosure, some embodiments thereof are now described by way of non-limiting example only with reference to the accompanying drawings, wherein:

[0019] Figure 1 It is a perspective top view of a known packaged electronic device with ghosting.

[0020] Figure 2A and Figure 2B They are Figure 1Perspective top and bottom views of packaged electronic devices;

[0021] Figures 3A to 3I It is shown that it can be implemented as Figure 1 The circuit topology of packaged electronic devices;

[0022] Figure 4 yes Figure 1 A schematic side view of the packaged electronic device connected to an external heat sink;

[0023] Figure 5 This is an electrical diagram of an inverter circuit that can be packaged in a dual-cooled package, thus forming one embodiment of this electronic device;

[0024] Figure 6 It can be used Figure 5 A simplified cross-section of the MOSFET transistor in the inverter circuit;

[0025] Figure 7 It can be used Figure 5 A simplified cross-section of another MOSFET transistor in the inverter circuit;

[0026] Figure 8A This is a side view of an embodiment of the electronic device prior to packaging, the electronic device including... Figure 6 The type of MOSFET transistor shown;

[0027] Figure 8B yes Figure 8A A top schematic representation of the arrangement of components and connection areas of an electronic device;

[0028] Figure 9A and 9B These are the cases after packaging when the leads are formed into protruding pins. Figure 8A Perspective top view and perspective bottom view of electronic components;

[0029] Figure 10A This is in an embodiment with lateral leads. Figure 8A A perspective top view of the lower part of the electronic device;

[0030] Figure 10B Is Figure 10A In the implementation method Figure 8A A perspective bottom view of the upper part of the electronic device;

[0031] Figure 10C Similar to the ones shown for ease of explanation Figure 8B Schematic representation;

[0032] Figure 10D yes Figures 10A to 10CA perspective top view of an electronic device, in which the upper and lower portions are superimposed and transparent;

[0033] Figure 10E yes Figure 10D A side view of the electronic device;

[0034] Figure 10F It is after packaging. Figure 10D and Figure 10E A side view of a portion of an electronic device;

[0035] Figure 10G It is based on a variant similar to Figure 10F Side view;

[0036] Figure 11 yes Figures 10A to 10E A perspective view of electronic components;

[0037] Figure 12 This occurs after encapsulation and coupling to the cooling structure. Figure 8A The cross-section of an electronic device;

[0038] Figure 13 Is Figure 7 The cross-section of this electronic device after packaging, in the case of a MOSFET transistor;

[0039] Figure 14A and Figure 14B These are respectively in embodiments with lateral leads. Figure 13 A perspective top view of the lower part and a perspective bottom view of the upper part of the electronic device;

[0040] Figure 14C It has a small shape variation. Figure 13 A schematic top view showing the arrangement of components and connection areas of an electronic device;

[0041] Figure 14D yes Figures 14A to 14B A perspective top view of an electronic device, in which the upper and lower portions are superimposed and transparent;

[0042] Figure 15 It is a cross-section of a portion of this electronic device having first-type leads;

[0043] Figure 16 It is a cross-section of a part of this electronic device with different types of leads;

[0044] Figure 17 yes Figure 16 A side view of the electronic device;

[0045] Figure 18It is a cross-section of a portion of this electronic device having another type of leads;

[0046] Figure 19 and Figure 20 These are perspective and side views of an electronic device coupled to a cooling structure with leads formed as protruding pins.

[0047] Figures 21 to 23 This is a side view showing the different possibilities of coupling surface-mount electronics to a cooling structure and to a bearing structure;

[0048] Figure 24 This is the electrical diagram of a full-bridge circuit that can be obtained using this electronic device;

[0049] Figure 25 It is based on Figure 6 Implementation Figure 24 The cross-section of a full-bridge circuit and an electronic device using MOSFET transistors;

[0050] Figure 26 yes Figure 25 A schematic top view showing the arrangement of components and connection areas of an electronic device;

[0051] Figure 27 It is based on Figure 7 Implementation Figure 26 The cross-section of a full-bridge circuit and an electronic device using MOSFET transistors; and

[0052] Figure 28 yes Figure 27 A schematic top view of the arrangement of components and connection areas of an electronic device.

[0053] The following description refers to the arrangement shown in the accompanying drawings; therefore, terms such as “above,” “below,” “upper,” “lower,” “right,” and “left” are used with reference to the accompanying drawings and should not be interpreted in a restrictive manner. Detailed Implementation

[0054] Figures 5 to 14D This involves packaged electronics that provide phase-inverter power modules (so-called three-phase inverters), which are advantageous for use in the automotive industry and can also be used in applications requiring high power delivery.

[0055] Figure 5 The electrical diagram of the three-phase inverter 20 is shown.

[0056] The three-phase inverter 20 is formed by three equal branches 21, each branch consisting of two power MOSFET transistors (also referred to as upper transistor 23 and lower transistor 24) connected in series, which are N-channel and dual-source transistors. When it is necessary to distinguish them, the branches 21 are also labeled as first branch 21A, second branch 21B, and third branch 21C.

[0057] The three-phase inverter 20 has multiple terminals, identified by the letters a to e. In the case of the first branch 21A, there are no superscript symbols; in the case of the second branch 21B, there is a single superscript symbol '; and in the case of the third branch 21C, there are double superscript symbols "". As a whole, the three-phase inverter 20 has the following terminals: first terminals a, a', a″; second terminals b, b', b″; third terminals c, c', c″; fourth terminals d, d', d″; and fifth terminals e, e', e″.

[0058] The first terminals a, a', and a″ are the drain terminals of the upper transistor 23 of each branch 21 and are electrically connected to each other (in a manner not shown).

[0059] The second terminals b, b', and b″ are the gate terminals of the upper transistor 23 of each branch 21 and are electrically connected to the corresponding output terminals (not shown) of the driver circuit.

[0060] The third terminals c, c', and c″ are the source terminal of the upper transistor 23 and the drain terminal of the lower transistor 24 of each branch 21, and are electrically isolated from each other and connected to the corresponding load (not shown).

[0061] The fourth terminals d, d', and d″ are the gate terminals of the lower transistor 24 of each branch 21 and are electrically connected to the corresponding output terminals (not shown) of the driver circuit.

[0062] The fifth terminals e, e', and e″ are the source terminals of the lower transistor 24 and are electrically connected to each other (in a manner not shown).

[0063] In a manner not shown, the upper transistor 23 and the lower transistor 24 may have corresponding driver source terminals, which in some applications serve as a reference for the gate voltage of the upper transistor 23, and are connected to an external metal region independently of each other.

[0064] The upper transistor 23 and the lower transistor 24 can be any type of power MOSFET transistor.

[0065] For example, Figure 6 The upper transistor 23 and the lower transistor 24 are shown as a possible implementation of a charge-balanced (also known as a superjunction) transistor.

[0066] In detail, the upper transistor 23 and the lower transistor 24 include a substrate 25 having an upper surface 25A and a lower surface 25B.

[0067] Substrate 25 forms a drain region 26 and is electrically contacted by a drain metal layer 27, which extends on the lower surface 25B of substrate 25 and is coupled to... Figure 5 The first terminal a, a', a″ or the third terminal c, c', c″.

[0068] The source region 28 faces the upper surface 25B and is contacted by a source metal layer 29, which extends on the upper surface 25A of the substrate 25 and is coupled to... Figure 5 The third terminal c, c', c″ or the fifth terminal e, e', e″.

[0069] An insulated gate region 30 extends over the upper surface 25A of the substrate 25 and has been coupled to Figure 5 The corresponding gate conductive portion 31 of the second terminal b, b', b″ or the fourth terminal d, d', d″.

[0070] Other implementations are also possible, such as those utilizing vertical silicon carbide technology, characterized in that the drain metal layer 27 is disposed on the lower surface 25B of the substrate 25, and the source metal layer 29 is disposed on the upper surface 25A of the substrate 25, such as... Figure 6 As shown.

[0071] Figure 7 The upper transistor 23 and the lower transistor 24 are shown as a possible implementation of a planar power MOSFET transistor made using gallium nitride (GaN) technology.

[0072] exist Figure 7 In this embodiment, each transistor 23, 24 includes a die 35 bonded to a conductive substrate 36; the latter is in contact with a source metallization layer 37 facing the underside of the transistor 23, 24.

[0073] The conductive substrate 36 forms a protrusion 38 that contacts the source contact region 39, which faces the upper side of the device and forms the driver source terminal. Figure 5 (Not shown in the image).

[0074] The source region 40 formed in the die 35 faces the upper surface of the die 35 and is contacted by a source contact structure 41 that extends above the die 35 and is coupled to... Figure 5 The third terminal c, c', c″ or the fifth terminal e, e', e″.

[0075] The drain region 42 formed in the die 35 faces the upper surface of the die 35 and is contacted by a drain contact structure 43 that extends above the die 35 and is coupled to... Figure 5 The first terminal a, a', a″ or the third terminal c, c', c″.

[0076] As is known to those skilled in the art, the upper transistor 23 and the lower transistor 24 also have gate conductive regions (not shown), which are coupled to Figure 5 The second terminal b, b', b″ or the fourth terminal d, d', d″.

[0077] Figure 8A , 8B 9A and 9B show the use of Figure 6 A three-phase inverter is formed and implemented using transistors 23, 24 of the type shown, or in a similar configuration with external contact pads. Figure 5 Electronic device 50 with the circuit structure shown.

[0078] Electronic device 50 includes six dies 51, which are generally equal in size and implement upper transistor 23 and lower transistor 24. For clarity, in the following text, where useful, die 51 is also referred to as first die 51A (implementing upper transistor 23) and second die 51B (implementing lower transistor 24).

[0079] Dies 51 face each other here, and as Figure 8A The arrangement is as can be seen in the diagram; that is, the first dies 51A are aligned with each other, for example, parallel to the first axis X of the Cartesian reference system XYZ, and the three second dies 51B are aligned with each other, also parallel to the first axis X and parallel to the first die group 51A. Each first die 51A is aligned with the corresponding second die 51B along the second axis Y of the Cartesian reference system XYZ to simplify the connection, as described below, although such alignment is not essential.

[0080] like Figure 8A The cross-section is represented in a simplified manner. Figure 8A The diagram shows an electronic device 50 prior to packaging, with a first substrate element 55 and a second substrate element 56 forming a connection and heat dissipation structure, sandwiching a die 51 between them. Specifically, Figure 8A The section shows the first die 51A and the second die 51B in a set of six dies 51. However, the same section also applies to the other pairs of dies 51A to 51B. Figure 8A The cross-section can be cut along line VIII-VIII, such as Figure 10A As shown.

[0081] Substrate elements 55 and 56 have an internal main side (facing die 51) and an external main side. The internal main side allows electrical connection of die 51, and the external main side faces the outside of electronic device 50, is electrically insulated from die 51, but thermally coupled to die 51 to allow heat dissipation of die 51.

[0082] Specifically, the substrate elements 55 and 56 include: a first conductive layer 57 disposed on the outside, typically a metal layer; a second conductive layer 58 disposed on the inside, typically a metal layer; and an intermediate insulating layer 59, typically a ceramic layer.

[0083] For example, here, substrate elements 55 and 56 are formed of DBC (direct bonded copper), and conductive layers 57 and 58 are formed of copper.

[0084] The second conductive layer 58 of the substrate elements 55 and 56 (arranged inside the interlayer forming the electronic device 50) is formed and forms a plurality of corresponding connection regions 52, which electrically couple the terminals of transistors 23 and 24 to each other and to the outside.

[0085] For details, refer to Figure 8A , Figure 8A It shows Figure 5 The upper transistor 23 on the right side and the lower transistor 24 on the left side of branch 21, the connection region 52 includes:

[0086] The first drain connection region 52A is formed by the second conductive layer 58 of the first substrate element 55 and is coupled to the drain terminals of all the upper transistors 23.

[0087] The first intermediate connection region 52B is formed by the second conductive layer 58 of the second substrate element 56 and is coupled to the corresponding source terminals of the upper transistor 23.

[0088] The second drain connection region 52C is formed by the second conductive layer 58 of the first substrate element 55 and is coupled to the drain terminal of the lower transistor 24 and the source terminal of the upper transistor 23. It is directly electrically connected to the intermediate connection region 52B and the third terminals c, c', and c″.

[0089] The source connection region 52D is formed by the second conductive layer 58 of the second substrate element 56 and is coupled to the source terminal of the lower transistor 24;

[0090] The first external coupling region 52E is formed by the second conductive layer 58 of the second substrate element 56, and is connected to the first drain region 52A and the first terminals a, a', a″. Figure 5 Direct electrical connection; and

[0091] The second external connection region 52F is formed by the second conductive layer 58 of the first substrate element 55, and is connected to the source connection region 52D and the fifth terminals e, e', e″. Figure 5 Direct electrical connection.

[0092] The connection region 52 can be provided by one or more etching processes that remove material from the second conductive layer 58 of the two substrate elements 55, 56 to define the connection regions 52A to 52F (when the etching extends through the entire thickness of the second conductive layer 58) and to provide a protrusion 32 (when the etching extends through a portion of the thickness of the second conductive layer 58) to allow the second conductive layers 58 to make electrical contact with each other or with the die 51.

[0093] Any height difference between the protrusions 32 of the two substrate elements 55, 56 in contact with each other and the protrusion 32 in contact with the die 51 can be compensated by a conductive material (such as solder paste or solder post).

[0094] Figure 9A and Figure 9B The following diagram shows the electronic device 50 after packaging, with the leads formed as protruding pins 53. As mentioned (see also...) Figure 10F , Figure 10G and Figure 12 The encapsulated mass block 54, made of resin or other moldable electrically insulating material, surrounds the encapsulated mass block 54. Figure 8A The sandwich structure shown allows the die 51 to be fully embedded and extends between the second conductive layers 58 and laterally to the insulating layer 59 and the first conductive layer 57, leaving only a portion of the protruding pin 53 protruding. Therefore, the package mass block 54 extends flush (e.g., coplanar) with the outer surface of the first conductive layer 57, which forms the upper and lower surfaces of the electronic device 50.

[0095] Since the substrate elements 55 and 56 are heat dissipation structures and transfer the heat generated by the die 51 to the outside, the electronic device 50 is a dual-cooling (DC) device, which allows for high and efficient heat dissipation, especially when coupled to an external cooling system, as discussed below.

[0096] An embodiment of electronic device 50, for example Figure 10A , Figure 10B , Figures 10D to 10E As shown, these figures illustrate in detail the possible shape and arrangement of the connection region 52 relative to the die 51 in the case of lateral leads. In these figures, for simplicity, the different regions are represented by… Figure 8A The same reference numerals are used to identify them. Specifically, areas 52A to 52F are visible in these figures.

[0097] In addition, special reference Figure 10A , Figure 10B and Figure 10D The second conductive layer 58 of the substrate elements 55 and 56 is also formed as follows:

[0098] First gate connection region 33A ( Figure 10B The second conductive layer 58 of the second substrate element 56 is formed and coupled to the gate terminal of the upper transistor 23;

[0099] Second gate connection region 33B Figure 10B The second conductive layer 58 of the second substrate element 56 is formed and coupled to the gate terminal of the lower transistor 24.

[0100] Third gate connection region 33C ( Figure 10A The second conductive layer 58, formed by the first substrate element 55, is coupled to the gate connection regions 33A and 33B, and is directly electrically connected to the second terminals b, b', b″ and directly electrically connected to the fourth terminals d, d', d″ (see also...). Figure 5 );as well as

[0101] Load connection area 33D ( Figure 10A The first substrate element 55 is formed by the second conductive layer 58, coupled to the first intermediate connection region 52B, and directly electrically connected to the third terminals c, c', and c″.

[0102] exist Figure 10A , Figure 10B , Figures 10D to 10G There are also visible ones in it:

[0103] First protrusion 32A ( Figure 10B , Figure 10C The second conductive layer 58 of the second substrate element 56 is formed, and forms Figure 10C The first intermediate connection region 52B is visible in the middle;

[0104] Second protrusion 32B ( Figure 10B , Figure 10C The second conductive layer 58 of the second substrate element 56 is formed, and forms Figure 10C The second intermediate connecting region 52C is visible in the middle;

[0105] Third protrusion 32C ( Figure 10B The second conductive layer 58, formed by the second substrate element 56, is used for gate connection;

[0106] The fourth protrusion 32D is formed by the second conductive layer 58 of the second substrate element 56 and forms the first external coupling region 52E.

[0107] Similar protrusions 32 are formed by the second conductive layer 58 of the first substrate element 55 and are not described in detail here.

[0108] Figure 10E and Figure 10F The image shows a side view of the electronic device 50 before packaging and a ghost view of the left side portion of the electronic device 50 after packaging (relative to...). Figure 10E ).

[0109] Figure 10G It shows Figure 10F A variant of it.

[0110] exist Figure 10E and Figure 10F In this context, electronic device 50 has a bar pin 73, as discussed below. Figure 10F In this configuration, the rod pin 73 contacts the unique second conductive layer 58 of the first substrate element 55. Figure 10G In this configuration, the rod pin 73 contacts the second conductive layer 58 of the first substrate element 55 and the second substrate element 56. In this case, the rod pin 73 typically does not have an electrical function but rather a structural support function, as also referred to below. Figure 16 Discussed.

[0111] The shape and arrangement of the connection area 52 relative to the die 51 can be Figures 10A to 10G I saw it in the middle.

[0112] As indicated above, electronic device 50 is a dual-cooled (DC) device and can be coupled to an external cooling system, such as, for example... Figure 12 As shown.

[0113] Here, the lower cooling structure 65 is in contact with the first conductive layer 57 of the first substrate element 55, and the upper cooling structure 66 is in contact with the first conductive layer 57 of the second substrate element 56.

[0114] In the illustrated example, cooling structures 65 and 66 use coolant; however, any type of cooling system suitable for the intended application can be used.

[0115] Due to the direct contact between cooling structures 65 and 66 and substrate elements 55 and 56, very effective heat dissipation is achieved.

[0116] Figure 13 , Figures 14A to 14D An electronic device 60 is shown, which uses an upper transistor 23 and a lower transistor 24, which are formed as planar power MOSFET transistors based on gallium nitride (GaN), such as... Figure 7 As shown.

[0117] In this case, where with Figure 8A The 50 identical electronic components are indicated by the same reference numerals, while the connection islands differ in shape to account for... Figure 5 The contact pads of the upper transistor 23 and the lower transistor 24 are arranged differently.

[0118] Specifically, in Figure 13 , Figures 14A to 14D Within it, there exists that is visible:

[0119] The first source connection region 62A is formed by the second conductive layer 58 of the first substrate element 55, and is connected to the upper transistor 23. Figure 7 The corresponding source metallization 37 of ) is electrically contacted, and is connected to the third terminals c, c', c″. Figure 5 )coupling;

[0120] The first intermediate connection region 62B is formed by the second conductive layer 58 of the second substrate element 56, and is connected to the first source connection region 62A and the source contact regions 39 and 40 of the upper transistor 23. Figure 7 ) and the drain contact structure 43 of the lower transistor 24 ( Figure 7 Electrical contact;

[0121] The second source connection region 62C is formed by the second conductive layer 58 of the first substrate element 55, and is connected to the lower transistor 24. Figure 7 The corresponding source metallization 37 electrical contacts are formed, and the fifth terminals e, e', e″ are formed. Figure 5 );

[0122] At least the second intermediate connection region 62D ( Figure 14B There are three of them. Figure 14C There is only one of them), which is formed by the second conductive layer 58 of the second substrate element 56, and is connected to the second source connection region 62C and source contact regions 39 and 40 of the lower transistor 24. Figure 7 Electrical contact;

[0123] The first external coupling region 62E is formed by the second conductive layer 58 of the second substrate element 56 and is in contact with the drain contact structure 43 of the upper transistor 23. Figure 7 It makes electrical contact and is coupled to the first terminals a, a', a″.

[0124] Figures 14A to 14D It also shows the formation Figure 5 The regions of the second terminals b, b', b″ and the fourth terminals d, d', d″.

[0125] Electronic devices 50 and 60 can be externally coupled using different types of leads.

[0126] Figure 15 This demonstrates a possible solution for external connections via protruding pins, while Figures 16 to 18 Various solutions suitable for surface mounting are shown, also known as leadless solutions, featuring lateral metal rods (hereinafter referred to as "rod leads") that may have uncovered solderable sides.

[0127] In detail, Figure 15 This illustrates a possible connection between the electronic device 70 and the carrier structure 67 (e.g., a printed circuit board (PCB)) when the leads are formed as protruding pins 53.

[0128] Electronic device 70 can be used as a target Figure 8A and 13 The electronic devices 50 and 60 are formed as described.

[0129] Each of the protruding pins 53 is connected to an external connection region (formed in the second conductive layer 58 of the first substrate element 55, and forming...) Figure 5 Between the corresponding regions between terminals a, a', a″; b, b', b″; c, c', c″; d, d', d″; e, e', e″) and the corresponding conductive regions (not shown) formed on the support structure 67.

[0130] If the electronic device 70 operates at very high voltage / power (e.g., up to 1200V) and requires advanced insulation conditions (high creepage distance), the package 54 may include a recess 68.

[0131] In this configuration, the recess 68 extends parallel to and adjacent to the side of the package 54 (typically on two opposite sides of the package 54), and the protruding pin 53 extends on the side of the package 54.

[0132] In this way, the surface distance between the prominent pin 53 and the internal area increases at different voltages.

[0133] Figure 15 The electronic device 70 is used for unilateral cooling because the first substrate element 55 is placed on the support structure 67 (e.g., PCB), and any cooling system (similar to...) Figure 11 The cooling systems 65 and 66 can be arranged only on the electronic device 70.

[0134] Figure 16 An electronic device 75 with a leadless package 54 is shown, the package 54 having rod leads, indicated by 73, the height of which is equal to that of the package 54.

[0135] Electronic device 75 can be used as targeted Figures 10A to 10E , Figures 14A to 14D The electronic devices 50 and 60 are formed as described.

[0136] Figure 16 The rod pin 73 of the electronic device 75 can be used as Figure 16 The connections shown are made to external connection areas 52 and 62.

[0137] In detail, Figure 16 Each of the rod pins 73 includes a vertical portion 73A and a protrusion 73B. The vertical portion 73A extends laterally to the substrate elements 55 and 56, and the protrusion 73B extends laterally to the vertical portion 73A and parallel to the substrate elements 55 and 56.

[0138] The protrusions 73B of the rod pins 73 extend toward the interior of the electronic device 75 and are each soldered to a corresponding connection area 52, which is formed in the second conductive layer 58 of the first substrate element 55 or the second substrate element 56.

[0139] However, based on the designer's technical considerations, more rod pins 73 can be connected to the same connection area 52.

[0140] exist Figure 16 In cross-section, the rod pin 73 is connected to a connection region formed in the second conductive layer 58 of the first substrate element 55. Alternatively, it can be connected to a connection region formed in the second conductive layer 58 of the second substrate element 56, or connected to both, as in example... Figure 10G As shown, it has, for example, a structural support function. Typically, the rod pins 73 of the electronic device 75 can be connected to the first substrate element 55 and / or the second substrate element 56.

[0141] Moreover, in this case, if the electronic device 75 is designed to operate at very high voltage / power and requires advanced insulation conditions, the package 74 may include a recess 68 to provide a high creepage distance.

[0142] As indicated above and Figure 17 See also (for electronic devices 50) Figure 11 The groove 68 extends parallel to and adjacent to the side of the package 54, and the rod pin 73 extends on the package 54.

[0143] Figures 16 to 17 The electronic device 75 is also used for unilateral cooling because the first substrate element 55 is placed on the support structure 67.

[0144] Figure 18Electronic device 85 is shown, in which a bar lead, indicated by 93, protrudes downward relative to package 54, with a height equal to that of the lower cooling structure 65.

[0145] Specifically, in Figure 18 In the middle, the strip lead 93 has a greater height relative to the package 54, and its height is exactly equal to the height of the package 54 plus the height of the upper cooling structures 65, 66.

[0146] In other words, such as Figure 18 As shown in the embodiment, the height of the strip lead 93 can be equal to the height extending from the surface 141 of the lower cooling structure 65 to the surface 143 of the upper cooling structure 66.

[0147] This allows the lower cooling structure 65 and the upper cooling structure 66 to be as follows: Figure 18 The arrangement is as shown. For example, in some embodiments, the corresponding surfaces 141, 143 are exposed on the opposite side from the package mass block 54.

[0148] Figures 19 to 23 High-power electronic modules that can be obtained using the aforementioned electronic devices 50, 60, 70, 75 and 85 are shown.

[0149] In detail, Figure 19 and Figure 20 A power module 150 is shown that can be obtained using electronics 50, 60 in a configuration with protruding pin 53.

[0150] Here, the upper cooling structure 66 is arranged to be in direct contact with the first conductive layer 57 of the second substrate element 56 (only when...). Figure 19 (See image below); conversely, the lower cooling structure 65 contacts the supporting structure 67 (only visible in the image below for clarity). Figure 20 (This is from the Chinese text.)

[0151] In the example shown, the upper cooling structure 66 has an upper channel 91 that allows cooling fluid to pass through; the lower cooling structure 65 has a lower channel 92 that allows cooling fluid to pass through.

[0152] Channels 91 and 92 are also connected to each other upstream and downstream of electronic devices 50, 60, and 70.

[0153] In the illustrated embodiment, the upper cooling structure 66 has protrusions 99 for increasing heat dissipation, and the lower cooling structure 65 has small pillars / columns 94 extending between the electronic devices 50, 60, 70 and the lower channel 92 and facilitating heat transfer.

[0154] Figure 21A high-power electronic module 155 is shown, which can be obtained using an electronic device 75 having a rod pin 73 of the same height as the corresponding electronic device 75.

[0155] Also here, the upper cooling structure 66 is arranged to directly contact the upper side of the electronic device 75 (and precisely contact the first conductive layer 57 of the second substrate element 56, in...) Figure 23 (Not visible in the middle), and the lower cooling structure 65 is in contact with the supporting structure 67.

[0156] Figure 22 A high-power electronic module 160 is shown, which can be obtained using an electronic device 85 with leads 83, the height of which is greater than the height of the corresponding electronic device 85.

[0157] Therefore, in this configuration, the lower cooling structure 65 can be arranged to directly contact the lower side of the electronic device 85 (and precisely contact the first conductive layer 57 of the first substrate element 55, in...) Figure 22 (Not visible in the middle).

[0158] Therefore, the supporting structure 67 is arranged below the lower cooling structure 65.

[0159] The rod pin 83 here has a height at least equal to the sum of the heights of the electronics 85 and the lower cooling structure 65, so that it can be electrically connected to the support structure 67.

[0160] In this way, the electronic module 160 has high heat dissipation and high stability.

[0161] Figure 23 An electronic module 165 is shown, which includes a plurality of electronic devices 85 (two in this case) stacked on top of each other.

[0162] Specifically, by utilizing the height of the rod pin 83, an intermediate cooling structure (indicated by 95) can be arranged between two stacked electronic devices 85. By designing the system such that the height of the rod pin 83 is equal to the height of the corresponding electronic device 85 and the cooling system 65, 95, the rod pin 83 can be electrically connected to each other and to the support structure 67.

[0163] In this way, the electronic module 165 is very compact and has... Figure 22 The advantages of the electronic module 160 have been highlighted.

[0164] Figure 24 The electrical diagram of the full-bridge circuit 100 is shown.

[0165] The full-bridge circuit 100 can be considered a simplified circuit of the three-phase inverter 20, and therefore it will be briefly described using the same reference numerals.

[0166] The full-bridge circuit 100 is formed by two equal branches 21 (specifically 21A and 21B), which are formed by the series connection of two power MOSFET transistors (again indicated here as upper transistor 23 and lower transistor 24).

[0167] The full-bridge circuit 100 has multiple terminals, including: corresponding first terminals a, a'; second terminals b, b'; third terminals c, c'; fourth terminals d, d'; and fifth terminals e, e'.

[0168] Also here, each transistor 23, 24 may have a driver source terminal not shown.

[0169] The upper transistor 23, the lower transistor 24, and the terminals a, a', b, b', c, c', d, d', e, e' are equivalent and coupled as described above for the three-phase inverter 20, so their description will not be repeated.

[0170] Specifically, the upper transistor 23 and the lower transistor 24 may have Figure 6 or Figure 7 The structure shown.

[0171] Therefore, also here, the full-bridge circuit 100 can be implemented by electronic device 105, such as Figure 25 As shown in the cross-section, or implemented by electronic device 110, such as Figure 27 The cross-section is shown in the figure.

[0172] As from Figure 25 and Figure 8A The comparison between them is noteworthy. Figure 25 The cross-section of the electronic device 105 is equal to Figure 8A The cross-section.

[0173] Similarly, Figure 27 The cross-section of electronic device 110 and Figure 13 Their cross-sections are equal.

[0174] on the contrary, Figure 28 The simplified connection scheme shown has only two parts (corresponding to two branches 21), instead of Figure 10C The three parts.

[0175] Therefore, electronic devices 105 and 110 are also provided as a sandwich structure comprising a first substrate element 55, a second substrate element 56, and dies 51 (four in total).

[0176] The substrate elements 55 and 56 are of the type discussed above. In particular, the second conductive layer 58 forms electrical connections between the dies 51 and with the outside, which will not be repeated here.

[0177] Electronic devices 105 and 110 can be connected to a substrate (not shown) via any type of lead, including protruding leads and rod leads; the rod leads can have different heights, as shown above. Figures 15 to 18 As described above, and coupled to cooling structures 65, 66, and 95 as discussed above.

[0178] In this way, even a reduction of up to 50% in board area can be achieved.

[0179] The electronic device described in this article has many advantages.

[0180] Specifically, in addition to providing very high heat dissipation, it also has less inductive parasitic effects, better thermal performance, and greater reliability due to the absence of internal bonding wires.

[0181] Electronic devices can also be very compact.

[0182] The assembly process is simplified, and the finished devices have high reliability.

[0183] The available high creepage distance allows electronics to be used in high-voltage and ultra-high-voltage applications, up to 1200V.

[0184] Finally, it will be apparent that modifications and variations can be made to the electronic devices described and illustrated herein without departing from the scope of this disclosure, as defined in the appended claims. For example, the different embodiments described may be combined to provide other solutions.

[0185] An electronic device (50, 60, 70, 75, 85, 105, 110) can be summarized as including at least a first branch and a second branch (21A, 21B, 21C), each branch including a first transistor and a second transistor (23, 24) arranged in series with each other. The electronic device includes a first substrate element (55), a second substrate element (56), and a plurality of dies (51) of semiconductor material. Each of the plurality of dies (51) integrates a corresponding transistor between the first transistor and the second transistor. The dies are arranged side by side with each other and between the first substrate element and the second substrate element, wherein the first substrate element and the second substrate element (55, 56) each include... The multilayer structure includes a first conductive layer (57), a second conductive layer (58), and an insulating layer (59), the insulating layer (59) being disposed between the first and second conductive layers. The first conductive layer (57) of the first substrate element and the second substrate element (55, 56) faces the outside of the electronic device and defines a first main surface and a second main surface of the electronic device. The second conductive layer (58) of the first substrate element and the second substrate element (55, 56) is shaped to form contact regions (52A to 52F, 33A to 33D; 62A to 62D) facing a plurality of dies (51) and selectively electrically contacting the plurality of dies (51).

[0186] The electronic device may also include a third branch (21C) comprising corresponding first transistors and corresponding second transistors (23, 24) arranged in series with each other, wherein the electronic device forms an inverter circuit (20).

[0187] Electronic devices can form a full-bridge circuit (100).

[0188] The first substrate element and the second substrate element (55, 56) can be formed from a DBC (direct bonded copper) substrate.

[0189] The first transistor and the second transistor (23, 24) may have a first conductive terminal (a, a', c, c'), a second conductive terminal (c, c', e, e'), and a control terminal (b, b', d, d'), wherein the second conductive layer (58) of the first substrate element (55) may be formed with: a first connection region (52A) coupling the first conductive terminal of the first transistor (23) of the first branch (21A) and the first conductive terminal of the first transistor (23) of the second branch (21B) to the first external terminal (a, a') of the electronic device; a second connection region (52C) ​​coupling the first conductive terminal of the second transistor (23) of the first branch (21A) to the second external terminal (c) of the electronic device; and a third connection region (52C) ​​coupling the first conductive terminal of the second transistor (24) of the second branch (21B) to the third external terminal (c') of the electronic device; and the second conductive layer (58) of the second substrate element (55) may have a first conductive terminal (a, a', c, c'), a second conductive terminal (c, c', e, e'), and a control terminal (b, b', d, d'). The two conductive layers (58) may form: at least a fourth connection region (52D) that couples the second conductive terminal of the second transistor of the first branch (21A) and the second conductive terminal of the second transistor of the second branch (21B) to the fourth external terminal (e, e') of the electronic device; a fifth connection region (52B) that couples the second connection region (52C) ​​to the second conductive terminal of the first transistor (23) of the first branch (21A); and a sixth connection region (52B) that couples the third connection region (52C) ​​to the second conductive terminal of the first transistor (23) of the second branch (21B), wherein the second conductive layer (58) of the first substrate element and / or the second substrate element (55, 56) forms an external control region (b, b', d, d') that is coupled to the control terminals of the first transistor and the second transistor of the first branch of the electronic device and the control terminals of the first transistor and the second transistor of the second branch (21A, 21B).

[0190] The first transistor and the second transistor (23, 24) may have first conductive terminals (a, a', c, c'), second conductive terminals (c, c', e, e'), and control terminals (b, b', d, d'), wherein the second conductive layer (58) of the first substrate element or the second substrate element (55, 56) may form a seventh connection region (61E), coupled to the first conductive terminals of the first transistor (23) of the first branch (21A) and the first conductive terminals of the first transistor (23) of the second branch (21B), and coupled to the fifth external terminal (a, a', c ... The eighth connection region (62B) couples the second conductive terminal of the first transistor (23) of the first branch (21A) to the first conductive terminal and the sixth external terminal (c) of the second transistor (23) of the first branch (21A) of the electronic device; and the ninth connection region (62B) couples the second conductive terminal of the first transistor (23) of the second branch (21B) to the first conductive terminal and the seventh external terminal (c') of the second transistor (24) of the second branch (21B) of the electronic device; and at least the tenth connection region (62D) couples the first branch (21A) to the second conductive terminal and the sixth external terminal (c') of the second transistor (24) of the second branch (21A) of the electronic device.

[0191] The second conductive terminal of the second transistor (24) and the second conductive terminal of the second transistor (24) of the second branch (21B) are coupled to the eighth external terminal (e, e') of the electronic device; the second conductive layer (58) of the first substrate element and / or the second substrate element (55, 56) forms an external control region (b, b', d, d'), which is coupled to the control terminals of the first transistor and the second transistor of the first branch (21A) and the control terminals of the first transistor and the second transistor of the second branch (21B) of the electronic device.

[0192] The electronic device may include a package mass block (54) that laterally surrounds a first substrate element (55) and a second substrate element (56) and embeds a plurality of dies (51). The package mass block (54a) is flush with the first conductive layer (57) of the first substrate element and the second substrate element (55, 56) at the first main surface and the second main surface of the electronic device, respectively.

[0193] The electronic device may include external connection leads (53, 73, 83) that are selectively coupled to contact regions (52A to 52F, 33A to 33D, 62A to 62D) of the second conductive layer (58) of the first substrate element and / or the second substrate element (55, 56).

[0194] External connection leads may include rod pins (73, 93) for surface mounting, the rod pins (73, 93) having lateral protrusions (73B) that make direct electrical contact with selective contact areas (52A to 52F, 33A to 33D; 62A to 62D).

[0195] The first substrate element and the second substrate element (55, 56) and the die (51) can define the device height, and the rod pin (93) has a greater height relative to the device height.

[0196] A power electronic module can be summarized as including: a support structure (67); a first electronic device; and a first cooling structure (66), wherein the first electronic device faces the support structure (67) with a first main surface and contacts the cooling structure with a second main surface.

[0197] The first electronic device may have a rod pin (93) with a height greater than the device height, and may also include a second cooling structure (65) disposed between the second surface of the first electronic device and the support structure (67).

[0198] The height of the rod pin (93) can be at least equal to the sum of the height of the first electronic device (85) and the height of the second cooling structure (65), and it is in direct electrical contact with the support structure (67).

[0199] The height of the rod pin (93) can be equal to the sum of the height of the first electronic device (85), the height of the first cooling structure (66), and the height of the second cooling structure (65), and can be in direct electrical contact with the support structure (67).

[0200] The power electronics module may also include a second electronics (85) disposed above the first electronics (85) and below the first cooling structure (66), and a third cooling structure (95) disposed between the first and second electronics (85).

[0201] The various embodiments described above can be combined to provide other embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in this specification and / or listed in the application data sheet are incorporated herein by reference in their entirety. Various aspects of the embodiments may be modified if it is necessary to employ concepts from various patents, applications, and publications to provide other embodiments.

[0202] In view of the detailed description above, these and other changes may be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in this specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents to which such claims are conferred. Therefore, the claims are not limited to this disclosure.

Claims

1. An electronic device, comprising: A first main surface and a second main surface, wherein the second main surface is opposite to the first main surface; The first branch includes a first transistor and a second transistor arranged in series; The second branch includes a third transistor and a fourth transistor arranged in series; First substrate element; The second substrate element is spaced apart from the first substrate element; as well as A plurality of dies are arranged side-by-side with each other and between the first substrate element and the second substrate element, the plurality of dies comprising: The first die includes the first transistor of the first branch; The second die includes the second transistor of the first branch; The third die includes the third transistor of the second branch; and The fourth die includes the fourth transistor of the second branch, and The first substrate element and the second substrate element each include a multilayer structure, the multilayer structure including a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer. The first conductive layer of the first substrate element and the first conductive layer of the second substrate element respectively face the outer side of the electronic device and respectively define the first main surface and the second main surface. The second conductive layer of the first substrate element and the second conductive layer of the second substrate element include contact regions that face the plurality of dies and selectively make electrical contact with the plurality of dies. The electronic device further includes: First external terminal; Second external terminal; Third external terminal; and The fourth external terminal, and wherein: The first transistor, the second transistor, the third transistor, and the fourth transistor each have a first conductive terminal, a second conductive terminal, and a control terminal. The second conductive layer of the first substrate element includes: The first connection region couples the first conductive terminal of the first transistor of the first branch to the first conductive terminal of the third transistor of the second branch, and the first connection region is coupled to the first external terminal. The second connection region couples the first conductive terminal of the first transistor in the first branch to the second external terminal; and The third connection region couples the first conductive terminal of the second transistor in the second branch to the third external terminal; The second conductive layer of the second substrate element includes: The fourth connection region couples the second conductive terminal of the second transistor of the first branch to the second conductive terminal of the fourth transistor of the second branch, and the second connection region is coupled to the fourth external terminal; The fifth connection region couples the fourth connection region to the second conductive terminal of the first transistor in the first branch; and The sixth connection region couples the third connection region to the first conductive terminal of the third transistor in the second branch. At least one of the second conductive layers of the first substrate element and the second substrate element includes an external control region, which is coupled to the control terminals of the first transistor, the second transistor, the third transistor, and the fourth transistor of the first branch and the second branch, respectively.

2. The electronic device according to claim 1 further includes a third branch, the third branch comprising a fifth transistor and a sixth transistor arranged in series.

3. The electronic device according to claim 1, wherein the first branch and the second branch are full-bridge circuits.

4. The electronic device of claim 1, wherein the first substrate element and the second substrate element are formed from a direct-bonded copper DBC substrate.

5. The electronic device according to claim 1, further comprising a packaging mass block, the packaging mass block laterally surrounding the first substrate element and the second substrate element and embedding the plurality of dies, the packaging mass block being coplanar with the first conductive layer of the first substrate element and the first conductive layer of the second substrate element at the first main surface and the second main surface, respectively.

6. The electronic device of claim 1, comprising an external connection lead selectively coupled to a contact region of the second conductive layer of at least one of the first substrate element and the second substrate element.

7. The electronic device of claim 6, wherein the external connection lead includes a rod pin for surface mounting, the rod pin having a lateral protrusion that is in direct electrical contact with a selective contact area.

8. The electronic device of claim 7, wherein the device height extends in a direction from the first main surface to the second main surface and from the first main surface to the second main surface, and the rod pin has a rod pin height that extends in the direction from the first main surface to the second main surface and is greater than the device height.

9. A power electronic module, comprising: Load-bearing structure; First cooling structure; A first electronic device, situated on the first cooling structure, comprises: A first main surface and a second main surface, the second main surface being opposite to the first main surface, the first main surface being located on the first cooling structure; The first branch includes a first transistor and a second transistor arranged in series; The second branch includes a third transistor and a fourth transistor arranged in series; First substrate element; A second substrate element, spaced apart from the first substrate element; and A plurality of dies are arranged side-by-side with each other and between the first substrate element and the second substrate element, the plurality of dies comprising: The first die includes the first transistor of the first branch; The second die includes the second transistor of the first branch; The third die includes the third transistor of the second branch; and The fourth die includes the fourth transistor of the second branch, and The first substrate element and the second substrate element each include a multilayer structure, the multilayer structure including a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer. The first conductive layer of the first substrate element and the first conductive layer of the second substrate element respectively face the outer side of the electronic device and respectively define the first main surface and the second main surface. The second conductive layer of the first substrate element and the second conductive layer of the second substrate element include contact regions, which face the plurality of dies and selectively make electrical contact with the plurality of dies. The power electronics module further includes: First external terminal; Second external terminal; Third external terminal; and The fourth external terminal, wherein: The first transistor, the second transistor, the third transistor, and the fourth transistor each have a first conductive terminal, a second conductive terminal, and a control terminal. The second conductive layer of the first substrate element includes: The first connection region couples the first conductive terminal of the first transistor of the first branch to the first conductive terminal of the third transistor of the second branch, and the first connection region is coupled to the first external terminal. The second connection region couples the first conductive terminal of the first transistor in the first branch to the second external terminal; and The third connection region couples the first conductive terminal of the second transistor in the second branch to the third external terminal; The second conductive layer of the second substrate element includes: The fourth connection region couples the second conductive terminal of the second transistor of the first branch to the second conductive terminal of the fourth transistor of the second branch, and the second connection region is coupled to the fourth external terminal; The fifth connection region couples the fourth connection region to the second conductive terminal of the first transistor in the first branch; and The sixth connection region couples the third connection region to the first conductive terminal of the third transistor in the second branch. At least one of the second conductive layers of the first substrate element and the second substrate element includes an external control region, which is coupled to the control terminals of the first transistor, the second transistor, the third transistor, and the fourth transistor of the first branch and the second branch, respectively.

10. The power electronic module according to claim 9, further comprising a second cooling structure on the second main surface of the electronic device.

11. The power electronic module according to claim 9, wherein: The first electronic device also includes: A first height extends from the first main surface to the second main surface in a direction from the first main surface to the second main surface; and A rod pin has a rod pin height extending in the direction from the first main surface to the second main surface; The first cooling structure has a second height extending in the direction from the first main surface to the second main surface; The height of the rod pin is greater than the sum of the first height and the second height; and The rod pin is in direct electrical contact with the load-bearing structure.

12. The power electronic module of claim 11, further comprising a second cooling structure on the second main surface of the first electronic device, the second cooling structure having a third height extending in the direction from the first main surface to the second main surface, and The height of the rod pin is equal to the sum of the first height of the first electronic device, the second height of the first cooling structure, and the third height of the second cooling structure, and the rod pin is in direct electrical contact with the support structure.

13. The power electronic module according to claim 11, further comprising: The second electronic device is arranged above the first electronic device and below the first cooling structure, and A third cooling structure is arranged between the first electronic device and the second electronic device.

14. An electronic device, comprising: The first substrate includes: First sidewall; A first surface and a second surface, wherein the second surface is opposite to the first surface; A first conductive layer is located on the first surface; A first insulating layer is on the first conductive layer; A second conductive layer is on the first insulating layer and at the second surface; The second substrate includes: Second sidewall; A third surface and a fourth surface, wherein the fourth surface is opposite to the third surface and the third surface faces the first substrate; A third conductive layer is located on the third surface; A second insulating layer is disposed on the second conductive layer; and A fourth conductive layer is present on the insulating layer and at the fourth surface; Multiple dies are on the first conductive layer and overlapped by the second conductive layer, and the multiple dies are coupled to the first conductive layer and the second conductive layer; A package quality block, located between the second surface of the first substrate and the third surface of the second substrate, the package quality block comprising: The portion extending outward from the first sidewall and the second sidewall; and A groove extends into the portion. The plurality of dies includes: The first branch of the die includes: A first die, having a first transistor; and The second die has a second transistor, which is connected in series with the first transistor; The second branch of the die includes: The third die, having a third transistor; and A fourth die has a fourth transistor, which is connected in series with the third transistor, and wherein: The first transistor, the second transistor, the third transistor, and the fourth transistor each have a first conductive terminal, a second conductive terminal, and a control terminal. The second conductive layer of the first substrate includes: A first connection region couples the first conductive terminal of the first transistor of the first branch to the first conductive terminal of the third transistor of the second branch; The second connection region, coupled to the first conductive terminal of the first transistor of the first branch; and The third connection region is the first conductive terminal of the second transistor coupled to the second branch; The third conductive layer of the second substrate includes: The fourth connection region couples the second conductive terminal of the second transistor of the first branch to the second conductive terminal of the fourth transistor of the second branch; The fifth connection region couples the fourth connection region to the second conductive terminal of the first transistor in the first branch; and The sixth connection region couples the third connection region to the first conductive terminal of the third transistor in the second branch. At least one of the second conductive layer of the first substrate and the third conductive layer of the second substrate includes an external control region, which is coupled to the control terminals of the first transistor, the second transistor, the third transistor, and the fourth transistor of the first branch and the second branch, respectively.

15. The electronic device of claim 14, wherein the plurality of dies further comprises: The third branch of the die includes: The fifth die, containing the fifth transistor; and The sixth die has a sixth transistor, which is connected in series with the fifth transistor.

16. The electronic device according to claim 14, further comprising: A package mass block extends around the first substrate and the second substrate, covering the first sidewall of the first substrate and the second sidewall of the second substrate, the package mass block comprising: The portion extending outward from the first sidewall and the second sidewall; and The groove extends into the package mass block, and The first height of the portion in the direction from the first main surface to the second main surface is equal to the second height of the device in the direction from the first main surface to the second main surface.

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