Voltage converter and method of operation thereof
By optimizing the transistor design and circuit structure of the voltage converter, the problem of uneven output voltage conversion speed was solved, achieving fast and uniform voltage conversion and reducing circuit area.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- EMEMORY TECH INC
- Filing Date
- 2023-03-17
- Publication Date
- 2026-05-01
AI Technical Summary
Existing voltage converters exhibit uneven output voltage conversion speeds when the input voltage changes, particularly slow conversion speeds from high logic levels to low logic levels, and require a large circuit area.
By employing a combined design of input transistors, control circuits, reset circuits, and holding circuits, the node voltage is rapidly switched by controlling the pulse voltage, reducing the number of transistors in the reset circuit, and optimizing the transistor channel width-to-length ratio and gate oxide thickness to achieve fast and symmetrical voltage switching.
It achieves uniform switching speed of output voltage from high logic level to low logic level and from low logic level to high logic level, with smaller circuit area and reduced transistor adjustment requirements in the reset circuit.
Smart Images
Figure CN116896270B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a level shifting technique, and more particularly to a high-speed voltage converter and its operation method. Background Technology
[0002] With the development of technology, various circuits have been developed. For example, voltage converters have been applied to a wide variety of circuit systems, and they can convert input voltages with a narrow voltage range into output voltages with a wider voltage range. In some related technologies, the output voltage changes slowly as the input voltage changes. Summary of the Invention
[0003] This disclosure relates to a voltage converter. The voltage converter includes an input transistor, a control circuit, a reset circuit, and a holding circuit. The input transistor receives an input voltage and a first reference voltage. The control circuit generates a pulse voltage based on one of a node voltage, an output voltage, and an inverting input voltage, as well as the input voltage. The reset circuit receives the first reference voltage and a second reference voltage, and is disabled by the pulse voltage when the input voltage changes from the first voltage to the second voltage, causing the node voltage to change from the second reference voltage to the first reference voltage; and is enabled by the pulse voltage when the input voltage changes from the second voltage to the first voltage, causing the node voltage to change from the first reference voltage to the second reference voltage. The reset circuit is coupled to the input transistor at the first node where the node voltage is generated. The holding circuit is coupled to the first node and generates an output voltage based on the node voltage, the first reference voltage, the second reference voltage, and the output voltage.
[0004] In some embodiments, the first reference voltage is lower than the second reference voltage.
[0005] In some embodiments, the control circuit includes a NOR gate. The NOR gate is used to generate pulse voltages based on the input voltage and the node voltage.
[0006] In some embodiments, the control circuit includes an inverter and a NOR gate. The inverter is used to generate an inverted output voltage based on the output voltage. The NOR gate is used to generate a pulse voltage based on the input voltage and the inverted output voltage.
[0007] In some embodiments, the control circuit is a pulse generator. The pulse generator includes multiple inverters and NOR gates. The inverters are used to generate an inverted input voltage based on the input voltage. The NOR gates are used to generate a pulse voltage based on the input voltage and the inverted input voltage.
[0008] In some embodiments, the voltage converter further includes a reset transistor. The reset transistor is used to receive a second reference voltage, is coupled to the first node, and is controlled by a reset signal.
[0009] In some embodiments, the reset circuit includes a first transistor, a second transistor, and a third transistor. The first transistor receives a first reference voltage and is controlled by a pulse voltage. The second transistor receives a second reference voltage, is coupled to the first transistor, and is controlled by a pulse voltage. The third transistor receives the second reference voltage, is coupled to the input transistor, and is controlled by the voltage at a second node between the first and second transistors.
[0010] In some embodiments, the holding circuit includes a fourth transistor and an inverter. The fourth transistor receives a second reference voltage, is coupled to the first node, and is controlled by the output voltage. The inverter inverts the node voltage to generate the output voltage.
[0011] In some embodiments, the input transistor and the first transistor are implemented using N-type transistors, and the second transistor, the third transistor, and the fourth transistor are implemented using P-type transistors.
[0012] In some embodiments, the channel width-to-length ratio of the input transistor is greater than that of the channel width-to-length ratio of the fourth transistor.
[0013] In some embodiments, the channel width-to-length ratio of the first transistor is greater than that of the second transistor.
[0014] In some embodiments, the reset circuit further includes a fourth transistor and a fifth transistor. The fourth transistor is coupled between the first transistor and the second transistor. The fourth transistor and the fifth transistor are bias-controlled.
[0015] In some embodiments, the first reference voltage is higher than the second reference voltage.
[0016] In some embodiments, the control circuit includes a NAND gate. The NAND gate is used to generate pulse voltages based on the input voltage and the node voltage.
[0017] In some embodiments, the reset circuit includes a first transistor, a second transistor, and a third transistor. The first transistor receives a first reference voltage and is controlled by a pulse voltage. The second transistor receives a second reference voltage, is coupled to the first transistor, and is controlled by a pulse voltage. The third transistor receives the second reference voltage, is coupled to the input transistor, and is controlled by the drain voltage of the first transistor.
[0018] In some embodiments, the holding circuit includes a fourth transistor and an inverter. The fourth transistor receives a second reference voltage, is coupled to the first node, and is controlled by the output voltage. The inverter inverts the node voltage to generate the output voltage.
[0019] In some embodiments, the input transistor and the first transistor are implemented using P-type transistors, and the second transistor, the third transistor, and the fourth transistor are implemented using N-type transistors.
[0020] Some embodiments disclosed herein relate to a method of operating a voltage converter. The method includes the following operations: when the input voltage changes from a first voltage to a second voltage, an input transistor is turned on by the input voltage, causing the node voltage to be pulled by a first reference voltage and the output voltage to be pulled by a second reference voltage; when the input voltage changes from the second voltage to the first voltage, a pulse voltage is generated to turn on a first transistor in a reset circuit, causing the node voltage to be pulled by the second reference voltage and the output voltage to be pulled by the first reference voltage; and the pulse voltage turns off the first transistor.
[0021] In some embodiments, the reset circuit includes the first transistor, the second transistor, and the third transistor. The first transistor receives a first reference voltage and is controlled by a pulse voltage. The second transistor receives a second reference voltage, is coupled to the first transistor, and is controlled by a pulse voltage. The third transistor receives the second reference voltage, is coupled to the input transistor, and is controlled by the voltage at a second node between the first and second transistors. The holding circuit includes a fourth transistor and an inverter. The fourth transistor receives the second reference voltage, is coupled to the first node, and is controlled by the output voltage. The inverter inverts the node voltage to generate the output voltage. The channel width-to-length ratio of the input transistor is greater than that of the fourth transistor.
[0022] In some embodiments, the reset circuit includes a first transistor, a second transistor, and a third transistor. The first transistor receives a first reference voltage and is controlled by a pulse voltage. The second transistor receives a second reference voltage, is coupled to the first transistor, and is controlled by a pulse voltage. The third transistor receives the second reference voltage, is coupled to the input transistor, and is controlled by the voltage at a second node between the first and second transistors. The holding circuit includes a fourth transistor and an inverter. The fourth transistor receives the second reference voltage, is coupled to the first node, and is controlled by the output voltage. The inverter inverts the node voltage to generate the output voltage. The channel width-to-length ratio of the first transistor is greater than that of the second transistor. Attached Figure Description
[0023] To make the above and other objects, features, advantages and embodiments disclosed herein more apparent and understandable, the accompanying drawings are described below:
[0024] Figure 1 This is a schematic diagram of a voltage converter illustrated according to some embodiments of this disclosure;
[0025] Figure 2It is illustrated in accordance with some embodiments of this disclosure. Figure 1 Waveform of the voltage in a voltage converter;
[0026] Figure 3 This is a schematic diagram of a voltage converter illustrated according to some embodiments of this disclosure;
[0027] Figure 4 This is a schematic diagram of a voltage converter illustrated according to some embodiments of this disclosure;
[0028] Figure 5 This is a schematic diagram of a voltage converter illustrated according to some embodiments of this disclosure;
[0029] Figure 6 This is a schematic diagram of a voltage converter illustrated according to some embodiments of this disclosure;
[0030] Figure 7 It is illustrated in accordance with some embodiments of this disclosure. Figure 6 Waveform diagram of the voltage in a voltage converter; and
[0031] Figure 8 This is a flowchart illustrating the operation method according to some embodiments of this disclosure. Detailed Implementation
[0032] The term "coupled" as used in this article can also refer to "electrical coupling," and the term "connection" can also refer to "electrical connection." "Coupled" and "connection" can also refer to two or more components cooperating or interacting with each other.
[0033] refer to Figure 1 . Figure 1 This is a schematic diagram of a voltage converter 100 illustrated according to some embodiments of the present disclosure. The voltage converter 100 is used to convert an input voltage IN with a smaller voltage range into an output voltage OUT with a larger voltage range.
[0034] by Figure 1 For example, voltage converter 100 includes input transistor MN0, control circuitry 120, reset circuitry 130, and holding circuitry 140.
[0035] The first terminal of input transistor MN0 receives ground voltage GND (e.g., a first reference voltage), the second terminal of input transistor MN0 is coupled to node N1, and the control terminal of input transistor MN0 receives input voltage IN. In other words, input transistor MN0 is controlled to turn on or off by input voltage IN. In this example, input transistor MN0 is implemented using an N-type transistor.
[0036] The control circuit 120 generates a pulse voltage H_PULSE based on the input voltage IN and the node voltage ZPO at node N1. Figure 1 For example, control circuit 120 includes a NOR gate 121. The first input of NOR gate 121 receives the input voltage IN, and the second input of NOR gate 121 receives the node voltage ZPO located at node N1. NOR gate 121 performs a NOR operation on the input voltage IN and the node voltage ZPO to generate a pulse voltage H_PULSE at the output of NOR gate 121.
[0037] The reset circuit 130 receives the ground voltage GND and the power supply voltage VHIGH (e.g., a second reference voltage higher than the first reference voltage). Furthermore, the reset circuit 130 is controlled by the pulse voltage H_PULSE. Figure 1 For example, reset circuit 130 includes transistors MN1, MP0, and MP1. A first terminal of transistor MN1 receives ground voltage GND, a second terminal of transistor MN1 is coupled to the first terminal of transistor MP0, and a control terminal of transistor MN1 receives a pulse voltage H_PULSE. In other words, transistor MN1 is controlled to turn on or off by the pulse voltage H_PULSE. A second terminal of transistor MP0 receives a power supply voltage VHIGH, and a control terminal of transistor MP0 receives the pulse voltage H_PULSE. In other words, transistor MP0 is also controlled to turn on or off by the pulse voltage H_PULSE. A first terminal of transistor MP1 is coupled to the second terminal of input transistor MN0 at node N1, a second terminal of transistor MP1 receives the power supply voltage VHIGH, and a control terminal of transistor MP1 is coupled to the second terminal of transistor MN1. In other words, transistor MP1 is controlled to turn on or off by the voltage at node N2 between transistors MN1 and MP0 (e.g., the drain voltage of transistor MN1). In this example, transistor MN1 is implemented using an N-type transistor, and transistors MP0 and MP1 are implemented using P-type transistors.
[0038] The circuit 140 is coupled to node N1 and generates the output voltage OUT based on the node voltage ZPO, ground voltage GND, power supply voltage VHIGH, and output voltage OUT. Figure 1 For example, the holding circuit 140 includes a transistor MP2 and an inverter 141. A first terminal of transistor MP2 is coupled to node N1, a second terminal of transistor MP2 receives the power supply voltage VHIGH, and a control terminal of transistor MP2 receives the output voltage OUT. In other words, transistor MP2 is controlled to turn on or off by the output voltage OUT. Inverter 141 generates the output voltage OUT based on the node voltage ZPO, the ground voltage GND, and the power supply voltage VHIGH. In other words, inverter 141 inverts the node voltage ZPO. Figure 1 For example, inverter 141 includes transistor MN5 and transistor MP5. A first terminal of transistor MN5 receives ground voltage GND, a second terminal of transistor MN5 is coupled to the first terminal of transistor MP5, and the control terminal of transistor MN5 receives node voltage ZPO. The second terminal of transistor MP5 receives power supply voltage VHIGH, and the control terminal of transistor MP5 also receives node voltage ZPO. In other words, transistors MN5 and MP5 are controlled by node voltage ZPO to turn on or off, thereby generating an output voltage OUT. In this example, transistor MN5 is implemented as an N-type transistor, and transistors MP2 and MP5 are implemented as P-type transistors.
[0039] Please refer to the above. Figure 1 and Figure 2 . Figure 2 It is illustrated in accordance with some embodiments of this disclosure. Figure 1 Waveform of the voltage in voltage converter 100.
[0040] by Figure 2 For example, before the transition period TS1, the output voltage OUT is at ground GND, and transistor MP2 is turned on according to the output voltage OUT. Transistor MP2 turns on the supply voltage VHIGH, so the node voltage ZPO is at the supply voltage VHIGH, which in turn turns on transistor MN5 to keep the output voltage OUT at ground GND. Alternatively, before the transition period TS1, the input voltage IN is at voltage V1 (e.g., a low logic level) and the input transistor MN0 is off, so the node voltage ZPO can be kept at the supply voltage VHIGH to keep the output voltage OUT at ground GND. Transistor MP2 is turned on by the output voltage OUT.
[0041] Next, during the transition period TS1 (i.e., the reset circuit 130 is disabled), the input voltage IN rises from voltage V1 to voltage V2 (e.g., a high logic level), and the input transistor MN0 is turned on by the input voltage IN. Since both transistor MP2 and the input transistor MN0 are turned on, a pull-up / pull-down contention path FP1 exists between transistor MP2 and the input transistor MN0. The input transistor MN0 can be designed to be stronger than transistor MP2. More specifically, in some embodiments, the channel width-to-length ratio of the input transistor MN0 is designed to be greater than that of the transistor MP2. For example, the channel width-to-length ratio of the input transistor MN0 can be 2-6 times that of the transistor MP2. In some other embodiments, the gate oxide thickness of the input transistor MN0 is designed to be thinner than that of the transistor MP2. Because the input transistor MN0 is turned on by the input voltage IN, the node voltage ZPO is quickly pulled down by the ground voltage GND through the turned-on input transistor MN0. Accordingly, the output voltage OUT generated by the inverter 141 is quickly pulled up by the power supply voltage VHIGH.
[0042] During the steady-state period SS1, when the output voltage OUT rises to the supply voltage VHIGH, transistor MP2 is quickly turned off and no quiescent current flows through the pull-up / pull-down contention path FP1. Therefore, the node voltage ZPO is held at ground GND, and the input voltage IN is held at voltage V2, such that the pulse voltage H_PULSE, the result of the NOR operation between the input voltage IN (V2) and the node voltage ZPO (GND), is held at voltage V1. Because the pulse voltage H_PULSE is held at voltage V1, transistor MN1 is turned off and transistor MP0 is turned on. The turned-on transistor MP0 turns on the supply voltage VHIGH to turn off transistor MP1. Therefore, the node voltage ZPO is not pulled up to the supply voltage VHIGH through transistor MP1. Accordingly, the node voltage ZPO is held at ground GND, the output voltage OUT is held at the supply voltage VHIGH, and the supply voltage VHIGH is higher than voltage V2.
[0043] During the transition period TS2 (i.e., when reset circuit 130 is enabled), the input voltage IN drops from voltage V2 to voltage V1. Since the input voltage IN and node voltage ZPO are at low logic levels at the start of the transition period TS2, the pulse voltage H_PULSE rises from voltage V1 to voltage V2 to turn on transistor MN1, and a pull-up / pull-down contention path FP2 exists between transistor MP0 and transistor MN1. Transistor MN1 can be designed to be stronger than transistor MP0. More specifically, in some embodiments, the channel width-to-length ratio of transistor MN1 is designed to be greater than that of transistor MP0. For example, the channel width-to-length ratio of transistor MN1 can be 2-6 times that of transistor MP0. In some other embodiments, the gate oxide thickness of transistor MN1 is designed to be thinner than that of transistor MP0. Therefore, the second terminal of transistor MN1 is rapidly pulled down by ground voltage GND through the turned-on transistor MN1. Because the second terminal of transistor MN1 (e.g., the control terminal of transistor MP1) is rapidly pulled down, transistor MP1 quickly turns on, and the node voltage ZPO is rapidly pulled up by the power supply voltage VHIGH through the conducting transistor MP1. Accordingly, the output voltage OUT generated by inverter 141 is rapidly pulled down by the ground voltage GND.
[0044] During the steady-state period SS2, when the node voltage ZPO rises to the supply voltage VHIGH, the pulse voltage H_PULSE rapidly drops from voltage V2 to voltage V1 to turn off transistor MN1, and no quiescent current flows through the pull-up / pull-down contention path FP2. Transistor MP0 is turned on based on the pulse voltage H_PULSE at voltage V1 to turn on the supply voltage VHIGH and turn off transistor MP1. Therefore, the input voltage IN is held at voltage V1, the pulse voltage H_PULSE is held at voltage V1, the node voltage ZPO is held at the supply voltage VHIGH, and the output voltage OUT is held at ground GND.
[0045] In some voltage converters in related technologies, the conversion speed of the output voltage from a high logic level to a low logic level differs significantly from the conversion speed of the output voltage from a low logic level to a high logic level. For example, the conversion speed of the output voltage from a high logic level to a low logic level is very slow.
[0046] Compared to the aforementioned related technologies, the transition speed of the output voltage from a high logic level to a low logic level in this disclosure is very close to the transition speed of the output voltage from a low logic level to a high logic level. In other words, both the transition speed of the output voltage from a high logic level to a low logic level and the transition speed of the output voltage from a low logic level to a high logic level are very fast.
[0047] In addition, compared to some related technologies, the reset circuit 130 disclosed herein has fewer transistors. Therefore, the circuit area of the disclosed circuit can be smaller. Furthermore, when the transistor size in the reset circuit 130 needs to be adjusted, fewer transistors need to be adjusted.
[0048] refer to Figure 3 . Figure 3 This is a schematic diagram of a voltage converter 300 illustrated according to some embodiments of the present disclosure. One of the main differences between voltage converter 300 and voltage converter 100 is that voltage converter 300 includes control circuitry 320 instead of control circuitry 120.
[0049] The control circuit 320 generates a pulse voltage H_PULSE based on the input voltage IN and the output voltage OUT. Figure 3 For example, control circuit 320 includes an inverter 321 and a NOR gate 322. The input of inverter 321 receives the output voltage OUT to generate an inverted output voltage OUT' based on the output voltage OUT. The first input of NOR gate 322 receives the input voltage IN, and the second input of NOR gate 322 receives the inverted output voltage OUT'. NOR gate 322 performs a NOR operation on the input voltage IN and the inverted output voltage OUT' to generate a pulse voltage H_PULSE at the output of NOR gate 322.
[0050] by Figure 2 For example, the trend of the output voltage OUT is almost opposite to the trend of the node voltage ZPO. Therefore, in Figure 3 In this circuit, the changing trend of the inverting output voltage OUT' is almost identical to that of the node voltage ZPO. Therefore, the operation of control circuit 320 is similar to that of control circuit 120, making the operation of voltage converter 300 similar to that of voltage converter 100.
[0051] refer to Figure 4 . Figure 4 This is a schematic diagram of a voltage converter 400 illustrated according to some embodiments of the present disclosure. One of the main differences between voltage converter 400 and voltage converter 100 is that voltage converter 400 includes control circuitry 420 instead of control circuitry 120. Another main difference between voltage converter 400 and voltage converter 100 is that voltage converter 400 includes holding circuitry 440, which includes... Figure 1 The circuit includes a holding circuit 140 and a reset transistor MP4. In this example, the reset transistor MP4 is implemented using a P-type transistor.
[0052] The control circuit 420 generates a pulse voltage H_PULSE based on the input voltage IN and the inverted input voltage IN'. The control circuit 420 is implemented using a pulse generator. Figure 4For example, control circuit 420 includes multiple inverters 421 and NOR gates 422. These inverters 421 receive an input voltage IN to generate an inverted input voltage IN' based on the input voltage IN. The first input of each NOR gate 422 receives the input voltage IN, and the second input of each NOR gate 422 receives the inverted input voltage IN'. The NOR gate 422 performs a NOR operation on the input voltage IN and the inverted input voltage IN' to generate a pulse voltage H_PULSE at the output of the NOR gate 422. These inverters 421 can provide a time delay, allowing the pulse voltage H_PULSE to transition from a low logic level to a high logic level after the time delay.
[0053] by Figure 2 For example, the trend of the input voltage IN is almost opposite to the trend of the node voltage ZPO. Similarly, in Figure 4 In this circuit, the changing trend of the inverting input voltage IN' is almost identical to that of the node voltage ZPO. Therefore, the operation of control circuit 420 is similar to that of control circuit 120, making the operation of voltage converter 400 similar to that of voltage converter 100.
[0054] In addition, the first terminal of the reset transistor MP4 is coupled to node N1, the second terminal of the reset transistor MP4 receives the power supply voltage VHIGH, and the control terminal of the reset transistor MP4 receives the reset signal RESET. In other words, the reset transistor MP4 is controlled by the reset signal RESET to turn on or off. In this example, the reset transistor MP4 is implemented by a P-type transistor. Before the voltage converter 400 starts operating (i.e., before the transition period TS1), the reset signal RESET has a low logic level. Therefore, the reset transistor MP4 is turned on, and the node voltage ZPO is pulled up to the power supply voltage VHIGH through the turned-on reset transistor MP4. Accordingly, the output voltage OUT is pulled down to the ground voltage GND. Therefore, the output voltage OUT is not in an unknown state.
[0055] refer to Figure 5 . Figure 5 This is a schematic diagram of a voltage converter 500 illustrated according to some embodiments of the present disclosure. One of the main differences between voltage converter 500 and voltage converter 100 is that the reset circuit 530 further includes transistors MN2 and MN3. In this example, transistors MN2 and MN3 are implemented by N-type transistors.
[0056] by Figure 5For example, transistor MN2 is coupled between transistor MP1 and input transistor MN0, and transistor MN3 is coupled between transistor MP0 and transistor MN1. The control terminals of transistors MN2 and MN3 receive a bias voltage VSN. Transistor MN2 is used to prevent excessive voltage at the second terminal of input transistor MN0 (e.g., the drain voltage of input transistor MN0). Similarly, transistor MN3 is used to prevent excessive voltage at the second terminal of transistor MN1 (e.g., the drain voltage of transistor MN1), so that input transistors MN0 and MN1 can operate in the safe operating area (SOA) without being damaged.
[0057] refer to Figure 6 . Figure 6 This is a schematic diagram of a voltage converter 600 illustrated according to some embodiments of the present disclosure.
[0058] by Figure 6 For example, voltage converter 600 includes input transistor TP0, control circuitry 620, reset circuitry 630, and holding circuitry 640.
[0059] The first terminal of input transistor TP0 receives a reference voltage VDD (e.g., a first reference voltage), the second terminal of input transistor TP0 is coupled to node NP1, and the control terminal of input transistor TP0 receives an input voltage IN. In other words, input transistor TP0 is controlled to turn on or off by the input voltage IN. In this example, input transistor TP0 is implemented using a P-type transistor.
[0060] The control circuit 620 generates a pulse voltage L_PULSE based on the input voltage IN and the node voltage ZPO at node NP1. Figure 6 For example, control circuit 620 includes NAND gate 621. The first input of NAND gate 621 receives the input voltage IN, and the second input receives the node voltage ZPO at node NP1. NAND gate 621 performs a NAND operation on the input voltage IN and the node voltage ZPO to generate a pulse voltage L_PULSE at the output of NAND gate 621.
[0061] The reset circuit 630 receives a reference voltage VDD and a reference voltage VBB (e.g., a second reference voltage lower than the first reference voltage). Furthermore, the reset circuit 630 is controlled by a pulse voltage L_PULSE. Figure 6For example, reset circuit 630 includes transistors TP1, TN1, and TN0. A first terminal of transistor TP1 receives a reference voltage VDD, a second terminal of transistor TP1 is coupled to the first terminal of transistor TN1, and a control terminal of transistor TP1 receives a pulse voltage L_PULSE. In other words, transistor TP1 is controlled to turn on or off by the pulse voltage L_PULSE. A second terminal of transistor TN1 receives a reference voltage VBB, and a control terminal of transistor TN1 receives the pulse voltage L_PULSE. In other words, transistor TN1 is also controlled to turn on or off by the pulse voltage L_PULSE. A first terminal of transistor TN0 is coupled to the second terminal of input transistor TP0 at node NP1, a second terminal of transistor TN0 receives the reference voltage VBB, and a control terminal of transistor TN0 is coupled to the second terminal of transistor TP1. In other words, transistor TN0 is controlled to turn on or off by the voltage at node NP2 between transistors TP1 and TN1 (i.e., the drain voltage of transistor TP1). In this example, transistor TP1 is implemented using a P-type transistor, and transistors TN1 and TN0 are also implemented using P-type transistors.
[0062] The circuit 640 is coupled to node NP1 and generates the output voltage OUT based on the node voltage ZPO, the reference voltage VDD, the reference voltage VBB, and the output voltage OUT. Figure 6 For example, the holding circuit 640 includes transistor TN2 and inverter 641. The first terminal of transistor TN2 is coupled to node NP1, the second terminal of transistor TN2 receives a reference voltage VBB, and the control terminal of transistor TN2 receives the output voltage OUT. In other words, transistor TN2 is controlled to turn on or off by the output voltage OUT. Inverter 641 generates the output voltage OUT based on the node voltage ZPO, the reference voltage VDD, and the reference voltage VBB. In other words, inverter 641 inverts the node voltage ZPO. Figure 6 For example, inverter 641 includes transistors TP5 and TN5. The first terminal of transistor TP5 receives a reference voltage VDD, the second terminal of transistor TP5 is coupled to the first terminal of transistor TN5, and the control terminal of transistor TP5 receives a node voltage ZPO. The second terminal of transistor TN5 receives a reference voltage VBB, and the control terminal of transistor TN5 receives the node voltage ZPO. In other words, transistors TP5 and TN5 are controlled by the node voltage ZPO to turn on or off, thereby generating an output voltage OUT. In this example, transistor TP5 is implemented as a P-type transistor, and transistors TN2 and TN5 are implemented as N-type transistors.
[0063] Please refer to the above. Figure 6 and Figure 7 . Figure 7It is illustrated in accordance with some embodiments of this disclosure. Figure 6 Waveform of the voltage in voltage converter 600.
[0064] by Figure 7 For example, before the transition period TS1, the output voltage OUT is at the reference voltage VDD, and transistor TN2 is turned on according to the control of the output voltage OUT. Transistor TN2 turns on the reference voltage VBB, so the node voltage ZPO is at the reference voltage VBB, which in turn turns on transistor TP5 to keep the output voltage OUT at the reference voltage VDD. Furthermore, before the transition period TS1, the input voltage IN is at voltage V2 and the input transistor TP0 is off, so the node voltage ZPO can be kept at the reference voltage VBB to keep the output voltage OUT at the reference voltage VDD. Transistor TN2 is turned on by the output voltage OUT.
[0065] Next, during the transition period TS1 (i.e., the reset circuit 630 is disabled), the input voltage IN drops from voltage V2 to voltage V1, and the input transistor TP0 is turned on by the input voltage IN. Since transistor TN2 and the input transistor TP0 are both turned on, a pull-up / pull-down contention path FP3 exists between the input transistor TP0 and transistor TN2. The input transistor TP0 can be designed to be stronger than transistor TN2. More specifically, in some embodiments, the channel width-to-length ratio of the input transistor TP0 is designed to be greater than that of transistor TN2. For example, the channel width-to-length ratio of the input transistor TP0 can be 2-6 times that of transistor TN2. In some other embodiments, the gate oxide thickness of TP0 is designed to be thinner than that of TN2. Because the input transistor TP0 is turned on by the input voltage IN, the node voltage ZPO is quickly pulled up by the reference voltage VDD through the turned-on input transistor TP0. Accordingly, the output voltage OUT generated by inverter 641 is quickly pulled down by the reference voltage VBB.
[0066] During the steady-state period SS1, when the output voltage OUT drops to the reference voltage VBB, transistor TN2 quickly turns off and no quiescent current flows through the pull-up / pull-down contention path FP3. Therefore, the node voltage ZPO is held at the reference voltage VDD, and the input voltage IN is held at voltage V1, such that the pulse voltage L_PULSE, the result of the NAND operation between the input voltage IN (V1) and the node voltage ZPO (VDD), is held at voltage V2. Because the pulse voltage L_PULSE is held at voltage V2, transistor TN1 turns on and transistor TP1 turns off. The turned-on transistor TN1 turns on the reference voltage VBB to turn off transistor TN0. Therefore, the node voltage ZPO is not pulled down to the reference voltage VBB through transistor TN0. Accordingly, the node voltage ZPO is held at the reference voltage VDD, and the output voltage OUT is held at the reference voltage VBB.
[0067] During the transition period TS2 (i.e., when reset circuit 630 is enabled), the input voltage IN rises from voltage V1 to voltage V2. Since the input voltage IN and node voltage ZPO have high logic levels at the start of the transition period TS2, the pulse voltage L_PULSE drops from voltage V2 to voltage V1 to turn on transistor TP1, and a pull-up / pull-down contention path FP4 exists between transistor TP1 and transistor TN1. Transistor TP1 can be designed to be stronger than transistor TN1. More specifically, in some embodiments, the channel width-to-length ratio of transistor TP1 is designed to be greater than that of transistor TN1. For example, the channel width-to-length ratio of transistor TP1 can be 2-6 times that of transistor TN1. In some other embodiments, the gate oxide thickness of transistor TP1 is designed to be thinner than that of transistor TN1. Therefore, the second terminal of transistor TP1 is quickly pulled up by the reference voltage VDD through the turned-on transistor TP1. Because the second terminal of transistor TP1 (e.g., the control terminal of transistor TN0) is quickly pulled up, transistor TN0 quickly turns on, and the node voltage ZPO is quickly pulled down by the reference voltage VBB through the conducting transistor TN0. Accordingly, the output voltage OUT generated by inverter 641 is quickly pulled up by the reference voltage VDD.
[0068] During the steady-state period SS2, when the node voltage ZPO drops to the reference voltage VBB, the pulse voltage L_PULSE rapidly rises from voltage V1 to voltage V2 to turn off transistor TP1, and no quiescent current flows through the pull-up / pull-down contention path FP4. Transistor TN1 is turned on based on the pulse voltage L_PULSE at voltage V2 to turn on the reference voltage VBB and turn off transistor TN0. Therefore, the input voltage IN is held at voltage V2, the pulse voltage L_PULSE is held at voltage V2, the node voltage ZPO is held at the reference voltage VBB, and the output voltage OUT is held at the reference voltage VDD.
[0069] refer to Figure 8 . Figure 8 This is a flowchart illustrating an operation method 800 according to some embodiments of this disclosure.
[0070] by Figure 8 For example, operation method 800 includes operations S810, S820, and S830. In some embodiments, operation method 800 can be applied to voltage converters 100, 300, 400, 500, or 600. For better understanding, the following will be used in conjunction with... Figure 1 The voltage converter 100 is described in terms of operation method 800.
[0071] In operation S810, when the input voltage IN changes from voltage V1 to voltage V2, the input transistor MN0 is turned on by the input voltage IN. Therefore, the node voltage ZPO is pulled down by the ground voltage GND through the turned-on input transistor MN0, and the output voltage OUT is pulled up by the power supply voltage VHIGH.
[0072] In operation S820, when the input voltage IN changes from voltage V2 to voltage V1, a pulse voltage H_PULSE is generated to turn on transistor MN1 in reset circuit 130. Therefore, node voltage ZPO is pulled up by power supply voltage VHIGH through the turned-on transistor MP1, and output voltage OUT is pulled down by ground voltage GND.
[0073] In operation of S830, when the node voltage ZPO is pulled up to the supply voltage VHIGH, the pulse voltage H_PULSE has a low logic level to turn off transistor MN1.
[0074] In summary, in this disclosure, the output voltage transition speed from high logic level to low logic level and the output voltage transition speed from low logic level to high logic level are both very fast.
[0075] Although this disclosure has been described above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art may make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.
[0076] [Symbol Explanation]
[0077] 100, 300, 400, 500, 600: Voltage converters
[0078] 120, 320, 420, 620: Control circuit
[0079] 121,322,422: NOR gate
[0080] 130, 530, 630: Reset circuit
[0081] 140, 440, 640: Holding circuit
[0082] 141,321,421,641: Inverters
[0083] 621: NAND gate
[0084] 800: Operating Methods
[0085] IN: Input voltage
[0086] OUT: Output voltage
[0087] MN0, TP0: Input transistors
[0088] GND: Ground voltage
[0089] N1, N2, NP1, NP2: Nodes
[0090] ZPO: Node voltage
[0091] H_PULSE, L_PULSE: Pulse voltage
[0092] VHIGH: Power supply voltage
[0093] MN1,MP0,MP1,MP2,MN5,MP5,MN2,MN3,TP1,TN1,TN0,TN2,TP5,TN5: Transistors
[0094] TS1, TS2: Transition Period
[0095] V1, V2: Voltage
[0096] FP1, FP2, FP3, FP4: Pull-up / Pull-down contention paths
[0097] SS1, SS2: Stable period
[0098] OUT': Inverting output voltage
[0099] MP4: Reset Transistor
[0100] IN': Inverting input voltage
[0101] RESET: Reset signal
[0102] VSN: Bias Voltage
[0103] VDD, VBB: Reference voltages
[0104] S810, S820, S830: Operation.
Claims
1. A voltage converter, characterized in that, Include: An input transistor is used to receive the input voltage and a first reference voltage; A control circuit is used to generate a pulse voltage based on one of the node voltage, the output voltage, and the inverting input voltage, as well as the input voltage. A reset circuit is configured to receive the first reference voltage and the second reference voltage, and when the input voltage changes from the first voltage to the second voltage, it is disabled by the pulse voltage, causing the node voltage to change from the second reference voltage to the first reference voltage; and when the input voltage changes from the second voltage to the first voltage, it is enabled by the pulse voltage, causing the node voltage to change from the first reference voltage to the second reference voltage, wherein the reset circuit is coupled to the input transistor at the first node that generates the node voltage; as well as A holding circuit, coupled to the first node, is used to generate the output voltage based on the node voltage, the first reference voltage, the second reference voltage, and the output voltage. The reset circuit includes: A first transistor is used to receive the first reference voltage and is controlled by the pulse voltage; The second transistor is used to receive the second reference voltage, is coupled to the first transistor, and is controlled by the pulse voltage; as well as The third transistor is used to receive the second reference voltage and is coupled to the input transistor, and is controlled by the voltage at the second node between the first transistor and the second transistor.
2. The voltage converter of claim 1, wherein the first reference voltage is lower than the second reference voltage.
3. The voltage converter according to claim 2, wherein the control circuit comprises: The NOR gate is used to generate the pulse voltage based on the input voltage and the node voltage.
4. The voltage converter of claim 2, wherein the control circuit comprises: An inverter, used to generate an inverted output voltage based on the output voltage; and The NOR gate is used to generate the pulse voltage based on the input voltage and the inverted output voltage.
5. The voltage converter of claim 2, wherein the control circuit is a pulse generator, and the pulse generator comprises: Multiple inverters are used to generate the inverted input voltage based on the input voltage; and The NOR gate is used to generate the pulse voltage based on the input voltage and the inverting input voltage.
6. The voltage converter according to claim 5, wherein, Also includes: A reset transistor is used to receive the second reference voltage, is coupled to the first node, and is controlled by a reset signal.
7. The voltage converter of claim 1, wherein the holding circuit comprises: A fourth transistor, used to receive the second reference voltage, coupled to the first node, and controlled by the output voltage; and An inverter is used to invert the node voltage to generate the output voltage.
8. The voltage converter of claim 7, wherein the input transistor and the first transistor are implemented by N-type transistors, and the second transistor, the third transistor and the fourth transistor are implemented by P-type transistors.
9. The voltage converter of claim 7, wherein the channel width-to-length ratio of the input transistor is greater than the channel width-to-length ratio of the fourth transistor.
10. The voltage converter of claim 7, wherein the channel width-to-length ratio of the first transistor is greater than the channel width-to-length ratio of the second transistor.
11. The voltage converter of claim 1, wherein the reset circuit further comprises: A fourth transistor is coupled between the first transistor and the second transistor; and The fifth transistor is coupled between the third transistor and the input transistor. The fourth and fifth transistors are bias-controlled.
12. The voltage converter of claim 1, wherein the first reference voltage is higher than the second reference voltage.
13. The voltage converter of claim 12, wherein the control circuit comprises: A NAND gate is used to generate the pulse voltage based on the input voltage and the node voltage.
14. The voltage converter of claim 12, wherein the holding circuit comprises: A fourth transistor, used to receive the second reference voltage, coupled to the first node, and controlled by the output voltage; and An inverter is used to invert the node voltage to generate the output voltage.
15. The voltage converter according to claim 14, characterized in that, The input transistor and the first transistor are implemented using P-type transistors, while the second transistor, the third transistor, and the fourth transistor are implemented using N-type transistors.
16. A method of operating a voltage converter according to claim 1, characterized in that, Include: When the input voltage changes from the first voltage to the second voltage, the input transistor is turned on by the input voltage, so that the node voltage is pulled by the first reference voltage and the output voltage is pulled by the second reference voltage; When the input voltage changes from the second voltage to the first voltage, the pulse voltage is generated to turn on the first transistor in the reset circuit, so that the node voltage is pulled by the second reference voltage and the output voltage is pulled by the first reference voltage; as well as The first transistor is disconnected by the pulse voltage.
17. The operating method according to claim 16, The holding circuit includes: A fourth transistor, used to receive the second reference voltage, coupled to the first node, and controlled by the output voltage; and An inverter is used to invert the node voltage to generate the output voltage. The channel width-to-length ratio of the input transistor is greater than that of the fourth transistor.
18. The operating method according to claim 16, The holding circuit includes: A fourth transistor, used to receive the second reference voltage, coupled to the first node, and controlled by the output voltage; and An inverter is used to invert the node voltage to generate the output voltage. The channel width-to-length ratio of the first transistor is greater than that of the second transistor.
Citation Information
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