Non-volatile memory device and manufacturing method thereof

Abstract

The present application provides a non-volatile memory device and a method for manufacturing the same, wherein the method comprises: forming a first gate oxide layer on a portion of a substrate; forming a second gate oxide layer on the remaining substrate; forming a floating gate polysilicon layer; forming a dielectric layer; forming a control gate polysilicon layer; forming a heavily doped region in the substrate; forming a step on the upper surface of a portion of the floating gate polysilicon layer; forming an interlayer insulating layer; and forming a first conductive plug, a second conductive plug, and a third conductive plug. By forming a combined oxide layer structure composed of a first gate oxide layer and a second gate oxide layer at the bottom of the floating gate polysilicon layer, the present application can effectively alleviate etching damage to the combined oxide layer at the bottom of the floating gate polysilicon layer when forming contact holes, thereby improving the electrical performance of the device. Furthermore, the present application forms a first capacitor, a second capacitor, and a third capacitor in parallel, and reduces the thickness of the second gate oxide layer in the third capacitor, thereby maximizing the electrostatic capacitance of the device capacitor.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a non-volatile memory device and a method for preparing the same. Background Art

[0002] Figure 1 This is a schematic diagram of the structure of a non-volatile memory device having a parallel capacitance structure of a gate oxide capacitor and a PIP capacitor in the prior art. An N-type heavily doped region (N+Junction) 6 is formed in the substrate. A low-voltage gate oxide 2 is formed on the surface of the substrate 1, and a P-type doped floating gate 3, an ONO dielectric layer (stacked oxide+nitride+oxide) 4, and a P-type doped control gate 5 are formed on the low-voltage gate oxide 2. Furthermore, an interlayer insulating layer 7 is formed on the P-type doped control gate 5, the P-type doped floating gate 3, and the N-type heavily doped region 6. Furthermore, a contact hole structure 1 8, a contact hole structure 2 9, a contact hole structure 2 ', and a contact hole structure 3 10 are formed in the interlayer insulating layer 7. At this point, a gate oxide capacitor (N-type heavily doped region 6-low-voltage gate oxide 2-floating gate 3) and a PIP capacitor (floating gate 3-ONO dielectric layer 4-control gate 5) are formed in the non-volatile memory device.

[0003] In addition, the structure of the back-end of the non-volatile memory device may refer to the existing structure of a conventional non-volatile memory device.

[0004] In existing non-volatile memory devices, the thickness of the low-voltage gate oxide layer is relatively thin, usually Below, the floating gate and control gate layers are made of polysilicon and serve as electrodes for a PIP (poly-insulation-poly) capacitor. The contact hole filling structure connects the floating gate layer, the control gate layer, and the heavily doped region, thereby connecting the gate oxide capacitor and the PIP capacitor in parallel, presenting the maximum capacitance of the capacitor.

[0005] like Figure 1 As shown, during contact hole etching, contact hole structure 8 connecting to floating gate 3 is typically formed on floating gate 3 with a gate oxide layer at the bottom to mitigate the effects of stress damage, film quality damage, and morphology damage caused by etching. To increase the electrostatic capacitance of the capacitor, a low-voltage gate oxide 2 is used at the bottom of floating gate 3 above the active area. When etching the contact hole for contact hole structure 8 above floating gate 3, stress damage, film quality damage, and morphology damage caused by etching can easily damage the thin low-voltage gate oxide 2, thereby affecting the electrical performance of the non-volatile memory device. Summary of the Invention

[0006] The present application provides a non-volatile memory device and a method for manufacturing the same, which can solve the problem that the formation of contact holes in the non-volatile memory device causes damage to the low-voltage gate oxide at the bottom of the floating gate, thereby affecting the electrical performance of the non-volatile memory device.

[0007] In one aspect, an embodiment of the present application provides a method for manufacturing a non-volatile memory device, comprising:

[0008] providing a substrate;

[0009] forming a first gate oxide layer, wherein the first gate oxide layer covers the substrate;

[0010] defining a high-voltage region and a low-voltage region on the substrate, and removing the first gate oxide layer in the low-voltage region;

[0011] forming a second gate oxide layer, wherein the second gate oxide layer covers the substrate of the low-voltage region, wherein the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, and the area of ​​the second gate oxide layer is greater than the area of ​​the first gate oxide layer;

[0012] forming a floating gate polysilicon layer, wherein the floating gate polysilicon layer covers the first gate oxide layer and the second gate oxide layer;

[0013] forming a dielectric layer, wherein the dielectric layer covers the floating gate polysilicon layer;

[0014] forming a control gate polysilicon layer, wherein the control gate polysilicon layer covers the dielectric layer;

[0015] Etching the control gate polysilicon layer, the dielectric layer, the floating gate polysilicon layer, and the first gate oxide layer in a first portion of the high voltage region to expose a first portion of the substrate, and etching the control gate polysilicon layer, the dielectric layer, the floating gate polysilicon layer, and the second gate oxide layer in a portion of the low voltage region to expose a second portion of the substrate;

[0016] performing an ion implantation process on the first substrate portion and the second substrate portion to form a plurality of heavily doped regions;

[0017] Etching the control gate polysilicon layer and the dielectric layer in the second portion of the high voltage region to the upper surface of the floating gate polysilicon layer to form a step;

[0018] forming an interlayer insulating layer, wherein the interlayer insulating layer covers the step, the control gate polysilicon layer, and the heavily doped region; and

[0019] forming a first conductive plug, a second conductive plug, and a plurality of third conductive plugs, wherein the first conductive plug penetrates the interlayer insulating layer and is connected to the floating gate polysilicon layer on the step surface, the second conductive plug penetrates the interlayer insulating layer and is connected to the control gate polysilicon layer, at least one of the third conductive plugs penetrates the interlayer insulating layer in the high-voltage region and is connected to the heavily doped region; and at least one of the third conductive plugs penetrates the interlayer insulating layer in the low-voltage region and is connected to the heavily doped region;

[0020] The heavily doped region, the first gate oxide layer and the floating gate polysilicon layer constitute a first capacitor; the floating gate polysilicon layer, the dielectric layer and the control gate polysilicon layer constitute a second capacitor; and the heavily doped region, the second gate oxide layer and the floating gate polysilicon layer constitute a third capacitor.

[0021] Optionally, in the method for preparing the non-volatile memory device, the thickness of the first gate oxide layer is greater than Preferably, the thickness of the first gate oxide layer is

[0022] Optionally, in the method for preparing the non-volatile memory device, the thickness of the second gate oxide layer is less than Preferably, the thickness of the second gate oxide layer is

[0023] Optionally, in the method for preparing the non-volatile memory device, the dielectric layer is an ONO dielectric layer.

[0024] Optionally, in the method for preparing the non-volatile memory device, an N-type heavily doped ion implantation process is performed on the first substrate portion and the second substrate portion to correspondingly form a plurality of N-type heavily doped regions.

[0025] Optionally, in the method for preparing the non-volatile memory device, the floating gate polysilicon layer and the control gate polysilicon layer are both P-type doped.

[0026] Optionally, in the method for preparing the non-volatile memory device, the material of the interlayer insulating layer is TEOS.

[0027] Optionally, in the method for manufacturing the non-volatile memory device, the step of forming the first conductive plug, the second conductive plug, and the third conductive plug includes:

[0028] Etching the interlayer insulating layer to form a first contact hole, a second contact hole, and a third contact hole in the interlayer insulating layer, wherein the first contact hole exposes the floating gate polysilicon layer at the step position, the second contact hole exposes the control gate polysilicon layer, and the third contact hole exposes the heavily doped region;

[0029] The first contact hole, the second contact hole, and the third contact hole are filled with a metal material to form a first conductive plug, a second conductive plug, and a third conductive plug, respectively. Optionally, the metal material filling the first contact hole, the second contact hole, and the third contact hole can be tungsten (W) or copper (Cu).

[0030] Optionally, in the method for manufacturing the non-volatile memory device, after performing an ion implantation process on the first and second substrate portions to form a plurality of heavily doped regions, and before etching the control gate polysilicon layer and the dielectric layer in the second portion of the high-voltage region to the upper surface of the floating gate polysilicon layer to form a step, the method for manufacturing the non-volatile memory device further comprises:

[0031] A thermal annealing process is performed to activate dopant ions in the heavily doped region.

[0032] On the other hand, an embodiment of the present application further provides a non-volatile memory device, comprising:

[0033] a substrate comprising a high-pressure region and a low-pressure region;

[0034] a first gate oxide layer, wherein the first gate oxide layer covers the substrate of the high voltage region;

[0035] a second gate oxide layer, wherein the second gate oxide layer covers the substrate of the low-voltage region, wherein the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, and the area of ​​the second gate oxide layer is greater than the area of ​​the first gate oxide layer;

[0036] a floating gate polysilicon layer, wherein the floating gate polysilicon layer covers the first gate oxide layer and the second gate oxide layer;

[0037] a dielectric layer, wherein the dielectric layer covers a portion of the floating gate polysilicon layer;

[0038] a control gate polysilicon layer, the control gate polysilicon layer covering the dielectric layer, wherein a surface of the floating gate polysilicon layer not covering the dielectric layer forms a step;

[0039] a plurality of heavily doped regions, each of which is located in the substrate;

[0040] an interlayer insulating layer, the interlayer insulating layer covering the step, the control gate polysilicon layer and the heavily doped region; and

[0041] a first conductive plug, a second conductive plug, and a plurality of third conductive plugs, wherein the first conductive plug penetrates the interlayer insulating layer and is connected to the floating gate polysilicon layer on the step surface, the second conductive plug penetrates the interlayer insulating layer and is connected to the control gate polysilicon layer, at least one of the third conductive plugs penetrates the interlayer insulating layer in the high-voltage region and is connected to the heavily doped region; and at least one of the third conductive plugs penetrates the interlayer insulating layer in the low-voltage region and is connected to the heavily doped region;

[0042] The heavily doped region, the first gate oxide layer and the floating gate polysilicon layer constitute a first capacitor; the floating gate polysilicon layer, the dielectric layer and the control gate polysilicon layer constitute a second capacitor; and the heavily doped region, the second gate oxide layer and the floating gate polysilicon layer constitute a third capacitor.

[0043] The technical solution of this application has at least the following advantages:

[0044] First, the present application forms a combined oxide layer structure of a first gate oxide layer and a second gate oxide layer at the bottom of the floating gate polysilicon layer on the same active area. The thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, thereby increasing the thickness of the combined oxide layer structure at the bottom of the contact hole and improving the film quality of the combined oxide layer structure at the bottom of the contact hole. This can effectively alleviate the damage of etching to the combined oxide layer at the bottom of the floating gate polysilicon layer when forming the contact hole, thereby improving the electrical performance of the NAND memory device.

[0045] Second, the present application forms a first capacitor, a second capacitor and a third capacitor in parallel on the active area by utilizing the heavily doped region, the first gate oxide layer and the floating gate polysilicon layer to form a first capacitor, the floating gate polysilicon layer, the dielectric layer and the control gate polysilicon layer to form a second capacitor, and the heavily doped region, the second gate oxide layer and the floating gate polysilicon layer to form a third capacitor, and in the third capacitor, the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer, and the area of ​​the second gate oxide layer is greater than the area of ​​the first gate oxide layer. The present application maximizes the electrostatic capacitance of the NAND memory device capacitor by thinning the thickness of the second gate oxide layer and expanding the area. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] Figure 1 It is a structural schematic diagram of a non-volatile memory device having a parallel capacitance structure of a low-voltage gate oxide capacitor and an ONO dielectric layer capacitor in the prior art;

[0048] Figure 2-Figure 14 Schematic diagram of a semiconductor structure in each process step of manufacturing a non-volatile memory device according to an embodiment of the present invention;

[0049] The description of the accompanying drawings is as follows:

[0050] 1-substrate, 2-low-voltage gate oxide, 3-P-type doped floating gate, 4-ONO dielectric layer, 5-P-type doped control gate 5, 6-N-type heavily doped region, 7-interlayer insulating layer, 8-contact hole structure 1, 9-contact hole structure 2, 9'-contact hole structure 2, 10-contact hole structure 3;

[0051] 12 - substrate, 13 - first gate oxide layer, 14 - first photoresist layer, 15 - second gate oxide layer, 16 - floating gate polysilicon layer, 17 - dielectric layer, 18 - control gate polysilicon layer, 19 - second photoresist layer, 20 - heavily doped region, 21 - third photoresist layer, 22 - interlayer insulating layer, 23 - first conductive plug, 24 - second conductive plug, 25 - third conductive plug, 25' - third conductive plug;

[0052] HV-high pressure area, LV-low pressure area. DETAILED DESCRIPTION

[0053] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0054] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0055] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0056] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0057] The present invention provides a method for preparing a non-volatile memory device. Figure 2-Figure 14 1 is a schematic diagram of a semiconductor structure in each process step of manufacturing a non-volatile memory device according to an embodiment of the present invention. The method for manufacturing the non-volatile memory device includes:

[0058] Step 1: Reference Figure 2 , Figure 2 1 is a schematic diagram of a semiconductor structure after forming a first gate oxide layer according to an embodiment of the present application, and a substrate 12 is provided.

[0059] Specifically, the substrate 12 can be one of single crystal silicon, polycrystalline silicon, and amorphous silicon. The substrate 12 can also be gallium arsenide, silicon gallium compound, etc. The substrate 12 can also have a silicon on insulating layer or an epitaxial layer on silicon structure; the substrate 12 can also be other semiconductor materials, which are not listed here one by one.

[0060] Step 2: Continue to refer Figure 2 , forming a first gate oxide layer 13 , wherein the first gate oxide layer 13 covers the substrate 12 .

[0061] In this embodiment, a diffusion process may be used to form the first gate oxide layer 13. The diffusion process includes but is not limited to a high-temperature furnace thermal oxidation process.

[0062] Preferably, the first gate oxide layer 13 is made of SiO 2 material.

[0063] Step 3: Reference Figure 3 and Figure 4 , Figure 3 is a schematic diagram of a semiconductor structure after the patterned first photoresist layer of an embodiment of the present application, Figure 4It is a schematic diagram of a semiconductor structure after the first gate oxide layer of the low voltage region is removed. A high voltage region HV and a low voltage region LV are defined on the substrate 12, and the first gate oxide layer 13 of the low voltage region LV is removed.

[0064] In this embodiment, a high voltage region HV and a low voltage region LV are defined on the substrate 12 , and the step of removing the first gate oxide layer 13 in the low voltage region LV may specifically include:

[0065] Step 3.1: forming a whole photoresist layer;

[0066] Step 3.2: If Figure 3 As shown, a high-voltage region HV and a low-voltage region LV are defined on the substrate 12. The entire photoresist layer is transformed into a patterned first photoresist layer 14 through exposure, development, and other processes. The patterned first photoresist layer 14 covers the first gate oxide layer 13 of the high-voltage region HV. At this time, the first gate oxide layer 13 of the low-voltage region LV is exposed.

[0067] Step 3.3: If Figure 4 As shown, a wet etching process is used to remove the first gate oxide layer 13 of the low voltage region LV; and

[0068] Step 3.4: Remove the patterned first photoresist layer 14 by an ashing process.

[0069] Step 4: Reference Figure 5 , Figure 5 1 is a schematic diagram of a semiconductor structure after forming a second gate oxide layer according to an embodiment of the present application. The second gate oxide layer 15 is formed by a diffusion process, ensuring that the second gate oxide layer 15 is formed only on the substrate 12 in the low voltage region LV.

[0070] The diffusion process includes but is not limited to a high-temperature furnace tube thermal oxidation process.

[0071] In this embodiment, the second gate oxide layer 15 may be formed by a high-temperature furnace thermal oxidation process.

[0072] Preferably, the thickness of the first gate oxide layer 13 is greater than the thickness of the second gate oxide layer 15 .

[0073] Preferably, the thickness of the first gate oxide layer 13 is greater than More preferably, the thickness of the first gate oxide layer 13 is selected to be

[0074] Furthermore, the thickness of the second gate oxide layer 15 is less than More preferably, the thickness of the second gate oxide layer 15 is selected to be

[0075] Preferably, the area of ​​the second gate oxide layer 15 is larger than the area of ​​the first gate oxide layer 13 .

[0076] The calculation formula for the electrostatic capacitance of a capacitor is: C = ε * A / T; where C is the electrostatic capacitance of the capacitor; ε represents the dielectric constant; A represents the area; and T represents the thickness. The thinner the thickness of the insulating dielectric layer in a capacitor, the greater the electrostatic capacitance of the capacitor. Therefore, in the embodiment of the present application, the thickness of the second gate oxide layer 15 is reduced, and the area of ​​the insulating dielectric layer (second gate oxide layer 15) in the third capacitor is set to be larger than the area of ​​the insulating dielectric layer (first gate oxide layer 13) in the first capacitor, thereby maximizing the electrostatic capacitance of the NAND memory device capacitor.

[0077] Step 5: Reference Figure 6 , Figure 6 1 is a schematic diagram of a semiconductor structure after forming a floating gate polysilicon layer according to an embodiment of the present application, wherein a floating gate polysilicon layer 16 is formed, and the floating gate polysilicon layer 16 covers the first gate oxide layer 13 and the second gate oxide layer 15 .

[0078] In this embodiment, the floating gate polysilicon layer 16 is P-type doped.

[0079] Step 6: Reference Figure 7 , Figure 7 1 is a schematic diagram of a semiconductor structure after a dielectric layer is formed according to an embodiment of the present application, wherein a dielectric layer 17 is formed, and the dielectric layer 17 covers the floating gate polysilicon layer 16 .

[0080] Preferably, the dielectric layer 17 is an ONO dielectric layer. Further, the dielectric layer 17 may specifically include: a stacked silicon oxide layer 1, a silicon nitride layer, and a stacked silicon oxide layer 2.

[0081] Step 7: Reference Figure 8 , Figure 8 1 is a schematic diagram of a semiconductor structure after forming a control gate polysilicon layer according to an embodiment of the present application, wherein a control gate polysilicon layer 18 is formed, and the control gate polysilicon layer 18 covers the dielectric layer 17 .

[0082] In this embodiment, the control gate polysilicon layer 18 is P-type doped.

[0083] Step 8: Reference Figure 9 and Figure 10 , Figure 9 is a schematic diagram of a semiconductor structure after forming a patterned second photoresist layer in an embodiment of the present application, Figure 10It is a schematic diagram of the semiconductor structure after the heavily doped region is formed in an embodiment of the present application, wherein the control gate polysilicon layer 18, the dielectric layer 17, the floating gate polysilicon layer 16 and the first gate oxide layer 13 in the first part of the high voltage region HV are etched to expose the first part of the substrate 12, and the control gate polysilicon layer 18, the dielectric layer 17, the floating gate polysilicon layer 16 and the second gate oxide layer 15 in the part of the low voltage region LV are etched to expose the second part of the substrate 12.

[0084] In this embodiment, step 8 may specifically include:

[0085] Step 8.1: forming a whole photoresist layer;

[0086] Step 8.2: If Figure 9 As shown, the entire photoresist layer is transformed into a patterned second photoresist layer 19 through exposure, development and other processes;

[0087] Step 8.3: If Figure 10 As shown, using the patterned second photoresist layer 19 as a mask, the control gate polysilicon layer 18, the dielectric layer 17, the floating gate polysilicon layer 16, and the first gate oxide layer 13 in the first portion of the high voltage region HV are etched to expose the first portion of the substrate 12, and the control gate polysilicon layer 18, the dielectric layer 17, the floating gate polysilicon layer 16, and the second gate oxide layer 15 in the portion of the low voltage region LV are etched to expose the second portion of the substrate 12; and

[0088] Step 8.4: Remove the patterned second photoresist layer 19 by an ashing process.

[0089] In the present application, because a contact hole and a first conductive plug are subsequently formed on the step surface of the floating gate polysilicon layer 16 in the high voltage region HV, the present application forms a thicker first gate oxide layer at the bottom of the floating gate polysilicon layer on the same active area, thereby increasing the thickness of the first gate oxide layer at the bottom of the contact hole and improving the film quality of the first gate oxide layer at the bottom of the contact hole. This can effectively alleviate the damage to the first gate oxide layer at the bottom of the floating gate polysilicon layer caused by etching when forming the contact hole, thereby improving the electrical performance of the NAND memory device.

[0090] Step 9: Continue to refer Figure 10 , performing an ion implantation process on the first portion of the substrate and the second portion of the substrate to form a plurality of heavily doped regions 20 accordingly.

[0091] In this embodiment, an N-type heavily doped ion implantation process is performed on the first and second substrate portions to form a plurality of N-type heavily doped regions 20. The N-type heavily doped ions may be arsenic ions (As) or phosphorus ions (Ph).

[0092] Furthermore, after performing an ion implantation process on the first and second substrate portions to correspondingly form a plurality of heavily doped regions (step 9), the method for preparing the non-volatile memory device further includes: performing a thermal annealing process on the semiconductor structure after step 9 to activate the doped ions in the heavily doped regions 20.

[0093] Specifically, after step 9, the semiconductor structure ( Figure 10 During the thermal annealing process performed on the semiconductor structure shown in FIG, the process temperature can be around 1000° C. and the thermal annealing time can last around 10 seconds.

[0094] Step 10: Reference Figure 11 and Figure 12 , Figure 11 is a schematic diagram of a semiconductor structure after forming a patterned third photoresist layer according to an embodiment of the present application. Figure 12 3 is a schematic diagram of the semiconductor structure after the step is formed in an embodiment of the present application. The control gate polysilicon layer 18 and the dielectric layer 17 in the second part of the high voltage region are etched to the upper surface of the floating gate polysilicon layer 16 to form a step.

[0095] In this embodiment, step 10 may specifically include:

[0096] Step 10.1: forming a whole photoresist layer;

[0097] Step 10.2: If Figure 11 As shown, the entire photoresist layer is transformed into a patterned third photoresist layer 21 through exposure, development and other processes;

[0098] Step 10.3: If Figure 12 As shown, the control gate polysilicon layer 18 and the dielectric layer 17 in the second portion of the high voltage region HV are etched to the upper surface of the floating gate polysilicon layer 16 to form a step; and

[0099] Step 10.4: Remove the patterned third photoresist layer 21 by an ashing process.

[0100] Step 11: Reference Figure 13 , Figure 131 is a schematic diagram of a semiconductor structure after an interlayer insulating layer is formed according to an embodiment of the present application. An interlayer insulating layer 22 is formed, and the interlayer insulating layer 22 covers the step, the control gate polysilicon layer 18 and the heavily doped region 20 .

[0101] In this embodiment, the interlayer insulating layer 22 is made of TEOS (tetraethoxysilane).

[0102] Step 12: Reference Figure 14 , Figure 14 This is a schematic diagram of the semiconductor structure after the first conductive plug, the second conductive plug and the third conductive plug are formed in an embodiment of the present application, forming a first conductive plug 23, a second conductive plug 24 and multiple third conductive plugs (for example, a third conductive plug 25' in the high-voltage area and a third conductive plug 25 in the low-voltage area), the first conductive plug 23 penetrates the interlayer insulating layer 22 and is connected to the floating gate polysilicon layer 16 on the step surface, the second conductive plug 24 penetrates the interlayer insulating layer 22 and is connected to the control gate polysilicon layer 18, at least one of the third conductive plugs 25' penetrates the interlayer insulating layer 22 in the high-voltage area and is connected to the heavily doped area 20; at least one of the third conductive plugs 25 penetrates the interlayer insulating layer 22 in the low-voltage area and is connected to the heavily doped area 20.

[0103] The heavily doped region 20, the first gate oxide layer 13, and the floating gate polysilicon layer 16 constitute a first capacitor; the floating gate polysilicon layer 16, the dielectric layer 17, and the control gate polysilicon layer 18 constitute a second capacitor (PIP capacitor); and the heavily doped region 20, the second gate oxide layer 15, and the floating gate polysilicon layer 16 constitute a third capacitor. The first capacitor, the second capacitor, and the third capacitor are connected in parallel.

[0104] In this embodiment, the steps of forming the first conductive plug 23, the second conductive plug 24, the third conductive plug 25, and the third conductive plug 25' include:

[0105] Step 12.1: Etching the interlayer insulating layer 22 to form a first contact hole, a second contact hole, and a third contact hole in the interlayer insulating layer 22, wherein the first contact hole exposes the floating gate polysilicon layer 16 at the stepped position, the second contact hole exposes the control gate polysilicon layer 18, and the third contact hole exposes the heavily doped region 20;

[0106] Step 12.2: If Figure 14As shown, metal materials are filled in the first contact hole, the second contact hole and the third contact hole to obtain a first conductive plug 23 , a second conductive plug 24 , a third conductive plug 25 and a third conductive plug 25 ′ respectively.

[0107] In this embodiment, the metal material filling the first contact hole, the second contact hole, and the third contact hole includes, but is not limited to, metals such as copper and tungsten.

[0108] In the present application, a first gate oxide layer is formed on a portion of the substrate at the bottom of the floating gate polysilicon layer on the same active area, and a second gate oxide layer is formed on the remaining substrate, thereby forming a combined oxide layer structure of the first gate oxide layer and the second gate oxide layer. This increases the thickness of the first gate oxide layer at the bottom of the contact hole, improves the film quality of the first gate oxide layer at the bottom of the contact hole, that is, improves the film quality of the combined oxide layer structure at the bottom of the contact hole, effectively alleviates etching damage to the combined oxide layer at the bottom of the floating gate polysilicon layer when forming the contact hole, and improves the electrical performance of the NAND memory device.

[0109] Furthermore, the present application forms a first capacitor, a second capacitor, and a third capacitor in parallel on the active area by utilizing the heavily doped region, the first gate oxide layer, and the floating gate polysilicon layer to form a first capacitor, the floating gate polysilicon layer, the dielectric layer, and the control gate polysilicon layer to form a second capacitor, and the heavily doped region, the second gate oxide layer, and the floating gate polysilicon layer to form a third capacitor, and in the third capacitor, the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer, and the area of ​​the second gate oxide layer is greater than the area of ​​the first gate oxide layer, and the thickness of the second gate oxide layer is less than 15. It can be seen that the present application increases the electrostatic capacitance of the capacitor of the NAND memory device to the maximum extent by reducing the thickness of the second gate oxide layer 15 and expanding the area of ​​the second gate oxide layer 15 in the third capacitor as much as possible.

[0110] Based on the same inventive concept, the present application also provides a non-volatile memory device, referring to Figure 14 , the non-volatile memory device comprises:

[0111] a substrate 12 comprising a high voltage region HV and a low voltage region LV;

[0112] a first gate oxide layer 13, wherein the first gate oxide layer 13 covers the substrate 12 of the high voltage region HV;

[0113] a second gate oxide layer 15, wherein the second gate oxide layer 15 covers the substrate 12 of the low voltage region LV, wherein the thickness of the first gate oxide layer 13 is greater than the thickness of the second gate oxide layer 15, and the area of ​​the second gate oxide layer 15 is greater than the area of ​​the first gate oxide layer 13;

[0114] a floating gate polysilicon layer 16 , wherein the floating gate polysilicon layer 16 covers the first gate oxide layer 13 and the second gate oxide layer 15 ;

[0115] a dielectric layer 17 , wherein the dielectric layer 17 covers a portion of the floating gate polysilicon layer 16 ;

[0116] a control gate polysilicon layer 18 , wherein the control gate polysilicon layer 18 covers the dielectric layer 17 , wherein a surface of the floating gate polysilicon layer 16 not covered by the dielectric layer 17 forms a step;

[0117] a plurality of heavily doped regions 20 , each of which is located in the substrate 12 ;

[0118] an interlayer insulating layer 22 , the interlayer insulating layer 22 covering the step, the control gate polysilicon layer 18 and the heavily doped region 20 ; and

[0119] a first conductive plug 23, a second conductive plug 24, and a plurality of third conductive plugs 25, wherein the first conductive plug 23 penetrates the interlayer insulating layer 22 and is connected to the floating gate polysilicon layer 16 on the step surface, the second conductive plug 24 penetrates the interlayer insulating layer 22 and is connected to the control gate polysilicon layer 18, at least one third conductive plug 25' penetrates the interlayer insulating layer 22 in the high-voltage region and is connected to the heavily doped region 20; and at least one third conductive plug 25 penetrates the interlayer insulating layer in the low-voltage region and is connected to the heavily doped region;

[0120] Among them, the heavily doped region 20, the first gate oxide layer 13 and the floating gate polysilicon layer 16 constitute a first capacitor; the floating gate polysilicon layer 16, the dielectric layer 17 and the control gate polysilicon layer 18 constitute a second capacitor; the heavily doped region 20, the second gate oxide layer 15 and the floating gate polysilicon layer 16 constitute a third capacitor.

[0121] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for preparing a non-volatile memory device, characterized in that: include: providing a substrate; forming a first gate oxide layer, wherein the first gate oxide layer covers the substrate; defining a high-voltage region and a low-voltage region on the substrate, and removing the first gate oxide layer in the low-voltage region; forming a second gate oxide layer, wherein the second gate oxide layer covers the substrate of the low-voltage region, wherein the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, and the area of ​​the second gate oxide layer is greater than the area of ​​the first gate oxide layer; forming a floating gate polysilicon layer, wherein the floating gate polysilicon layer covers the first gate oxide layer and the second gate oxide layer; forming a dielectric layer, wherein the dielectric layer covers the floating gate polysilicon layer; forming a control gate polysilicon layer, wherein the control gate polysilicon layer covers the dielectric layer; Etching the control gate polysilicon layer, the dielectric layer, the floating gate polysilicon layer, and the first gate oxide layer in a first portion of the high voltage region to expose a first portion of the substrate, and etching the control gate polysilicon layer, the dielectric layer, the floating gate polysilicon layer, and the second gate oxide layer in a portion of the low voltage region to expose a second portion of the substrate; performing an ion implantation process on the first substrate portion and the second substrate portion to form a plurality of heavily doped regions; Etching the control gate polysilicon layer and the dielectric layer in the second portion of the high voltage region to the upper surface of the floating gate polysilicon layer to form a step; forming an interlayer insulating layer, wherein the interlayer insulating layer covers the step, the control gate polysilicon layer, and the heavily doped region; and forming a first conductive plug, a second conductive plug, and a plurality of third conductive plugs, wherein the first conductive plug penetrates the interlayer insulating layer and is connected to the floating gate polysilicon layer on the step surface, the second conductive plug penetrates the interlayer insulating layer and is connected to the control gate polysilicon layer, at least one of the third conductive plugs penetrates the interlayer insulating layer in the high-voltage region and is connected to the heavily doped region; and at least one of the third conductive plugs penetrates the interlayer insulating layer in the low-voltage region and is connected to the heavily doped region; The heavily doped region, the first gate oxide layer and the floating gate polysilicon layer constitute a first capacitor; the floating gate polysilicon layer, the dielectric layer and the control gate polysilicon layer constitute a second capacitor; and the heavily doped region, the second gate oxide layer and the floating gate polysilicon layer constitute a third capacitor.

2. The method for preparing a non-volatile memory device according to claim 1, wherein: The thickness of the first gate oxide layer is greater than 250Å.

3. The method for preparing a non-volatile memory device according to claim 1, wherein: The thickness of the second gate oxide layer is less than 80Å.

4. The method for manufacturing a non-volatile memory device according to claim 1, wherein: The dielectric layer is an ONO dielectric layer.

5. The method for manufacturing a non-volatile memory device according to claim 1, wherein: An N-type heavily doped ion implantation process is performed on the first substrate portion and the second substrate portion to correspondingly form a plurality of N-type heavily doped regions.

6. The method for manufacturing a non-volatile memory device according to claim 1, wherein: The floating gate polysilicon layer and the control gate polysilicon layer are both P-type doped.

7. The method for manufacturing a non-volatile memory device according to claim 1, wherein: The material of the interlayer insulating layer is TEOS.

8. The method for manufacturing a non-volatile memory device according to claim 1, wherein: The steps of forming the first conductive plug, the second conductive plug and the third conductive plug include: Etching the interlayer insulating layer to form a first contact hole, a second contact hole, and a third contact hole in the interlayer insulating layer, wherein the first contact hole exposes the floating gate polysilicon layer at the step position, the second contact hole exposes the control gate polysilicon layer, and the third contact hole exposes the heavily doped region; Metal materials are filled in the first contact hole, the second contact hole and the third contact hole to obtain a first conductive plug, a second conductive plug and a third conductive plug respectively.

9. The method for manufacturing a non-volatile memory device according to claim 1, wherein: After performing an ion implantation process on the first and second substrate portions to form a plurality of heavily doped regions, and before etching the control gate polysilicon layer and the dielectric layer in the second portion of the high-voltage region to the upper surface of the floating gate polysilicon layer to form a step, the method for preparing the non-volatile memory device further includes: A thermal annealing process is performed to activate dopant ions in the heavily doped region.

10. A non-volatile memory device, characterized in that: include: a substrate comprising a high-pressure region and a low-pressure region; a first gate oxide layer, wherein the first gate oxide layer covers the substrate of the high voltage region; a second gate oxide layer, wherein the second gate oxide layer covers the substrate of the low-voltage region, wherein the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, and the area of ​​the second gate oxide layer is greater than the area of ​​the first gate oxide layer; a floating gate polysilicon layer, wherein the floating gate polysilicon layer covers the first gate oxide layer and the second gate oxide layer; a dielectric layer, wherein the dielectric layer covers a portion of the floating gate polysilicon layer; a control gate polysilicon layer, the control gate polysilicon layer covering the dielectric layer, wherein a surface of the floating gate polysilicon layer not covering the dielectric layer forms a step; a plurality of heavily doped regions, each of which is located in the substrate; an interlayer insulating layer, the interlayer insulating layer covering the step, the control gate polysilicon layer and the heavily doped region; and a first conductive plug, a second conductive plug, and a plurality of third conductive plugs, wherein the first conductive plug penetrates the interlayer insulating layer and is connected to the floating gate polysilicon layer on the step surface, the second conductive plug penetrates the interlayer insulating layer and is connected to the control gate polysilicon layer, at least one of the third conductive plugs penetrates the interlayer insulating layer in the high-voltage region and is connected to the heavily doped region; and at least one of the third conductive plugs penetrates the interlayer insulating layer in the low-voltage region and is connected to the heavily doped region; The heavily doped region, the first gate oxide layer and the floating gate polysilicon layer constitute a first capacitor; the floating gate polysilicon layer, the dielectric layer and the control gate polysilicon layer constitute a second capacitor; and the heavily doped region, the second gate oxide layer and the floating gate polysilicon layer constitute a third capacitor.

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