A light-emitting control driving circuit, a display panel, and a display device.

Abstract

This application provides a light-emitting control driving circuit, a display panel, and a display device. The light-emitting control driving circuit includes cascaded shift register units. Each shift register unit includes a first output unit, a first input unit, and a voltage control unit. The input terminal of the first input unit is electrically connected to a first voltage signal line, and its output terminal is electrically connected to the output terminal of the shift register unit. The input terminal of the first input unit is electrically connected to the trigger terminal of the shift register unit, and its output terminal is electrically connected to the control terminal of the first output unit. The first terminal of the voltage control unit is electrically connected to the control terminal of the first output unit. During a first on-time period of the first input unit, the first input unit transmits an enable signal to the control terminal of the first output unit, and the voltage control unit transmits a signal with the same polarity as the enable signal to the control terminal of the first output unit. This application can improve the stability and control effect of the light-emitting control driving circuit and avoid the occurrence of step-like signals.

Description

[Technical Field]

[0001] This application relates to the field of display technology, and in particular to a light-emitting control driving circuit, a display panel, and a display device. [Background Technology]

[0002] In display devices, the pixel circuits used to drive the light-emitting devices to emit light typically require a light-emitting control signal for control. Therefore, a light-emitting control driver circuit is included in the display device to generate the light-emitting control signal.

[0003] However, in existing light emission control driving circuits, the light emission control signals they generate have a poor control effect on the pixel circuits, which affects the display effect.

[0004] [Application Content]

[0005] In view of this, embodiments of this application provide a light-emitting control driving circuit, a display panel, and a display device to solve the above problems.

[0006] In a first aspect, embodiments of this application provide a light-emitting control driving circuit, including multiple cascaded shift register units. Each shift register unit includes a first output unit, a first input unit, and a voltage control unit. The input terminal of the first input unit is electrically connected to a first voltage signal line, and its output terminal is electrically connected to the output terminal of the shift register unit. The input terminal of the first input unit is electrically connected to the trigger terminal of the shift register unit, and its output terminal is electrically connected to the control terminal of the first output unit. The first terminal of the voltage control unit is electrically connected to the control terminal of the first output unit. During a first on-time period of the first input unit, the first input unit transmits an enable signal to the control terminal of the first output unit, and the voltage control unit transmits a signal with the same polarity as the enable signal to the control terminal of the first output unit.

[0007] Secondly, based on the same inventive concept, embodiments of this application provide a display panel, including the light-emitting control driving circuit as provided in the first aspect.

[0008] Thirdly, based on the same inventive concept, embodiments of this application provide a display device, including a display panel as provided in the second aspect.

[0009] In this embodiment, during the first on-time of the first input unit, the first input unit transmits an enable signal to the control terminal of the first output unit to control the first output unit to turn on. The signal on the first voltage signal line is transmitted to the output terminal of the shift register unit through the first output unit, thereby changing the original signal potential of the output terminal. At this time, the signal transmitted by the voltage control unit to the control terminal of the first output unit has the same polarity as the enable signal transmitted by the first input unit, which is equivalent to strengthening the control capability of the enable signal transmitted by the first input unit on the first output unit. This can further control the first output unit to remain on, thereby enabling the signal on the first voltage signal line to be continuously transmitted to the output terminal of the shift register unit until the signal potential of the output terminal is equivalent to the signal potential on the first voltage signal line. This avoids the problem of the shift register unit outputting a stepped signal, and thus helps to improve the control effect of the light-emitting control driving circuit. [Attached Image Description]

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a light-emitting control driving circuit in related technologies;

[0012] Figure 2 for Figure 1 The diagram shows a timing diagram of a light-emitting control driving circuit.

[0013] Figure 3 A schematic diagram of a light-emitting control driving circuit provided in an embodiment of this application;

[0014] Figure 4 This application scenario provides an example of a light-emitting control driving circuit.

[0015] Figure 5 A partial schematic diagram of a shift register unit provided in an embodiment of this application;

[0016] Figure 6 This is a schematic diagram of the output signal of a shift register unit related to this application;

[0017] Figure 7 A partial schematic diagram of another shift register unit provided in an embodiment of this application;

[0018] Figure 8 A partial schematic diagram of another shift register unit provided in an embodiment of this application;

[0019] Figure 9 for Figure 8 The diagram shows a timing diagram related to the shift register unit.

[0020] Figure 10 A schematic diagram of a shift register unit provided in an embodiment of this application;

[0021] Figure 11 for Figure 10 A timing diagram of a shift register unit is shown.

[0022] Figure 12 A schematic diagram of yet another shift register unit provided in an embodiment of this application;

[0023] Figure 13 A schematic diagram of yet another shift register unit provided in an embodiment of this application;

[0024] Figure 14 for Figure 13 A timing diagram of a shift register unit is shown.

[0025] Figure 15 This is a schematic diagram of a display device provided in an embodiment of this application.

Detailed Implementation Methods

[0026] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0027] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0028] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0029] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0030] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0031] It should be understood that although terms such as "first," "second," etc., may be used to describe output units, voltage signal lines, transistors, etc., in the embodiments of this application, these output units, voltage signal lines, transistors, etc., should not be limited to these terms. These terms are only used to distinguish output units, voltage signal lines, transistors, etc., from each other. For example, without departing from the scope of the embodiments of this application, a first output unit may also be referred to as a second output unit, and similarly, a second output unit may also be referred to as a first output unit.

[0032] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0033] Figure 1 This is a schematic diagram of a light-emitting control driving circuit in related technologies. Figure 2 for Figure 1 The diagram shows a timing diagram of a light-emitting control driving circuit.

[0034] In related technologies, such as Figure 1 As shown, the light-emitting control driving circuit 100' includes transistors M1'-M12' and capacitors C1'-C4', and the connection method of transistors M1'-M12' and capacitors C1'-C4' is as follows. Figure 1 As shown, I will not go into details here.

[0035] In this circuit, transistor M5' receives a trigger signal STV' at its first terminal, is electrically connected to the gate of transistor M11' at its second terminal, and receives a first clock signal CK' at its gate. Transistor M11' receives a low-level signal VGL' at its first terminal, and is electrically connected to the output terminal OUT' of the light-emitting control driving circuit 100' at its second terminal. Transistor M10' transmits the low-level signal VGL' to the output terminal OUT' of the light-emitting control driving circuit 100'. The low-level signal VGL' can be an effective light-emitting control signal output by the light-emitting control driving circuit 100', meaning that when the light-emitting control driving circuit 100' outputs the low-level signal VGL', it can control the transistors in the pixel circuit to turn on.

[0036] In addition, such as Figure 1As shown, the light-emitting control driving circuit 100' also receives a high-level signal VGH' and a second clock signal XCK'. Under the control of the trigger signal STV', the first clock signal CK', and the second clock signal XCK', the light-emitting control driving circuit 100' outputs a low-level signal VGL' and a high-level signal VGH' in an orderly manner. The high-level signal VGH' can be an ineffective light-emitting control signal output by the light-emitting control driving circuit 100'. When the light-emitting control driving circuit 100' outputs a high-level signal VGH', it can control the transistors in the pixel circuit to turn off.

[0037] The inventors of this application, through research, discovered that, combined with... Figure 2 As shown, in stage T1', the trigger signal STV' and the first clock signal CK' will transmit valid signals, namely low-level signals VGL'. The low-level trigger signal STV' can be transmitted to the gate of transistor M11' through the turned-on transistor M5' and control transistor M11' to turn on. At this time, the low-level signal VGL' received by the first terminal of transistor M11' can be transmitted to the output terminal OUT' of the light-emitting control driving circuit 100', thereby pulling down the potential of the output terminal OUT' signal.

[0038] However, based on the switching characteristics of the transistor, when the potential of the output terminal OUT' signal decreases from the high-level signal VGH' to the potential VGL'+Vth, the transistor M11' will turn off, where Vth is the threshold voltage of the transistor M11'. In stage T2', when the second clock signal XCK' transitions from high to low, the coupling effect of capacitor C2' will pull down the gate potential of the transistor M11', thereby controlling the transistor M11' to turn on again, and thus continuing to pull down the potential of the output terminal OUT' signal.

[0039] Thus, during the transition of the output signal OUT' from a high-level signal VGH' to a low-level signal VGL', a stepped signal will appear. When the signal output by the light-emitting control driving circuit 100' is pulled down, it cannot be directly reduced to a lower potential, which will cause the transistors in the pixel circuit to not be fully turned on, affecting the display effect.

[0040] Through meticulous and in-depth research, the inventors of this application have provided a solution to the problems existing in related technologies.

[0041] Figure 3 This is a schematic diagram of a light-emitting control driving circuit provided in an embodiment of this application. Figure 4 This application scenario provides an example of a light-emitting control driving circuit.

[0042] This application provides a light-emitting control driving circuit 10, such as... Figure 3As shown, the light emission control driving circuit 10 includes multiple cascaded shift register units 100. In two adjacent shift register units 100, the valid light emission control signal output by the output terminal OUT of one can be used as the trigger signal of the other.

[0043] like Figure 4 As shown, the light emission control driving circuit 10 provided in this application embodiment can be set in the non-display area NA of the display panel 01. The output terminal OUT of each shift register unit 100 is electrically connected to the light emission control signal line Emit in the display area AA of the display panel 01. The multiple shift register units 100 included in the light emission control driving circuit 10 can sequentially output valid light emission control signals to the light emission control signal line Emit to control the transistors electrically connected to the light emission device in the display area AA to turn on row by row.

[0044] Figure 5 This is a partial schematic diagram of a shift register unit provided in an embodiment of this application.

[0045] like Figure 5 As shown, the shift register unit 100 includes a first output unit 11, a first input unit 21, and a voltage control unit 31.

[0046] The input terminal of the first output unit 11 is electrically connected to the first voltage signal line L1, and the output terminal is electrically connected to the output terminal OUT of the shift register unit 100. The first output unit 11 is used to receive the signal transmitted by the first voltage signal line L1 and provide it to the output terminal OUT of the shift register unit 100. That is, when the first output unit 11 is turned on, the signal on the first voltage signal line L1 is transmitted to the output terminal OUT of the shift register unit 100.

[0047] Optionally, the signal transmitted by the first output unit 11 to the output terminal OUT of the shift register unit 100 is an effective light-emitting control signal, which can be a low-level signal VGL.

[0048] The input terminal of the first input unit 21 is electrically connected to the trigger terminal IN of the shift register unit 100, and the output terminal is electrically connected to the control terminal of the first output unit 11. The first input unit 21 is used to receive the trigger signal and provide it to the control terminal of the first output unit 11 to control the switching state of the first output unit 11.

[0049] The first terminal of the voltage control unit 31 is electrically connected to the control terminal of the first output unit 11. During the first turn-on period of the first input unit 21, the first input unit 21 transmits an enable signal to the control terminal of the first output unit 11. This enable signal can control the first output unit 11 to turn on. The voltage control unit 31 also transmits a signal with the same polarity as the aforementioned enable signal to the control terminal of the first output unit 11.

[0050] Optionally, during the first on-time of the first input unit 21, the signal received by the trigger terminal IN is an enable signal that can control the first output unit 11 to turn on. This enable signal can be transmitted to the control terminal of the first output unit 11 through the on-time first input unit 21, and control the first output unit 11 to turn on. At this time, the voltage control unit 31 also transmits an enable signal that can turn on the first output unit 11 to the control terminal.

[0051] For example, during the first turn-on period of the first input unit 21, the first input unit 21 transmits a low-level enable signal to the control terminal of the first output unit 11 to control the first output unit 11 to turn on. At this time, the voltage control unit 31 transmits a low-level signal with the same polarity as the aforementioned enable signal to the control terminal of the first output unit 11.

[0052] The first activation period of the first input unit 21 can be the period during which the ineffective light emission control signal and the effective light emission control signal output by the shift register unit 100 switch between each other.

[0053] Figure 6 This is a schematic diagram of the output signal of a shift register unit related to this application.

[0054] For example, combined Figure 5 and Figure 6 As shown, during the first turn-on period T1 of the first input unit 21, the trigger terminal IN of the shift register unit 100 receives a low-level signal, and the first output unit 11 transmits a low-level signal to the output terminal OUT of the shift register unit 100, so that the output signal of the shift register unit 100 is converted from a high-level signal to a low-level signal.

[0055] In this embodiment, during the first turn-on period of the first input unit 21, after the first input unit 21 transmits an enable signal to the control terminal of the first output unit 11 and controls the first output unit 11 to turn on, the signal on the first voltage signal line L1 will be transmitted to the output terminal OUT of the shift register unit 100 through the first output unit 11, thereby changing the original signal potential of the output terminal OUT. At this time, the signal transmitted by the voltage control unit 31 to the control terminal of the first output unit 11 has the same polarity as the enable signal transmitted by the first input unit 21, which is equivalent to strengthening the control capability of the enable signal transmitted by the first input unit 21 on the first output unit 11. It can further control the first output unit 11 to remain in the turn-on state, which is beneficial to ensure that the signal on the first voltage signal line L1 can be continuously transmitted to the output terminal OUT of the shift register unit 100 until the signal potential of the output terminal OUT is equivalent to the signal potential on the first voltage signal line L1. This avoids the problem of the output terminal OUT of the shift register unit 100 outputting a stepped signal, thereby improving the control effect of the light emission control driving circuit 10.

[0056] For example, such as Figure 6 As shown, during the first turn-on period T1 of the first input unit 21, the signal output from the output terminal OUT of the shift register unit 100 can be directly pulled down from a high level to a low level that meets the requirements, relative to... Figure 2 The related technologies shown avoid the occurrence of step-shaped signals and improve the stability and control effect of the light emission control drive circuit 10.

[0057] Please continue to refer to this. Figure 5 The shift register unit 100 also includes a second output unit 12. The input terminal of the second output unit 12 is electrically connected to the second voltage signal line L2, and the output terminal is electrically connected to the output terminal OUT of the shift register unit 100. The second output unit 12 is used to receive the signal transmitted by the second voltage signal line L2 and provide it to the output terminal OUT of the shift register unit 100. That is, when the second output unit 12 is turned on, the signal on the second voltage signal line L2 is transmitted to the output terminal OUT of the shift register unit 100.

[0058] The signal output by the second output unit 12 has the opposite polarity to the signal output by the first output unit 11.

[0059] Of course, the second output unit 12 and the first output unit 11 transmit signals to the output terminal OUT of the shift register unit 100 at different times.

[0060] Optionally, the signal transmitted by the second output unit 12 to the output terminal OUT of the shift register unit 100 is an ineffective light-emitting control signal, which can be a high-level signal VGH.

[0061] In this embodiment, the second output unit 12 and the first output unit 11 can transmit signals to the output terminal OUT of the shift register unit 100 in a time-division manner, thereby controlling the shift register unit 100 to output valid light-emitting control signals and invalid light-emitting control signals in a time-division manner. The valid light-emitting control signal referred to here is the transistor controlled by the light-emitting control signal line Emit, which is electrically connected to the output terminal OUT of the shift register unit 100, turning on after receiving the valid light-emitting control signal. The invalid light-emitting control signal referred to here is the transistor controlled by the light-emitting control signal line Emit, which is electrically connected to the output terminal OUT of the shift register unit 100, turning off after receiving the invalid light-emitting control signal.

[0062] Figure 7 This is a partial schematic diagram of another shift register unit provided in an embodiment of this application.

[0063] In one technical solution of this application embodiment, such as Figure 7 As shown, the voltage control unit 31 includes a first capacitor C1. One plate of the first capacitor C1 is electrically connected to the control terminal of the first output unit 11, and the other plate is electrically connected to the output terminal OUT of the shift register unit 100.

[0064] As can be seen from the above statement that the effective light-emitting control signal output from the output terminal OUT can be used as the trigger signal of another shift register unit 100, in the same shift register unit 100, the effective light-emitting control signal transmitted by the first output unit 11 to the output terminal OUT of the shift register unit 100 has the same polarity as the enable signal transmitted by the first input unit 21 to the control terminal of the first output unit 11.

[0065] Therefore, in this technical solution, during the first turn-on period of the first input unit 21, when the first output unit 11 transmits a valid light-emitting control signal to the output terminal OUT of the shift register unit 100, the signal at the output terminal OUT will change from the original ineffective light-emitting control signal to a valid light-emitting control signal. At this time, due to the coupling effect of the first capacitor C1, the potential change of the output terminal OUT signal will enhance the enable signal transmitted by the first input unit 21 to the first output unit 11, which is equivalent to transmitting a signal with the same polarity as the enable signal transmitted by the first input unit 21 to the control terminal of the first output unit 11. This helps to ensure that the first output unit 11 remains on until the signal potential of the output terminal OUT is equivalent to the signal potential on the first voltage signal line L1, thus avoiding the problem of the shift register unit 100 outputting a stepped signal.

[0066] For example, combining Figure 6 and Figure 7As shown, the effective light-emitting control signal transmitted by the first output unit 11 to the output terminal OUT of the shift register unit 100 is a low-level signal. During the first turn-on period T1 of the first input unit 21, the trigger terminal IN receives a low-level trigger signal, that is, the enable signal transmitted by the first input unit 21 to the control terminal of the first output unit 11 is a low-level signal. When the first output unit 11 transmits a low-level signal to the output terminal OUT of the shift register unit 100, the signal at the output terminal OUT will change from a high-level signal to a low-level signal. Due to the coupling effect of the first capacitor C1, the potential change of the output terminal OUT signal will pull down the potential of the control terminal of the first output unit 11, thereby controlling the first output unit 11 to remain on, so that the signal at the output terminal OUT can be directly pulled down to a lower potential.

[0067] Figure 8 This is a partial schematic diagram of another shift register unit provided in an embodiment of this application.

[0068] In another technical solution of this application embodiment, such as Figure 8 As shown, the second terminal of the voltage control unit 31 is electrically connected to the third voltage signal line L3. During the first turn-on period of the first input unit 21, the voltage control unit 31 transmits the voltage on the third voltage signal line L3 to the control terminal of the first output unit 11.

[0069] Of course, during the first turn-on period of the first input unit 21, the polarity of the signal on the third voltage signal line L3 is the same as the polarity of the enable signal transmitted by the first input unit 21.

[0070] Specifically, during the first turn-on period of the first input unit 21, when the enable signal transmitted by the first input unit 21 is a low-level signal, the voltage on the third voltage signal line L3 is not greater than the voltage of the enable signal transmitted by the first input unit 21 to the control terminal of the first output unit 11. That is, the voltage potential on the third voltage signal line L3 can be less than or equal to the potential of the enable signal transmitted by the first input unit 21 to the first output unit 11.

[0071] Optionally, the third voltage signal line L3 is electrically connected to the first voltage signal line L1. The third voltage signal line L3 and the first voltage signal line L1 transmit the same low-level signal VGL.

[0072] In this technical solution, during the first turn-on period of the first input unit 21, after the first input unit 21 transmits an enable signal to the control terminal of the first output unit 11 and controls the first output unit 11 to turn on, the first output unit 11 transmits an effective light-emitting control signal to the output terminal OUT of the shift register unit 100, thereby changing the original signal potential of the output terminal OUT. At this time, the voltage control unit 31 transmits the voltage on the third voltage signal line L3 to the control terminal of the first output unit 11. Since the polarity of the voltage signal on the third voltage signal line L3 is the same as the polarity of the enable signal transmitted by the first input unit 21, it is equivalent to strengthening the control capability of the enable signal transmitted by the first input unit 21 on the first output unit 11. It can further control the first output unit 11 to remain in the turn-on state until the signal potential of the output terminal OUT is equivalent to the signal potential on the first voltage signal line L1, thus avoiding the problem of the shift register unit 100 outputting a stepped signal.

[0073] Figure 9 for Figure 8 The diagram shows a timing diagram related to the shift register unit.

[0074] In one embodiment of this application, please continue to refer to Figure 8 The voltage control unit 31 includes a first transistor M1, the first electrode of the first transistor M1 is electrically connected to the first terminal of the voltage control unit 31, the second electrode is electrically connected to the second terminal of the voltage control unit 31, and the gate is electrically connected to the control terminal of the voltage control unit 31.

[0075] Specifically, the first terminal of the first transistor M1 is electrically connected to the control terminal of the first output unit 11, the second terminal is electrically connected to the third voltage signal line L3, and the gate is electrically connected to the first control line S1.

[0076] Combination Figure 9 As shown, during the first turn-on period T1 of the first input unit 21, the first control line S1 transmits a valid signal (such as a low-level signal) to control the first transistor M1 to turn on, and the signal on the third voltage signal line L3 can be transmitted to the control terminal of the first output unit 11 through the turned-on first transistor M1.

[0077] Please continue to refer to this. Figure 7 and Figure 8 In one embodiment of this application, the first output unit 11 includes a second transistor M2. The first terminal of the second transistor M2 is electrically connected to the output terminal OUT of the shift register unit 100, the second terminal is electrically connected to the first voltage signal line L1, and the gate is electrically connected to the output terminal of the first input unit 21. The first terminal of the second transistor M2 can be its source and the second terminal can be its drain.

[0078] The second output unit 12 includes a third transistor M3. The first terminal of the third transistor M3 is electrically connected to the second voltage signal line L2, and the second terminal is electrically connected to the output terminal OUT of the shift register unit 100.

[0079] The second transistor M2 and the third transistor M3 have the same channel type.

[0080] Furthermore, both the second transistor M2 and the third transistor M3 can be P-type transistors.

[0081] In this embodiment, the second transistor M2 in the first output unit 11 and the third transistor M3 in the second output unit 12 are configured to have the same channel type. This is beneficial for simplifying the fabrication process of the shift register unit 100 and for making it easier to control the second transistor M2 and the third transistor M3 to be turned on in a time-division manner.

[0082] Optionally, such as Figure 8 As shown, when the unit control unit 31 includes a first transistor M1, the channel type of the first transistor M1 is the same as the channel type of the second transistor M2.

[0083] Figure 10 This is a schematic diagram of a shift register unit provided in an embodiment of this application. Figure 11 for Figure 10 The diagram shows a timing diagram of a shift register unit.

[0084] In one embodiment of this application, such as Figure 10 As shown, the shift register unit 100 also includes a second capacitor C2. One plate of the second capacitor C2 is electrically connected to the control terminal of the first output unit 11, and the other plate is electrically connected to the first clock signal line XCK. The first clock signal line XCK transmits pulse signals.

[0085] It should be noted that, Figure 8 It can be Figure 10 A partial schematic diagram of the shift register unit shown.

[0086] Combination Figure 10 and Figure 11As shown, during the first turn-on period T1 of the first input unit 21, the polarity of the signal transmitted by the first clock signal line XCK can be opposite to the polarity of the enable signal transmitted by the first input unit 21. In the subsequent period T2 of the first turn-on period T1 of the first input unit 21, the polarity of the signal transmitted by the first clock signal line XCK can be the same as the polarity of the enable signal transmitted by the first input unit 21. Due to the coupling effect of the second capacitor C2, the signal variation transmitted by the first clock signal line XCK can further enhance the control capability of the enable signal transmitted by the first input unit 21 on the first output unit 11, thereby facilitating further control of the first output unit 11 to remain continuously on, so that the output terminal OUT of the shift register unit 100 continuously outputs a valid light-emitting control signal.

[0087] To illustrate the technical solution of this application more clearly, the following will be combined with... Figure 10 and Figure 11 right Figure 10 The operation of the shift register unit 100 shown will be explained.

[0088] like Figure 10 As shown, the first input unit 21 includes a fourth transistor M4. The first terminal of the fourth transistor M4 is electrically connected to the trigger terminal IN, the second terminal is electrically connected to the gate of the second transistor M2, and the gate is electrically connected to the second clock signal line CK. Furthermore, the shift register unit 100 also includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5. The specific connection methods of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 are as follows... Figure 10 As shown, details will not be elaborated further here. To facilitate a description of the operation of the shift register unit 100, Figure 10 The diagram also illustrates the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5. The first node N1 is electrically connected to the gate of the second transistor M2, and the second node N2 is electrically connected to the gate of the third transistor M3. The positions of the third node N3, the fourth node N4, and the fifth node N5 are shown in the diagram. Figure 10 As shown, details will not be elaborated upon here. It should be noted that... Figure 10 The transistors shown are all illustrated as P-type transistors.

[0089] Combination Figure 11As shown, taking the transmission of low-level signal VGL on the first voltage signal line L1 and the third voltage signal line L3, and the transmission of high-level signal VGH on the second voltage signal line L2 as an example, the working process of the shift register unit 100 includes four stages, P1-P4.

[0090] In phase P1, the first control line S1 transmits a high-level signal, and the first transistor M1 is turned off. The second clock signal line CK transmits a low-level signal, the first clock signal line XCK transmits a high-level signal, and the trigger terminal IN provides a high-level signal. The eighth transistor M8 turns on, providing the high-level signal of the trigger terminal IN to the fourth node N4, while the ninth transistor M9 and the tenth transistor M10 turn off. The seventh transistor M7 turns on, providing a low-level signal to the third node N3. The third node N3 controls the eleventh transistor M11 to turn on, providing the high-level signal of the first clock signal line XCK to the fifth node N5. The fourth transistor M4 turns on, providing the high-level signal of the trigger terminal IN to the first node N1. In this phase, the first node N1, the third node N3, the fourth node N4, and the fifth node N5 are reset. Specifically, the first node N1 is at a high level, the fourth node N4 is at a high level, the fifth node N5 is at a high level, the third node N3 is at a low level, the second node N2 maintains the high level of the previous phase, and the second transistor M2 and the third transistor M3 are both in the off state.

[0091] In phase P2, the first control line S1 transmits a high-level signal, and the first transistor M1 is turned off. The second clock signal line CK transmits a high-level signal, the first clock signal line XCK transmits a low-level signal, and the trigger terminal IN provides a low-level signal. During this phase, the signal transmitted by the first clock signal line XCK controls the twelfth transistor M12 to turn on. At this moment, the first node N1 is at a high-level potential, the potential of the second node N2 is pulled low, the third transistor M3 turns on, and the high-level signal VGH on the second voltage signal line L2 is transmitted to the output terminal OUT of the shift register unit 100, which outputs a high-level signal.

[0092] In phase P3, the second clock signal line CK transmits a low-level signal, the first clock signal line XCK transmits a high-level signal, the trigger terminal IN provides a low-level signal, the eighth transistor M8 is turned on again, the fourth node N4 is written with a low-level signal and maintained at a low potential; the seventh transistor M7 is turned on, the third node N3 is written with a low potential; the fourth transistor M4 is turned on, the first node N1 is written with a low potential, controlling the second transistor M2 to turn on, the low-level signal VGL on the first voltage signal line L1 is transmitted to the output terminal OUT of the shift register unit 100, pulling down the high-level signal of the output terminal OUT in the previous phase; at the same time, the first control line S1 transmits a low-level signal, the first transistor M1 is turned on, the low-level signal VGL on the third voltage signal line L3 can further pull down the potential of the first node N1, controlling the second transistor M2 to remain on until the output terminal OUT of the shift register unit 100 outputs a low-level signal that meets the requirements. During this stage, the low potential of the first node N1 controls the thirteenth transistor M13 to turn on, writes the high-level signal VGH on the second voltage signal line L2 to the second node N2, controls the second node N2 to maintain a high potential, and the third transistor M3 turns off.

[0093] In the fourth stage P4, the signal of the first clock signal line XCK will decrease from high level to low level. At this time, due to the effect of the second capacitor C2, the first node N1 continues to maintain a low potential, the second transistor M2 continues to be turned on, and the output terminal OUT of the shift register unit 100 continues to output a low-level signal that meets the requirements.

[0094] By repeating the above process, the shift register unit 100 can output a low-level effective light-emitting control signal at a certain frequency.

[0095] In the above process, stage P3 can be the first start time period T1 of the first input unit 21, and stage P4 can be the next stage T2 after the first start time period T1 of the first input unit 21.

[0096] Figure 12 This is a schematic diagram of another shift register unit provided in an embodiment of this application.

[0097] Figure 12 The shift register unit 100 shown is... Figure 10 The difference in the shift register unit 100 shown may be only that: the voltage control unit 31 includes a first capacitor C1, one plate of the first capacitor C1 is electrically connected to the gate of the second transistor M2, and the other plate is electrically connected to the output terminal OUT of the shift register unit 100.

[0098] It should be noted that, Figure 7 It can be Figure 12 A partial schematic diagram of the shift register unit shown.

[0099] Figure 13 This is a schematic diagram of yet another shift register unit provided in an embodiment of this application. Figure 14 for Figure 13 The diagram shows a timing diagram of a shift register unit.

[0100] In one embodiment of this application, the second output unit 12 transmits a non-enable signal, i.e., a non-effective light emission control signal, to the output terminal OUT of the shift register unit 100. This non-enable signal can be a high-level signal.

[0101] The number of levels corresponding to the time period of the disabled signal output by shift register unit 100 is m, where m ≥ 1. Here, the number of levels corresponding to the time period of the disabled signal means that the time period of the disabled signal output by the nth level shift register unit 100 overlaps with the time periods of the disabled signals output by the (n+1)th level shift register unit 100, the (n+2)th level shift register unit 100 to the (n+m-1)th level shift register unit 100, where n ≥ 1.

[0102] For example, when m=3 and n=1, the time period during which the first-level shift register unit 100 outputs the disabled signal overlaps with the time periods during which the second-level shift register unit 100 and the third-level shift register unit 100 output the disabled signal.

[0103] Among them, in multiple cascaded shift register units 100, such as Figure 13 As shown, the control terminal of the voltage control unit 31 in the nth-level shift register unit 100 is electrically connected to the control terminal of the second output unit 12 in the (n+m)th-level shift register unit 100, where n≥1. Figure 13 This only illustrates the connection of the control terminal of the voltage control unit 31 when m=1.

[0104] Based on the working process of the shift register unit 100 and the characteristics of the cascaded shift register units 100, it can be seen that in the P3 stage of the nth-level shift register unit 100, the potential of the second node N2 in the (n+m)th-level shift register unit 100 is low.

[0105] like Figure 14 As shown, in stage P3 of the nth-level shift register unit 100, the potential of the second node N2 in the (n+1)th-level shift register unit 100 is low, which can control the voltage control unit 31 in the nth-level shift register unit 100 to turn on. This ensures that the first output unit 11 in the nth-level shift register unit 100 remains on, allowing the nth-level shift register unit 100 to directly output a lower potential that meets the requirements in stage P3, thus avoiding the problem of step-like signals.

[0106] In this embodiment, the control terminal of the voltage control unit 31 in the nth-level shift register unit 100 can be electrically connected to the control terminal of the second output unit 12 in the (n+m)th-level shift register unit 100. This eliminates the need to set up a separate control signal line for the voltage control unit 31, which helps to reduce the number of signal lines electrically connected to the shift register unit 100 and reduces the manufacturing difficulty and cost.

[0107] like Figure 4 As shown, this application embodiment also provides a display panel 01, which includes the light-emitting control driving circuit 10 provided in the above embodiment. Exemplarily, the display panel 01 can be a liquid crystal display panel, an organic light-emitting diode display panel, a sub-millimeter light-emitting diode display panel (mini-LED), or a micro light-emitting diode display panel (micro-LED), and this application embodiment does not limit it to this type.

[0108] In the display panel 01, during the first turn-on period of the first input unit 21, after the first input unit 21 transmits an enable signal to the control terminal of the first output unit 11 and controls the first output unit 11 to turn on, the signal on the first voltage signal line L1 will be transmitted to the output terminal OUT of the shift register unit 100 through the first output unit 11, thereby changing the original signal potential of the output terminal OUT. At this time, the signal transmitted by the voltage control unit 31 to the control terminal of the first output unit 11 has the same polarity as the enable signal transmitted by the first input unit 21, which is equivalent to strengthening the control capability of the enable signal transmitted by the first input unit 21 on the first output unit 11. It can further control the first output unit 11 to remain in the turn-on state, which is conducive to the signal on the first voltage signal line L1 being continuously transmitted to the output terminal OUT of the shift register unit 100 until the signal potential of the output terminal OUT is equivalent to the signal potential on the first voltage signal line L1. This avoids the problem of the output terminal OUT of the shift register unit 100 outputting a stepped signal, thereby improving the control effect of the light emission control driving circuit 10 and improving the display effect of the display panel 01.

[0109] Figure 15 This is a schematic diagram of a display device provided in an embodiment of this application.

[0110] This application embodiment also provides a display device 02, such as Figure 15 As shown, it includes the display panel 01 provided in the above embodiments. For example, the display device 02 may be an electronic device such as a mobile phone, computer, television, smart wearable device (e.g., smartwatch), and in-vehicle display device, and the embodiments of this application do not limit it in this way.

[0111] In the display device 02, during the first turn-on period of the first input unit 21, after the first input unit 21 transmits an enable signal to the control terminal of the first output unit 11 and controls the first output unit 11 to turn on, the signal on the first voltage signal line L1 will be transmitted to the output terminal OUT of the shift register unit 100 through the first output unit 11, thereby changing the original signal potential of the output terminal OUT. At this time, the signal transmitted by the voltage control unit 31 to the control terminal of the first output unit 11 has the same polarity as the enable signal transmitted by the first input unit 21, which is equivalent to strengthening the control capability of the enable signal transmitted by the first input unit 21 on the first output unit 11. It can further control the first output unit 11 to remain in the turn-on state, which is beneficial to ensure that the signal on the first voltage signal line L1 can be continuously transmitted to the output terminal OUT of the shift register unit 100 until the signal potential of the output terminal OUT is equivalent to the signal potential on the first voltage signal line L1. This avoids the problem of the output terminal OUT of the shift register unit 100 outputting a stepped signal, which in turn helps to improve the control effect of the light emission control driving circuit 10 and improve the display effect of the display device 02.

[0112] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A light-emitting control driving circuit, characterized in that, This includes multiple cascaded shift register units, each shift register unit comprising: The first output unit has its input terminal electrically connected to the first voltage signal line and its output terminal electrically connected to the output terminal of the shift register unit. The first input unit has its input terminal electrically connected to the trigger terminal of the shift register unit and its output terminal electrically connected to the control terminal of the first output unit. A voltage control unit, wherein a first terminal of the voltage control unit is electrically connected to the control terminal of the first output unit, and during a first turn-on period of the first input unit, the first input unit transmits an enable signal to the control terminal of the first output unit, and the voltage control unit transmits a signal with the same polarity as the enable signal to the control terminal of the first output unit. The shift register unit further includes a second output unit, the input terminal of which is electrically connected to the second voltage signal line, and the output terminal of which is electrically connected to the output terminal of the shift register unit. The signal output by the second output unit has the opposite polarity to the signal output by the first output unit. The second output unit transmits a de-enable signal to the output terminal of the shift register unit. The number of stages corresponding to the time period during which the shift register unit outputs the de-enable signal is m, where m ≥ 1. In the multiple cascaded shift register units, the control terminal of the voltage control unit in the nth stage shift register unit is electrically connected to the control terminal of the second output unit in the (n+m)th stage shift register unit, where n ≥ 1.

2. The light-emitting control driving circuit according to claim 1, characterized in that, The voltage control unit includes a first capacitor, one plate of which is electrically connected to the control terminal of the first output unit, and the other plate is electrically connected to the output terminal of the shift register unit.

3. The light-emitting control driving circuit according to claim 1, characterized in that, The second terminal of the voltage control unit is electrically connected to the third voltage signal line. During the first turn-on period of the first input unit, the voltage control unit transmits the voltage on the third voltage signal line to the control terminal of the first output unit.

4. The light-emitting control driving circuit according to claim 3, characterized in that, During the first activation period of the first input unit, the voltage on the third voltage signal line is not greater than the voltage of the enable signal transmitted from the first input unit to the control terminal of the first output unit.

5. The light-emitting control driving circuit according to claim 4, characterized in that, The third voltage signal line is electrically connected to the first voltage signal line.

6. The light-emitting control driving circuit according to claim 3, characterized in that, The voltage control unit includes a first transistor, wherein a first electrode of the first transistor is electrically connected to a first terminal of the voltage control unit, a second electrode is electrically connected to a second terminal of the voltage control unit, and a gate is electrically connected to a control terminal of the voltage control unit.

7. The light-emitting control driving circuit according to claim 6, characterized in that, The first output unit includes a second transistor, wherein the first terminal of the second transistor is electrically connected to the output terminal of the shift register unit, the second terminal is electrically connected to the first voltage signal line, and the gate is electrically connected to the output terminal of the first input unit; The second output unit includes a third transistor, wherein the first terminal of the third transistor is electrically connected to the second voltage signal line, and the second terminal is electrically connected to the output terminal of the shift register; The second transistor and the third transistor have the same channel type.

8. The light-emitting control driving circuit according to claim 7, characterized in that, Both the second transistor and the third transistor are P-type transistors.

9. The light-emitting control driving circuit according to claim 7, characterized in that, The first transistor and the second transistor have the same channel type.

10. The light-emitting control driving circuit according to claim 1, characterized in that, The shift register unit further includes a second capacitor, one plate of which is electrically connected to the control terminal of the first output unit, and the other plate is electrically connected to the first clock signal line.

11. A display panel, characterized in that, The display panel includes the light-emitting control driving circuit as described in any one of claims 1-10.

12. A display device, characterized in that, Includes the display panel as described in claim 11.

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