Memory, semiconductor structure and method of forming the same

Abstract

The present disclosure relates to the technical field of semiconductor technology, and discloses a memory, a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a substrate; forming a plurality of groups of support columns spaced apart along a first direction in the substrate, each group of support columns being spaced apart along a second direction, and the first direction intersecting the second direction; forming a support layer filling a top gap between adjacent support columns; forming an epitaxial column on the top of each support column by an epitaxial growth process; and forming a capacitor structure on the surface of a structure formed by each epitaxial column and each support column. The forming method of the semiconductor structure can increase the storage capacity and improve the product yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a memory, a semiconductor structure, and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration, and high transfer speed. Capacitors, as the core component of DRAM, are mainly used to store electrical charge.

[0003] In the typical process of manufacturing capacitors, overlapping support and sacrificial layers are formed on a substrate. These layers are then etched to create a porous structure that houses the capacitor. The sacrificial layer is removed after the capacitor is formed. However, due to limitations in the fabrication process, the etching depth varies in different areas during the formation of the porous structure. After removing the sacrificial layer, some capacitors fail due to being suspended, and these capacitors are prone to collapse, resulting in low device yield.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a memory, a semiconductor structure and a method for forming the same, which can increase storage capacity and improve product yield.

[0006] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising:

[0007] Provide substrate;

[0008] Multiple sets of support pillars are formed in the substrate at intervals along a first direction, and each set of support pillars is at intervals along a second direction, wherein the first direction intersects the second direction;

[0009] A support layer is formed to fill the top gap between adjacent support columns;

[0010] Epitaxial pillars are formed on the top of each of the aforementioned support pillars using an epitaxial growth process;

[0011] A capacitor structure is formed on the surface of the structure jointly formed by the epitaxial pillars and the support pillars.

[0012] In one exemplary embodiment of this disclosure, the support layer includes a first extension and a second extension, the first extension filling the top gap of each of the support columns distributed along the first direction, and the second extension filling the top gap of each of the support columns distributed along the second direction.

[0013] In one exemplary embodiment of this disclosure, forming a plurality of sets of support pillars spaced apart along a first direction within the substrate, each set of support pillars being spaced apart along a second direction, the first direction intersecting the second direction, includes:

[0014] A plurality of first trenches extending along a first direction are formed in the substrate, and each of the first trenches is spaced apart along a second direction.

[0015] Fill the first trench with insulating material;

[0016] The substrate and the insulating material are etched along the second direction to form multiple sets of support pillars spaced apart along the second direction within the substrate.

[0017] In one exemplary embodiment of this disclosure, the substrate includes a first doped region and a second doped region adjacently distributed along the thickness direction, and the formation method further includes:

[0018] The first doped region is p-type doped;

[0019] The second doped region is n-type doped, and the support pillar is located in the second doped region and is in contact with and connected to the first doped region.

[0020] In one exemplary embodiment of this disclosure, the substrate and the insulating material are etched along the second direction to form a plurality of sets of support pillars spaced apart along the second direction within the substrate, including:

[0021] The substrate and the insulating material are etched along the second direction using the Bosch ETCH process to form a plurality of second trenches spaced apart along the first direction. The second trenches extend into the first doped region, and the portion of the trench extending into the first doped region has a dimension in the first direction that is greater than the spacing between two adjacent support pillars.

[0022] In one exemplary embodiment of this disclosure, forming the first extension and the second extension includes:

[0023] The insulating material is filled in the second trench, and the insulating material located in the second trench and the insulating material located in the first trench together constitute a sacrificial layer;

[0024] The sacrificial layer is etched back so that the surface of the sacrificial layer is lower than the surface of the support post;

[0025] A reference support layer is formed to cover the sacrificial layer, the reference support layer filling the top gap of each of the support columns;

[0026] The reference support layer is etched along the second direction to form a third trench between two adjacent sets of support pillars, and the reference support layer between the support pillars distributed along the second direction is retained to form a second extension;

[0027] The insulating material is filled into the third trench;

[0028] The insulating material in the third trench is etched along the first direction to remove the insulating material located between adjacent support pillars;

[0029] The gaps between the support columns distributed along the first direction are filled with support material to form a first extension.

[0030] In one exemplary embodiment of this disclosure, the forming method further includes:

[0031] Before forming a capacitor structure on the surface of the structure jointly formed by the epitaxial pillars and the support pillars, the sacrificial layer and the insulating material located in the second doped region are removed.

[0032] In one exemplary embodiment of this disclosure, the first doped region further includes a plurality of conductive contact plugs arranged in an array, the orthographic projection of the capacitor structure in the first doped region at least partially overlaps with the conductive contact plugs, and the capacitor structure is in contact with the conductive contact plugs.

[0033] In one exemplary embodiment of this disclosure, the thickness of the support layer is 10 nm to 50 nm.

[0034] In one exemplary embodiment of this disclosure, forming a capacitor structure on the surface of the structure jointly formed by the epitaxial pillars and the support pillars includes:

[0035] A conformally attached lower electrode layer is formed on the surface of the structure jointly formed by the epitaxial pillar and the support pillar, and the end of the lower electrode layer near the first doped region is in contact with the conductive contact plug.

[0036] A capacitor dielectric layer is formed on the surface of the lower electrode layer;

[0037] An upper electrode layer is formed on the surface of the lower electrode layer.

[0038] In one exemplary embodiment of this disclosure, the upper electrode layer fills the gaps between each of the support pillars and each of the epitaxial pillars, and the forming method further includes:

[0039] The capacitor structure is etched back to form a channel;

[0040] A protective layer is formed within the trench, and the protective layer fills the trench.

[0041] In one exemplary embodiment of this disclosure, the ratio of the height of the extension post to the height of the support post is one-third to five-thirds.

[0042] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0043] The substrate includes multiple sets of support pillars spaced apart along a first direction, each set of support pillars spaced apart along a second direction, the first direction intersecting the second direction;

[0044] A support layer is provided to fill the top gap between adjacent support columns;

[0045] Multiple extension pillars are formed one-to-one on the top of each of the aforementioned support pillars;

[0046] A capacitor structure is formed on the surface of the structure jointly formed by the epitaxial pillars and the support pillars.

[0047] In one exemplary embodiment of this disclosure, the support layer includes a first extension and a second extension, the first extension filling the top gap of each of the support columns distributed along the first direction, and the second extension filling the top gap of each of the support columns distributed along the second direction.

[0048] In one exemplary embodiment of this disclosure, the substrate includes a first doped region and a second doped region adjacent to each other along the thickness direction, the first doped region being a P-type doped region and the second doped region being an N-type doped region, the support pillar being located in the second doped region and in contact with the first doped region.

[0049] In an exemplary embodiment of this disclosure, a plurality of first trenches extending along a first direction and spaced apart along a second direction and a plurality of second trenches extending along the second direction and spaced apart along the first direction are formed in the substrate. In the first direction, the support post is located between two adjacent second trenches, and in the second direction, the support post is located between two adjacent first trenches. In the thickness direction of the substrate, both the first trenches and the second trenches extend into the first doped region. The portion of the second trench extending into the first doped region has a dimension in the first direction that is larger than the spacing between two adjacent support posts. Insulating material is formed in both the first trenches located in the first doped region and the second trenches located in the first doped region.

[0050] In one exemplary embodiment of this disclosure, the first doped region further includes a plurality of conductive contact plugs arranged in an array, the orthographic projection of the capacitor structure in the first doped region at least partially overlaps with the conductive contact plugs, and the capacitor structure is in contact with the conductive contact plugs.

[0051] In one exemplary embodiment of this disclosure, the thickness of the support layer is 10 nm to 50 nm.

[0052] In one exemplary embodiment of this disclosure, the capacitor structure includes:

[0053] The lower electrode layer is conformally attached to the surface of the structure formed by the epitaxial pillar and the support pillar, and the end of the lower electrode layer near the first doped region is in contact with the conductive contact plug.

[0054] A capacitor dielectric layer is formed on the surface of the lower electrode layer;

[0055] An upper electrode layer is formed on the surface of the lower electrode layer.

[0056] In one exemplary embodiment of this disclosure, the upper electrode layer fills the gap between each of the support pillars and each of the epitaxial pillars, and the end of the capacitor structure facing away from the support layer is lower than the top of the epitaxial pillars. The semiconductor structure further includes:

[0057] A protective layer covers the surface of the capacitor structure and fills the gaps between the epitaxial pillars.

[0058] In one exemplary embodiment of this disclosure, the ratio of the height of the extension post to the height of the support post is one-third to five-thirds.

[0059] According to one aspect of this disclosure, a memory is provided, comprising the semiconductor structure described in any one of the foregoing claims.

[0060] The memory, semiconductor structure, and method for forming the present disclosure involve growing epitaxial pillars on support pillars using an epitaxial growth process, followed by forming a capacitor structure on the surface of the structure jointly formed by the support pillars and the epitaxial pillars. In this process, on the one hand, the height of the initially etched support pillars can be appropriately reduced, avoiding insufficient etching and preventing the subsequently formed capacitor structure from becoming suspended. On the other hand, the lower support pillar height prevents the support pillars from collapsing, thereby preventing the capacitor structure formed on them from collapsing; simultaneously, a support layer can be used to support the capacitor structure, further preventing collapse and improving product yield. Furthermore, forming epitaxial pillars on the support pillars using an epitaxial process increases the pillar height, thereby increasing the height of the capacitor structure formed on its surface, thus increasing the capacitor's storage capacity.

[0061] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0062] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0063] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0064] Figure 2 This is a schematic diagram of the structure after step S120 is completed in the embodiment of this disclosure;

[0065] Figure 3 Here is a flowchart of step S120 in the disclosed implementation method;

[0066] Figure 4 This is a schematic diagram of the structure after step S1201 is completed in the embodiment of this disclosure;

[0067] Figure 5 This is a schematic diagram of the structure after step S1202 is completed in the embodiment of this disclosure;

[0068] Figure 6 This is a schematic diagram of the structure after step S130 is completed in the embodiment of this disclosure;

[0069] Figure 7 A flowchart illustrating the formation of the first extension and the second extension in the disclosed embodiment;

[0070] Figure 8This is a schematic diagram of the structure after step S310 is completed in the embodiment of this disclosure;

[0071] Figure 9 This is a schematic diagram of the structure after step S320 is completed in the embodiment of this disclosure;

[0072] Figure 10 This is a schematic diagram of the structure after step S330 is completed in the embodiment of this disclosure;

[0073] Figure 11 This is a schematic diagram of the structure after step S340 is completed in the embodiment of this disclosure;

[0074] Figure 12 This is a schematic diagram of the structure after step S350 is completed in the embodiment of this disclosure;

[0075] Figure 13 This is a schematic diagram of the structure after step S360 is completed in the embodiment of this disclosure;

[0076] Figure 14 This is a schematic diagram of the structure after step S370 is completed in the embodiment of this disclosure;

[0077] Figure 15 This is a schematic diagram of the structure after step S140 is completed in the embodiment of this disclosure;

[0078] Figure 16 This is a top view of the structure after step S140 is completed in this embodiment of the present disclosure;

[0079] Figure 17 This is a schematic diagram of the structure after step S150 is completed in the embodiment of this disclosure;

[0080] Figure 18 This is a schematic diagram of the structure after step S160 is completed in the embodiment of this disclosure;

[0081] Figure 19 This is a top view of the structure after step S160 is completed in the embodiment of this disclosure;

[0082] Figure 20 Here is a flowchart of step S150 in the disclosed implementation method;

[0083] Figure 21 This is a schematic diagram of the structure after step S1501 is completed in the embodiment of this disclosure;

[0084] Figure 22 This is a top view of the structure after step S1501 is completed in this embodiment of the present disclosure;

[0085] Figure 23 This is a schematic diagram of the structure after step S170 is completed in the embodiment of this disclosure;

[0086] Figure 24 This is a schematic diagram of the structure after step S180 is completed in the embodiment of this disclosure.

[0087] Explanation of reference numerals in the attached figures:

[0088] 1. Substrate; 11. Support pillar; 12. First trench; 13. Second trench; 14. Third trench; 15. Fourth trench; 1501. Isolation trench; 101. First doped region; 102. Second doped region; 200. Reference support layer; 2. Support layer; 21. First extension; 22. Second extension; 3. Epitaxial pillar; 4. Capacitor structure; 41. Lower electrode layer; 42. Capacitor dielectric layer; 43. Upper electrode layer; 5. Insulating material; 6. Protective layer; A. First direction; B. Second direction. Detailed Implementation

[0089] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0090] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0091] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion meaning and that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” “third,” and “fourth,” etc., are used only as markers and are not a limitation on the number of objects.

[0092] With the development of semiconductor technology, there is a huge demand for smaller and more integrated memory. Capacitors are the core component of memory, primarily used to store electrical charge. As memory size shrinks, achieving the same capacitance or increasing it further becomes increasingly difficult, as stated in the capacitance formula (…). As can be seen from A=2πr*h), when using materials with the same dielectric constant, the only way to increase the storage capacity of a capacitor is to reduce the thickness of the dielectric layer and increase the surface area of ​​the capacitor. However, reducing the thickness of the dielectric layer can easily lead to excessive leakage current and low product yield.

[0093] In related technologies, increasing the capacitor's surface area is commonly used to increase its storage capacity. During capacitor manufacturing, overlapping support and sacrificial layers are formed on a substrate, and these layers are etched to create a porous structure with a high aspect ratio. The sacrificial layer is then removed after the capacitor is formed. However, due to limitations in the fabrication process, the etching depth of the film layer varies in different etched areas during the formation of the porous structure with a high aspect ratio. After removing the sacrificial layer, some capacitors fail due to being suspended, and these capacitors are prone to collapse, resulting in a low device yield.

[0094] Based on this, the present disclosure provides a method for forming a semiconductor structure to solve the above-mentioned technical problems. Figure 1 A flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this disclosure is shown. See also... Figure 1 As shown, the forming method may include steps S110-S150, wherein:

[0095] Step S110: Provide a substrate;

[0096] Step S120: Multiple sets of support pillars spaced apart along a first direction are formed in the substrate, and each set of support pillars is spaced apart along a second direction, wherein the first direction intersects the second direction.

[0097] Step S130: Form a support layer that fills the top gap between adjacent support columns;

[0098] Step S140: An epitaxial growth process is used to form epitaxial pillars on the top of each of the support pillars.

[0099] Step S150: A capacitor structure is formed on the surface of the structure jointly formed by each of the epitaxial pillars and each of the support pillars.

[0100] The semiconductor structure formation method disclosed herein involves growing epitaxial pillars on support pillars using an epitaxial growth process, followed by forming a capacitor structure on the surface of the structure jointly formed by the support pillars and the epitaxial pillars. In this process, on the one hand, the height of the initially etched support pillars can be appropriately reduced, avoiding insufficient etching and preventing the subsequently formed capacitor structure from becoming suspended. On the other hand, the lower support pillar height prevents the support pillars from collapsing, thereby preventing the capacitor structure formed on them from collapsing and improving product yield. Simultaneously, a support layer can be used to support the capacitor structure, further preventing collapse and improving product yield. Furthermore, forming epitaxial pillars on the support pillars using an epitaxial process increases the pillar height, thereby increasing the height of the capacitor structure formed on its surface, thus increasing the capacitor's storage capacity.

[0101] The steps of the method for forming a semiconductor structure according to the present disclosure will be described in detail below:

[0102] like Figure 1 As shown, in step S110, a substrate is provided.

[0103] like Figure 2 As shown, substrate 1 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular in shape, and its material can be silicon or other semiconductor materials. No special restrictions are made on the shape and material of substrate 1 here.

[0104] Substrate 1 may include a substrate (not shown) and an insulating layer (not shown) formed on the substrate. Multiple conductive contact plugs (not shown) are formed within the insulating layer and are arranged side-by-side. The insulating layer separates the conductive contact plugs, preventing coupling between them or the generation of parasitic capacitance. The conductive contact plugs may be made of conductors or semiconductor materials, such as tungsten, copper, or polycrystalline silicon.

[0105] For example, the insulating layer may have multiple vias arranged in an array, each of which may be a through hole. Conductive contact plugs may be formed within the vias. For example, conductive contact plugs may be formed within the vias by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods may also be used to form conductive contact plugs, which will not be listed here.

[0106] This disclosure may include multiple groups of conductive contact plugs spaced apart along a first direction A. For example, the conductive contact plugs in each group may be equally spaced along the first direction A; multiple groups of conductive contact plugs may be spaced apart along a second direction B. For example, each group of conductive contact plugs may be equally spaced along the second direction B. The first direction A and the second direction B may be perpendicular to each other. That is, the conductive contact plugs may be arranged in an array in rows and columns.

[0107] It should be noted that perpendicularity can be absolute or approximate. Deviations are inevitable during manufacturing. In this disclosure, angular deviations may occur due to manufacturing limitations, resulting in a slight difference in the angle between the first direction A and the second direction B. As long as the angular deviation between the first direction A and the second direction B is within a preset range, the first direction A and the second direction B can be considered perpendicular. For example, the preset range can be 10°, meaning that the angle between the first direction A and the second direction B can be considered perpendicular when it is greater than or equal to 80° and less than or equal to 100°.

[0108] In one embodiment, a shallow trench isolation structure (not shown in the figure) and a bit line structure (not shown in the figure) may be provided in the substrate 1. The shallow trench isolation structure can divide the substrate 1 into multiple active regions. The bit line structure and the conductive contact plug are located on the top of the active regions and are arranged alternately with the conductive contact plug in the substrate 1.

[0109] like Figure 1 As shown, in step S120, multiple sets of support pillars are formed in the substrate at intervals along a first direction, and each set of support pillars is at intervals along a second direction, wherein the first direction intersects the second direction.

[0110] like Figure 2 As shown, multiple support pillars 11 can be formed within the substrate 1 using an etching process. In this disclosure, multiple groups of support pillars 11 spaced apart along a first direction A can be formed within the substrate 1. For example, the support pillars 11 in each group can be equally spaced along the first direction A; multiple groups of support pillars 11 can be spaced apart along a second direction B. For example, each group of support pillars 11 can be equally spaced along the second direction B. The first direction A and the second direction B can be different directions; for example, the first direction A and the second direction B can intersect, or for instance, the first direction A and the second direction B can be perpendicular to each other. That is, the support pillars 11 can be arranged in an array in rows and columns.

[0111] In one exemplary embodiment of this disclosure, multiple sets of support pillars 11 are formed in the substrate 1, spaced apart along a first direction A. Each set of support pillars 11 is spaced apart along a second direction B, where the first direction A intersects the second direction B. That is, step S120 may include steps S1201-S1203. Figure 3 A flowchart of step S120 in this embodiment of the present disclosure is shown, see [link to flowchart]. Figure 3 As shown, where:

[0112] Step S1201: A plurality of first trenches extending along a first direction are formed in the substrate, and each of the first trenches is spaced apart along a second direction.

[0113] like Figure 4As shown, a plurality of first trenches 12 can be formed in the substrate 1 using photolithography. Each first trench 12 can extend along a first direction A, and the plurality of first trenches 12 can be spaced apart along a second direction B. For example, a photoresist layer can be formed on the surface of the substrate 1 by spin coating or other methods. The material of the photoresist layer can be positive or negative photoresist, without special limitation. The shape of the surface of the photoresist layer away from the substrate 1 can be the same as the shape of the surface of the substrate 1. A photomask can be used to expose the photoresist layer, and the pattern of the photomask can match the pattern required for each first trench 12. Subsequently, the exposed photoresist layer can be developed to form a developing area, which exposes the substrate 1, and the pattern of the developing area can be the same as the pattern required for the first trench 12. The size of the developing area can be the same as the size of the required first trench 12. Anisotropic etching can be performed on the substrate 1 in the developing area to expose each conductive contact plug corresponding to the first trench 12. In this embodiment, the structure after step S1201 is as follows. Figure 4 As shown.

[0114] Step S1202: Fill the first trench with insulating material.

[0115] The insulating material 5 can be filled into the first trench 12 using methods such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and the insulating material 5 can fill the entire first trench 12. In one embodiment, the insulating material 5 can be an oxide, for example, silicon oxide. In this embodiment, the structure after step S1202 is as follows: Figure 5 As shown.

[0116] Step S1203: Etch the substrate and the insulating material along the second direction to form multiple sets of support pillars spaced apart along the second direction within the substrate.

[0117] An etching process can be used to etch the substrate 1 and the insulating material 5 in each of the first trenches 12 along the second direction B to form support pillars 11 within the substrate 1. For example, a Bosch ETCH process can be used to etch the substrate 1 and the insulating material 5 along the second direction B to form multiple second trenches 13 spaced apart along the first direction A. The bottom dimension of each second trench 13 can be larger than the spacing between two adjacent support pillars 11 to reduce direct contact between the subsequently formed capacitor structure and the substrate 1, thereby reducing leakage current. The material of the support pillars 11 can be the same as the material of the substrate 1; for example, it can be monocrystalline silicon. The height of the support pillars 11 can be 50nm to 100nm, for example, it can be 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm, and of course, other heights are also possible, which will not be listed here.

[0118] In this process, the second trench 13 can be formed by etching in stages. After each etching, a protective layer can be formed on the sidewall surface of the etched trench structure. Specifically, sulfur hexafluoride plasma can be used to etch the substrate 1 and the insulating material 5 multiple times. Each etching can form a trench structure. In the next etching process, the bottom of the trench structure formed in the previous etching can be further etched to extend the depth of the trench structure, thereby forming the second trench 13. It should be noted that after each etching, a protective layer can be formed on the surface of the trench structure using C4F8 plasma, thereby avoiding damage to the sidewall of the trench structure formed in the previous etching in the next etching process. After the last etching, it is not necessary to form a protective layer at the bottom of the trench structure. In the embodiment of this disclosure, the structure after completing step S1203 is as follows: Figure 2 As shown.

[0119] In one exemplary embodiment of this disclosure, the substrate 1 may include a first doped region 101 and a second doped region 102. The first doped region 101 and the second doped region 102 may be distributed adjacent to each other and may be stacked along the thickness direction. The first doped region 101 and the second doped region 102 have the same shape, and the boundary of the second doped region 102 as projected onto the first doped region 101 coincides with the boundary of the first doped region 101. The formation method of this disclosure may further include steps S210 and S220, wherein:

[0120] Step S210: Perform p-type doping on the first doped region.

[0121] The substrate 1 can be p-type doped by ion implantation. For example, p-type doping material can be doped into the first doping region 101 to form a p-type semiconductor in the first doping region 101.

[0122] In one exemplary embodiment of this disclosure, the p-type doped material can be an element located in Group III of the periodic table. For example, it can be boron, but it can also be a material of other elements, which will not be listed here.

[0123] In one exemplary embodiment of this disclosure, each conductive contact plug may be located within the first doped region 101, and each conductive contact plug may be arranged in an array within the first doped region 101.

[0124] Step S220: The second doped region is n-type doped, and the support pillar is located in the second doped region and is in contact with the first doped region.

[0125] The substrate 1 can be n-type doped by ion implantation to form a pn junction in the substrate 1. For example, n-type doping material can be doped into the second doping region 102 to form an n-type semiconductor in the second doping region 102. The p-type semiconductor in the first doping region 101 and the n-type semiconductor in the second doping region 102 can form a pn junction.

[0126] In one exemplary embodiment of this disclosure, the n-type doped material can be an element located in Group IV of the periodic table, for example, it can be phosphorus, and of course, it can also be a material of other elements, which will not be listed here.

[0127] In one exemplary embodiment of this disclosure, the support post 11 may be located in the second doped region 102, and its end near the first doped region 101 may be in contact with the first doped region 101. That is, the support post 11 may be an n-type semiconductor, and a pn junction may be formed between the support post 11 and the first doped region 101, which can reduce leakage current through the depletion region of the pn junction.

[0128] In one exemplary embodiment of this disclosure, the second trench 13 may extend into the first doped region 101, and the portion extending into the first doped region 101 may have a dimension in the first direction A that is greater than the spacing between two adjacent support pillars 11. Since the bottom dimension of the second trench 13 is greater than the spacing between adjacent support pillars 11, direct contact between the capacitor structure subsequently formed in the second trench 13 and the substrate 1 can be reduced. Simultaneously, leakage current can be reduced and product yield improved by the arrangement of the pn junction.

[0129] like Figure 1 As shown, in step S130, a support layer is formed to fill the top gap between adjacent support columns.

[0130] In one exemplary embodiment of this disclosure, the support layer 2 may include a first extension 21 and a second extension 22. The first extension 21 and the second extension 22 may fill the ends of the support pillars 11 that are away from the first doped region 101. For example, the first extension 21 may fill the top gaps of each support pillar 11 distributed along the first direction A. The first extension 21 can provide lateral support for each support pillar 11 distributed along the first direction A in the first direction A, thereby preventing the support pillars 11 from collapsing. The second extension 22 may fill the top gaps of each support pillar 11 distributed along the second direction B. The second extension 22 can provide lateral support for each support pillar 11 distributed along the second direction B in the second direction B, thereby further preventing the support pillars 11 from collapsing.

[0131] In one exemplary embodiment of this disclosure, the thickness of the support layer 2 can be 10nm to 50nm. For example, it can be 10nm, 20nm, 30nm, 40nm, or 50nm. Of course, other thicknesses are also possible, which will not be listed here. In this embodiment of the disclosure, the structure after completing step S130 is as follows: Figure 6 As shown.

[0132] In one exemplary embodiment of this disclosure, forming the first extension 21 and the second extension 22 includes steps S310-S370. Figure 7 A schematic diagram showing the formation of the first extension 21 and the second extension 22 in an embodiment of this disclosure is shown. See also Figure 7 As shown, where:

[0133] Step S310: Fill the second trench with the insulating material, wherein the insulating material in the second trench and the insulating material in the first trench together constitute a sacrificial layer.

[0134] The insulating material 5 can be filled into the second trench 13 using processes such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the insulating material 5 can also be filled into the second trench 13 in other ways. No special limitation is made on the filling method of the insulating material 5 here.

[0135] In one embodiment, the insulating material 5 may fill the second trench 13 such that the top surfaces of the insulating material 5 in the first trench 12 and the insulating material 5 in the second trench 13 are flush. The insulating material 5 in the second trench 13 and the insulating material 5 in the first trench 12 may together form a sacrificial layer. The insulating material 5 filling the second trench 13 may be the same as the insulating material 5 filling the first trench 12; for example, its material may be silicon oxide.

[0136] It should be noted that, for ease of process, insulating material 5 can be deposited simultaneously on the surface of the support column 11. Filling can be stopped after the insulating material 5 in the second trench 13 has filled the gaps between the support columns 11. Subsequently, a chemical polishing process can be used to polish the insulating material 5 deposited on the surface of the support column 11, thereby removing the insulating material 5 on the surface of the support column 11, leaving only the insulating material 5 in the second trench 13. In this embodiment, the structure after step S310 is as follows... Figure 8 As shown.

[0137] Step S320: Etch back the sacrificial layer so that the surface of the sacrificial layer is lower than the surface of the support post.

[0138] In one embodiment, a wet etching process can be used to etch back the sacrificial layer, thereby making the surface of the sacrificial layer lower than the top surface of the support pillar 11. For example, an acidic solution can be used for wet etching, such as hydrofluoric acid, for example, buffered hydrofluoric acid (BHF), 49% hydrofluoric acid, or dilute hydrofluoric acid (DHF). When DHF is used as the etching solution, the ratio of hydrofluoric acid to deionized water can be 1:1 to 1:10. No specific limitations are placed on the ratio and concentration of the etching solution. Of course, a dry etching process can also be used to etch back the surface of the sacrificial layer, as long as the surface of the sacrificial layer is lower than the surface of the support pillar 11 by a first predetermined height. No specific limitations are placed on the specific process of the back etching.

[0139] In one exemplary embodiment of this disclosure, the first preset height can be 10nm to 50nm. For example, it can be 10nm, 20nm, 30nm, 40nm, or 50nm. Of course, other heights are also possible, which will not be listed here. In this embodiment of the disclosure, the structure after completing step S320 is as follows: Figure 9 As shown.

[0140] Step S330: A reference support layer is formed to cover the sacrificial layer, the reference support layer filling the top gap of each of the support columns.

[0141] A support material can be deposited on the surface of the sacrificial layer using processes such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form a reference support layer 200 covering the sacrificial layer. This reference support layer 200 can fill the gaps between the tops of each support pillar 11. In one embodiment, the support material can be silicon nitride.

[0142] It should be noted that, for process convenience, support material can be deposited simultaneously on the surface of the support pillars 11. Filling can be stopped after the support material on the sacrificial layer surface fills the gaps between the support pillars 11. Subsequently, a chemical polishing process can be used to polish the support material deposited on the surface of the support pillars 11, thereby removing the support material on the surface of the support pillars 11 and retaining only the support material on the surface of the sacrificial layer, thus forming a reference support layer 200 on the surface of the sacrificial layer. In this embodiment, the structure after step S330 is as follows... Figure 10 As shown.

[0143] Step S340: Etch the reference support layer along the second direction to form a third trench between two adjacent sets of support pillars, and retain the reference support layer between the support pillars distributed along the second direction to form a second extension.

[0144] Multiple third grooves 14 can be formed within the reference support layer 200. The third grooves 14 can extend along the second direction B, and the multiple third grooves 14 can be arranged at intervals along the first direction A. The sets of support columns 11 distributed along the first direction A can be arranged alternately with each third groove 14 along the first direction A. The depth of the third groove 14 can be the same as the thickness of the reference support layer 200, that is, the third groove 14 can penetrate the reference support layer 200 in the thickness direction.

[0145] In one exemplary embodiment of this disclosure, a photoresist layer can be formed on the surface of the reference support layer 200 by spin coating or other methods. The material of the photoresist layer can be positive or negative photoresist, without particular limitation. A photomask can be used to expose the photoresist layer, and the pattern of the photomask can match the required pattern of the third trench 14. Subsequently, the exposed photoresist layer can be developed to form multiple development areas, each of which exposes the reference support layer 200. The pattern of the development area can be the same as the required pattern of the third trench 14, and the width of the development area can be the same as the required size of the third trench 14. The reference support layer 200 can be etched in the development areas to form each third trench 14 exposing the sacrificial layer. In this embodiment of the disclosure, the structure after step S340 is as follows: Figure 11 As shown.

[0146] It should be noted that during the formation of the third trench 14, the reference support layer 200 covered by the photoresist layer can be retained. This portion of the reference support layer 200 is located between the support pillars 11 distributed along the second direction B, and the reference support layer 200 retained in this etching can be defined as the second extension 22. After the formation of the third trench 14, the photoresist layer can be removed by ashing or other processes, thereby exposing the second extension 22 formed by etching.

[0147] Step S350: Fill the third trench with the insulating material.

[0148] The insulating material 5 can be filled in the third trench 14 using processes such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the insulating material 5 can also be filled in the third trench 14 by other means. No special limitation is made on the filling method of the insulating material 5 here.

[0149] In one embodiment, the insulating material 5 may fill the third trench 14 such that the insulating material 5 in the third trench 14 is flush with the surface of the second extension 22 and each support post 11. The insulating material 5 filling the third trench 14 may be the same as the insulating material 5 filling the first trench 12 and the second trench 13, for example, its material may be silicon oxide.

[0150] It should be noted that, for ease of process, insulating material 5 can be deposited simultaneously on the surface of the support column 11. Filling can be stopped after the insulating material 5 in the third trench 14 has filled the gaps between the support columns 11. Subsequently, a chemical polishing process can be used to polish the insulating material 5 deposited on the surface of the support column 11, thereby removing the insulating material 5 on the surface of the support column 11, leaving only the insulating material 5 in the third trench 14. In this embodiment, the structure after step S350 is as follows... Figure 12 As shown.

[0151] Step S360: Etch the insulating material in the third trench along the first direction to remove the insulating material located between adjacent support pillars.

[0152] The insulating material 5 between the support columns 11 distributed along the first direction A can be removed by etching process to form a fourth trench 15. The fourth trench 15 may include a plurality of spaced isolation grooves 1501. In the first direction A, each isolation groove 1501 may be adjacent to each support column 11 and arranged alternately.

[0153] For example, a photoresist layer can be formed on the surface of the structure jointly formed by the insulating material 5 and the support pillars 11 by spin coating or other methods. The material of the photoresist layer can be positive or negative photoresist, without special limitation. The shape of the surface of the photoresist layer away from the substrate 1 can be the same as the shape of the surface of the substrate 1. The photoresist layer can be exposed using a mask, the pattern of which can match the required pattern of each fourth trench 15. Subsequently, the exposed photoresist layer can be developed to form a developing area, which exposes the insulating material 5 between the support pillars 11 distributed along the first direction A, and the pattern of the developing area can be the same as the required pattern of the fourth trench 15, and the size of the developing area can be the same as the required size of the fourth trench 15. The insulating material 5 can be selectively etched in the developing area to form the fourth trench 15, which exposes the sacrificial layer after etch-back.

[0154] It should be noted that after forming the fourth trench 15, the photoresist layer can be removed by ashing or other processes. In this embodiment, the structure after completing step S360 is as follows: Figure 13 As shown.

[0155] Step S370: Fill the gaps between the support columns distributed along the first direction with support material to form a first extension.

[0156] Support material can be filled into the fourth trench 15 to form the first extension 21. For example, the support material can be filled into the fourth trench 15 by processes such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, other methods can also be used to fill the fourth trench 15 with support material. No special limitation is made here on the filling method of the support material.

[0157] In one embodiment, the support material may fill the fourth trench 15 such that the support material in the fourth trench 15 is flush with the surfaces of the second extension 22 and each support post 11. The support material filling the fourth trench 15 may be the same as the material of the second extension 22, for example, it may be silicon nitride.

[0158] It should be noted that, for process convenience, support material can be deposited simultaneously on the surfaces of the insulating material 5 filled in the support column 11, the first extension 21, and the third groove 14. Deposition can be stopped after the support material in the fourth groove 15 fills the gaps between the support columns 11. Subsequently, a chemical polishing process can be used to polish the support material deposited on the surfaces of the insulating material 5 filled in the support column 11, the first extension 21, and the third groove 14, thereby removing the support material on the surfaces of the insulating material 5 filled in the support column 11, the first extension 21, and the third groove 14, leaving only the support material in the fourth groove 15, so as to form the first extension 21 in the fourth groove 15. In this embodiment of the present disclosure, the structure after completing step S370 is as follows: Figure 14 As shown.

[0159] like Figure 1 As shown, in step S140, an epitaxial growth process is used to form epitaxial pillars on the top of each of the support pillars.

[0160] Monocrystalline silicon can be epitaxially grown on the top of each support pillar 11 using an epitaxial growth process. During this process, due to limitations imposed by the insulating material 5 and the support material, a monocrystalline silicon film layer will not form on the surface of the insulating material 5 and the support material; it will only form on the top of the support pillar 11. In this process, the height of the pillars can be increased through the epitaxial growth process, thereby increasing the height of the capacitor structure formed on its surface and thus increasing the capacitor's storage capacity. Furthermore, the etching process can be avoided, preventing insufficient etching and improving product yield. In this embodiment, the structure after step S140 is as follows... Figure 15 and Figure 16 As shown.

[0161] In one exemplary embodiment of this disclosure, the ratio of the height of the extension post 3 to the height of the support post 11 can be one-third to five-thirds. For example, the height of the extension post 3 can be the same as the height of the support post 11, or the height of the extension post 3 can be one-third, two-thirds, four-thirds, or five-thirds of the height of the support post 11. Of course, the extension post 3 can also have other heights, which will not be listed here.

[0162] like Figure 1 As shown, in step S150, a capacitor structure is formed on the surface of the structure jointly formed by each of the extended pillars and each of the support pillars.

[0163] A capacitor structure 4 can be formed on the sidewall of the structure jointly formed by each epitaxial pillar 3 and each support pillar 11, conforming to the sidewall surface of each epitaxial pillar 3 and each support pillar 11. The orthogonal projection of the capacitor structure 4 on the first doped region 101 can at least partially overlap with the conductive contact plug in the first doped region 101, thereby ensuring that the capacitor structure 4 can be in contact with the conductive contact plug so that the charge collected by the capacitor structure 4 can be stored through the conductive contact plug.

[0164] For example, the capacitor structure 4 can be formed on the sidewalls of the structure jointly formed by each epitaxial pillar 3 and each support pillar 11 using methods such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other processes can also be used to form the capacitor structure 4; no specific limitations are placed on the formation process of the capacitor structure 4 here. In this embodiment, the structure after step S150 is as follows: Figure 17 As shown.

[0165] In one exemplary embodiment of this disclosure, the method of forming this disclosure may further include:

[0166] Step S160: Before forming a capacitor structure on the surface of the structure jointly formed by each of the epitaxial pillars and each of the support pillars, the sacrificial layer and the insulating material located in the second doped region are removed.

[0167] Before forming the capacitor structure 4, the sacrificial layer and insulating material 5 filled between each support post 11 can be removed, thereby exposing the sidewalls of each support post 11. This allows the capacitor structure 4 to be formed simultaneously on the sidewalls of each extension post 3 and each support post 11, which helps to increase the height of the capacitor structure 4 and improve the storage capacity.

[0168] It should be noted that, in the above process, the sacrificial layer located in the first doped region 101 can be retained. Since the size of the sacrificial layer in the second trench 13 of the first doped region 101 in the first direction A is larger than the distance between two adjacent support pillars 11, the contact between the substrate 1 and the support pillars 11 can be reduced by the sacrificial layer. In addition, the depletion region of the pn junction formed by the first doped region 101 and the second doped region 102 can be used to reduce leakage current.

[0169] For example, the sacrificial layer and insulating material 5 can be removed by a wet etching process. For instance, an acidic solution can be used for wet etching, such as hydrofluoric acid, specifically buffered hydrofluoric acid (BHF), 49% hydrofluoric acid, or dilute hydrofluoric acid (DHF). When DHF is used as the etching solution, the ratio of hydrofluoric acid to deionized water can be 1:1 to 1:10. No specific limitations are placed on the ratio or concentration of the etching solution. In this embodiment, the structure after step S160 is as follows: Figure 18 and Figure 19 As shown.

[0170] In one exemplary embodiment of this disclosure, the capacitor structure 4 may include a lower electrode layer 41, a capacitor dielectric layer 42, and an upper electrode layer 43. After removing the sacrificial layer and insulating material 5 located in the second doped region 102, the capacitor structure 4 is formed on the surface of the structure jointly formed by each epitaxial pillar 3 and each support pillar 11. That is, step S150 may include steps S1501-S1503. Figure 20 A flowchart of step S150 in an embodiment of this disclosure is shown, see [link to flowchart]. Figure 20 As shown, where:

[0171] Step S1501: A conformally attached lower electrode layer is formed on the surface of the structure jointly formed by the epitaxial pillar and the support pillar, and the end of the lower electrode layer near the first doped region is in contact with the conductive contact plug.

[0172] A lower electrode layer 41 can be formed on the sidewalls of the epitaxial pillar 3 and the support pillar 11. Specifically, a lower electrode layer 41 conformally fitted to the sidewall surfaces of the epitaxial pillar 3 and the support pillar 11 can be formed on the sidewalls of the epitaxial pillar 3 and the support pillar 11. For ease of fabrication, the lower electrode layer 41 can be formed simultaneously on the sidewalls of the epitaxial pillar 3 and the support pillar 11 and on the top surface of the epitaxial pillar 3. Subsequently, the lower electrode layer 41 located on the top surface of the epitaxial pillar 3 can be removed, leaving only the lower electrode layer 41 on the sidewalls of the epitaxial pillar 3 and the support pillar 11. Furthermore, the lower electrode layer 41 can be connected to a conductive contact plug to input the stored charge in the lower electrode layer 41 to the conductive contact plug, thereby achieving capacitance storage. In this embodiment, the structure after step S1501 is as follows: Figure 21 and Figure 22 As shown.

[0173] For example, the lower electrode layer 41 can be formed on the sidewalls of the epitaxial pillar 3 and the support pillar 11 by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the lower electrode layer 41 can also be formed by other processes. The material of the lower electrode layer 41 can be rubidium, rubidium oxide, titanium, titanium nitride or tungsten, etc. Of course, it can also be other materials that can be used as electrodes. No special limitation is made on the material and formation process of the lower electrode layer 41 here.

[0174] Step S1502: A capacitor dielectric layer is formed on the surface of the lower electrode layer.

[0175] A conformally attached capacitor dielectric layer 42 can be formed on the surface of the lower electrode layer 41. For example, the capacitor dielectric layer 42 can be a thin film formed on the surface of the lower electrode layer 41. The capacitor dielectric layer 42 can be formed by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the capacitor dielectric layer 42 can also be formed by other methods, which will not be listed here.

[0176] The capacitor dielectric layer 42 can be a single-layer film structure made of the same material, or a hybrid film structure made of different materials. For example, it can include materials with a high dielectric constant, such as strontium titanate, aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, silicon nitride, or mixtures thereof. Of course, it can also be other materials, which will not be listed here.

[0177] Step S1503: An upper electrode layer is formed on the surface of the lower electrode layer.

[0178] The material of the upper electrode layer 43 can be a conductive material. For example, it can be rubidium, rubidium oxide, titanium, titanium nitride or tungsten, etc. Of course, it can also be other materials that can be used as electrodes. No special limitation is made on the material of the upper electrode layer 43 here.

[0179] The upper electrode layer 43 can be formed on the surface of the capacitor dielectric layer 42 by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the upper electrode layer 43 can also be formed by other processes, which are not specifically limited here.

[0180] For ease of manufacturing, the upper electrode layer 43 can fill the gaps between the support pillars 11 and the gaps between the epitaxial pillars 3. Since the capacitor dielectric layer 42 is conformally attached to the surface of the lower electrode layer 41, and the lower electrode layer 41 is conformally attached to the surfaces of the epitaxial pillars 3 and the support pillars 11, the upper electrode layer 43 can fill the gaps between the capacitor dielectric layers 42. In this disclosure, the upper electrode layer 43, the capacitor dielectric layer 42, and the lower electrode layer 41 together constitute the capacitor structure 4 of this disclosure.

[0181] In one exemplary embodiment of this disclosure, the method of forming this disclosure may further include:

[0182] Step S170: Etch back the capacitor structure to form a channel.

[0183] In one embodiment, a wet etching process can be used to etch back the capacitor structure 4, thereby making the surface of the capacitor structure 4 lower than the top surface of the epitaxial pillar 3. For example, an acidic solution can be used for wet etching, such as hydrofluoric acid, for example, buffered hydrofluoric acid (BHF), 49% hydrofluoric acid, or dilute hydrofluoric acid (DHF). When DHF is used as the etching solution, the ratio of hydrofluoric acid to deionized water can be 1:1 to 1:10. No specific limitations are placed on the ratio and concentration of the etching solution. Of course, a dry etching process can also be used to etch back the surface of the capacitor structure 4, as long as the surface of the capacitor structure 4 is lower than the surface of the support pillar 11 by a second preset height. No specific limitations are placed on the specific process of the back etching.

[0184] In one exemplary embodiment of this disclosure, the second preset height can be 60nm to 150nm. For example, it can be 60nm, 80nm, 100nm, 1200nm, 140nm, or 150nm. Of course, other heights are also possible, which will not be listed here. In this embodiment of the disclosure, the structure after completing step S170 is as follows: Figure 23-24 As shown.

[0185] Step S180: A protective layer is formed in the channel, and the protective layer fills the channel.

[0186] The protective layer 6 can be made of an insulating material 5, for example, silicon oxide. The insulating material 5 in the protective layer 6 can isolate the capacitor structure 4 from other structures formed subsequently, preventing coupling or short circuits. Furthermore, during the subsequent etching process to form other structures, the protective layer 6 can protect the surface of the capacitor structure 4, preventing damage and improving product yield. For example, word line structures and transistors can be formed in the protective layer 6. During this process, the protective layer 6 can isolate the word line structures and transistors from the capacitor structure 4, preventing coupling or short circuits between the transistors and the capacitor structure 4.

[0187] In one embodiment, insulating material 5 can be deposited on the surface of capacitor structure 4 using processes such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition to form a protective layer 6 covering capacitor structure 4, which can fill the channel.

[0188] The protective layer 6 can fill the gaps between the tops of each epitaxial pillar 3. For ease of processing, insulating material 5 can be deposited simultaneously on the surface of the epitaxial pillar 3. Filling can be stopped after the insulating material 5 on the surface of the capacitor structure 4 has filled the gaps between each epitaxial pillar 3. Subsequently, a chemical polishing process can be used to polish the insulating material 5 deposited on the surface of the epitaxial pillar 3, thereby removing the insulating material 5 on the surface of the epitaxial pillar 3, leaving only the insulating material 5 on the surface of the capacitor structure 4, thus forming the protective layer 6 on the surface of the capacitor structure 4. In this embodiment, the structure after step S180 is as follows: Figure 24 As shown.

[0189] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0190] This disclosure also provides a semiconductor structure, which may include a capacitor structure 4 and a transistor, wherein the transistor may be formed on the capacitor structure 4, such as... Figure 23 As shown, the semiconductor structure may include a substrate 1, a support layer 2, multiple epitaxial pillars 3, and a capacitor structure 4, wherein:

[0191] The substrate 1 includes multiple sets of support pillars 11 spaced apart along a first direction A, and each set of support pillars 11 spaced apart along a second direction B, wherein the first direction A and the second direction B intersect.

[0192] Support layer 2 fills the top gap between adjacent support columns 11;

[0193] Multiple extension columns 3 are formed one-to-one on the top of each support column 11;

[0194] The capacitor structure 4 is formed on the surface of the structure jointly formed by each of the extension pillars 3 and each of the support pillars 11.

[0195] The semiconductor structure disclosed herein allows for the growth of epitaxial pillars 3 on support pillars 11 via an epitaxial growth process, followed by the formation of a capacitor structure 4 on the surface of the structure jointly formed by the support pillars 11 and the epitaxial pillars 3. In this process, on the one hand, the height of the initially etched support pillars 11 can be appropriately reduced to avoid insufficient etching, preventing the subsequently formed capacitor structure 4 from becoming suspended. On the other hand, the lower height of the support pillars 11 prevents them from collapsing, thereby preventing the capacitor structure 4 formed on them from collapsing; simultaneously, the capacitor structure 4 can be supported by the support layer 2, further preventing collapse and improving product yield. Furthermore, by forming epitaxial pillars 3 on the support pillars 11, the pillar height can be increased, thereby increasing the height of the capacitor structure 4 formed on its surface, thus increasing the capacitor's storage capacity.

[0196] The specific details of the semiconductor structure according to the embodiments of this disclosure are described in detail below:

[0197] like Figure 2 As shown, substrate 1 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular in shape, and its material can be silicon or other semiconductor materials. No special restrictions are made on the shape and material of substrate 1 here.

[0198] The substrate 1 may include a base and an insulating layer formed on the base. Multiple conductive contact plugs are formed within the insulating layer, which separates the conductive contact plugs to prevent coupling or parasitic capacitance between them. The conductive contact plugs may be made of conductive or semiconductor materials, such as tungsten, copper, or polycrystalline silicon.

[0199] For example, the insulating layer may have multiple vias arranged in an array, each of which may be a through hole. Conductive contact plugs may be formed within the vias. For example, conductive contact plugs may be formed within the vias by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods may also be used to form conductive contact plugs, which will not be listed here.

[0200] This disclosure may include multiple groups of conductive contact plugs spaced apart along a first direction A. For example, the conductive contact plugs in each group may be equally spaced along the first direction A; multiple groups of conductive contact plugs may be spaced apart along a second direction B. For example, each group of conductive contact plugs may be equally spaced along the second direction B. The first direction A and the second direction B may be perpendicular to each other. That is, the conductive contact plugs may be arranged in an array in rows and columns.

[0201] It should be noted that perpendicularity can be absolute or approximate. Deviations are inevitable during manufacturing. In this disclosure, angular deviations may occur due to manufacturing limitations, resulting in a slight difference in the angle between the first direction A and the second direction B. As long as the angular deviation between the first direction A and the second direction B is within a preset range, the first direction A and the second direction B can be considered perpendicular. For example, the preset range can be 10°, meaning that the angle between the first direction A and the second direction B can be considered perpendicular when it is greater than or equal to 80° and less than or equal to 100°.

[0202] In one embodiment, a shallow trench isolation structure and a bit line structure may be provided in the substrate 1. The shallow trench isolation structure can divide the substrate 1 into multiple active regions. The bit line structure and the conductive contact plug are both located on the top of the active regions and are arranged alternately with the conductive contact plug in the substrate 1.

[0203] In one exemplary embodiment of this disclosure, the substrate 1 may include a first doped region 101 and a second doped region 102, which may be distributed adjacently and stacked along the thickness direction. The substrate 1 may be p-type doped using ion implantation. For example, p-type doping material may be doped into the first doped region 101 to form a p-type semiconductor in the first doped region 101. The p-type doping material may be an element located in Group III of the periodic table; for example, it may be boron, but it may also be other elements, which will not be listed here.

[0204] In one exemplary embodiment of this disclosure, each conductive contact plug may be located in the first doped region 101, and each conductive contact plug may be distributed in an array in the doped region.

[0205] The substrate 1 can be n-type doped using ion implantation to form a pn junction. For example, an n-type dopant material can be doped into the second doped region 102 to form an n-type semiconductor in the second doped region 102. The p-type semiconductor in the first doped region 101 and the n-type semiconductor in the second doped region 102 can form a pn junction. The n-type dopant material can be an element located in Group IV of the periodic table. For example, it can be phosphorus. Of course, it can also be materials of other elements, which will not be listed here.

[0206] In this disclosure, multiple sets of support pillars 11 spaced apart along a first direction A can be formed within the substrate 1. For example, the support pillars 11 in each set can be equally spaced along the first direction A; the multiple sets of support pillars 11 can also be spaced apart along a second direction B. For example, each set of support pillars 11 can be equally spaced along the second direction B. The first direction A and the second direction B can be different directions; for example, the first direction A and the second direction B can intersect, or for instance, the first direction A and the second direction B can be perpendicular to each other. That is, the support pillars 11 can be arranged in an array in rows and columns.

[0207] The material of the support pillar 11 can be the same as that of the substrate 1, for example, it can be single crystal silicon. The height of the support pillar 11 can be 50nm to 100nm, for example, it can be 50nm, 60nm, 70nm, 80nm, 90nm or 100nm, of course, it can also be other heights, which will not be listed here.

[0208] In one exemplary embodiment of this disclosure, the support post 11 may be located in the second doped region 102, and its end near the first doped region 101 may be in contact with the first doped region 101. That is, the support post 11 may be an n-type semiconductor, and a pn junction may be formed between the support post 11 and the first doped region 101, which can reduce leakage current through the depletion region of the pn junction.

[0209] In one exemplary embodiment of this disclosure, such as Figure 4 As shown, a plurality of first trenches 12 can be formed in the substrate 1, each first trench 12 extending along a first direction A, and the plurality of first trenches 12 can be distributed at intervals along a second direction B. In the second direction B, support pillars 11 can be located between two adjacent first trenches 12, and each support pillar 11 can be alternately arranged with each first trench 12. In the thickness direction of the substrate 1, the first trenches 12 can extend into the first doped region 101.

[0210] like Figure 2 As shown, a plurality of second trenches 13 may be formed in the substrate 1. Each second trench 13 may extend along the second direction B, and the plurality of second trenches 13 may be distributed at intervals along the first direction A. In the first direction A, support pillars 11 are located between two adjacent second trenches 13, and each support pillar 11 may be arranged alternately with each second trench 13. In the thickness direction of the substrate 1, the second trenches 13 may extend into the first doped region 101. The portion of the second trenches 13 extending into the first doped region 101 has a dimension in the first direction A that is greater than the spacing between two adjacent support pillars 11.

[0211] Insulating material 5 can be formed in both the first trench 12 and the second trench 13. The insulating material 5 can be silicon oxide. Since the size of the insulating material 5 in the second trench 13 of the first doped region 101 in the first direction A is larger than the distance between two adjacent support pillars 11, the contact between the substrate 1 and the support pillars 11 can be reduced by the insulating material 5. In addition, the depletion region of the pn junction formed by the first doped region 101 and the second doped region 102 can be combined to reduce leakage current.

[0212] like Figure 6 As shown, the support layer 2 can fill the top gaps between adjacent support columns 11, providing lateral support for the support columns 11 and preventing them from collapsing. In an exemplary embodiment of this disclosure, the support layer 2 may include a first extension 21 and a second extension 22. The first extension 21 and the second extension 22 can fill the ends of the support columns 11 that are away from the first doped region 101. For example, the first extension 21 can fill the top gaps between each support column 11 distributed along the first direction A, providing lateral support for each support column 11 distributed along the first direction A and preventing them from collapsing; the second extension 22 can fill the top gaps between each support column 11 distributed along the second direction B, providing lateral support for each support column 11 distributed along the second direction B and further preventing them from collapsing.

[0213] In one exemplary embodiment of this disclosure, the thickness of the support layer 2 can be 10nm to 50nm. For example, it can be 10nm, 20nm, 30nm, 40nm or 50nm. Of course, it can also be other thicknesses, which will not be listed here.

[0214] like Figure 15 As shown, epitaxial pillars 3 can be formed one-to-one on the top of each support pillar 11. For example, single-crystal silicon can be epitaxially grown on the top of each support pillar 11 through an epitaxial growth process. During this process, due to the limitations of the insulating material 5 and the support material, a single-crystal silicon film layer will not be formed on the surface of the insulating material 5 and the support material during the epitaxial growth process. Only a single-crystal film layer will be formed on the top of the support pillar 11. In the above process, the height of the pillar can be increased by the epitaxial process, so as to increase the height of the capacitor structure 4 formed on its surface, thereby increasing the capacitor storage capacity. In addition, the etching process can be avoided, which can avoid the problem of insufficient etching and improve the product yield.

[0215] In one exemplary embodiment of this disclosure, the ratio of the height of the extension post 3 to the height of the support post 11 can be one-third to five-thirds. For example, the height of the extension post 3 can be the same as the height of the support post 11, or the height of the extension post 3 can be one-third, two-thirds, four-thirds, or five-thirds of the height of the support post 11. Of course, the extension post 3 can also have other heights, which will not be listed here.

[0216] like Figure 17 As shown, the capacitor structure 4 can conformally fit onto the sidewall surface of each epitaxial pillar 3 and each support pillar 11. The orthographic projection of the capacitor structure 4 in the first doped region 101 can at least partially overlap with the conductive contact plug in the first doped region 101, thereby ensuring that the capacitor structure 4 can contact and connect with the conductive contact plug so as to store the charge collected by the capacitor structure 4 through the conductive contact plug.

[0217] For example, the capacitor structure 4 can be formed on the sidewall of the structure jointly formed by each epitaxial pillar 3 and each support pillar 11 by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the capacitor structure 4 can also be formed by other processes. No special limitation is made on the formation process of the capacitor structure 4 here.

[0218] In one exemplary embodiment of this disclosure, the capacitor structure 4 may include a lower electrode layer 41, a capacitor dielectric layer 42, and an upper electrode layer 43, wherein:

[0219] The lower electrode layer 41 can be conformally attached to the surface of the structure jointly formed by the epitaxial pillar 3 and the support pillar 11. Specifically, the lower electrode layer 41 can be formed on the sidewall of the epitaxial pillar 3 and the support pillar 11, conformally attached to the sidewall surface of the epitaxial pillar 3 and the support pillar 11. The lower electrode layer 41 can be conformally attached to the sidewall surface of the epitaxial pillar 3 and the support pillar 11. It can be a thin film formed on the sidewall surface of the epitaxial pillar 3 and the support pillar 11, or it can be a coating formed on the sidewall surface of the epitaxial pillar 3 and the support pillar 11. The specific form of the lower electrode layer 41 is specifically defined here.

[0220] The end of the lower electrode layer 41 near the first doped region 101 can be connected to a conductive contact plug to input the electrical charge stored in the lower electrode layer 41 to the conductive contact plug, thereby realizing capacitance storage.

[0221] The material of the lower electrode layer 41 can be rubidium, rubidium oxide, titanium, titanium nitride or tungsten, etc. Of course, it can also be other materials that can be used as electrodes. No special limitation is made on the material of the lower electrode layer 41 here.

[0222] For example, the lower electrode layer 41 can be formed on the sidewalls of the epitaxial pillar 3 and the support pillar 11 by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the lower electrode layer 41 can also be formed by other processes. The material of the lower electrode layer 41 can be rubidium, rubidium oxide, titanium, titanium nitride or tungsten, etc. Of course, it can also be other materials that can be used as electrodes. No special limitation is made on the material and formation process of the lower electrode layer 41 here.

[0223] The capacitor dielectric layer 42 can be attached to the surface of the lower electrode layer 41 in a conformal manner. It can be a thin film formed on the surface of the lower electrode layer 41 or a coating formed on the surface of the lower electrode layer 41. The specific form of the capacitor dielectric layer 42 is specifically defined here.

[0224] For example, the capacitor dielectric layer 42 can be a thin film formed on the surface of the lower electrode layer 41. The capacitor dielectric layer 42 can be formed by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the capacitor dielectric layer 42 can also be formed by other methods, which will not be listed here.

[0225] The capacitor dielectric layer 42 can be a single-layer film structure made of the same material, or a hybrid film structure made of different materials. For example, it can include materials with a high dielectric constant, such as strontium titanate, aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, silicon nitride, or mixtures thereof. Of course, it can also be other materials, which will not be listed here.

[0226] The upper electrode layer 43 may be formed on the surface of the lower electrode layer 41. The material of the upper electrode layer 43 may be a conductive material, for example, it may be rubidium, rubidium oxide, titanium, titanium nitride or tungsten, etc. Of course, it may also be other materials that can be used as electrodes. No special limitation is made on the material of the upper electrode layer 43 here.

[0227] The upper electrode layer 43 can be formed on the surface of the capacitor dielectric layer 42 by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the upper electrode layer 43 can also be formed by other processes, which are not specifically limited here.

[0228] The upper electrode layer 43 can fill the gaps between the support pillars 11 and the gaps between the epitaxial pillars 3. Since the capacitor dielectric layer 42 is conformally attached to the surface of the lower electrode layer 41, and the lower electrode layer 41 is conformally attached to the surfaces of the epitaxial pillars 3 and the support pillars 11, the upper electrode layer 43 can fill the gaps between the capacitor dielectric layers 42. In this disclosure, the upper electrode layer 43, the capacitor dielectric layer 42, and the lower electrode layer 41 together constitute the capacitor structure 4 of this disclosure.

[0229] In one exemplary embodiment of this disclosure, the capacitor structure 4 can be etched back so that the end of the capacitor structure 4 facing away from the support layer 2 is lower than the top of the epitaxial pillar 3. In one embodiment, a wet etching process can be used to etch back the capacitor structure 4, thereby making the surface of the capacitor structure 4 lower than the top surface of the epitaxial pillar 3. For example, an acidic solution can be used for wet etching, such as hydrofluoric acid, for example, buffered hydrofluoric acid (BHF), 49% hydrofluoric acid, or dilute hydrofluoric acid (DHF). When DHF is used as the etching solution, the ratio of hydrofluoric acid to deionized water can be 1:1 to 1:10. The ratio and concentration of the etching solution are not specifically limited here. Of course, a dry etching process can also be used to etch back the surface of the capacitor structure 4, as long as the surface of the capacitor structure 4 is lower than the surface of the support pillar 11 by a second preset height. The specific process of the back etching is not specifically limited here.

[0230] In one exemplary embodiment of this disclosure, the second preset height can be 60nm to 150nm. For example, it can be 60nm, 80nm, 100nm, 1200nm, 140nm or 150nm. Of course, it can also be other heights, which will not be listed here.

[0231] The semiconductor structure disclosed herein also includes a protective layer 6, such as Figure 24 As shown, the protective layer 6 can be made of an insulating material 5, for example, silicon oxide. The insulating material 5 in the protective layer 6 can isolate the capacitor structure 4 from other structures formed subsequently, preventing coupling or short circuits. Furthermore, during the subsequent etching process to form other structures, the protective layer 6 can protect the surface of the capacitor structure 4, preventing damage and improving product yield. For example, word line structures and transistors can be formed in the protective layer 6. During this process, the protective layer 6 can isolate the word line structures and transistors from the capacitor structure 4, preventing coupling or short circuits between the transistors and the capacitor structure 4.

[0232] In one embodiment, insulating material 5 can be deposited on the surface of capacitor structure 4 using processes such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form a protective layer 6 covering capacitor structure 4.

[0233] The protective layer 6 can fill the gap between the tops of each epitaxial pillar 3. For ease of processing, insulating material 5 can be deposited simultaneously on the surface of the epitaxial pillar 3. The filling can be stopped after the insulating material 5 on the surface of the capacitor structure 4 has filled the gap between each epitaxial pillar 3. Then, a chemical polishing process can be used to polish the insulating material 5 deposited on the surface of the epitaxial pillar 3, thereby removing the insulating material 5 on the surface of the epitaxial pillar 3, leaving only the insulating material 5 on the surface of the capacitor structure 4, so as to form a protective layer 6 on the surface of the capacitor structure 4.

[0234] This disclosure also provides a memory, which may include the semiconductor structure described in any of the above embodiments. The specific details, formation process and beneficial effects of the memory have been described in detail in the corresponding semiconductor structure formation method and semiconductor structure, and will not be repeated here.

[0235] For example, the memory can be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. Of course, it can also be other storage devices, which will not be listed here.

[0236] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; Multiple sets of support pillars are formed in the substrate at intervals along a first direction, and each set of support pillars is at intervals along a second direction, wherein the first direction intersects the second direction; A support layer is formed to fill the top gap between adjacent support columns; Epitaxial pillars are formed on the top of each of the aforementioned support pillars using an epitaxial growth process; A capacitor structure is formed on the surface of the structure jointly formed by the epitaxial pillars and the support pillars; The support layer includes a first extension and a second extension, wherein the first extension fills the top gap of each of the support columns distributed along the first direction, and the second extension fills the top gap of each of the support columns distributed along the second direction. The method involves forming multiple sets of support pillars spaced apart along a first direction within the substrate, each set of support pillars being spaced apart along a second direction, the first direction intersecting the second direction, including: A plurality of first trenches extending along a first direction are formed in the substrate, and each of the first trenches is spaced apart along a second direction. Fill the first trench with insulating material; The substrate and the insulating material are etched along the second direction to form multiple sets of support pillars spaced apart along the second direction within the substrate.

2. The forming method according to claim 1, characterized in that, The substrate includes a first doped region and a second doped region distributed adjacent to each other along the thickness direction, and the formation method further includes: The first doped region is p-type doped; The second doped region is n-type doped, and the support pillar is located in the second doped region and is in contact with and connected to the first doped region.

3. The forming method according to claim 2, characterized in that, The substrate and the insulating material are etched along the second direction to form a plurality of sets of support pillars spaced apart along the second direction within the substrate, including: The substrate and the insulating material are etched along the second direction using a Bosch process to form a plurality of second trenches spaced apart along the first direction. The second trenches extend into the first doped region, and the portion of the trench extending into the first doped region has a dimension in the first direction that is greater than the spacing between two adjacent support pillars.

4. The forming method according to claim 3, characterized in that, Forming the first extension and the second extension includes: The insulating material is filled in the second trench, and the insulating material located in the second trench and the insulating material located in the first trench together constitute a sacrificial layer; The sacrificial layer is etched back so that the surface of the sacrificial layer is lower than the surface of the support post; A reference support layer is formed to cover the sacrificial layer, the reference support layer filling the top gap of each of the support columns; The reference support layer is etched along the second direction to form a third trench between two adjacent sets of support pillars, and the reference support layer between the support pillars distributed along the second direction is retained to form a second extension. The insulating material is filled into the third trench; The insulating material in the third trench is etched along the first direction to remove the insulating material located between adjacent support pillars; The gaps between the support columns distributed along the first direction are filled with support material to form a first extension.

5. The forming method according to claim 4, characterized in that, The forming method further includes: Before forming a capacitor structure on the surface of the structure jointly formed by the epitaxial pillars and the support pillars, the sacrificial layer and the insulating material located in the second doped region are removed.

6. The forming method according to claim 2, characterized in that, The first doped region further includes a plurality of conductive contact plugs arranged in an array. The orthographic projection of the capacitor structure in the first doped region at least partially overlaps with the conductive contact plugs, and the capacitor structure is in contact with the conductive contact plugs.

7. The forming method according to claim 1, characterized in that, The thickness of the support layer is 10nm~50nm.

8. The forming method according to claim 6, characterized in that, The formation of a capacitor structure on the surface of the structure jointly formed by the epitaxial pillars and the support pillars includes: A conformally attached lower electrode layer is formed on the surface of the structure jointly formed by the epitaxial pillar and the support pillar, and the end of the lower electrode layer near the first doped region is in contact with the conductive contact plug. A capacitor dielectric layer is formed on the surface of the lower electrode layer; An upper electrode layer is formed on the surface of the lower electrode layer.

9. The forming method according to claim 8, characterized in that, The upper electrode layer fills the gaps between each of the support pillars and each of the epitaxial pillars, and the forming method further includes: The capacitor structure is etched back to form a channel; A protective layer is formed within the trench, and the protective layer fills the trench.

10. The forming method according to any one of claims 1-9, characterized in that, The ratio of the height of the extension column to the height of the support column is one-third to five-thirds.

11. A semiconductor structure, characterized in that, include: The substrate includes multiple sets of support pillars spaced apart along a first direction, each set of support pillars spaced apart along a second direction, the first direction intersecting the second direction; A support layer is provided to fill the top gap between adjacent support columns; Multiple extension pillars are formed one-to-one on the top of each of the aforementioned support pillars; A capacitor structure is formed on the surface of the structure jointly formed by each of the said epitaxial pillars and each of the said support pillars; The support layer includes a first extension and a second extension, wherein the first extension fills the top gap of each of the support columns distributed along the first direction, and the second extension fills the top gap of each of the support columns distributed along the second direction. The substrate includes a first doped region and a second doped region adjacent to each other along the thickness direction. The first doped region is a P-type doped region, and the second doped region is an N-type doped region. The support pillar is located in the second doped region and is in contact with the first doped region.

12. The semiconductor structure according to claim 11, characterized in that, The substrate has a plurality of first trenches extending along the first direction and spaced apart along the second direction, and a plurality of second trenches extending along the second direction and spaced apart along the first direction. In the first direction, the support post is located between two adjacent second trenches, and in the second direction, the support post is located between two adjacent first trenches. In the thickness direction of the substrate, both the first trench and the second trench extend into the first doped region, and the portion of the second trench extending into the first doped region has a dimension in the first direction that is greater than the spacing between two adjacent support pillars; insulating material is formed in both the first trench located in the first doped region and the second trench located in the first doped region.

13. The semiconductor structure according to claim 11, characterized in that, The first doped region further includes a plurality of conductive contact plugs arranged in an array. The orthographic projection of the capacitor structure in the first doped region at least partially overlaps with the conductive contact plugs, and the capacitor structure is in contact with the conductive contact plugs.

14. The semiconductor structure according to claim 11, characterized in that, The thickness of the support layer is 10nm~50nm.

15. The semiconductor structure according to claim 13, characterized in that, The capacitor structure includes: The lower electrode layer is conformally attached to the surface of the structure formed by the epitaxial pillar and the support pillar, and the end of the lower electrode layer near the first doped region is in contact with the conductive contact plug. A capacitor dielectric layer is formed on the surface of the lower electrode layer; An upper electrode layer is formed on the surface of the lower electrode layer.

16. The semiconductor structure according to claim 15, characterized in that, The upper electrode layer fills the gaps between each of the support pillars and each of the epitaxial pillars, and the end of the capacitor structure facing away from the support layer is lower than the top of the epitaxial pillars. The semiconductor structure further includes: A protective layer covers the surface of the capacitor structure and fills the gaps between the epitaxial pillars.

17. The semiconductor structure according to any one of claims 11-16, characterized in that, The ratio of the height of the extension column to the height of the support column is one-third to five-thirds.

18. A memory, characterized in that, Includes the semiconductor structure described in any one of claims 11-17.

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