Chip structure, chip manufacturing methods and solid-state drives

Abstract

This invention discloses a chip structure, a chip manufacturing method, and a solid-state drive (SSD). The chip structure includes a substrate, a die, and at least one bridging component. The substrate includes a die mounting position and several pins. The die is disposed on the die mounting position and includes several solder pads. The bridging component is disposed on the die. Some solder pads of the die are connected to corresponding pins of the substrate. Each bridging component connects to multiple solder pads of the same signal on the die. This invention reduces the cost of chip iteration and updates.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a chip structure, a chip manufacturing method, and a solid-state drive. Background Technology

[0002] When chips are iterated and updated, they are often upgraded based on the previous generation. The positions of the chip solder pads are generally the same, but there are also differences. This means that the newly introduced chips cannot be sampled on the existing frame or substrate, and the frame or substrate needs to be redesigned, resulting in excessive costs. Summary of the Invention

[0003] This invention provides a chip structure, a chip manufacturing method, and a solid-state drive, aiming to reduce the cost of chip iteration and updates.

[0004] To achieve the above objectives, the chip structure proposed in this invention includes:

[0005] The substrate includes die placement areas and several pins;

[0006] A bare die, disposed at the bare die placement position, the bare die including a plurality of solder pads;

[0007] At least one bridging element is disposed on the bare die;

[0008] Some of the solder pads of the die are connected to corresponding pins of the substrate, and at least one of the bridging components connects multiple solder pads of the die with the same signal, and / or at least one of the bridging components connects a pin of the substrate and at least one solder pad of the die, and the signal of the pin and solder pad connected by the same bridging component is the same.

[0009] In some embodiments, the bridging component includes a plurality of spaced conductive portions, each conductive portion being electrically connected to the other, each conductive portion being connected to at least one of a plurality of solder pads to which its bridging component is connected, and the conductive portion being disposed adjacent to the solder pad to which it is connected.

[0010] In some embodiments, the bridging element is a single element that extends along the distribution direction of the solder feet.

[0011] In some embodiments, there are multiple bridging components, and the signals of the solder pads connected to each bridging component are different.

[0012] In some embodiments, the die is bonded to the die placement position, and the bridging member is bonded to the die.

[0013] In some embodiments, the bridging element is a metal sheet.

[0014] In some embodiments, the die is bonded to the die placement position, and the bridging member is bonded to the die.

[0015] The chip manufacturing method proposed in this invention includes:

[0016] The bare die is fixed onto the substrate;

[0017] Bridging and wire bonding are performed so that at least one bridging element is disposed on the bare die, and a portion of the solder pads of the bare die are connected to the corresponding pins of the substrate. At least one bridging element connects multiple solder pads of the bare die with the same signal, and / or at least one bridging element connects a pin of the substrate and at least one solder pad of the bare die, and the signal of the pin and solder pad connected by the same bridging element is the same.

[0018] Perform encapsulation processing.

[0019] In some embodiments, the bridging and wire bonding process includes:

[0020] At least one bridging element is provided on the bare die;

[0021] The solder pads of the bare die are respectively wired to the corresponding pins of the substrate;

[0022] Connect at least one of the bridges to the solder pads of multiple identical signals on the die, and / or connect at least one of the bridges to a pin of the substrate and at least one solder pad of the die;

[0023] In some embodiments, the bridging and wire bonding process includes:

[0024] The solder pads of the bare die are respectively wired to the corresponding pins of the substrate;

[0025] At least one bridging element is provided on the bare die;

[0026] Connect at least one of the bridging components to the solder pads of multiple identical signals on the die, and / or connect at least one of the bridging components to a pin of the substrate and at least one solder pad of the die.

[0027] The present invention proposes a solid-state drive, comprising at least one of the above-described chip structures, or at least one chip manufactured by the above-described chip manufacturing method.

[0028] The technical solution of the chip structure of the present invention provides a bridging component on the die, which connects some of the die's solder pads to the corresponding pins of the substrate. At least one bridging component connects multiple solder pads of the same signal on the die, and / or at least one bridging component connects a pin of the substrate to at least one solder pad on the die. This allows dies with a mismatch between the number of solder pads and the number of pins on the substrate, or dies with a mismatch between the signal distribution order of the solder pads and the signal distribution order of the pins on the substrate, to still use the substrate to package functional chip components. Thus, during chip iteration and updates, new dies can reuse the substrate (lead frame or substrate, etc.) of previous dies without needing to redesign the lead frame or substrate, significantly reducing the cost of chip iteration and updates. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the chip structure in one embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of the chip structure in one embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of the chip structure in one embodiment of the present invention;

[0032] Figure 4 This is a schematic diagram of the chip structure in one embodiment of the present invention;

[0033] Figure 5 This is a schematic diagram of the chip structure in one embodiment of the present invention;

[0034] Figure 6 This is a schematic diagram of the chip structure in one embodiment of the present invention;

[0035] Figure 7 This is a schematic flowchart of a chip manufacturing method according to an embodiment of the present invention;

[0036] Figure 8 This is a schematic flowchart of a chip manufacturing method according to an embodiment of the present invention;

[0037] Figure 9 This is a schematic flowchart of a chip manufacturing method according to an embodiment of the present invention. Detailed Implementation

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0039] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0040] It should also be noted that when a component is described as "fixed to" or "set on" another component, it can be directly on the other component or there may be an intervening component present. When a component is described as "connected to" another component, it can be directly connected to the other component or there may be an intervening component present.

[0041] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0042] This invention proposes a chip structure.

[0043] Reference Figures 1 to 6 The chip structure includes a substrate 10, a die 20, and at least one bridging element 30. The substrate 10 may be a lead frame or a substrate, and includes a plurality of pins 11 and a die mounting position 12. The die 20 is disposed on the die mounting position 12 and may be bonded to the die mounting position 12 by silver paste or insulating adhesive, or by other methods. The die 20 includes a plurality of solder pads 21. The bridging element 30 is disposed on the die 20 and may be disposed on the die 20 by adhesive bonding or other methods. Some of the solder pads 21 of the die 20 are connected to the pins 11 of the substrate 10. Each bridging element 30 connects to multiple solder pads 21 of the die 20 with the same signal, and / or at least one bridging element 30 connects a pin 11 of the substrate 10 and at least one solder pad 21 of the die 20, and the signals of the pins 11 and solder pads 21 connected to the same bridging element 30 are the same.

[0044] The bare die 20 is a chip that has been diced and tested from a wafer but has not yet been packaged. It cannot be directly used in actual circuits. The bare die 20 needs to be packaged before it can be used as a basic component. Therefore, after the bare die 20 is placed on the substrate 10 and all the solder pins 21 of the bare die 20 are connected, it is packaged to obtain a chip component that can be used in the circuit. The bare die mounting position 12 of the substrate 10 provides physical support for the bare die 20. The pins 11 of the substrate 10 and the solder pins 21 of the bare die 20 are connected according to the same signal, and one pin 11 is connected to one solder pin 21 with the same signal. The connection method between the pins 11 and the solder pins 21 can be wire bonding or other connection methods. The chip structure of this embodiment also includes a package shell (not shown in the figure). The bare die 20 is packaged in the package shell, the substrate 10 is basically located in the package shell, and the outer ends of the pins 11 of the substrate 10 are exposed outside the package shell.

[0045] The shape of the bridging component 30 is not specifically limited; it can be rectangular, circular, or other shapes.

[0046] See Figure 1 and Figure 2 In the chip structure of this embodiment, some solder pads 21 of the die 20 are connected to the pins 11 of the substrate 10 via wire bonding. Each bridging component 30 connects multiple solder pads 21 of the die 20 with the same signal. Among the multiple solder pads 21 with the same signal, one solder pad 21 may be connected to the pin 11 with the same signal, while the rest are solder pads 21 that are not connected to the pin 11. This allows the additional solder pads 21 of the die 20 compared to the pins 11 of the substrate 10, i.e., the solder pads 21 that are not connected to the corresponding pins 11, to be connected and made conductive with the pins 11 of the same signal through the bridging interconnection of the bridging component 30. For example, die 20 has 48 solder pins 21, and 45 of these solder pins 21 are connected to the 45 pins 11 of substrate 10. Four signal-connecting solder pins 21 (such as four VCC signal solder pins 21) are connected to a bridge 30. The four signal-connecting solder pins 21 connected to the bridge 30 include three solder pins 21 not connected to pins 11 and one solder pin 21 connected to pins 11. Alternatively, die 20 may have 64 solder pins 21, and 58 of these solder pins 21 are connected to the 58 pins 11 of substrate 10. Pin 11 is connected accordingly. The remaining 6 solder pins 21 are for 3 WE signals and 3 VCCQ signals. The 3 WE signal solder pins 21 are connected to a bridge 30 (denoted as the first bridge), and the 3 VCCQ signal solder pins 21 are connected to another bridge 30 (denoted as the second bridge). The solder pin 21 connected to the WE signal pin 11 is also connected to the first bridge, and the solder pin 21 connected to the VCCQ signal pin 11 is also connected to the second bridge.

[0047] See Figure 3 and Figure 4 In some embodiments, at least one solder pin 21 connected to the bridging member 30 may also be solder pin 21 not connected to the pin 11 of the substrate 10, and the bridging member 30 is connected to the corresponding signal pin 11 of the substrate 10, such that each solder pin 21 of the same signal connected to the bridging member 30 is connected to the same signal pin 11 of the substrate 10. For example, the die 20 has 48 solder pins 21, 45 solder pins 21 of the die 20 are connected to the 45 pins 11 of the substrate 10, and the remaining 3 solder pins 21 of the same signal (such as the 3 solder pins 21 of the VCC signal) are connected to a bridging member 30, and the bridging member 30 is connected to a pin 11 of the substrate 10, the signal of which is the same as the signal of the remaining 3 solder pins 21 (such as the pin 11 of the VCC signal).

[0048] For example, the signal distribution sequence of pins 11 on substrate 10 is CE-1, R / B-1, R / B-3, WP-1, WE-1, VCCQ, VSS, VCC3.3, while the signal distribution sequence of solder pins 21 on the new die 20 is CE-1, R / B-1, R / B-3, WP-1, VCCQ, VSS, VCC3.3, WE-1. Then, the solder pins 21 and pins 11 of signals such as CE-1, R / B-1, R / B-3, WP-1, VCCQ, VSS, and VCC3.3 can be connected by wire bonding in sequence. The solder pin 21 of the WE-1 signal can be connected by wire bonding to the bridging component 30, and the bridging component 30 is connected by wire bonding to the pin 11 of the WE-1 signal. In this way, the die 20, whose signal distribution sequence of solder pins 21 does not match the signal distribution sequence of pins 11 on substrate 10, can still use substrate 10 to package a functional chip component.

[0049] See Figures 1-4 In some embodiments, a first bridging component may wire-connect multiple solder pins 21 of the same signal on the die 20 (denoted as first signal solder pins). Among the multiple first signal solder pins, one solder pin 21 may be connected to a pin 11 with the same signal, while the rest may be solder pins 21 not connected to pin 11. That is, the first signal solder pins can be connected and made conductive to the pin 11 of the same signal through the bridging interconnection of the first bridging component. A second bridging component may wire-connect at least one solder pin 21 of the die 20 (denoted as second signal solder pins). The second signal solder pins may all be solder pins 21 of the same signal that are not connected to the pin 11 of the substrate 10. Then, it is only necessary to connect the second bridging component to the pin 11 of the signal corresponding to the second signal solder pin to make the second signal solder pin connected by the second bridging component also connected and made conductive to the pin of the signal corresponding to the second signal solder pin.

[0050] For example, die 20 has 64 solder pins 21. 58 solder pins 21 of die 20 are connected to the 58 pins 11 of substrate 10. The remaining 6 solder pins 21 are for 3 VCCQ signals and 3 VSS signals. The solder pins 21 for the 3 VCCQ signals are connected to the first bridging component, and one of the VCCQ solder pins 21 connected to the VCCQ signal pin 11 is also connected to the first bridging component. The solder pins 21 for the 3 VSS signals are connected to the second bridging component, and the second bridging component is connected to one of the VSS signal pins 11. For example, the signal distribution order near the VSS signal pin 11 on substrate 10 is CE-1, R / B-1, R / B-3, WP-1, VCCQ, VSS, VCC3.3, while the signal distribution order of the solder pins 21 of the new die 20 is CE-1, R / B-3, R / B-4, R / B-5, R / B-6, R / B-7, R / B-8, R / B-9, R / B-1, R / B-1, R / B-1, R / B-3, R / B-1, VCCQ, VSS, VCC3.3. Given the signals CE-1, R / B-3, WP-1, VCCQ, VCC3.3, and VSS, the solder pads 21 and pins 11 of these signals can be connected sequentially via wire bonding. The solder pad 21 of the VSS signal can be connected to the second bridging component via wire bonding. The second bridging component is connected to the pin 11 of the VSS signal. In this way, solder pads 21 of the same signal that are not connected to the corresponding pins can be interconnected through the first bridging component and connected to the pin 11 of the same signal to conduct. It also allows the bare die 20, whose signal distribution order of solder pads 21 does not match the signal distribution order of the pins 11 of the substrate 10, to use the substrate 10 through the second bridging component to package a functional chip component.

[0051] In some embodiments, the chip structure may also be: Figure 1 and Figure 2 The connection method of the embodiment and Figure 3 and Figure 4 The combination of connection methods in the embodiments, that is, a portion of the bridging component 30 adopts Figure 1 and Figure 2 The connection method shown is used in another part of the bridging component 30. Figure 3 and Figure 4 The connection method shown.

[0052] The chip structure can select a suitable connection scheme from the above options based on the design and actual needs.

[0053] The technical solution of the chip structure in this embodiment provides a bridging component 30 on the die 20, which connects some of the solder pads 21 of the die 20 to the pins 11 of the substrate 10. At least one bridging component 30 connects multiple solder pads 21 of the die 20 with the same signal, and / or at least one bridging component 30 connects one pin 11 of the substrate 10 and at least one solder pad 21 of the die 20. This allows a die 20 with a number of solder pads 21 that does not match the number of pins 11 of the substrate 10, or a die 20 with a signal distribution order of solder pads 21 that does not match the signal distribution order of pins 11 of the substrate 10, to still use the substrate 10 to package a functional chip component. Thus, when the chip is iterated and updated, the new die 20 can use the same substrate 10 (lead frame or substrate, etc.) as the previous die 20, without having to redesign the lead frame or substrate, which greatly reduces the cost of chip iteration and updates.

[0054] In some embodiments, after some solder pads 21 of the die 20 are wire-connected to the corresponding pins 11 of the substrate 10, solder pads 21 with the same signal that are not wire-connected to the corresponding pins 11 of the substrate 10 can be wire-connected to the bridging member 30. Then the bridging member 30 can be wire-connected to a pin 11, which has the same signal as the solder pad 21 connected to the bridging member 30, thereby enabling signal interconnection between the solder pads 21 with the same signal that are not connected to the pin 11 and the pin 11.

[0055] For example, after some of the solder pins 21 of the bare die 20 are wired to the corresponding pins 11 of the substrate 10, the solder pins 21 that are not wired to the corresponding pins 11 of the substrate 10 are VCC signals. Then the solder pins 21 that are wired to the bridging component 30 are VCC signals. Then the bridging component 30 can be wired to a VCC signal pin 11.

[0056] Reference Figure 5 and Figure 6 In this embodiment, the bridging component 30 includes a plurality of spaced conductive portions 31, each conductive portion 31 being electrically connected, each conductive portion 31 being connected to at least one of the plurality of solder feet 21 to which its bridging component 30 is connected, and the conductive portion 31 being disposed adjacent to the solder foot 21 to which it is connected.

[0057] In some embodiments, multiple conductive portions 31 are provided at intervals and are provided adjacent to solder feet 21 that are not connected to pins 11, so that solder feet 21 that are far apart in the same signal can be easily connected to the bridging member 30.

[0058] Reference Figure 5Taking a bridging component 30 including two conductive parts 31 as an example, after some solder pins 21 of the bare die 20 are wire-connected to the corresponding pins 11 of the substrate 10, the solder pins 21 that are not wire-connected to the corresponding pins 11 of the substrate 10 can be partially wire-connected to one conductive part 31 of the bridging component 30, and the other part can be wire-connected to the other conductive part 31 of the bridging component 30. Then the bridging component 30 can be wire-connected to a solder pin 21 that is wire-connected to the pins 11 of the substrate 10, thereby realizing the signal interconnection between the solder pins 21 and the pins 11 that have the same signal but are not connected to the corresponding pins 11.

[0059] Reference Figure 6 Taking a bridging component 30 including two conductive parts 31 as an example, after some solder pins 21 of the bare die 20 are wire-connected to the corresponding pins 11 of the substrate 10, the solder pins 21 that are not wire-connected to the corresponding pins 11 of the substrate 10 can be wire-connected to one conductive part 31 of the bridging component 30 in part, and wire-connected to the other conductive part 31 of the bridging component 30 in part. Then, one conductive part 31 of the bridging component 30 is wire-connected to one pin 11 of the substrate 10. This pin 11 is the same pin 11 as the solder pin 21 connected to the bridging component 30, so that the signal interconnection between the solder pins 21 and the pin 11 that have the same signal but are not connected to the corresponding pin 11 can be realized.

[0060] Reference Figure 1 In this embodiment, there is one bridging member 30, which extends along the distribution direction of the solder feet 21.

[0061] Thus, the bridging component 30 extends along the distribution direction of the solder feet 21, making it easier to connect the bridging component 30 and the solder feet 21.

[0062] Reference Figure 2 and Figure 4 In this embodiment, there are multiple bridging components 30, and the signals of the solder feet 21 connected to each bridging component 30 are different.

[0063] Reference Figure 2For example, when there are two bridging components 30, after some of the solder pins 21 of the bare die 20 are wired to the corresponding pins 11 of the substrate 10, the solder pins 21 that are not wired to the corresponding pins 11 of the substrate 10 are VCCQ signal and VCC signal respectively. Then, the solder pin 21 representing the VCCQ signal can be wired to one bridging component 30, and the solder pin 21 representing the VCC signal can be wired to another bridging component 30. Then, one bridging component 30 can be wired to one solder pin 21 of the VCCQ signal, and the solder pin 21 of the VCCQ signal can be connected to the corresponding pin 11 of the VCCQ signal. The other bridging component 30 can be wired to one solder pin 21 representing the VCC signal that is wired to the pin 11 of the substrate 10. Thus, the signal interconnection between the solder pins 21 of the VCCQ signal and the solder pins 21 of the VCC signal and the corresponding pins 11 of the signal can be realized.

[0064] Reference Figure 4 For example, when there are two bridging components 30, after some of the solder pins 21 of the bare die 20 are wired to the corresponding pins 11 of the substrate 10, the solder pins 21 that are not wired to the corresponding pins 11 of the substrate 10 are VCCQ signal and VCC signal respectively. Then, the solder pin 21 representing the VCCQ signal can be wired to one bridging component 30, and the solder pin 21 representing the VCC signal can be wired to another bridging component 30. Then, one bridging component 30 can be wired to the pin 11 of one VCCQ signal, and the other bridging component 30 can be wired to the pin 11 of one VCC signal, thereby realizing the signal interconnection between the solder pins 21 of the VCCQ signal and the solder pins 21 of the VCC signal and the corresponding signal pins 11.

[0065] In some embodiments, the bridging element 30 can be a metal sheet, such as an aluminum sheet or a copper sheet; of course, in other embodiments, the bridging element 30 can also be a non-sheet structure, and the bridging element 30 can also be made of other conductive materials.

[0066] In some embodiments, the bare die 20 is bonded to the bare die placement position 12, and the bare die 20 may be bonded to the bare die placement position 12 by silver paste or insulating adhesive, and the bridging component 30 is bonded to the bare die 20.

[0067] This invention also proposes a chip manufacturing method.

[0068] Reference Figure 7 The chip manufacturing method in this embodiment includes:

[0069] Step S10: Fix the bare die onto the substrate;

[0070] Step S20: Perform bridging and wire bonding.

[0071] Step S30: Perform the encapsulation process.

[0072] In some embodiments, in step S10, the bare sheet can be fixed to the substrate by adhesive bonding.

[0073] Referring to the accompanying drawings of the embodiment of the chip structure described above, after bridging and wire bonding in step S20, at least one bridging element 30 is obtained on the die. Some of the solder pads 21 of the die 20 are connected to the pins 11 of the substrate 10. At least one bridging element connects multiple solder pads of the same signal on the die, and / or, at least one bridging element connects a pin of the substrate and at least one solder pad of the die, and the signal of the pin and solder pad connected by the same bridging element is the same.

[0074] Combined with reference Figure 1 and Figure 2 In step S20, the solder pads 21 of the die 20 can be wired to the corresponding pins 11 of the substrate 10. Each bridging component 30 wires to multiple solder pads 21 of the die 20 with the same signal. Among the multiple solder pads 21 with the same signal, one solder pad 21 may be connected to the pin 11 with the same signal, and the rest may be solder pads 21 not connected to the pin 11. This allows the additional solder pads 21 of the die 20 compared to the pins 11 of the substrate 10, i.e., the solder pads 21 that are not connected to the corresponding pins 11, to be connected and made conductive to the pins 11 with the same signal through the bridging interconnection of the bridging component 30. For example, die 20 has 48 solder pins 21, and 45 of these solder pins 21 are connected to the 45 pins 11 of substrate 10. Four signal-connecting solder pins 21 (such as four VCC signal solder pins 21) are connected to a bridge 30. The four signal-connecting solder pins 21 connected to the bridge 30 include three solder pins 21 not connected to pins 11 and one solder pin 21 connected to pins 11. Alternatively, die 20 may have 64 solder pins 21, and 58 of these solder pins 21 are connected to the 58 pins 11 of substrate 10. Pin 11 is connected accordingly. The remaining 6 solder pins 21 are for 3 WE signals and 3 VCCQ signals. The 3 WE signal solder pins 21 are connected to a bridge 30 (denoted as the first bridge), and the 3 VCCQ signal solder pins 21 are connected to another bridge 30 (denoted as the second bridge). The solder pin 21 connected to the WE signal pin 11 is also connected to the first bridge, and the solder pin 21 connected to the VCCQ signal pin 11 is also connected to the second bridge.

[0075] Combined with reference Figure 3 and Figure 4In step S20, at least one solder pad 21 of the same signal not connected to the pin 11 of the substrate 10 (e.g., at least one solder pad 21 of the VCC signal) on the die 20 can be wire-connected to the bridging component 30, and the bridging component 30 can be connected to the corresponding signal pin 11 of the substrate 10. This ensures that each solder pad 21 of the same signal connected to the bridging component 30 is connected to the corresponding signal pin 11 of the substrate 10. For example, the die 20 has 48 solder pads 21, 45 of which are connected to the 45 pins 11 of the substrate 10. The remaining 3 solder pads 21 of the same signal (e.g., 3 solder pads 21 of the VCC signal) are connected to a bridging component 30, and the bridging component 30 is connected to a pin 11 of the substrate 10. The signal of this pin 11 is the same as the signal of the remaining 3 solder pads 21 (e.g., the pin 11 of the VCC signal). For example, the signal distribution sequence of pins 11 on substrate 10 is CE-1, R / B-1, R / B-3, WP-1, WE-1, VCCQ, VSS, VCC3.3, while the signal distribution sequence of solder pins 21 on the new die 20 is CE-1, R / B-1, R / B-3, WP-1, VCCQ, VSS, VCC3.3, WE-1. Then, the solder pins 21 and pins 11 of signals such as CE-1, R / B-1, R / B-3, WP-1, VCCQ, VSS, and VCC3.3 can be connected by wire bonding in sequence. The solder pin 21 of the WE-1 signal can be connected by wire bonding to the bridging component 30, and the bridging component 30 is connected by wire bonding to the pin 11 of the WE-1 signal. In this way, the die 20, whose signal distribution sequence of solder pins 21 does not match the signal distribution sequence of pins 11 on substrate 10, can still use substrate 10 to package a functional chip component.

[0076] In step S20, the above-mentioned Figure 1 and Figure 2 The connection method of the embodiment and Figure 3 and Figure 4 The combination of connection methods in the embodiments, that is, a portion of the bridging component 30 adopts Figure 1 and Figure 2 The connection method shown is used in another part of the bridging component 30. Figure 3 and Figure 4 The connection method shown.

[0077] The bridging and wire bonding process in step S20 can be performed by selecting a suitable connection scheme from the above options based on the chip structure design and actual requirements. Step S20 can result in a structure as described in any embodiment of the chip structure above.

[0078] In step S30, after the signal interconnection between the solder pads 21 on the die 20 and the pins 11 of the substrate 10 is completed, the die 20 is encapsulated in the package housing, the substrate 10 is basically located inside the package housing, and the outer ends of the pins 11 of the substrate 10 are exposed outside the package housing.

[0079] Of course, the chip manufacturing method of this embodiment also includes a pre-processing step to obtain a bare die before step S10, which will not be described in detail here.

[0080] The chip manufacturing method of this embodiment provides a bridging component 30 on the die 20, which connects some of the solder pads 21 of the die 20 to the pins 11 of the substrate 10. At least one bridging component 30 connects multiple solder pads 21 of the die 20 with the same signal, and / or at least one bridging component 30 connects one pin 11 of the substrate 10 and at least one solder pad 21 of the die 20. This allows a die 20 with a number of solder pads 21 that does not match the number of pins 11 of the substrate 10, or a die 20 with a signal distribution order of solder pads 21 that does not match the signal distribution order of pins 11 of the substrate 10, to still use the substrate 10 to package a functional chip component. Thus, when the chip is iterated and updated, the new die 20 can use the same substrate 10 (lead frame or substrate, etc.) as the previous die 20, without having to redesign the lead frame or substrate, which greatly reduces the cost of chip iteration and updates.

[0081] Reference Figure 8 In this embodiment, step S20, which involves bridging and wire bonding, includes:

[0082] Step S21: Provide at least one bridging element on the bare die;

[0083] Step S22: Connect the solder pads of the bare die to the corresponding pins of the substrate by wire bonding.

[0084] Step S23: Connect at least one bridging component to the solder pads of multiple identical signals on the die, and / or connect at least one bridging component to a pin of the substrate and at least one solder pad of the die.

[0085] In some embodiments, in step S21, only one bridging element may be provided on the bare die, or multiple bridging elements may be provided.

[0086] Referring to the accompanying drawings of the embodiment of the chip structure described above, in step S22, after at least one bridging element 30 is provided on the die 20 in step S21, some of the solder pads 21 of the die 20 are wire-connected to the corresponding pins 11 of the substrate 10. For example, if the signal distribution sequence of some pins 11 on the substrate 10 is WP-1, WE-1, VCCQ, VSS, VCC3.3, and the signal distribution sequence of the solder pads 21 of the new die 20 is WP-1, WE-1, VCCQ, VSS, VCC3.3, then the corresponding pins are wire-connected in sequence.

[0087] In step S23, after connecting some of the solder pads 21 of the die 20 to the corresponding pins 11 of the substrate 10 in step S22, at least one bridging component 30 is connected to multiple solder pads 21 of the same signal of the die 20, and / or, at least one bridging component 30 is connected to a pin 11 of the substrate 10 and at least one solder pad 21 of the die 20.

[0088] Combined with reference Figure 1 and Figure 2 For example, the signal distribution sequence of pin 11 on substrate 10 is WP-1, WE-1, VCCQ, VSS, VCC3.3, while the signal distribution sequence of solder pin 21 on the new die 20 is WP-1, WE-1, VCCQ, VSS, VCC3.3, WP-1. Pin 11 is connected to solder pin 21 in sequence, and the solder pin 21 of the extra WP-1 signal is connected to the bridging component 30. Then, the bridging component 30 is wire-connected to the solder pin 21 of another WP-1 signal.

[0089] Combined with reference Figure 3 and Figure 4 For example, the signal distribution sequence of pin 11 on substrate 10 is WP-1, WE-1, VCCQ, VSS, VCC3.3, while the signal distribution sequence of solder pin 21 on the new die 20 is WP-1, WE-1, VSS, VCC3.3, WP-1, VCCQ. Pin 11 and solder pin 21 are connected in sequence. Solder pin 21 of VCCQ signal is connected to bridge 30. Then, bridge 30 is connected to pin 11 of VCCQ signal.

[0090] In step S23, the above can also be... Figure 1 and Figure 2 The connection method of the embodiment and Figure 3 and Figure 4 The combination of connection methods in the embodiments, that is, a portion of the bridging component 30 adopts Figure 1 and Figure 2 The connection method shown is used in another part of the bridging component 30. Figure 3 and Figure 4 The connection method shown.

[0091] See Figure 9 In some embodiments, step S20, which involves bridging and wire bonding, includes:

[0092] Step S24: Connect the solder pads of the bare die to the corresponding pins of the substrate by wire bonding.

[0093] Step S25: Provide at least one bridging element on the bare die;

[0094] Step S26: Connect at least one bridging element to the solder pads of multiple identical signals on the die, and / or connect at least one bridging element to a pin of the substrate and at least one solder pad of the die.

[0095] Referring to the accompanying drawings of the embodiment of the chip structure described above, in step S24, some of the solder pads 21 of the die 20 are wire-connected to the corresponding pins 11 of the substrate 10. For example, if the signal distribution sequence of some pins 11 on the substrate 10 is WP-1, WE-1, VCCQ, VSS, VCC3.3, and the signal distribution sequence of the solder pads 21 of the new die 20 is WP-1, WE-1, VCCQ, VSS, VCC3.3, then the corresponding pins are wire-connected in sequence.

[0096] In some embodiments, in step S25, after connecting some solder pads 21 of the bare die 20 to the corresponding pins 11 of the substrate 10 by wire bonding in step S24, only one bridging member 30 or multiple bridging members 30 may be provided on the bare die 20.

[0097] In step S26, after at least one bridging element 30 is provided on the die 20 in step S25, at least one bridging element 30 is connected to the solder pins 21 of multiple identical signals of the die 20, and / or, at least one bridging element 30 is connected to a pin 11 of the substrate 10 and at least one solder pin 21 of the die 20.

[0098] Combined with reference Figure 1 and Figure 2 For example, the signal distribution sequence of pin 11 on substrate 10 is WP-1, WE-1, VCCQ, VSS, VCC3.3, while the signal distribution sequence of solder pin 21 on the new die 20 is WP-1, WE-1, VCCQ, VSS, VCC3.3, WP-1. Pin 11 is connected to solder pin 21 in sequence, and the solder pin 21 of the extra WP-1 signal is connected to the bridging component 30. Then, the bridging component 30 is wire-connected to the solder pin 21 of another WP-1 signal.

[0099] Combined with reference Figure 3 and Figure 4For example, the signal distribution sequence of pin 11 on substrate 10 is WP-1, WE-1, VCCQ, VSS, VCC3.3, while the signal distribution sequence of solder pin 21 on the new die 20 is WP-1, WE-1, VSS, VCC3.3, WP-1, VCCQ. Pin 11 and solder pin 21 are connected in sequence. Solder pin 21 of VCCQ signal is connected to bridge 30. Then, bridge 30 is connected to pin 11 of VCCQ signal.

[0100] In step S26, the above-mentioned Figure 1 and Figure 2 The connection method of the embodiment and Figure 3 and Figure 4 The combination of connection methods in the embodiments, that is, a portion of the bridging component 30 adopts Figure 1 and Figure 2 The connection method shown is used in another part of the bridging component 30. Figure 3 and Figure 4 The connection method shown.

[0101] The present invention further proposes a solid-state drive, which includes at least one chip structure or a chip manufactured by at least one chip manufacturing method. The specific structure of the chip structure is as described in the above embodiments. Since the solid-state drive adopts all the technical solutions of all the above chip structure embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0102] The above description is only a part or preferred embodiment of the present invention. Neither the text nor the drawings should limit the scope of protection of the present invention. All equivalent structural transformations made using the content of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect applications in other related technical fields, are included within the scope of protection of the present invention.

Claims

1. A chip structure, characterized in that, include: The substrate includes die placement areas and several pins; A bare die, disposed at the bare die placement position, the bare die including a plurality of solder pads; At least one bridging element is disposed on the bare die; A portion of the solder pads of the die are connected to corresponding pins of the substrate; at least one of the bridging components connects multiple solder pads of the die with the same signal, and / or at least one of the bridging components connects a pin of the substrate and at least one solder pad of the die, and the signal of the pin and solder pad connected by the same bridging component is the same. The bridging component includes a plurality of spaced conductive parts, each conductive part being electrically connected to the other, and each conductive part being connected to at least one of the plurality of solder feet to which its bridging component is connected, and the conductive part being disposed adjacent to the solder foot to which it is connected.

2. The chip structure according to claim 1, characterized in that, The bridging element is a single component, which extends along the distribution direction of the solder feet.

3. The chip structure according to claim 1, characterized in that, There are multiple bridging components, and the signals of the solder feet connected to each bridging component are different.

4. The chip structure according to claim 1, characterized in that, The bridging component is a metal sheet.

5. The chip structure according to claim 1, characterized in that, The bare die is bonded to the bare die placement position, and the bridging component is bonded to the bare die.

6. A solid-state drive, characterized in that, It includes at least one chip structure as described in any one of claims 1-5.

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