An intelligent chip detection system and method based on optical communication

Abstract

The present application belongs to the technical field of intelligent chip detection, and particularly relates to an intelligent chip detection system and method based on optical communication. The present application detects the intelligent chip step by step through multi-stage determination, and can also find out whether the front-end signal introduction device is abnormal during the detection process, and can also troubleshoot the faults of the intelligent chip. The timely discovery of faults can facilitate maintenance. Meanwhile, during the load test of the intelligent chip, the last input load signal can be adjusted in time according to the delay timing, so as to avoid the continuous operation of the intelligent chip under the condition of exceeding its own load, provide a safe environment for the detection of the intelligent chip, and avoid the phenomenon of damage to the intelligent chip during the detection process.

Description

Technical Field

[0001] This invention belongs to the field of intelligent chip testing technology, specifically relating to an intelligent chip testing system and method based on optical-optical communication. Background Technology

[0002] With the rapid development of information technology, the application of smart chips is becoming increasingly widespread. They act as the central nervous system of various smart devices. Smart chips generally work together with sensing systems and power transmission systems, complementing each other and leveraging their respective advantages. Generally, a smart chip is equivalent to a microcontroller, responsible for processing the collected sensing signals and converting them into instructions to transmit to the transmission system to achieve the initial desired effect. Therefore, in order to ensure that smart chips can operate normally, it is essential to test them one by one before applying them to specific devices.

[0003] In existing technologies, the testing of smart chips often involves simply running the chip for a certain period of time with the maximum load signal input according to the application requirements of the smart chip, thereby evaluating its quality. While this method can complete the testing, it also causes significant damage to the smart chip. For products that do not meet the load requirements, it may directly lead to their scrapping and make them unrepairable. However, it is easy to find equipment on the market that corresponds to products that do not meet the load requirements, and they can still be used. The situation where products are scrapped directly during testing obviously increases production costs. Based on this, this solution provides a testing method that enables smart chips to be tested in a safe environment. Summary of the Invention

[0004] The purpose of this invention is to provide a smart chip detection system and method based on optical-optical communication, which enables smart chips to be detected in a safe environment and avoids damage to the smart chips during the detection process.

[0005] The specific technical solution adopted by this invention is as follows:

[0006] A method for detecting smart chips based on optical-optical communication, comprising:

[0007] Acquire the detection signal of the smart chip, wherein the detection signal includes an input signal and an output signal, and each input signal corresponds to an output signal;

[0008] The input signal is acquired and input into the smart chip, and it is determined whether the smart chip can output a test signal.

[0009] If not, the smart chip will be directly identified as a level one abnormal chip;

[0010] If so, the test signal is compared with the output signal to obtain the signal deviation.

[0011] The signal deviation is used to determine whether the smart chip is functioning properly.

[0012] If the value of the signal deviation is zero, the smart chip is determined to be in transient normal condition.

[0013] If the value of the signal deviation is not zero, the smart chip is determined to be in a transient state, and the signal deviation is input to the calibration model, the calibration result is output, and it is determined whether the transient state is continuous.

[0014] If the transient abnormality continues, the smart chip is determined to be in a transient normal state, and the input signal is determined to be abnormal.

[0015] If the transient anomaly is intermittent and the value in the calibration result is zero, then the smart chip is determined to be abnormal and the smart chip is marked as a level two abnormal chip.

[0016] Obtain the secondary faulty chip and connect it to the diagnostic equipment to determine the fault type;

[0017] The smart chip that is determined to be transiently normal is calibrated as a transiently normal chip, and the transiently normal chip is input into the load detection model to obtain the test load.

[0018] Obtain the standard load of the smart chip and compare it with the test load;

[0019] If the test load is less than the standard load, the transient normal chip is identified as a level 2 abnormal chip.

[0020] If the test load is greater than or equal to the standard load, the transient normal chip is determined to be a qualified chip.

[0021] In a preferred embodiment, the step of inputting the signal deviation into the calibration model, outputting the calibration result, and determining whether the transient anomaly is continuous includes:

[0022] Obtain the input signal corresponding to the signal deviation and calibrate it as a calibration signal;

[0023] Obtain calibration chips, wherein multiple calibration chips are provided, and all of them are smart chips that are determined to be normal;

[0024] The calibration signal is input into the calibration chip and a temporary signal is output. The temporary signal is compared with the output signal, and the comparison result is calibrated as the calibration deviation.

[0025] Obtain the value of the calibration deviation and compare it with the signal deviation.

[0026] If the calibration deviation and the signal deviation are the same, then the transient anomaly is determined to be continuous.

[0027] If the value of the calibration deviation is different from that of the signal deviation, then the transient abnormality is determined to be intermittent.

[0028] In a preferred embodiment, after determining that the input signal is abnormal, the front-end signal input device corresponding to the input signal is replaced and calibrated as a verification device;

[0029] The input signal of the verification device is input into the transient normal chip, and it is determined whether the test signal is consistent with the output signal.

[0030] If so, the verification device will be replaced with a front-end signal input device;

[0031] If not, continue to replace the front-end signal input device corresponding to the input signal.

[0032] In a preferred embodiment, the step of acquiring the secondary faulty chip, connecting it to a diagnostic device, and determining the fault type includes:

[0033] Obtain a fault dataset, wherein the fault dataset includes interface faults, circuit faults, and pin faults;

[0034] Among them, the troubleshooting priority of interface faults is higher than that of pin faults, and the troubleshooting priority of pin faults is higher than that of circuit faults.

[0035] The secondary abnormal chips are connected to the diagnostic equipment one by one according to the investigation priority from high to low to obtain the fault type of the secondary abnormal chip. There are n fault types, and the value of n is a positive integer.

[0036] In a preferred embodiment, the step of inputting the transient normal chip into the load detection model to obtain the test load includes:

[0037] The load signals are acquired and input one by one into the transient normal chip, which outputs real-time test signals.

[0038] Obtain the output timing of the real-time test signal;

[0039] Obtain the maximum delay timing of the real-time test signal and compare it with the output timing, and stop inputting the load signal when the output timing equals the maximum delay timing;

[0040] Obtain the load semaphore under the maximum delay timing and calibrate it as the test load.

[0041] In a preferred embodiment, the specific process of obtaining the maximum delay timing of the real-time test signal and comparing it with the output timing is as follows:

[0042] If the maximum delay timing is greater than the output timing, then the input of the load signal is increased;

[0043] If the maximum delay timing is equal to the output timing, then the load semaphore in this state is directly calibrated as the test load.

[0044] If the maximum delay timing is less than the output timing, then the input of the load signal is stopped, and the corresponding output timing is marked as the timing to be evaluated.

[0045] All the output time series are input into the trend analysis model to obtain the changing trend value of the output time series;

[0046] The difference between the timing sequence to be evaluated and the maximum delay timing sequence is obtained, and combined with the trend value to calculate and output the load signal adjustment amount;

[0047] Adjust the last input load signal according to the load signal adjustment amount, and summarize all load signals to obtain the test load amount.

[0048] In a preferred embodiment, the load test model further includes a drive capability detection module for detecting the drive capability of the smart chip, the specific process of which is as follows;

[0049] The test load is obtained and input into the transient normal chip to obtain the test fan-out value of the transient normal chip;

[0050] Obtain the rated index and compare it with the test fan-out value;

[0051] If the test fan-out value is greater than or equal to the rated value, the transient normal chip is calibrated as a qualified chip.

[0052] If the tested fan-out value is less than the rated value, the transient normal chip will be calibrated as a level 2 abnormal chip.

[0053] In a preferred embodiment, the step of inputting all the output time series into a trend analysis model to obtain the trend value of the output time series includes:

[0054] Obtain the output timing of all the aforementioned real-time test signals;

[0055] Obtain the standard function from the trend analysis model;

[0056] Input all the output timing data into a standard function to obtain the trend value of the output timing data.

[0057] The present invention also provides a smart chip detection system based on optical-optical communication, applied to the above-mentioned smart chip detection method based on optical-optical communication, comprising:

[0058] The first acquisition module is used to acquire the detection signal of the smart chip, wherein the detection signal includes an input signal and an output signal, and each input signal corresponds to an output signal;

[0059] A primary test module is used to acquire input signals and input them into the smart chip to determine whether the smart chip can output test signals.

[0060] If not, the smart chip will be directly identified as a level one abnormal chip;

[0061] If so, the test signal is compared with the output signal to obtain the signal deviation.

[0062] A secondary testing module is used to determine whether the smart chip is functioning properly based on the signal deviation.

[0063] If the value of the signal deviation is zero, the smart chip is determined to be in transient normal condition.

[0064] If the value of the signal deviation is not zero, the smart chip is determined to be in a transient state, and the signal deviation is input to the calibration model, the calibration result is output, and it is determined whether the transient state is continuous.

[0065] If the transient abnormality continues, the smart chip is determined to be in a transient normal state, and the input signal is determined to be abnormal.

[0066] If the transient anomaly is intermittent and the value in the calibration result is zero, then the smart chip is determined to be abnormal and the smart chip is marked as a level two abnormal chip.

[0067] The second acquisition module is used to acquire the secondary abnormal chip, connect it to the diagnostic equipment, and determine the fault type.

[0068] A load detection module is used to calibrate the smart chip that is determined to be transiently normal as a transiently normal chip, and input the transiently normal chip into the load detection model to obtain the test load.

[0069] A determination module is used to obtain the standard load of the smart chip and compare it with the test load.

[0070] If the test load is less than the standard load, the transient normal chip is identified as a level 2 abnormal chip.

[0071] If the test load is greater than or equal to the standard load, the transient normal chip is determined to be a qualified chip.

[0072] And, a smart chip detection terminal based on optical-optical communication, comprising:

[0073] At least one processor;

[0074] and a memory communicatively connected to the at least one processor;

[0075] The memory stores a computer program that can be executed by the at least one processor, which is then executed by the at least one processor to enable the at least one processor to perform the above-described intelligent chip detection method based on optical-optical communication.

[0076] The technical effects achieved by this invention are as follows:

[0077] This invention uses a multi-level judgment method to detect the smart chip step by step. During the detection process, it can also detect whether the front-end signal input device is abnormal, and it can also troubleshoot the smart chip. Timely detection of faults facilitates repair. At the same time, when the smart chip is subjected to load testing, the last input load signal can be adjusted in time according to the delay sequence to prevent the smart chip from running continuously beyond its own load. This provides a safe environment for the detection of the smart chip and avoids the phenomenon of damage to the smart chip during the detection process. Attached Figure Description

[0078] Figure 1 This is a flowchart of the method provided by the present invention;

[0079] Figure 2 This is a system module diagram provided by the present invention. Detailed Implementation

[0080] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0081] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0082] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in a preferred embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that mutually excludes other embodiments.

[0083] Please see Figure 1 and Figure 2 As shown, this invention provides a smart chip detection method based on optical-optical communication, comprising:

[0084] S1. Obtain the detection signal of the smart chip, wherein the detection signal includes an input signal and an output signal, and each input signal corresponds to an output signal;

[0085] S2. Acquire the input signal and input it into the smart chip to determine whether the smart chip can output a test signal;

[0086] If not, the smart chip will be directly labeled as a level one abnormal chip;

[0087] If so, the test signal is compared with the output signal to obtain the signal deviation.

[0088] S3. Determine whether the smart chip is functioning properly based on the signal deviation.

[0089] If the signal deviation is zero, the smart chip is considered to be in transient normal condition.

[0090] If the signal deviation value is not zero, the smart chip is determined to be in a transient abnormality. The signal deviation is then input into the calibration model, the calibration result is output, and it is determined whether the transient abnormality is continuous.

[0091] S4. If the transient abnormality continues, the smart chip is determined to be in a normal transient state, and the input signal is determined to be abnormal.

[0092] S5. If the transient anomaly is intermittent and the value in the calibration result is zero, the smart chip is determined to be abnormal and the smart chip is marked as a level 2 abnormal chip.

[0093] S6. Obtain the secondary fault chip and connect it to the diagnostic equipment to determine the fault type;

[0094] S7. The smart chip that is determined to be transiently normal is calibrated as a transiently normal chip, and the transiently normal chip is input into the load detection model to obtain the test load.

[0095] S8. Obtain the standard load of the smart chip and compare it with the test load;

[0096] If the test load is less than the standard load, the chip that is in transient normal condition will be identified as a level 2 abnormal chip.

[0097] If the test load is greater than or equal to the standard load, the chip that is in transient normal condition is judged as a qualified chip.

[0098] As described in steps S1-S8 above, the intelligent chip generally works in conjunction with the sensing system and the power transmission system, complementing each other and leveraging their respective advantages. Generally, the intelligent chip is equivalent to a microcontroller, responsible for processing the collected sensing signals and converting them into instructions to transmit to the transmission system to achieve the initial desired effect. Therefore, the intelligent chip plays a central role. To ensure the normal operation of the intelligent chip, it is essential to perform individual tests before applying it to specific devices. The testing process mainly includes load testing and signal transmission testing. Only when both are qualified can the intelligent chip be determined as a qualified chip. In this embodiment, the intelligent chip is first tested one by one using preset input and output signals. For intelligent chips that cannot output test signals, they are directly determined as level one abnormal chips, specifically determined by the signal deviation. Only when the value is zero can the smart chip be determined to be transiently normal. If there is a signal deviation and its value is not zero, the smart chip is determined to be transiently abnormal. For a smart chip with transient abnormality, there are two situations: abnormal input signal and abnormal smart chip itself. This implementation method is based on the calibration model to determine whether the transient abnormality is continuous. A smart chip with continuous transient abnormality is a transiently normal chip. Of course, if the transient abnormality is intermittent and the calibration result is zero, the transient abnormal smart chip is determined to be a secondary abnormal chip. For secondary abnormal chips, the fault type can be determined by connecting to diagnostic equipment. Then, a load detection model is used to perform load testing on the transiently normal chip to evaluate whether the transiently normal chip is a qualified chip. In this way, the quality of the smart chip can be strictly controlled before it is put into use or sold, ensuring the pass rate of the smart chip.

[0099] In a preferred embodiment, the steps of inputting the signal deviation into the calibration model, outputting the calibration result, and determining whether the transient anomaly is continuous include:

[0100] S301. Obtain the input signal corresponding to the signal deviation and calibrate it as a calibration signal;

[0101] S302. Obtain the calibration chip, wherein there are multiple calibration chips, all of which are smart chips that are determined to be normal;

[0102] S303. Input the calibration signal into the calibration chip and output a temporary signal. Compare the temporary signal with the output signal and calibrate the comparison result as the calibration deviation.

[0103] S304. Obtain the value of the calibration deviation and compare it with the signal deviation.

[0104] If the calibration deviation and the signal deviation are the same, then the transient anomaly is determined to be continuous.

[0105] If the calibration deviation and the signal deviation are different, then a transient abnormality is determined to be intermittent.

[0106] As described in steps S301-S304 above, the calibration model is executed based on the normal smart chip. In this embodiment, it is calibrated as a calibration chip. The calibration deviation is obtained based on the temporary signal output by the calibration chip after testing. If the value of the calibration deviation is the same as the value of the signal deviation, it indicates that the transient abnormality is continuous, which means that the smart chip participating in the detection is consistent with the normal smart chip. Then it can be indicated that the input signal is abnormal. If the value of the calibration deviation is different from the value of the signal deviation, it will be determined that the transient abnormality is discontinuous. If the value of the calibration deviation is zero, it can be determined that the smart chip is abnormal and the smart chip is calibrated as a secondary abnormal chip. Of course, there may also be cases where the value of the calibration deviation is not zero, which also corresponds to the abnormality of the input signal.

[0107] In a preferred embodiment, after determining that the input signal is abnormal, the front-end signal input device corresponding to the input signal is replaced and calibrated as a verification device.

[0108] Input the input signal of the calibration device into the transient normal chip and determine whether the test signal is consistent with the output signal;

[0109] If so, replace the verification device with the front-end signal input device;

[0110] If not, continue to replace the front-end signal input device corresponding to the input signal.

[0111] In the above scenario, if an abnormal input signal occurs, the corresponding front-end signal input device needs to be replaced to ensure that the subsequent detection process can continue. Of course, before replacing the front-end signal input device, its feasibility needs to be verified. The verification process is based on a transiently normal chip. Only after the input signal input through the verification device matches the corresponding output signal can it be replaced as the front-end signal input device. Then, this device can be used to continue inputting signals to the smart chip that has not been tested.

[0112] In a preferred embodiment, the steps of acquiring the secondary faulty chip, connecting it to a diagnostic device, and determining the fault type include:

[0113] S601. Obtain the fault dataset, which includes interface faults, circuit faults, and pin faults.

[0114] Among them, the troubleshooting priority of interface faults is higher than that of pin faults, and the troubleshooting priority of pin faults is higher than that of circuit faults.

[0115] S602. Connect the secondary abnormal chips to the diagnostic device one by one according to the order of investigation priority from high to low, and obtain the fault type of the secondary abnormal chip. There are n fault types, and the value of n is a positive integer.

[0116] As described in steps S601-S602 above, when troubleshooting the faults of the secondary abnormal chip, the troubleshooting of interface faults, circuit faults and pin faults is performed one by one according to the troubleshooting priority. The troubleshooting priority is sorted according to the difficulty of troubleshooting. For the same secondary abnormal chip, there may be multiple fault types at the same time. Different repair plans can be formulated for different situations. Of course, after each fault is troubleshooted and repaired, a signal test will be performed to avoid unnecessary diagnostic processes.

[0117] In a preferred embodiment, the step of inputting the transient normal chip into the load detection model to obtain the test load includes:

[0118] S701: Acquire load signals and input them one by one into the transient normal chip. The transient normal chip outputs real-time test signals.

[0119] S702, Obtain the output timing of the real-time test signal;

[0120] S703: Obtain the maximum delay timing of the real-time test signal, compare it with the output timing, and stop inputting the load signal when the output timing equals the maximum delay timing;

[0121] S704: Obtain the load semaphore under the maximum delay timing and calibrate it as the test load.

[0122] As described in steps S701-S704 above, when performing load testing on a transient normal chip, the load test is performed by continuously adding load signals. Then, the output timing of the real-time test signal is obtained for judgment. For a qualified smart chip, in order to ensure the timeliness of the signal transmission process, a maximum delay timing is required to ensure the timeliness of signal transmission. By continuously adding load signals, the test load under the maximum delay timing can be obtained. Based on the test load of the smart chip, the maximum load it can bear can be determined, and then a device that is compatible with it can be matched.

[0123] In addition, it should be noted that since the production of smart chips may be based on known supporting equipment, a minimum load can be preset according to the operating requirements of the supporting equipment before the test load is determined. When the test load is lower than the minimum load, the smart chip corresponding to the test load is determined to be a first-level abnormal chip. Among them, the first-level abnormal chip is identified as a defective chip and needs to be reworked and remanufactured.

[0124] In a preferred embodiment, the specific process of obtaining the maximum delay timing of the real-time test signal and comparing it with the output timing is as follows:

[0125] S7031. If the maximum delay timing is greater than the output timing, then increase the input of the load signal;

[0126] S7032. If the maximum delay timing is equal to the output timing, then the load semaphore in this state is directly calibrated as the test load.

[0127] S7033. If the maximum delay timing is less than the output timing, then stop the input of the load signal and mark the corresponding output timing as the timing to be evaluated.

[0128] S7034. Input all output time series data into the trend analysis model to obtain the trend values ​​of the output time series data.

[0129] S7035: Obtain the difference between the timing sequence to be evaluated and the maximum delay timing sequence, and combine it with the trend value to calculate and output the load signal adjustment amount;

[0130] S7036. Adjust the last input load signal according to the load signal adjustment amount, and summarize all load signals to obtain the test load amount.

[0131] As described in steps S7031-S7036 above, for each smart chip, when performing load testing and the input load signal is completely consistent, it may not necessarily be exactly equal to the test load corresponding to the maximum timing. Therefore, it is necessary to adjust the load signal input on the last side to meet the condition of achieving the maximum timing. In this embodiment, the output timing is first analyzed for trend. During this process, the input values ​​of the load signals participating in the trend analysis are the same, so the change trend value of the output timing can be obtained. Based on the change trend value, the load signal adjustment amount can be obtained by combining the maximum delay timing and the load signal. Finally, the load signal input to the smart chip is adjusted according to the load signal adjustment amount, thereby ensuring the safe input of the load signal during the smart chip detection process.

[0132] In a preferred embodiment, the load test model further includes a drive capability detection module for detecting the driving capability of the smart chip, the specific process of which is as follows;

[0133] Step 1: Obtain the test load and input it into the transient normal chip to obtain the test fan-out value of the transient normal chip;

[0134] Step 2: Obtain the rated parameters and compare them with the test fan-out value;

[0135] Step 3: If the tested fan-out value is greater than or equal to the rated value, then the transiently normal chip is calibrated as a qualified chip;

[0136] Step 4: If the tested fan-out value is less than the rated value, then the transiently normal chip is marked as a level 2 abnormal chip.

[0137] As described in steps 1 to 4 above, the ability of the smart chip to process load signals is also one of the conditions reflecting its quality. A rated index can be preset according to the operating requirements of the supporting equipment. That is, the test fan-out value of the smart chip cannot be less than the rated index. Otherwise, it will be judged as a level 2 abnormal chip. After fault diagnosis, if its test fan-out value still does not reach the rated index, it will be judged as a non-conforming product and will not be included in the subsequent output timing detection process.

[0138] In a preferred embodiment, the step of inputting all output time series data into a trend analysis model to obtain the trend values ​​of the output time series includes:

[0139] Stp1: Obtain the output timing of all real-time test signals;

[0140] Stp2, Obtain standard functions from trend analysis models;

[0141] Stp3: Input all output timing data into the standard function to obtain the trend value of the output timing data.

[0142] As described in steps Stp1-Stp3 above, when calculating the trend value of the output timing, it is necessary to first obtain the output timing of all real-time test signals, and then call the corresponding standard function from the trend analysis model: In the formula, Q represents the trend value of the output timing, n represents the number of output timing values, and S... i This represents the output timing within the interval 1 to n. Based on this formula, the trend value of the output timing change can be calculated. Then, by combining the maximum delay timing and the load signal, the load signal adjustment amount can be obtained. The specific calculation formula is as follows: In the formula, T represents the load signal adjustment amount, and F j S represents the load signal before the last load signal input.z S represents the maximum input timing. q This indicates the output timing before the last load signal input, which allows us to determine the load amount that should be input for the last load signal. The purpose of this setting is to prevent the smart chip from overloading during the detection process and to avoid damage to the smart chip during the detection process.

[0143] The present invention also provides a smart chip detection system based on optical-optical communication, applied to the above-mentioned smart chip detection method based on optical-optical communication, comprising:

[0144] The first acquisition module is used to acquire the detection signal of the smart chip, wherein the detection signal includes an input signal and an output signal, and each input signal corresponds to an output signal;

[0145] The first-level test module is used to acquire input signals and input them into the smart chip to determine whether the smart chip can output test signals.

[0146] If not, the smart chip will be directly labeled as a level one abnormal chip;

[0147] If so, the test signal is compared with the output signal to obtain the signal deviation.

[0148] The secondary test module is used to determine whether the smart chip is functioning properly based on the signal deviation.

[0149] If the signal deviation is zero, the smart chip is considered to be in transient normal condition.

[0150] If the signal deviation value is not zero, the smart chip is determined to be in a transient abnormality. The signal deviation is then input into the calibration model, the calibration result is output, and it is determined whether the transient abnormality is continuous.

[0151] If the transient abnormality continues, the smart chip is determined to be in a normal transient state, and the input signal is determined to be abnormal.

[0152] If the transient anomaly is intermittent and the value in the calibration result is zero, the smart chip is determined to be abnormal and the smart chip is marked as a level 2 abnormal chip.

[0153] The second acquisition module is used to acquire the secondary abnormal chip and connect it to the diagnostic equipment to determine the fault type.

[0154] The load detection module is used to calibrate the smart chip that is determined to be transiently normal as a transiently normal chip, and input the transiently normal chip into the load detection model to obtain the test load.

[0155] The determination module is used to obtain the standard load of the smart chip and compare it with the test load.

[0156] If the test load is less than the standard load, the chip that is in transient normal condition will be identified as a level 2 abnormal chip.

[0157] If the test load is greater than or equal to the standard load, the chip that is in transient normal condition is judged as a qualified chip.

[0158] As mentioned above, when testing smart chips, the first acquisition module acquires the detection signal of the smart chip. The detection signal corresponds to the input signal and the output signal. To ensure the authenticity of the data, each set of input signals corresponds to only one set of output signals. Then, the testing module performs the first test on the smart chip, using its ability to output a signal as the evaluation criterion. This allows for the screening out of some first-level abnormal chips, which are then judged as unqualified chips. For smart chips that can output signals, the second-level testing module further tests them to screen out second-level abnormal chips. At the same time, it can also detect whether the operation of the front-end signal input device is normal. After that, chips that are transiently normal are screened out and subjected to load testing. Combined with the judgment module, qualified smart chips are determined. This testing process involves multiple judgment processes, all of which can be nested step by step using if...else conditional functions. Of course, other algorithms that can implement this process can also be used. The purpose is to screen out qualified products among the smart chips participating in the test.

[0159] And, a smart chip detection terminal based on optical-optical communication, comprising:

[0160] At least one processor;

[0161] and memory that is communicatively connected to at least one processor;

[0162] The memory stores a computer program that can be executed by at least one processor, which is then executed by the at least one processor to enable the at least one processor to perform the aforementioned smart chip detection method based on optical-to-optical communication.

[0163] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0164] The above description is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention. Structures, devices, and operating methods not specifically described or explained in this invention are implemented according to conventional methods in the art unless otherwise specified or limited.

Claims

1. A method for detecting intelligent chips based on optical-optical communication, characterized in that: include: Acquire the detection signal of the smart chip, wherein the detection signal includes an input signal and an output signal, and each input signal corresponds to an output signal; The input signal is acquired and input into the smart chip, and it is determined whether the smart chip can output a test signal. If not, the smart chip will be directly identified as a level one abnormal chip; If so, the test signal is compared with the output signal to obtain the signal deviation. The signal deviation is used to determine whether the smart chip is functioning properly. If the value of the signal deviation is zero, the smart chip is determined to be in transient normal condition. If the value of the signal deviation is not zero, the smart chip is determined to be in a transient state, and the signal deviation is input to the calibration model, the calibration result is output, and it is determined whether the transient state is continuous. If the transient abnormality continues, the smart chip is determined to be in a transient normal state, and the input signal is determined to be abnormal. If the transient anomaly is intermittent and the value in the calibration result is zero, then the smart chip is determined to be abnormal and the smart chip is marked as a level two abnormal chip. Obtain the secondary faulty chip and connect it to the diagnostic equipment to determine the fault type; The smart chip that is determined to be transiently normal is calibrated as a transiently normal chip, and the transiently normal chip is input into the load detection model to obtain the test load. Obtain the standard load of the smart chip and compare it with the test load; If the test load is less than the standard load, the transient normal chip is identified as a level 2 abnormal chip. If the test load is greater than or equal to the standard load, the transient normal chip is determined to be a qualified chip. The step of inputting the transient normal chip into the load detection model to obtain the test load includes: The load signals are acquired and input one by one into the transient normal chip, which outputs a real-time test signal; the output timing of the real-time test signal is acquired. Obtain the maximum delay timing of the real-time test signal and compare it with the output timing, and stop inputting the load signal when the output timing equals the maximum delay timing; Obtain the load semaphore under the maximum delay timing and calibrate it as the test load. The specific process of obtaining the maximum delay timing of the real-time test signal and comparing it with the output timing is as follows: If the maximum delay timing is greater than the output timing, then the input of the load signal is increased; If the maximum delay timing is equal to the output timing, then the load semaphore in this state is directly calibrated as the test load. If the maximum delay timing is less than the output timing, then the input of the load signal is stopped, and the corresponding output timing is marked as the timing to be evaluated. All the output time series are input into the trend analysis model to obtain the changing trend value of the output time series; The difference between the timing sequence to be evaluated and the maximum delay timing sequence is obtained, and combined with the trend value to calculate and output the load signal adjustment amount; Adjust the last input load signal according to the load signal adjustment amount, and summarize all load signals to obtain the test load amount.

2. The intelligent chip detection method based on optical-optical communication according to claim 1, characterized in that: The steps of inputting the signal deviation into the calibration model, outputting the calibration result, and determining whether the transient anomaly is continuous include: Obtain the input signal corresponding to the signal deviation and calibrate it as a calibration signal; Obtain calibration chips, wherein multiple calibration chips are provided, and all of them are smart chips that are determined to be normal; The calibration signal is input into the calibration chip and a temporary signal is output. The temporary signal is compared with the output signal, and the comparison result is calibrated as the calibration deviation. Obtain the value of the calibration deviation and compare it with the signal deviation. If the calibration deviation and the signal deviation are the same, then the transient anomaly is determined to be continuous. If the value of the calibration deviation is different from that of the signal deviation, then the transient abnormality is determined to be intermittent.

3. The intelligent chip detection method based on optical-optical communication according to claim 1, characterized in that: After determining that the input signal is abnormal, the front-end signal import device corresponding to the input signal is replaced and calibrated as a verification device. The input signal of the verification device is input into the transient normal chip, and it is determined whether the test signal is consistent with the output signal. If so, the verification device will be replaced with a front-end signal input device; If not, continue to replace the front-end signal import device corresponding to the input signal.

4. The intelligent chip detection method based on optical-optical communication according to claim 1, characterized in that: The step of acquiring the secondary faulty chip, connecting it to diagnostic equipment, and determining the fault type includes: Obtain a fault dataset, wherein the fault dataset includes interface faults, circuit faults, and pin faults; Among them, the troubleshooting priority of interface faults is higher than that of pin faults, and the troubleshooting priority of pin faults is higher than that of circuit faults. The secondary abnormal chips are connected to the diagnostic equipment one by one according to the investigation priority from high to low to obtain the fault type of the secondary abnormal chip. There are n fault types, and the value of n is a positive integer.

5. The intelligent chip detection method based on optical-optical communication according to claim 1, characterized in that: The load detection model also includes a drive capability detection module for detecting the drive capability of the smart chip, and the specific process is as follows; The test load is obtained and input into the transient normal chip to obtain the test fan-out value of the transient normal chip; Obtain the rated index and compare it with the test fan-out value; If the test fan-out value is greater than or equal to the rated value, the transient normal chip is calibrated as a qualified chip. If the tested fan-out value is less than the rated value, the transient normal chip will be calibrated as a level 2 abnormal chip.

6. The intelligent chip detection method based on optical-optical communication according to claim 1, characterized in that: The step of inputting all the output time series into the trend analysis model to obtain the trend value of the output time series includes: Obtain the output timing of all the aforementioned real-time test signals; Obtain the standard function from the trend analysis model; Input all the output timing data into a standard function to obtain the trend value of the output timing data.

7. A smart chip detection system based on optical-optical communication, applied to the smart chip detection method based on optical-optical communication as described in any one of claims 1 to 6, characterized in that: include: The first acquisition module is used to acquire the detection signal of the smart chip, wherein the detection signal includes an input signal and an output signal, and each input signal corresponds to an output signal; A primary test module is used to acquire input signals and input them into the smart chip to determine whether the smart chip can output test signals. If not, the smart chip will be directly identified as a level one abnormal chip; If so, the test signal is compared with the output signal to obtain the signal deviation. A secondary testing module is used to determine whether the smart chip is functioning properly based on the signal deviation. If the value of the signal deviation is zero, the smart chip is determined to be in transient normal condition. If the value of the signal deviation is not zero, the smart chip is determined to be in a transient state, and the signal deviation is input to the calibration model, the calibration result is output, and it is determined whether the transient state is continuous. If the transient abnormality continues, the smart chip is determined to be in a transient normal state, and the input signal is determined to be abnormal. If the transient anomaly is intermittent and the value in the calibration result is zero, then the smart chip is determined to be abnormal and the smart chip is marked as a level two abnormal chip. The second acquisition module is used to acquire the secondary abnormal chip, connect it to the diagnostic equipment, and determine the fault type. A load detection module is used to calibrate the smart chip that is determined to be transiently normal as a transiently normal chip, and input the transiently normal chip into the load detection model to obtain the test load. A determination module is used to obtain the standard load of the smart chip and compare it with the test load. If the test load is less than the standard load, the transient normal chip is identified as a level 2 abnormal chip. If the test load is greater than or equal to the standard load, the transient normal chip is determined to be a qualified chip.

8. A smart chip detection terminal based on optical-optical communication, characterized in that: include: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores a computer program that can be executed by the at least one processor, which is then executed by the at least one processor to enable the at least one processor to perform the smart chip detection method based on optical-optical communication as described in any one of claims 1 to 6.

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