Methods for forming semiconductor structures

Abstract

A method for forming a semiconductor structure includes: providing a substrate comprising a first region and a second region, wherein the first region and the second region each have a plurality of mutually discrete initial composite structures, the initial composite structures comprising a plurality of alternately stacked initial sacrificial layers and a plurality of initial channel layers; forming a first doped film and a first isolation layer on the surface of the plurality of initial composite structures on the first region; forming a second doped film on the surface of the first isolation layer and the surface of the plurality of initial composite structures on the second region; after forming the second doped film, performing a first heat treatment to drive first particles to be doped into the initial composite structures on the first region and drive second particles to be doped into the initial composite structures on the second region, thereby forming a plurality of mutually discrete first composite structures on the first region and a plurality of mutually discrete second composite structures on the second region. This improves the performance of the semiconductor structure and reduces the processing difficulty.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] In the current semiconductor field, the FinFET (Fin Field-Effect Transistor) is an emerging multi-gate device. Compared with planar metal-oxide-semiconductor field-effect transistors (MOSFETs), FinFETs have stronger short-channel rejection and higher operating current, and are now widely used in various semiconductor devices. However, with the further development of semiconductor technology, the transistor size has shrunk to below a few nanometers. The size of FinFETs themselves has already reached its limit. Limitations in fin spacing, short-channel effect, leakage current, and materials have made transistor manufacturing precarious, and even the physical structure cannot be completed.

[0003] Gate-all-around (GAA) devices have become a new direction for research and development in the industry. This technology is characterized by the gate completely surrounding the channel on all four sides. The source and drain no longer contact the substrate; instead, multiple source and drain electrodes, arranged laterally and perpendicularly to the gate in linear (rod-like), planar, or sheet-like shapes, are used to achieve the basic structure and function of a MOSFET. This design largely solves various problems caused by reducing the gate spacing, including capacitance effects. Furthermore, since the channel is surrounded by the gate on all four sides, the channel current flows more smoothly than with the three-sided enclosure of a FinFET.

[0004] However, as an important direction for development in the industry, gate-all-around devices still require further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure, so as to improve the performance of the semiconductor structure and reduce the difficulty of the process.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region, the first region and the second region respectively having a plurality of mutually discrete initial composite structures, the initial composite structure including a plurality of initial sacrificial layers and a plurality of initial channel layers alternately stacked along the normal direction of the substrate surface; forming a first doped film and a first isolation layer on the surface of the plurality of initial composite structures on the first region, the material of the first doped film containing first particles; forming a second doped film on the surface of the first isolation layer and the surface of the plurality of initial composite structures on the second region, the material of the second doped film containing second particles; after forming the second doped film, performing a first heat treatment to drive the first particles to be doped into the initial composite structures on the first region and drive the second particles to be doped into the initial composite structures on the second region, thereby forming a plurality of mutually discrete first composite structures on the first region and a plurality of mutually discrete second composite structures on the second region.

[0007] Optionally, the first heat treatment process includes an annealing process.

[0008] Optionally, the process parameters for the first heat treatment include a duration ranging from 1 second to 30 seconds.

[0009] Optionally, the process parameters for the first heat treatment include a temperature range of 600 degrees Celsius to 1100 degrees Celsius.

[0010] Optionally, the first composite structure includes a plurality of first sacrificial layers and a plurality of first channel layers alternately stacked along the normal direction of the substrate surface, wherein the first sacrificial layers and the first channel layers are doped with the first particles, and the second composite structure includes a plurality of second sacrificial layers and a plurality of second channel layers alternately stacked along the normal direction of the substrate surface, wherein the second sacrificial layers and the second channel layers are doped with the second particles.

[0011] Optionally, it further includes: after the first heat treatment, removing the first sacrificial layer; after removing the first sacrificial layer, forming a first gate structure spanning a plurality of first channel layers and a first source / drain structure located in the first channel layers on both sides of the first gate structure on the first region, the first gate structure surrounding each first channel layer, and the sidewall of the first gate structure having a first gate sidewall; after the first heat treatment, removing the second sacrificial layer; after removing the second sacrificial layer, forming a second gate structure spanning a plurality of second channel layers and a second source / drain structure located in the second channel layers on both sides of the second gate structure on the second region, and the second gate structure surrounding each second channel layer, and the sidewall of the second gate structure having a second gate sidewall.

[0012] Optionally, the first doped film is in contact with the top surface and sidewalls of a plurality of initial composite structures on the first region.

[0013] Optionally, the second doped film is in contact with the top surface and sidewalls of a plurality of initial composite structures on the second region.

[0014] Optionally, the substrate has isolation fins between it and each of the initial composite structures, and the method of forming the semiconductor structure further includes forming a first bottom isolation layer between the surface of the substrate and adjacent isolation fins before forming the second doped film.

[0015] Optionally, the surface of the first bottom isolation layer is flush with the bottom surface of the initial composite structure.

[0016] Optionally, the method for forming the first doped film, the first isolation layer, and the first bottom isolation layer includes: forming an initial bottom isolation layer on the substrate, between adjacent isolation fins, and on the surfaces of a plurality of initial composite structures before forming the first doped film and the first isolation layer; etching the initial bottom isolation layer on the first region until the surfaces of a plurality of initial composite structures on the first region are exposed to form an intermediate bottom isolation layer; forming an initial first doped film on the surface of the intermediate bottom isolation layer and on the surfaces of a plurality of initial composite structures on the first region; forming an initial first isolation layer on the surface of the initial first doped film; etching the intermediate bottom isolation layer, the initial first isolation layer, and the initial first doped film between the intermediate bottom isolation layer and the initial first isolation layer on the isolation fins on the second region to form the first doped film, the first isolation layer, and the first bottom isolation layer.

[0017] Optionally, the surface of the initial first isolation layer is higher than the surface of the initial first doped film.

[0018] Optionally, the method for forming the initial first isolation layer includes: forming an initial first isolation material layer on the surface of the initial first doped film; and planarizing the initial first isolation material layer to form the initial first isolation layer.

[0019] Optionally, the method for forming the initial first isolation layer further includes performing a second heat treatment after forming the initial first isolation material layer and before planarizing the initial first isolation material layer.

[0020] Optionally, the process parameters for the second heat treatment include a temperature range of 400 degrees Celsius to 600 degrees Celsius.

[0021] Optionally, it further includes: forming a second isolation layer on the surface of the second doped film, wherein the surface of the second isolation layer is higher than the surface of the first doped film; and removing the first doped film, the second doped film, the first isolation layer, and the second isolation layer after performing the first heat treatment.

[0022] Optionally, the method for forming the second isolation layer includes: forming a second isolation material layer on the surface of the second doped film; and planarizing the second isolation material layer.

[0023] Optionally, the method for forming the second isolation layer further includes performing a third heat treatment after forming the second isolation material layer and before planarizing the second isolation material layer.

[0024] Optionally, the process parameters for the third heat treatment include a temperature range of 400 degrees Celsius to 600 degrees Celsius.

[0025] Optionally, the method for removing the first doped film, the second doped film, the first isolation layer, and the second isolation layer includes: after the first heat treatment, re-etching the first isolation layer, the second isolation layer, the first doped film, and the second doped film until the top surface and sidewall surface of the first composite structure and the second composite structure are exposed.

[0026] Optionally, the method for removing the first doped film, the second doped film, the first isolation layer, and the second isolation layer further includes: planarizing the first isolation layer, the second isolation layer, the first doped film, and the second doped film after the first heat treatment and before etching back the first isolation layer, the second isolation layer, the first doped film, and the second doped film.

[0027] Optionally, the formation process of the first doped film includes: plasma-enhanced atomic layer deposition, chemical vapor deposition, or epitaxial growth.

[0028] Optionally, the formation process of the second doped film includes: plasma-enhanced atomic layer deposition, chemical vapor deposition, or epitaxial growth.

[0029] Optionally, the material of the initial sacrificial layer includes germanium silicon, and the material of the initial channel layer includes silicon.

[0030] Optionally, the first particle comprises one of boron and phosphorus, and the second particle comprises the other of boron and phosphorus.

[0031] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0032] The semiconductor structure formation method provided by the present invention involves forming a first doped film and a first isolation layer on the surface of a plurality of initial composite structures in the first region, wherein the material of the first doped film contains first particles; forming a second doped film on the surface of the first isolation layer and a plurality of initial composite structures in the second region, wherein the material of the second doped film contains second particles; after forming the second doped film, a first heat treatment is performed to drive the first particles to be doped into the initial composite structures in the first region and to drive the second particles to be doped into the initial composite structures in the second region, thereby forming a plurality of mutually discrete first composite structures in the first region and a plurality of mutually discrete second composite structures in the second region. Therefore, not only can channel layers doped with different particles be formed in the first and second regions respectively to meet the device design requirements, but also the performance of the semiconductor structure is improved and the manufacturing process is simplified. Attached Figure Description

[0033] Figures 1 to 4 This is a cross-sectional structural diagram of each step in a method for forming a semiconductor structure;

[0034] Figures 5 to 16 This is a schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0035] As described in the background section, the existing technology has high process difficulty and the performance of the semiconductor devices formed needs to be improved. The following is an explanation and analysis with reference to an embodiment.

[0036] Figures 1 to 4 This is a cross-sectional schematic diagram of each step in a method for forming a semiconductor structure.

[0037] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 including a first region S1 and a second region S2.

[0038] The first region S1 and the second region S2 each have a plurality of mutually independent initial composite structures 110, wherein the initial composite structure 110 includes a plurality of initial sacrificial layers 111 and a plurality of initial channel layers 112 alternately stacked along the normal direction of the surface of the substrate 100.

[0039] The initial sacrificial layer 111 is made of germanium silicon, and the initial channel layer 112 is made of silicon.

[0040] An isolation fin 120 is provided between the substrate 100 and the initial composite structure 110, and an isolation layer 130 (STI) is provided between adjacent isolation fins 120.

[0041] Please refer to Figure 2A first mask layer 140 is formed on the isolation layer 130 and several initial composite structures 110 on the second region S2. The first mask layer 140 exposes the surface of the isolation layer 130 and several initial composite structures 110 on the first region S1 (e.g., Figure 1 (as shown in the image) surface.

[0042] Please continue to refer to this. Figure 2 Using the first mask layer 140 as a mask, ion implantation is performed on the exposed initial composite structures 110 to dope N-type ions in the initial composite structures 110 on the first region S1, thereby forming a plurality of mutually discrete first composite structures 150 on the first region S1.

[0043] The first composite structure 150 includes a plurality of first sacrificial layers 151 and a plurality of first channel layers 152 alternately stacked along the normal direction of the surface of the substrate 100.

[0044] Please refer to Figure 3 After forming several first composite structures 150, the first mask layer 140 is removed.

[0045] Next, please continue to refer to... Figure 3 A second mask layer 160 is formed on the isolation layer 130 and several first composite structures 150 on the first region S1, and the second mask layer 160 exposes the isolation layer 130 and several initial composite structures 110 on the second region S2 (e.g., Figure 1 (as shown in the image).

[0046] Please continue to refer to this. Figure 3 Using the second mask layer 160 as a mask, ion implantation is performed on the exposed initial composite structures 110 to dope P-type ions in the initial composite structures 110 on the second region S2, thereby forming a number of mutually discrete second composite structures 170 on the second region S2.

[0047] The first composite structure 170 includes a plurality of second sacrificial layers 171 and a plurality of second channel layers 172 alternately stacked along the normal direction of the surface of the substrate 100.

[0048] Please refer to Figure 4 After forming several second sacrificial layers 171, heat treatment is performed.

[0049] However, in the above method, during the process of ion implantation of the exposed initial composite structures 110 using the first mask layer 140 as a mask, and during the process of ion implantation of the exposed initial composite structures 110 using the second mask layer 160 as a mask, the ions bombard the initial composite structures 110, causing damage to the crystal structure of the initial composite structure 110 material. Therefore, it is necessary not only to activate the implanted ions (the N-type ions and the P-type ions) through the heat treatment, but also to repair the damaged crystal structure through the heat treatment. Thus, the heat treatment is not only at a high temperature (600 degrees Celsius to 1100 degrees Celsius), but also for a long time (5 minutes to 15 minutes).

[0050] The high-temperature and prolonged heat treatment causes a significant amount of germanium in the first sacrificial layer 151 to diffuse into the first channel layer 152, and a significant amount of germanium in the second sacrificial layer 171 to diffuse into the second channel layer 172. This diffused germanium not only directly affects the material properties of the first and second channel layers 152, but also reduces the thickness H1 of the first channel layer 152 (e.g., ...). Figure 4 (as shown) and the thickness H2 of the second channel layer 172 (as shown) Figure 4 As shown) compared to the initial channel layer 112 thickness Ht1 (as shown) Figure 1 The changes (as shown) cause a large deviation between the thickness H1 of the first channel layer 152 and the thickness H2 of the second channel layer 172 and the target thickness. This results in poor performance of the semiconductor structure.

[0051] Furthermore, on the one hand, in the subsequent etching process to remove the first sacrificial layer 151, the diffused germanium will cause the etching process to have a lower selectivity for the materials of the first sacrificial layer 151 and the first channel layer 152. Similarly, in the subsequent etching process to remove the second sacrificial layer 171, the diffused germanium will cause the etching process to have a lower selectivity for the materials of the second sacrificial layer 171 and the second channel layer 172. On the other hand, the diffused germanium will cause the thickness H1 of the first channel layer 152 and the thickness H2 of the second channel layer 172 to change compared to the initial thickness Ht of the sacrificial layer 111, and will also cause the thickness H3 of the first sacrificial layer 151 to change (e.g., ...). Figure 4 (as shown) and the thickness H4 of the second sacrificial layer 171 (as shown) Figure 4 As shown) compared to the initial sacrificial layer 111 (as shown) Figure 1 The thickness Ht2 (as shown) will also change. Therefore, the process windows for the subsequent etching processes to remove the first sacrificial layer 151 and the second sacrificial layer 171 are small, resulting in greater process difficulty.

[0052] In summary, the above methods are difficult to manufacture and produce semiconductor structures with poor performance.

[0053] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure. This method involves forming a first doped film and a first isolation layer on the surface of several initial composite structures in a first region. The material of the first doped film contains first particles. Next, a second doped film is formed on the surface of the first isolation layer and several initial composite structures in a second region. The material of the second doped film contains second particles. After forming the second doped film, a first heat treatment is performed to drive the first particles to be doped into the initial composite structures in the first region and to drive the second particles to be doped into the initial composite structures in the second region. This forms several discrete first composite structures in the first region and several discrete second composite structures in the second region. This method not only enables the formation of channel layers doped with different particles in the first and second regions to meet device design requirements but also improves the performance of the semiconductor structure and reduces the processing difficulty.

[0054] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0055] Figures 5 to 16 This is a schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0056] First, a substrate is provided, comprising a first region and a second region, each having a plurality of mutually discrete initial composite structures. Each initial composite structure includes a plurality of initial sacrificial layers and a plurality of initial channel layers alternately stacked along the normal direction of the substrate surface. For specific steps in forming the substrate and the initial composite structures, please refer to [reference needed]. Figures 5 to 6 .

[0057] Please refer to Figure 5 Provides an initial base of 200.

[0058] The material of the initial substrate 200 includes semiconductor materials.

[0059] In this embodiment, the material of the initial substrate 200 includes silicon.

[0060] In other embodiments, the material of the initial substrate includes silicon carbide, silicon-germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0061] Please continue to refer to this. Figure 5 A plurality of initial sacrificial material layers 210 and a plurality of initial channel material layers 220 are formed on the surface of the initial substrate 200, and the plurality of initial sacrificial material layers 210 and the plurality of initial channel material layers 220 are stacked alternately along the normal direction of the surface of the initial substrate 200.

[0062] The initial sacrificial material layer 210 provides material for forming the initial sacrificial layer.

[0063] In this embodiment, the material of the initial sacrificial material layer 210 includes germanium and silicon.

[0064] In this embodiment, the process for forming the initial sacrificial material layer 210 includes an epitaxial growth process (EPI).

[0065] The initial channel material layer 220 provides material for forming the initial channel layer.

[0066] In this embodiment, the material of the initial channel material layer 220 includes silicon.

[0067] In this embodiment, the process for forming the initial channel material layer 220 includes an epitaxial growth process.

[0068] Please refer to Figure 6 The initial sacrificial material layer 210, the initial channel material layer 220 and the initial substrate 200 are etched to form a substrate 300 and a number of mutually independent initial composite structures 320.

[0069] Specifically, the substrate 300 includes a first region I and a second region II.

[0070] In this embodiment, the first region I and the second region II are used to form semiconductor devices of different conductivity types. Specifically, the first region I is used to form an N-type semiconductor device, and the second region II is used to form a P-type semiconductor device.

[0071] In other embodiments, the first region is used to form a P-type semiconductor device and the second region is used to form an N-type semiconductor device.

[0072] The substrate 300 is made of semiconductor materials.

[0073] In this embodiment, the material of the substrate 300 includes silicon.

[0074] In other embodiments, the substrate material includes silicon carbide, silicon-germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0075] Specifically, the first region I and the second region II each have a plurality of mutually independent initial composite structures 320, wherein the initial composite structure 320 includes a plurality of initial sacrificial layers 321 and a plurality of initial channel layers 322 alternately stacked along the normal direction of the surface of the substrate 300.

[0076] In this embodiment, the material of the initial sacrificial layer 321 includes germanium silicon.

[0077] In this embodiment, the material of the initial channel layer 322 includes silicon.

[0078] In this embodiment, the process of etching a plurality of initial sacrificial material layers 210, a plurality of initial channel material layers 220 and the initial substrate 200 includes at least one of dry etching process and wet etching process.

[0079] In this embodiment, while etching a plurality of initial sacrificial material layers 210, a plurality of initial channel material layers 220 and the initial substrate 200 to form a substrate 300 and a plurality of mutually discrete initial composite structures 320, an isolation fin 310 is formed between the substrate 300 and each initial composite structure 320.

[0080] Specifically, the top surface of the isolation fin 310 is in contact with the bottom surface of the initial composite structure 320.

[0081] Specifically, the method of etching a plurality of initial sacrificial material layers 210, a plurality of initial channel material layers 220 and the initial substrate 200 to form the substrate 300, a plurality of isolation fins 310 and a plurality of initial composite structures 320 includes: forming a plurality of mutually discrete fin mask structures (not shown in the figure) on a composite layer (not shown in the figure) composed of a plurality of initial sacrificial material layers 210 and a plurality of initial channel material layers 220; using the plurality of fin mask structures as masks, etching a plurality of initial sacrificial material layers 210, a plurality of initial channel material layers 220 and the initial substrate 200 until the substrate 300, a plurality of isolation fins 310 and a plurality of initial composite structures 320 are formed.

[0082] In this embodiment, after forming the substrate 300, the plurality of isolation fins 310, and the plurality of initial composite structures 320, the plurality of fin mask structures are retained. By retaining the fin mask structures, the protection of the initial composite structure, as well as the subsequently formed first and second composite structures, can be enhanced in subsequent processes, thereby further reducing the damage caused to the initial composite structure, the first composite structure, and the second composite structure by subsequent processes.

[0083] In other embodiments, after forming the substrate, several isolation fins and several initial composite structures, several fin mask structures are removed.

[0084] Please continue to refer to this. Figure 6 In this embodiment, a protective film 330 is formed on the surface of the substrate 300, the surfaces of the plurality of isolation fins 310, and the surfaces of the plurality of initial composite structures 320.

[0085] By forming the protective film 330, on the one hand, the substrate 300, the isolation fin 310, and the initial composite structure 320 can be protected against oxidation and the damage caused to the surfaces of the substrate 300, the isolation fin 310, and the initial composite structure 320 by subsequent processes can be reduced. On the other hand, the interface states of the formed substrate 300, isolation fin 310, and initial composite structure 320 can be improved. Thus, the performance of the semiconductor structure is better improved.

[0086] In this embodiment, the protective film 330 is also located on the surface of several fin mask structures.

[0087] In this embodiment, the material of the protective film 330 includes at least one of silicon, silicon nitride, and silicon oxide.

[0088] In this embodiment, the formation process of the protective film 330 includes: chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0089] Next, a first doped film and a first isolation layer are formed on the surface of several initial composite structures 320 in the first region I, wherein the material of the first doped film contains first particles.

[0090] In this embodiment, a first bottom isolation layer is formed between the surface of the substrate 300 and the adjacent isolation fin 310 before the subsequent formation of the second doped film.

[0091] For the specific steps of forming the first doped film, the first isolation layer, and the first bottom isolation layer, please refer to [link / reference]. Figures 7 to 10 .

[0092] Please refer to Figure 7An initial bottom isolation layer 340 is formed on the surface of the substrate 300, between adjacent isolation fins 310, and on the surface of several initial composite structures 320.

[0093] The initial bottom isolation layer 340 is used to provide material for the subsequent formation of the first bottom isolation layer.

[0094] Furthermore, during the subsequent formation of the first doped film, the initial bottom isolation layer 340 on the second region II (i.e., the middle bottom isolation layer above the subsequent isolation fin) can separate the initial composite structures 320 on the second region II from the material of the first doped film (i.e., the subsequently formed initial first doped film). Therefore, the first doped film can be formed on the basis of avoiding surface contact between the initial first doped film and the initial composite structures 320 on the second region II, so as to further reduce or avoid the diffusion of the first particles contained in the material of the first doped film to the initial composite structures 320 on the second region II.

[0095] In this embodiment, the material of the initial bottom insulating layer 340 includes oxides.

[0096] In this embodiment, the surface of the initial bottom isolation layer 340 is higher than the top surface of the initial composite structure 320.

[0097] This increases the spacing between the initial first doped film and the surface of the initial composite structure 320 on the second region II. This not only better reduces or avoids the diffusion of first particles into the initial composite structure 320 on the second region II, but also further reduces the risk of residual initial first doped film material on the surface of the initial composite structure 320 on the second region II. Simultaneously, it helps to reduce the difficulty of the subsequent etching process for removing the initial first doped film on the second region II. Therefore, the performance of the semiconductor structure is further improved, and the manufacturing process is further simplified.

[0098] In this embodiment, the method for forming the initial bottom isolation layer 340 includes: forming an initial bottom isolation material layer (not shown in the figure) on the surface of the substrate 300, between adjacent isolation fins 310, and on the surface of a plurality of initial composite structures 320; and planarizing the initial bottom isolation material layer to form the initial bottom isolation layer 340. This allows for better control of the height of the initial bottom isolation layer 340 and improves the surface flatness of the initial bottom isolation layer 340.

[0099] In this embodiment, the process for planarizing the initial bottom isolation material layer includes chemical mechanical polishing (CMP).

[0100] Next, please refer to Figure 8The initial bottom isolation layer 340 on the first region I is etched until the surface of several initial composite structures 320 on the first region I is exposed, forming an intermediate bottom isolation layer 341.

[0101] In this embodiment, the surface of the intermediate bottom isolation layer 341 on the first region I is flush with the bottom surface of the initial composite structure 320 on the first region I. Thus, through the intermediate bottom isolation layer 341, not only can the subsequently formed initial first doped film be spaced apart from the substrate 300 of the second region II, the isolation fin 310 on the second region II, and the initial composite structure 320 on the second region II, but it can also block the contact between the initial first doped film and the substrate 300 and the isolation fin 310 of the first region I, thereby reducing the first particles that diffuse to the substrate 300 and the isolation fin 310, and further improving the performance of the semiconductor structure.

[0102] In this embodiment, the method for etching the initial bottom isolation layer 340 on the first region I includes: forming a first mask layer (not shown in the figure) on the surface of the initial bottom isolation layer 340 on the second region II, the first mask layer exposing the surface of the initial bottom isolation layer 340 on the first region I; using the first mask layer as a mask, etching the exposed initial bottom isolation layer 340 until the surface of the initial bottom isolation layer 340 on the first region I is flush with the bottom surface of the initial composite structure 320 (or the top surface of the isolation fin 310) on the first region I, forming an intermediate bottom isolation layer 341.

[0103] In this embodiment, since the protective film 330 is formed, during the etching of the initial bottom isolation layer 340 on the first region I, the protective film 330 on the surface of the initial composite structure 320 on the first region I is also etched to expose the surface of the initial composite structure 320 on the first region I, so that the subsequently formed first doped film can contact the surface of the initial composite structure 320 on the first region I.

[0104] In this embodiment, the etching process for the initial bottom isolation layer 340 on the first region I includes at least one of dry etching and wet etching.

[0105] In this embodiment, after forming the intermediate bottom isolation layer 341, the first mask layer is removed.

[0106] Please continue to refer to this. Figure 8 An initial first doped film 350 is formed on the surface of the intermediate bottom isolation layer 341 and on the surface of a plurality of initial composite structures 320 on the first region I.

[0107] The initial first doped film 350 provides materials for the subsequent formation of the first doped film.

[0108] In this embodiment, the material of the initial first doped film 350 contains first particles.

[0109] In this embodiment, the first particle includes boron, and the second particle, which will be described later, includes phosphorus.

[0110] In other embodiments, the first particle comprises phosphorus, and the second particle comprises boron.

[0111] In this embodiment, an initial first doped film 350 is formed on the surface of the intermediate bottom isolation layer 341, the top surface and sidewall surface of a plurality of initial composite structures 320 on the first region I.

[0112] In this embodiment, the formation process of the initial first doped film 350 includes: plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVDALD), or epitaxial growth. Therefore, the formation process of the initial first doped film 350 causes little or no damage to the lattice of the initial composite structure 320 and the remaining formed semiconductor structures.

[0113] Preferably, the initial first doped film 350 is formed using a plasma-enhanced atomic layer deposition process or a chemical vapor deposition process. This allows for the formation of an initial first doped film 350 with good thickness uniformity, further improving the uniformity of the distribution of the first particles doped in the subsequently formed plurality of first channel layers and plurality of first sacrificial layers.

[0114] In this embodiment, the process parameters for forming the initial first doped film 350 include: a temperature below 800 degrees Celsius.

[0115] Please refer to Figure 9 An initial first isolation layer 360 is formed on the surface of the initial first doped film 350.

[0116] In this embodiment, the initial first isolation layer 360 provides materials for forming the first isolation layer.

[0117] In this embodiment, the surface of the initial first isolation layer 360 is higher than the surface of the initial first doped film 350.

[0118] The purpose of making the surface of the initial first isolation layer 360 higher than the surface of the initial first doped film 350 is to form a higher first isolation layer subsequently, so as to further increase the distance between the subsequently formed second doped film and the initial composite structure 320 on the first region I.

[0119] In this embodiment, the material of the initial first isolation layer 360 includes oxides.

[0120] In this embodiment, the process for forming the initial first isolation layer 360 includes a deposition process or a spin coating process, wherein the deposition process includes a chemical vapor deposition process or a physical vapor deposition process.

[0121] In this embodiment, the method for forming the initial first isolation layer 360 includes: forming an initial first isolation material layer (not shown in the figure) on the surface of the initial first doped film 350, wherein the surface of the first isolation material layer is higher than the surface of the initial first doped film 350; and planarizing the initial first isolation material layer to form the initial first isolation layer 360.

[0122] In this embodiment, the method for forming the initial first isolation layer 360 further includes performing a second heat treatment after forming the initial first isolation material layer and before planarizing the initial first isolation material layer. Therefore, the material density of the initial first isolation material layer is improved, thereby enabling better planarization of the initial first isolation material layer.

[0123] Specifically, the temperature of the second heat treatment is lower than the temperature of the first heat treatment that drives the first and second particles to achieve doping; that is, the temperature used in the second heat treatment is lower. Therefore, during the second heat treatment, the risk of particles contained in the material of the initial sacrificial layer 321 (germanium particles in germanium-silicon in this embodiment) diffusing to the initial channel layer 322 is small.

[0124] In this embodiment, the second heat treatment process includes an annealing process.

[0125] Specifically, the process parameters for the second heat treatment include a temperature range of 400 degrees Celsius to 600 degrees Celsius.

[0126] In other embodiments, a second heat treatment is not performed to better reduce the risk of particles contained in the material of the initial sacrificial layer diffusing into the initial channel layer.

[0127] Please refer to Figure 10 The intermediate bottom isolation layer 341, the initial first isolation layer 360, and the initial first doped film 350 between the intermediate bottom isolation layer 341 and the initial first isolation layer 360 are etched on the second region II. A first bottom isolation layer 342 is formed between the surface of the substrate 300 and the adjacent isolation fin 310. A first doped film 351 is formed on the surface of a plurality of initial composite structures 320 and the first bottom isolation layer 342 on the first region I. A first isolation layer 361 is formed on the surface of the first doped film 351.

[0128] The first doped film 351 is in contact with the surface of several initial composite structures 320 on the first region I.

[0129] In this embodiment, the first doped film 351 is located on the top surface and sidewalls of a plurality of initial composite structures 320 on the first region I. Accordingly, the first doped film 351 is in contact with the top surface and sidewalls of the plurality of initial composite structures 320 on the first region I.

[0130] Therefore, the first doped film 351 can make more surface contact with the initial composite structure 320 on the first region I. Consequently, during the subsequent first heat treatment, the first particles contained in the material 351 within the first doped film can diffuse from various surfaces of the initial composite structure 320 on the first region I to the initial sacrificial layers 321 and initial channel layers 322 of the initial composite structure 320 on the first region I. Furthermore, the first particles can be more uniformly doped into the subsequent first channel layers and first sacrificial layers of the first composite structure, improving the uniformity of doping distribution. Especially compared to ion implantation, where dopant distribution is highly dependent on implantation depth, this significantly improves the uniformity of the first particle distribution in the first channel layers and first sacrificial layers of the first composite structure. This not only better improves the performance of the semiconductor device but also facilitates a greater etching selectivity ratio between the first sacrificial layer and the first channel layer during the subsequent etching process to remove the first sacrificial layer, thereby further increasing the process window of the etching process.

[0131] In this embodiment, the material of the first doped film 351 comprises first particles. Specifically, the first particles include boron particles. In other embodiments, the first particles include phosphorus particles.

[0132] In this embodiment, the surface of the first bottom isolation layer 342 is flush with the bottom surface of the initial composite structure 320. Therefore, the first doped film 351 and the subsequently formed second doped film can be better separated from the isolation fin 310 and the substrate 300 below the initial composite structure 320, so as to further reduce the first and second particles that diffuse to the isolation fin 310 and the substrate 300, thereby further improving the performance of the semiconductor structure.

[0133] Specifically, the method of etching the intermediate bottom isolation layer 341, the initial first isolation layer 360, and the initial first doped film 350 between the intermediate bottom isolation layer 341 and the initial first isolation layer 360 on the second region II includes: forming a second mask layer (not shown in the figure) on the surface of the initial first isolation layer 360 on the first region I; using the second mask layer as a mask, etching the initial first isolation layer 360, the intermediate bottom isolation layer 341, and the initial first doped film 350 between the intermediate bottom isolation layer 341 and the initial first isolation layer 360 on the second region II until the surfaces of a plurality of initial composite structures 320 on the second region II are exposed, and the surface of the intermediate bottom isolation layer 341 on the second region II is flush with the bottom surface (or the top surface of the isolation fin 310) of the initial composite structure 320 on the second region II.

[0134] In this embodiment, the process of etching the intermediate bottom isolation layer 341, the initial first isolation layer 360, and the initial first doped film 350 between the intermediate bottom isolation layer 341 and the initial first isolation layer 360 on the second region II includes at least one of dry etching process and wet etching process.

[0135] In this embodiment, since the protective film 330 is formed, during the etching of the intermediate bottom isolation layer 341, the initial first isolation layer 360, and the initial first doped film 350 between the intermediate bottom isolation layer 341 and the initial first isolation layer 360 on the second region II, the protective film 330 on the surface of the initial composite structure 320 on the second region II is also etched to expose the surface of the initial composite structure 320 on the second region II, so that the subsequently formed second doped film can contact the surface of the initial composite structure 320 on the second region II.

[0136] Please refer to Figure 11 A second doped film 370 is formed on the surface of the first isolation layer 361 and the surface of a plurality of initial composite structures 320 on the second region II, wherein the material of the second doped film 370 contains second particles.

[0137] In this embodiment, the second doped film 370 is located on the top surface and sidewalls of a plurality of initial composite structures 320.

[0138] Therefore, the second doped film 370 can make more surface contact with the initial composite structure 320 on the second region II. Thus, during the subsequent first heat treatment, the second particles contained in the material of the second doped film 370 can diffuse from various surfaces of the initial composite structure 320 on the second region II to the initial sacrificial layers 321 and initial channel layers 322 of the initial composite structure 320 on the second region II. Consequently, the second particles can be more uniformly doped into the subsequent second composite structure's second channel layers and second sacrificial layers to improve the uniformity of doping distribution. Especially compared to ion implantation processes where dopant distribution is highly dependent on implantation depth, this significantly improves the uniformity of the second particle distribution in the second composite structure's second channel layers and second sacrificial layers. This not only better improves the performance of the semiconductor device but also facilitates a greater etching selectivity ratio between the second sacrificial layer and the second channel layer in the subsequent etching process to remove the second sacrificial layer, thereby further increasing the process window of the etching process.

[0139] In this embodiment, the second particle includes phosphorus particles.

[0140] In other embodiments, the second particle includes a boron particle.

[0141] In this embodiment, after the first doped film 351 and the first bottom isolation layer 342 are formed, the first isolation layer 361 not only exposes the surfaces of several initial composite structures 320 on the second region II, but also exposes the surface of the first bottom isolation layer 342 on the second region II. Therefore, the second doped film 370 is also formed on the surface of the first bottom isolation layer 342 on the second region II.

[0142] In this embodiment, the formation process of the second doped film 370 includes: plasma-enhanced atomic layer deposition, chemical vapor deposition, or epitaxial growth. Therefore, the formation process of the second doped film 370 causes little or no damage to the lattice of the initial composite structure 320 and the remaining formed semiconductor structures on the second region II.

[0143] Preferably, the second doped film 370 is formed using a plasma-enhanced atomic layer deposition process or a chemical vapor deposition process. This allows for the formation of a second doped film 370 with good thickness uniformity, further improving the uniformity of the distribution of second particles doped in the subsequently formed plurality of second channel layers and plurality of second sacrificial layers.

[0144] In this embodiment, the process parameters for forming the second doped film 370 include: a temperature below 800 degrees Celsius.

[0145] Please refer to Figure 12A second isolation layer 380 is formed on the surface of the second doped film 370, and the surface of the second isolation layer 380 is higher than the surface of the second doped film 370.

[0146] The second isolation layer 380 provides sacrificial material for subsequent processes that remove the first doped film 351, the second doped film 370, and the first isolation layer 361.

[0147] In this embodiment, the material of the second insulating layer 380 includes oxides.

[0148] In this embodiment, the method for forming the second isolation layer 380 includes: forming a second isolation material layer (not shown in the figure) on the surface of the second doped film 370; and planarizing the second isolation material layer.

[0149] The process for forming the second isolation material layer includes a deposition process or a spin coating process, wherein the deposition process includes a chemical vapor deposition process or a physical vapor deposition process.

[0150] In this embodiment, the method for forming the second isolation layer 380 further includes performing a third heat treatment after forming the second isolation material layer and before planarizing the second isolation material layer. This improves the material density of the second isolation layer 380, enabling a better planarization process.

[0151] Specifically, the temperature of the third heat treatment is lower than the temperature of the first heat treatment that drives the first and second particles to achieve doping; that is, the temperature used in the third heat treatment is lower. Therefore, similar to the second heat treatment process, the risk of particles contained in the material of the initial sacrificial layer 321 (germanium particles in germanium-silicon in this embodiment) diffusing into the initial channel layer 322 is small.

[0152] In this embodiment, the third heat treatment process includes an annealing process.

[0153] Specifically, the process parameters for the third heat treatment include a temperature range of 400 degrees Celsius to 600 degrees Celsius.

[0154] In another embodiment, a second isolation material layer is formed on the surface of the second doped film before a subsequent first heat treatment; a third heat treatment is performed after the subsequent first heat treatment; and after the third heat treatment, the second isolation material layer is planarized to form a second isolation layer on the surface of the second doped film.

[0155] In another embodiment, after a subsequent first heat treatment, a second isolation material layer is formed on the surface of the second doped film; after the formation of the second isolation material layer, a third heat treatment is performed; after the third heat treatment, the second isolation material layer is planarized to form a second isolation layer on the surface of the second doped film.

[0156] In other embodiments, a third heat treatment is not performed to better reduce the risk of particles contained in the material of the initial sacrificial layer diffusing into the initial channel layer.

[0157] Next, please refer to Figure 13 The process involves a first heat treatment, which drives the first particle to be doped into the initial composite structure 320 in the first region I, and drives the second particle to be doped into the initial composite structure 320 in the second region II, thereby forming a plurality of mutually discrete first composite structures 410 in the first region I and a plurality of mutually discrete second composite structures 420 in the second region II.

[0158] The first composite structure 410 includes a plurality of first sacrificial layers 411 and a plurality of first channel layers 412 alternately stacked along the normal direction of the surface of the substrate 300, wherein the first sacrificial layers 411 and the first channel layers 412 are both doped with the first particles.

[0159] The second composite structure 420 includes a plurality of second sacrificial layers 421 and a plurality of second channel layers 422 alternately stacked along the normal direction of the surface of the substrate 300, wherein the second sacrificial layers 421 and the second channel layers 422 are both doped with the second particles.

[0160] Since a first doped film 351 and a first isolation layer 361 are formed on the surface of several initial composite structures 320 on the first region I, and the material of the first doped film 351 contains first particles, a second doped film 370 is then formed on the surface of the first isolation layer 361 and the surface of several initial composite structures 320 on the second region II. The material of the second doped film 370 contains second particles. After the formation of the second doped film 370, a first heat treatment is performed to drive the first particles to be doped into the initial composite structures 320 on the first region I and to drive the second particles to be doped into the initial composite structures 320 on the second region II. Several mutually discrete first composite structures 410 are formed on the first region I, and several mutually discrete second composite structures 420 are formed on the second region II. Therefore, several first channel layers 412 and several second channel layers 422 doped with different particles can be formed on the first region I and the second region II respectively to meet the design requirements. Furthermore, the performance of the semiconductor structure is improved and the process difficulty is reduced.

[0161] Specifically, since a first doped film 351 and a first isolation layer 361 are formed on the surface of a plurality of initial composite structures 320 on the first region I, and a second doped film 370 is formed on the surface of the first isolation layer 361 and the surface of a plurality of initial composite structures 320 on the second region II, on the one hand, the first doped film 351 can contact the surface of the initial composite structures 320 on the first region I, and the second doped film 370 can contact the surface of the initial composite structures 320 on the second region II; on the other hand, the second doped film 370 is separated from the first doped film 351 and the plurality of initial composite structures 320 on the first region I by the first isolation layer 361. Thus, after the second doped film 370 is formed, the first heat treatment enables the first particles in the first doped film 351 to diffuse into the initial composite structure 320 on the first region I, and activates the first particles diffused into the initial composite structure 320, forming a plurality of first composite structures 410 doped with the first particles on the first region I. At the same time, the second particles in the second doped film 370 diffuse into the initial composite structure 320 on the second region II, and activate the second particles diffused into the initial composite structure 320, forming a plurality of second composite structures 420 doped with the second particles on the second region I. Thus, channel layers doped with different particles are formed on the first region I and the second region II respectively, to meet the design requirements of semiconductor devices.

[0162] Based on this, on the one hand, since the formation of the first composite structure 410 and the second composite structure 420 is achieved by forming a first doped film 351 and a first isolation layer 361 on the surface of the first doped film 351 on the surface of the first isolation layer 361 and a second doped film 370 on the surface of the first composite structure 320 on the surface of the second composite structure 320 on the surface of the first isolation layer 361 and the second composite structure 420 on the surface of the second isolation layer, and by performing a first heat treatment after forming the second isolation film, the process before the first heat treatment has less bombardment on the initial composite structure 320 and the semiconductor structure formed below the initial composite structure 320 and less damage to the material lattice (especially compared with the ion implantation process), the time required for lattice repair in the first heat treatment is short. The first heat treatment is mainly used to diffuse and activate the first particles and the second particles into the initial composite structure 320 on the first region I and the second region II, respectively, so as to achieve the formation of a plurality of first composite structures 410 doped with the first particles and a plurality of first composite structures 420 doped with the second particles. Thus, the time required for the first heat treatment is short.

[0163] First, by shortening the time required for the first heat treatment, the number of particles (including germanium in this embodiment) diffusing from the initial sacrificial layer 321 to the initial channel layer 322 during the first heat treatment process is reduced. Therefore, not only is the content of the diffused particles in the first channel layer 412 and the second channel layer 422 reduced, but the film thickness variation of the first channel layer 412 and the second channel layer 422 compared to the initial channel layer 322 is also reduced. This improves the performance of the semiconductor devices subsequently formed based on the first channel layer 412 and the second channel layer 422, respectively.

[0164] Secondly, on the one hand, by reducing the content of diffused particles in the first channel layer 412 and the second channel layer 422, the first sacrificial layer 411 formed after the first heat treatment is also doped with the first particles, and the second sacrificial layer 421 is also doped with the second particles. Therefore, the etching selectivity ratio of the materials of the first sacrificial layer 411 and the first channel layer 412 in the subsequent etching process for removing the first sacrificial layer 411, and the etching selectivity ratio of the materials of the second sacrificial layer 421 and the second channel layer 422 in the etching process for removing the second sacrificial layer 421, can be effectively increased. On the other hand, reducing the particles (including germanium in this embodiment) diffused from the initial sacrificial layer 321 to the initial channel layer 322 can also reduce the film thickness variation of the first sacrificial layer 411 and the second sacrificial layer 421 compared to the initial sacrificial layer 321. Therefore, after the first heat treatment, the first channel layer 412, the second channel layer 422, the first sacrificial layer 411 and the second sacrificial layer 421 with small deviations from the expected film thickness can be formed. This increases the process window for subsequent etching processes to remove the first sacrificial layer 411 and the second sacrificial layer 421, and reduces the process difficulty.

[0165] Furthermore, since the first composite structure 410 and the second composite structure 420 are formed by diffusing and activating the first and second particles into the initial composite structure 320 after the initial sacrificial material layer 210 and the initial channel material layer 220 are formed, the difficulty of the epitaxial growth process for forming the initial sacrificial material layer 210 and the initial channel material layer 220 is reduced compared to the epitaxial growth process of in-situ doping in a specific region.

[0166] In summary, this improves the performance of semiconductor structures and reduces the difficulty of manufacturing processes.

[0167] In this embodiment, the first heat treatment process includes an annealing process.

[0168] Preferably, the process parameters for the first heat treatment include a duration ranging from 1 second to 30 seconds.

[0169] Preferably, the process parameters for the first heat treatment include a temperature range of 600 degrees Celsius to 1100 degrees Celsius.

[0170] Please refer to Figure 14 Remove the first doped film 351, the second doped film 370, the first isolation layer 361, and the second isolation layer 380.

[0171] In this embodiment, the method for removing the first doped film 351, the second doped film 370, the first isolation layer 361, and the second isolation layer 380 includes: planarizing the first doped film 351, the second doped film 370, the first isolation layer 361, and the second isolation layer 380 until the top surface of a plurality of fin mask structures is exposed; after planarizing the first doped film 351, the second doped film 370, the first isolation layer 361, and the second isolation layer 380, the first doped film 351, the second doped film 370, the first isolation layer 361, the second isolation layer 380, and a portion of the first bottom isolation layer 342.

[0172] In this embodiment, while removing the first doped film 351, the second doped film 370, the first isolation layer 361 and the second isolation layer 380, a second bottom isolation layer 343 is formed with a surface lower than the top surface of the isolation fin 310.

[0173] In some other embodiments, the first doped film, the second doped film, the first isolation layer, and the second isolation layer are etched back until the surface of the first bottom isolation layer is exposed.

[0174] In some other embodiments, instead of performing a planarization step, the first doped film, the second doped film, the first isolation layer, and the second isolation layer are directly etched back.

[0175] In this embodiment, during the process of etching back the first doped film 351, the second doped film 370, the first isolation layer 361 and the second isolation layer 380, several of the fin mask structures are also etched to remove several of the fin mask structures.

[0176] In this embodiment, the process of planarizing the second isolation layer 380, the second doped film 351, the first isolation layer 361, and the first doped film 351 includes a chemical mechanical polishing process.

[0177] In this embodiment, the process of etching back the first doped film 351, the second doped film 370, the first isolation layer 361, the second isolation layer 380, and part of the first bottom isolation layer 342 includes at least one of dry etching process and wet etching process.

[0178] Next, after the first heat treatment, the first sacrificial layer 411 is removed; after removing the first sacrificial layer 411, a first gate structure spanning several first channel layers 412 and a first source / drain structure located in the first channel layers 412 on both sides of the first gate structure are formed on the first region I, the first gate structure surrounding each first channel layer 412, and the sidewall of the first gate structure having a first gate sidewall; after the first heat treatment, the second sacrificial layer 421 is removed; after removing the second sacrificial layer 421, a second gate structure spanning several second channel layers 422 and a second source / drain structure located in the second channel layers 422 on both sides of the second gate structure are formed on the second region II, and the second gate structure surrounding each second channel layer 422, and the sidewall of the second gate structure having a second gate sidewall.

[0179] For details on the process of removing the first sacrificial layer 411 and the second sacrificial layer 421, and forming the first gate structure, the second gate structure, the first gate sidewall, the second gate sidewall, the first source / drain structure, and the second source / drain structure, please refer to [link to documentation]. Figures 15 to 16 .

[0180] Please refer to Figure 15 After the first thermal treatment, several mutually independent pseudo-gate structures (not shown) are formed on the second bottom isolation layer 343. The pseudo-gate structure on the first region I spans the first composite structure 410, and the pseudo-gate structure on the second region II spans the second composite structure 420. A first gate sidewall (not shown) is formed on the sidewall of the pseudo-gate structure on the first region I. A second gate sidewall (not shown) is formed on the sidewall of the pseudo-gate structure on the second region II. A first source / drain structure (not shown) is formed in the first composite structure 410 on both sides of the pseudo-gate structure on the first region I. A second source / drain structure (not shown) is formed in the second composite structure 420 on both sides of the pseudo-gate structure on the second region II. After forming the first source / drain structure and the second source / drain structure, a dielectric layer (not shown) is formed on the second bottom isolation layer 343, and the surface of the dielectric layer exposes the top surface of the pseudo-gate structure. The pseudo-gate structure is removed, and a gate opening 510 is formed in the dielectric layer, and the gate opening 510 exposes the first composite structure 410 and the second composite structure 420.

[0181] Please continue to refer to this. Figure 15 Remove the first sacrificial layer 411 and the second sacrificial layer 421 exposed in the gate opening 510, form a first gate trench 511 between adjacent first channel layers 412 and between adjacent first channel layers 412 and isolation fins 310, and form a second gate trench 512 between adjacent second channel layers 422 and between adjacent second channel layers 422 and isolation fins 310.

[0182] The process for removing the first sacrificial layer 411 and the second sacrificial layer 421 exposed in the gate opening 510 includes at least one of dry etching and wet etching.

[0183] Please refer to Figure 16 A first gate structure 521 is formed in the gate opening 510 and the first gate trench 511 in the first region I; a second gate structure 522 is formed in the gate opening 510 and the second gate trench 512 in the second region II.

[0184] Thus, a first gate structure 521 spanning several first channel layers 412 is formed on the first region I, and a first source / drain structure (not shown) located in the first channel layers 412 on both sides of the first gate structure 521. The first gate structure 521 surrounds (encircles) each first channel layer 412, and the sidewall of the first gate structure 521 has a first gate sidewall.

[0185] Thus, a second gate structure 522 spanning several second channel layers 422 is formed on the second region II, and a second source / drain structure (not shown) located in the second channel layers 422 on both sides of the second gate structure 522, and the second gate structure 522 surrounds (encircles) each second channel layer 422, and the sidewall of the second gate structure 522 has a second gate sidewall.

[0186] Please continue to refer to this. Figure 16 An interlayer dielectric layer 530 is formed on the dielectric layer, the first gate structure 521, and the second gate structure 522; a plurality of conductive structures 540 are formed in the interlayer dielectric layer 530, and each conductive structure 540 is in contact with the top surface of the first gate structure 521 or the top surface of the second gate structure 522.

[0187] In this embodiment, before forming the interlayer dielectric layer 530, an etch stop layer 531 is formed on the dielectric layer, the first gate structure 521, and the second gate structure 522, and the conductive structure 540 also penetrates the etch stop layer 531.

[0188] In other embodiments, no etch stop layer is formed.

[0189] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region and a second region, the first region and the second region respectively having a plurality of mutually discrete initial composite structures, the initial composite structures including a plurality of initial sacrificial layers and a plurality of initial channel layers alternately stacked along the normal direction of the substrate surface; A first doped film is formed on the surface of several initial composite structures in the first region, and a first isolation layer is located on the surface of the first doped film, wherein the material of the first doped film contains first particles; A second doped film is formed on the surface of the first isolation layer and on the surface of a plurality of initial composite structures in the second region, wherein the material of the second doped film contains second particles. After the second doped film is formed, a first heat treatment is performed to drive the first particles to be doped into the initial composite structure in the first region and to drive the second particles to be doped into the initial composite structure in the second region, thereby forming a plurality of mutually discrete first composite structures in the first region and a plurality of mutually discrete second composite structures in the second region.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first heat treatment process includes an annealing process.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process parameters for the first heat treatment include a duration ranging from 1 second to 30 seconds.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process parameters for the first heat treatment include a temperature range of 600 degrees Celsius to 1100 degrees Celsius.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first composite structure includes a plurality of first sacrificial layers and a plurality of first channel layers alternately stacked along the normal direction of the substrate surface, wherein the first sacrificial layers and the first channel layers are doped with the first particles. The second composite structure includes a plurality of second sacrificial layers and a plurality of second channel layers alternately stacked along the normal direction of the substrate surface, wherein the second sacrificial layers and the second channel layers are doped with the second particles.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, Also includes: After the first heat treatment, the first sacrificial layer is removed; after removing the first sacrificial layer, a first gate structure spanning several first channel layers and a first source / drain structure located in the first channel layers on both sides of the first gate structure are formed on the first region, the first gate structure surrounding each first channel layer, and the sidewall of the first gate structure having a first gate sidewall; after the first heat treatment, the second sacrificial layer is removed; after removing the second sacrificial layer, a second gate structure spanning several second channel layers and a second source / drain structure located in the second channel layers on both sides of the second gate structure are formed on the second region, and the second gate structure surrounding each second channel layer, and the sidewall of the second gate structure having a second gate sidewall.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first doped film is in contact with the top surface and sidewalls of several initial composite structures on the first region.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second doped film is in contact with the top surface and sidewalls of several initial composite structures on the second region.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate has isolation fins between it and each of the initial composite structures, and the method of forming the semiconductor structure further includes forming a first bottom isolation layer between the surface of the substrate and adjacent isolation fins before forming the second doped film.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The surface of the first bottom isolation layer is flush with the bottom surface of the initial composite structure.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the first doped film, the first isolation layer, and the first bottom isolation layer includes: forming an initial bottom isolation layer on the substrate, between adjacent isolation fins, and on the surfaces of a plurality of initial composite structures before forming the first doped film and the first isolation layer; etching the initial bottom isolation layer on the first region until the surfaces of the plurality of initial composite structures on the first region are exposed to form an intermediate bottom isolation layer; forming an initial first doped film on the surface of the intermediate bottom isolation layer and on the surfaces of the plurality of initial composite structures on the first region; forming an initial first isolation layer on the surface of the initial first doped film; and etching the intermediate bottom isolation layer, the initial first isolation layer, and the initial first doped film between the intermediate bottom isolation layer and the initial first isolation layer on the isolation fins on the second region to form the first doped film, the first isolation layer, and the first bottom isolation layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The surface of the initial first isolation layer is higher than the surface of the initial first doped film.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The method for forming the initial first isolation layer includes: forming an initial first isolation material layer on the surface of the initial first doped film; and planarizing the initial first isolation material layer to form the initial first isolation layer.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The method for forming the initial first isolation layer further includes performing a second heat treatment after forming the initial first isolation material layer and before planarizing the initial first isolation material layer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The process parameters for the second heat treatment include a temperature range of 400 degrees Celsius to 600 degrees Celsius.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: A second isolation layer is formed on the surface of the second doped film, the surface of the second isolation layer being higher than the surface of the first doped film; after performing a first heat treatment, the first doped film, the second doped film, the first isolation layer and the second isolation layer are removed.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for forming the second isolation layer includes: forming a second isolation material layer on the surface of the second doped film; and planarizing the second isolation material layer.

18. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for forming the second isolation layer further includes performing a third heat treatment after forming the second isolation material layer and before planarizing the second isolation material layer.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The process parameters for the third heat treatment include a temperature range of 400 degrees Celsius to 600 degrees Celsius.

20. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for removing the first doped film, the second doped film, the first isolation layer, and the second isolation layer includes: after the first heat treatment, re-etching the first isolation layer, the second isolation layer, the first doped film, and the second doped film until the top surface and sidewall surface of the first composite structure and the second composite structure are exposed.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, The method for removing the first doped film, the second doped film, the first isolation layer, and the second isolation layer further includes: planarizing the first isolation layer, the second isolation layer, the first doped film, and the second doped film after the first heat treatment and before etching back the first isolation layer, the second isolation layer, the first doped film, and the second doped film.

22. The method for forming a semiconductor structure as described in claim 1, characterized in that, The formation process of the first doped film includes: plasma-enhanced atomic layer deposition, chemical vapor deposition, or epitaxial growth.

23. The method for forming a semiconductor structure as described in claim 1, characterized in that, The formation process of the second doped film includes: plasma-enhanced atomic layer deposition, chemical vapor deposition, or epitaxial growth.

24. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the initial sacrificial layer includes germanium silicon, and the material of the initial channel layer includes silicon.

25. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first particle comprises one of boron and phosphorus, and the second particle comprises the other of boron and phosphorus.

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