Linearizing a differential RF power amplifier by bias control using cross-coupled components

Abstract

The present disclosure relates to linearizing a differential radio frequency power amplifier by bias control using cross-coupling components. The amplifier may include a first terminal and a second terminal receiving a first input signal and a second input signal, and a differential amplifier providing differential amplification of the first input signal and the second input signal. The differential amplifier may include a first differential amplifier stage receiving the first input signal and a second differential amplifier stage receiving the second input signal. The amplifier may further include a first bias circuit for biasing the first differential amplifier stage, wherein the first bias circuit is connected to the second input terminal to provide an inverting bias control of the first differential amplifier stage. The amplifier may further include a second bias circuit for biasing the second differential amplifier stage, wherein the second bias circuit is connected to the first input terminal to provide an inverting bias control of the second differential amplifier stage.

Description

Technical Field

[0001] The present disclosure relates generally to radio frequency (RF) power amplifiers, and more particularly to RF amplifiers in communication devices. Background Art

[0002] Advanced mobile communication systems such as 5G use spectrally efficient complex modulation schemes to achieve high data throughput within limited spectrum resources. Radio frequency (RF) power amplifiers (PAs) are key components of such communication systems. In addition, advanced communication systems place increasingly stringent requirements on RF PAs in order to meet technical requirements such as high peak-to-average power ratio (PAPR) and ultra-wideband signals while maintaining high efficiency. Maintaining efficiency is particularly important in mobile applications because efficiency directly affects battery life and thermal management issues. Therefore, there is a need to develop systems and methods for high performance and efficient power amplification. Summary of the invention

[0003] An amplification device is disclosed according to one or more illustrative embodiments. In one illustrative embodiment, the amplification device includes a first input terminal receiving a first input signal and a second input terminal receiving a second input signal. In another illustrative embodiment, the amplification device includes a differential amplifier providing differential amplification of the first input signal and the second input signal, wherein the differential amplifier includes a first differential amplifier stage receiving the first input signal and a second differential amplifier stage receiving the second input signal. In another illustrative embodiment, the amplification device includes a first bias circuit, the first bias circuit including a first buffer biasing the first differential amplifier stage, wherein the first bias circuit is connected to the second input terminal to provide an inverting bias control of the first differential amplifier stage. In another illustrative embodiment, the amplification device includes a second bias circuit, the second bias circuit including a second buffer biasing the second differential amplifier stage, wherein the second bias circuit is connected to the first input terminal to provide an inverting bias control of the second differential amplifier stage.

[0004] A multi-stage amplifier is disclosed according to one or more illustrative embodiments. In one illustrative embodiment, the multi-stage amplifier includes two or more amplifier stages, wherein at least one of the two or more amplifier stages includes a first input terminal receiving a first input signal, a second input terminal configured to receive a second input signal, and a differential amplifier providing differential amplification of the first input signal and the second input signal. In another illustrative embodiment, the differential amplifier includes a first differential amplifier stage and a second differential amplifier stage, wherein the first differential amplifier stage includes one or more transistors and is configured to receive the first input signal, and the second differential amplifier stage includes one or more transistors and is configured to receive the second input signal. In another illustrative embodiment, the differential amplifier further includes a first bias circuit, wherein the first bias circuit includes a first buffer biasing the first differential amplifier stage, wherein the first bias circuit is connected to the second input terminal to provide an inverting bias control of the first differential amplifier stage. In another illustrative embodiment, the differential amplifier further includes a second bias circuit, wherein the second bias circuit includes a second buffer biasing the second differential amplifier stage, wherein the second bias circuit is connected to the first input terminal to provide an inverting bias control of the second differential amplifier stage.

[0005] A communication device is disclosed according to one or more illustrative embodiments. In one illustrative embodiment, the communication device includes a transmitter that generates an input transmit signal. In another illustrative embodiment, the communication device includes one or more amplifiers that receive the input transmit signal. In another illustrative embodiment, at least one of the one or more amplifiers includes: an input transformer for receiving the input transmit signal and generating a first input signal and a second input signal; a first input terminal for receiving the first input signal; a second input terminal configured for receiving the second input signal; and a differential amplifier that provides differential amplification of the first input signal and the second input signal. In another illustrative embodiment, the differential amplifier includes a first differential amplifier stage and a second differential amplifier stage, the first differential amplifier stage includes one or more transistors and is configured to receive the first input signal, and the second differential amplifier stage includes one or more transistors and is configured to receive the second input signal. In another illustrative embodiment, the differential amplifier further includes a first bias circuit, the first bias circuit includes a first buffer that biases the first differential amplifier stage, wherein the first bias circuit is connected to the second input terminal to provide an inverting bias control of the first differential amplifier stage. In another illustrative embodiment, the differential amplifier further includes a second bias circuit, the second bias circuit including a second buffer biasing the second differential amplifier stage, wherein the second bias circuit is connected to the first input terminal to provide an inverting bias control of the second differential amplifier stage, wherein the first and second differential amplifier stages provide first and second amplified output signals. In another illustrative embodiment, the communication device further includes an output transformer configured to receive the first and second amplified output signals and generate an amplified transmit signal. In another illustrative embodiment, the communication device further includes an antenna configured to broadcast the amplified transmit signal.

[0006] It should be understood that both the foregoing general description and the following detailed description are exemplary and illustrative only and do not necessarily limit the present invention. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present invention and together with the general description serve to explain the principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Those skilled in the art may better appreciate the numerous advantages of the present disclosure by referring to the accompanying drawings.

[0008] Figure 1A is a conceptual diagram of a cross-coupled differential amplifier according to one or more embodiments of the present disclosure.

[0009] Figure 1B is a conceptual diagram of a cross-coupled differential amplifier including an input matching circuit and an output matching circuit according to one or more embodiments of the present disclosure.

[0010] Figure 1Cis a conceptual diagram of a cross-coupled differential amplifier including cross-coupling capacitors between bases of emitter follower transistors and opposite differential input signals according to one or more embodiments of the present disclosure.

[0011] Figure 1D is a conceptual diagram of a cross-coupled differential amplifier including cross-coupling capacitors between emitters of emitter follower transistors and opposite differential input signals according to one or more embodiments of the present disclosure.

[0012] Figure 1E is a conceptual diagram of a cross-coupled differential amplifier having a cross-coupling circuit including an amplifier and a phase shifter according to one or more embodiments of the present disclosure.

[0013] Figure 1F is a conceptual schematic diagram of a cross-coupled differential amplifier with a cross-coupling circuit implemented as an external block to provide anti-phase injection for bias control.

[0014] Figure 2 is a graph illustrating the reduction in base voltage of a typical amplifier with a differential input signal of increasing power in accordance with one or more embodiments of the present disclosure.

[0015] Figure 3A is a conceptual block diagram of an amplifier including a conventional coupling circuit for coupling a bias circuit to an input signal in accordance with one or more embodiments of the present disclosure.

[0016] Figure 3B According to one or more embodiments of the present disclosure Figure 3A A conceptual block diagram of an amplifier illustrated as a differential amplifier.

[0017] Figure 4A is a simulated graph of a basic voltage swing between the base and emitter nodes of an emitter follower transistor in a bias circuit for various bias control techniques according to one or more embodiments of the present disclosure.

[0018] Figure 4B is a simulated graph of a direct current (DC) voltage between the base and emitter nodes of an emitter follower transistor in a bias circuit for various bias control techniques according to one or more embodiments of the present disclosure.

[0019] Figure 5A is a simulated graph of amplitude modulation to amplitude modulation (AMAM) characteristics of an amplifier using various bias control techniques according to one or more embodiments of the present disclosure.

[0020] Figure 5Bis a simulated graph of amplitude modulation to phase modulation (AMPM) characteristics of an amplifier using various bias control techniques according to one or more embodiments of the present disclosure.

[0021] Fig. 6A is an envelope simulation of the base voltage of a differential amplifier stage as a function of the supply voltage (Vcc) according to one or more embodiments of the present disclosure.

[0022] Figure 6B is an envelope simulation of the base voltage of a differential amplifier stage as a function of the power of a differential output signal according to one or more embodiments of the present disclosure.

[0023] Fig. 7A is a conceptual diagram of a multi-stage amplifier including a main amplifier stage and a driver amplifier stage according to one or more embodiments of the present disclosure.

[0024] Figure 7B is a conceptual diagram of a fully differential multi-stage amplifier illustrating multiple differential amplifier stages according to one or more embodiments of the present disclosure.

[0025] Figure 7C is a conceptual diagram of a three-stage amplifier according to one or more embodiments of the present disclosure.

[0026] Figure 8 is a block diagram illustration of a cross-coupled differential amplifier implemented in a communication device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] Reference will now be made in detail to the disclosed subject matter illustrated in the accompanying drawings. The present disclosure has been shown and described with respect to specific embodiments and specific features thereof. The embodiments set forth herein are to be considered illustrative and not restrictive. It will be readily apparent to those skilled in the art that various changes and modifications may be made in form and detail without departing from the spirit and scope of the present disclosure.

[0028] Embodiments of the present disclosure are directed to a highly linear differential radio frequency (RF) power amplifier (PA) utilizing anti-phase bias control based on cross-coupled anti-phase signals.

[0029] It is contemplated herein that achieving high efficiency RF power amplification in advanced systems such as, but not limited to, mobile communication systems may require advances in RF PA design over existing technologies. For example, existing technologies such as envelope tracking (ET) with digital pre-distortion (DPD) may provide reasonable efficiency and linearity for some less demanding applications. For example, ET may replace a fixed DC power supply with a dynamic supply voltage, and DPD may linearize the output signal by applying a pre-distorted input signal at the input of the RF PA. However, the performance of such technologies may be limited in advanced systems such as, but not limited to, 5G communication systems, because relatively high peak-to-average power ratios (PAPRs) and ultra-wideband signals may cause distortion of the supply voltage and RF dispersion.

[0030] It is further contemplated herein that inverted bias control of amplifier stages within a differential RF amplifier based on cross-coupled signals from opposite inputs provides high linearity performance suitable for a variety of demanding applications including, but not limited to, 5G mobile communication systems. In addition, the high linearity differential RF amplifier disclosed herein can provide considerable flexibility in amplifier system design. In some applications, reliance on technologies such as ET or DPD can be reduced or eliminated. In some applications, the systems and methods disclosed herein can achieve performance improvements in technologies such as ET or DPD because the range of such technologies can be less stressed.

[0031] Reference now Figures 1A to 8 , according to one or more embodiments of the present disclosure, systems and methods for providing a high linearity differential RF PA are described in more detail.

[0032] Figure 1A 1 is a conceptual diagram of a cross-coupled differential amplifier 100 according to one or more embodiments of the present disclosure. Specifically, the cross-coupled differential amplifier 100 is a differential amplifier that provides an in-phase differential output signal 102a (e.g., a first output signal) and an out-of-phase differential output signal 102b (e.g., a second output signal) (collectively referred to as differential output signal 102 herein) based on differential amplification of an in-phase differential input signal 104a (e.g., a first input signal) and an out-of-phase differential input signal 104b (e.g., a second input signal) (collectively referred to as differential output signal 102 herein).

[0033] The cross-coupled differential amplifier 100 can operate on a differential input signal 104 of any frequency, frequency range, or frequency band. For example, the differential input signal 104 may have, but is not limited to, a frequency in the range of MHz to GHz. In some embodiments, the cross-coupled differential amplifier 100 has an operating range that includes frequencies suitable for communication in a spectrum band allocated to 5G communications, such as, but not limited to, frequencies ranging from 410 MHz to 7125 MHz (e.g., frequency range 1) or frequencies ranging from 24.25 GHz to 52.6 GHz (frequency range 2). In some embodiments, the cross-coupled differential amplifier 100 has an operating range that includes frequencies suitable for communication in a spectrum band allocated to long-term evolution (LTE) communications, such as, but not limited to, FDD or TDD LTE bands. However, it should be understood that the cross-coupled differential amplifier 100 disclosed herein is not limited to an operating range associated with any particular communication standard. In fact, reference to any particular frequency, frequency band, or communication standard is for illustrative purposes only and should not be construed as limiting.

[0034] The cross-coupled differential amplifier 100 may have any architecture known in the art suitable for providing differential amplification. In some embodiments, the cross-coupled differential amplifier 100 includes an in-phase differential amplifier stage 106a (e.g., a first differential amplifier stage) for receiving an in-phase differential input signal 104a and an out-of-phase differential amplifier stage 106b (e.g., a second differential amplifier stage) for receiving an out-of-phase differential input signal 104b, wherein the in-phase differential amplifier stage 106a and the out-of-phase differential amplifier stage 106b are collectively referred to herein as differential amplifier stages 106. For example, Figure 1A As illustrated, differential amplifier stage 106 may accept differential input signal 104 through series capacitor 108 .

[0035] The in-phase differential amplifier stage 106a and the out-of-phase differential amplifier stage 106b may include any combination or design of components suitable for forming the differential cross-coupled differential amplifier 100. For example, the in-phase differential amplifier stage 106a and / or the out-of-phase differential amplifier stage 106b may include one or more transistors (e.g., bipolar junction transistors, heterojunction bipolar transistors (HBTs), field effect transistors (FETs), or any other suitable transistor type). As an illustration, the in-phase differential amplifier stage 106a and / or the out-of-phase differential amplifier stage 106b may include two transistors in a cascode configuration. As another example, the in-phase differential amplifier stage 106a and / or the out-of-phase differential amplifier stage 106b may include one or more operational amplifiers.

[0036] It should be understood that the terms "in-phase" and "out-of-phase" used with reference to various aspects of the cross-coupled differential amplifier 100 are for illustrative purposes only and do not limit the present disclosure. For example, the in-phase differential input signal 104a and the out-of-phase differential input signal 104b may be generally understood as any first input signal and second input signal. In some embodiments, one of the differential input signals 104 may be connected to ground or otherwise referenced to ground. In this way, a single input signal may be provided as an input to the amplifier. Similarly, the in-phase differential amplifier stage 106a and the out-of-phase differential amplifier stage 106b may be generally understood as the first and second differential amplifier stages 106, and the in-phase differential output signal 102a and the out-of-phase differential output signal 102b may be generally understood as the first and second output signals.

[0037] The cross-coupled differential amplifier 100 may further include impedance matching circuitry or be coupled to impedance matching circuitry to match the input or output to additional components. For example, the impedance matching circuitry may include any combination of active or passive elements known in the art suitable for impedance matching, including but not limited to resistors, capacitors, inductors, transistors, or transformers.

[0038] Figure 1B 1 is a conceptual diagram of a cross-coupled differential amplifier 100 including an input matching circuit 110a and an output matching circuit 110b according to one or more embodiments of the present disclosure. Specifically, the input and output matching circuits 110 include transformers (eg, an input transformer and an output transformer). Figure 1B Further illustrating the configuration of the cross-coupled differential amplifier 100 includes a single input signal 112 and a single output signal 114 (both referenced to ground).

[0039] The reverse bias control of the cross-coupled differential amplifier 100 using the cross-coupled differential input signal 104 will now be described in more detail according to one or more embodiments of the present disclosure.

[0040] It is contemplated herein that the base voltage of the cross-coupled differential amplifier 100 may change as the power of the differential input signal 104 increases due to increased current consumption, thermal issues, or the like. Figure 2 is a graph illustrating the reduction in base voltage of a typical amplifier (or amplifier stage) with a differential input signal 104 of increasing power according to one or more embodiments of the present disclosure. Therefore, it may be desirable to control the bias level of the cross-coupled differential amplifier 100 to promote linear operation in the presence of power variations.

[0041] Reference again Figure 1A and 1BIn some embodiments, the cross-coupled differential amplifier 100 includes a bias circuit 116 for biasing the differential amplifier stage 106. For example, the cross-coupled differential amplifier 100 may include an in-phase bias circuit 116a (e.g., a first bias circuit 116a) for biasing the in-phase differential amplifier stage 106a and an out-of-phase bias circuit 116b (e.g., a second bias circuit 116b) for biasing the out-of-phase differential amplifier stage 106b.

[0042] The bias circuit 116 may include any combination or design of components suitable for controlling bias conditions (e.g., operating points of constituent transistors or the like) of the in-phase differential amplifier stage 106a and / or the out-of-phase differential amplifier stage 106b. In some embodiments, the bias circuit 116 (e.g., the in-phase bias circuit 116a or the out-of-phase bias circuit 116b) includes a buffer (e.g., a buffer amplifier) ​​that provides selected voltage and current conditions to the corresponding differential amplifier stage 106 (e.g., the in-phase differential amplifier stage 106a or the out-of-phase bias circuit 116b). Such a buffer may be formed using any design having any combination of components known in the art, such as, but not limited to, operational amplifiers or transistors.

[0043] For example, the bias circuit 116 may include a buffer formed by one or more transistors in a voltage follower configuration (e.g., a configuration that provides unity gain), where a selected voltage is provided to the input of the buffer to control the operating point of the corresponding differential amplifier stage 106. As an illustration, the voltage follower may be formed as a BJT in a common collector configuration (e.g., an emitter follower configuration), two cascaded BJTs in a common collector configuration forming a Darlington pair, a plurality of cascaded BJTs, or the like. However, it should be understood that the bias circuit 116 may include any type of transistor, including but not limited to a bipolar junction transistor (BJT), a heterojunction bipolar transistor (HBT), a field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET), or a pseudomorphic high electron mobility transistor (PHEMT). In this manner, any examples depicting a particular transistor type herein are purely illustrative, such that such examples may be extended to other transistor types. For example, the voltage follower may be formed by one or more FETs in a common drain configuration.

[0044] In some embodiments, the bias circuit 116 further injects a cross-coupled anti-phase signal from the opposite differential input signal 104 to provide an anti-phase bias control of the differential amplifier stage 106. In this manner, the bias control voltage of a particular differential amplifier stage 106 can fluctuate based on changes in the opposite differential input signal 104. It is contemplated herein that this configuration can provide highly linear and robust bias control over a wide power range (e.g., associated with high PAPR of 5G mobile communications or the like). For example, the in-phase bias circuit 116a for the in-phase differential amplifier stage 106a can utilize a cross-coupled input from the out-of-phase differential input signal 104b, while the out-of-phase bias circuit 116b for the out-of-phase differential amplifier stage 106b can utilize a cross-coupled input from the in-phase differential input signal 104a.

[0045] The bias circuit 116 for the differential amplifier stage 106 may be connected to the opposite differential input signal 104 using any combination of active or passive elements suitable for providing an inverted injection for bias control, which are referred to herein as cross-coupling circuits 118. For example, the cross-coupling circuit 118 may include, but is not limited to, one or more capacitors, one or more phase shifters, one or more transistors, or one or more amplifiers (e.g., additional amplifiers for providing amplification of the opposite differential input signal 104 for bias control purposes). Furthermore, the bias circuit 116 and the cross-coupling circuit 118 may be connected in any suitable configuration to provide an inverted injection for inverted bias control. For example, the inverted bias control may be achieved by cross-coupling the bias circuit 116 with the opposite differential input signal 104 using one or more transistors in various voltage follower configurations, such as, but not limited to, a common collector configuration, a common source configuration, a common base configuration, or a common gate configuration. In this manner, the inverse differential input signal 104 may be provided as an input to a voltage follower in the bias circuit 116. In some applications, the bias circuit 116 may further provide a DC voltage to the input of the voltage follower so that bias control of the differential amplifier stage 106 may be provided by a combination of the DC voltage and the inverted signal.

[0046] In some embodiments, the bias circuit 116 for the differential amplifier stage 106 is connected to the opposing differential input signal 104 via one or more capacitors as a cross-coupling circuit 118 . Figure 1C and 1D Two non-limiting examples of using cross-coupling capacitors 120 are described.

[0047] exist Figure 1C and 1D, the bias circuits 116 are each illustrated as a BJT transistor 122 (eg, voltage follower transistor 122) in a voltage follower configuration coupled to a corresponding differential amplifier stage 106 through a resistor 124. In this manner, each voltage follower transistor 122 is in an emitter follower configuration. Figure 1C and 1D Further illustrated is a bias drive element 126 coupled to the input of the voltage follower transistor 122. In this particular illustration, the base of the voltage follower transistor 122 is connected across one or more diodes 128 and a decoupling capacitor 130 tied to ground, which are connected to the source 132 through a resistor 134. However, it should be understood that Figure 1C and 1D and the associated descriptions are provided for illustrative purposes only and should not be construed as limiting.In fact, the concepts disclosed herein may be extended to any suitable design of the bias circuit 116, including but not limited to different transistor types or different buffer designs.

[0048] Figure 1C is a conceptual diagram of a cross-coupled differential amplifier 100 including a cross-coupling capacitor 120 between the base of a voltage follower transistor 122 (eg, typically the input of a buffer) and an opposite differential input signal 104 according to one or more embodiments of the present disclosure. For example, Figure 1C A cross-coupling capacitor 120a is illustrated connected between the base of a voltage follower transistor 122a of the in-phase bias circuit 116a and an out-of-phase input terminal providing an out-of-phase differential input signal 104b. Similarly, Figure 1C The cross-coupling capacitor 120b is illustrated as being connected between the base of the voltage follower transistor 122b of the out-of-phase bias circuit 116b and the non-inverting input terminal providing the non-inverting differential input signal 104a. In this manner, an inverted signal is injected into the base of each voltage follower transistor 122, as illustrated by inset 136. Specifically, inset 136 illustrates fluctuations (e.g., V E ) and the anti-phase fluctuations (e.g., V B Thus, the reverse injection provides a basic voltage swing (V BE ), which increases with increasing power, which enables consistent linear performance over a wide power range.

[0049] It is contemplated herein that specific values ​​of the cross-coupling capacitors 120 and elements of the bias circuit 116 (e.g., the decoupling capacitors 120) may be selected to tune the performance of the cross-coupled differential amplifier 100. In this configuration, each of the cross-coupled cross-coupling capacitors 120 forms a capacitive voltage divider with the corresponding decoupling capacitor 130 across the diode 128. Thus, if the value of the cross-coupling capacitors 120 increases while the value of the decoupling capacitors 120 decreases, the amount of anti-phase injection to be coupled to the bias circuit 116 increases. However, the amount of anti-phase injection should be balanced with the delay introduced between the alternating current (AC) signal path of the differential input signal 104 and the direct current (DC) signal path in the bias circuit 116. Furthermore, the decoupling capacitors 120 both divide the anti-phase signal through the cross-coupling capacitors 120 and rectify the DC base voltage of the voltage follower transistor 122. Therefore, the values ​​of the cross-coupling capacitors 120, the decoupling capacitors 120, and the size of the voltage follower transistor 122 can be selected to maximize the basic voltage swing between the base node and the emitter node of the voltage follower transistor 122 (or to provide the basic voltage swing within a selected tolerance) while also providing an acceptable delay between the AC signal path of the differential input signal 104 and the DC path in the bias circuit 116.

[0050] Figure 1D is a conceptual diagram of a cross-coupled differential amplifier 100 including a cross-coupling capacitor 120 between the emitter of a voltage follower transistor 122 and an opposite differential input signal 104 according to one or more embodiments of the present disclosure. Figure 1D The illustrated design may be advantageous for, but not limited to, applications where it is beneficial to have a reduced DC voltage associated with the differential amplifier stage 106. For example, the appropriate DC voltage level may be determined by various factors such as, but not limited to, the RF system design or the HBT process.

[0051] In some embodiments, the cross-coupled differential amplifier 100 includes a multi-element cross-coupling circuit 118 between the bias circuit 116 for the differential amplifier stage 106 and the opposite differential input signal 104. Such a multi-element cross-coupling circuit 118 may provide increased control over the amount of anti-phase injection of the bias circuit 116 and any delay between the AC signal path of the differential input signal 104 and the DC path in the bias circuit 116.

[0052] For example, the cross-coupling circuit 118 may include a circuit connected between the bias circuit 116 for the differential amplifier stage 106 and the opposite differential input signal 104 to provide an anti-phase bias control by injecting the opposite differential input signal 104. As another example, the cross-coupling circuit 118 may include one or more phase shifters (e.g., AC phase delay) that control the phase delay between the AC signal path of the differential input signal 104 and the DC path in the bias circuit 116.

[0053] As an illustration, Figure 1E is a conceptual diagram of a cross-coupled differential amplifier 100 having a cross-coupling circuit 118 including an amplifier and a phase shifter according to one or more embodiments of the present disclosure. Figure 1E The cross-coupled circuit 118 in includes an amplifier 138 (eg, a limited gain amplifier for bias control purposes) having a positive source terminal 140a connected to the in-phase bias circuit 116a and a negative source terminal 140b connected to the out-of-phase bias circuit 116b.

[0054] For example, the positive source terminal 140a may (but need not) be connected to the base or emitter of the voltage follower transistor 122 in the in-phase bias circuit 116a. Similarly, the negative source terminal 140b may (but need not) be connected to the base or emitter of the voltage follower transistor 122 in the out-of-phase bias circuit 116b.

[0055] Figure 1E The cross-coupling circuit 118 in the embodiment further includes a phase shifter 142a connected between the positive input terminal 144a of the amplifier 138 and the in-phase input terminal providing the in-phase differential input signal 104a, and a phase shifter 142b connected between the negative input terminal 144b and the out-phase input terminal providing the out-phase differential input signal 104b. In this way, the cross-coupling circuit 118 can provide a cross-coupled anti-phase signal to the bias circuit 116. In addition, this design enables the amplitude of the anti-phase signal provided to the bias circuit 116 to be selected, while the phase shifter 142 enables the phase of the anti-phase signal to be selected.

[0056] General reference Figures 1C to 1E , it should be understood that Figures 1C to 1E and the associated description are provided for illustrative purposes only and should not be construed as limiting. For example, the cross-coupled differential amplifier 100 may include a bias circuit 116 having any suitable design such that Figures 1C to 1EThe specific embodiments in the drawings are non-limiting illustrations. In addition, the cross-coupling circuits 118 can be connected to the bias circuit 116 in any manner suitable for providing an inverted signal from the opposite differential input signal 104 for inverted bias control. The cross-coupled differential amplifier 100 can generally include one or more cross-coupling circuits 118, which include any combination of active or passive components, such that Figures 1C to 1E The specific embodiments described are non-limiting illustrations.

[0057] Figure 1F is a conceptual diagram of a cross-coupled differential amplifier 100 having a cross-coupling circuit 118 implemented as an external block (e.g., external circuitry or the like) to provide anti-phase injection for bias control. In this manner, the cross-coupling circuit 118 can provide any degree of complexity or manufacturing technology suitable for providing anti-phase injection for bias control.

[0058] Reference now Figures 3A to 6B , the performance of the cross-coupled differential amplifier 100 is described in more detail.

[0059] One conventional approach to improving the linearity of an amplifier as input signal power increases is to provide coupling between the input signal and bias circuitry for the associated amplifier stage. Figure 3A is a conceptual block diagram of an amplifier 302 including a conventional coupling circuit 304 that couples a bias circuit 116 to an input signal 112 in accordance with one or more embodiments of the present disclosure.

[0060] Figure 3B According to one or more embodiments of the present disclosure Figure 3A 3 is a conceptual block diagram of an amplifier 302 that is a differential amplifier. Specifically, in addition to the coupling circuit for bias control, Figure 3B The architecture of the amplifier 302 is similar to Figure 3A In this way, the impact of the coupling technique for bias control can be more clearly illustrated.

[0061] exist Figure 3B , the in-phase bias circuit 116a associated with the in-phase differential amplifier stage 106a is connected to the in-phase input terminal providing the in-phase differential input signal 104a via capacitor 306a. In addition, the out-of-phase bias circuit 116b associated with the out-of-phase differential amplifier stage 106b is connected to the out-of-phase input terminal providing the out-of-phase differential input signal 104b via capacitor 306b. In this manner, capacitor 306a and capacitor 306b form a coupling circuit 304 without cross coupling.

[0062] This conventional bias control technique may provide a mechanism for adjusting the bias current to the in-phase differential amplifier stage 106a based on the power level of the in-phase differential input signal 104a and adjusting the bias current to the out-of-phase differential amplifier stage 106b based on the power level of the out-of-phase differential input signal 104b. For example, this may provide a relatively low bias current at a relatively low power level and a relatively higher bias current as the power level increases. This configuration may further provide a constant base voltage and a fluctuating emitter voltage in the event that the differential input signal 104 fluctuates.

[0063] Another method (not illustrated) of improving the linearity of the amplifier circuit may be to provide cross-coupling between the differential output signal 102 and the opposite differential input signal 104. For example, cross-coupling between the output signal and the input signal of an amplifier is generally described in U.S. Pat. No. 7,697,915, issued Apr. 13, 2010, which is incorporated herein by reference in its entirety.

[0064] However, it is contemplated herein that conventional bias control techniques based on no cross-coupling or bias control based on cross-coupling between output and input signals may provide insufficient linearity for demanding applications such as, but not limited to, 5G communication systems. For example, bias control based on cross-coupling between output and input signals is a form of positive feedback that can affect gain peaking and make the amplifier dependent on output load impedance. It is further contemplated herein that the systems and methods disclosed herein provide simple and robust bias control.

[0065] Figures 4A to 6B Various graphs illustrating the performance characteristics of amplifier circuits having different bias control schemes. Specifically, Figures 4A to 6B Describe as Figure 1C The depicted cross-coupled differential amplifier 100 (labeled 402), as Figure 3B Depicted are the performance of amplifier 302 (eg, without cross coupling) (labeled 404 ) and an amplifier (labeled 406 ) having a similar architecture but without any coupling circuitry between bias circuit 116 and differential input signal 104 .

[0066] Figure 4A is a simulated graph of a basic voltage swing between the base and emitter nodes of the voltage follower transistor 122 in the bias circuit 116 for various bias control techniques according to one or more embodiments of the present disclosure. Figure 4B is a simulated graph of a DC voltage between the base and emitter nodes of a voltage follower transistor 122 in a bias circuit 116 for various bias control techniques according to one or more embodiments of the present disclosure. Figure 4A and 4BAs illustrated, conventional coupling between the bias circuit 116 for the differential amplifier stage 106 and the associated differential input signal 104 (see, for example, Figure 3B ) provides better performance across different power levels than a simple amplifier without any coupling. However, as disclosed herein (see, for example, Figure 1C ), the reverse bias control based on the cross-coupling between the bias circuit 116 for the differential amplifier stage 106 and the opposite differential input signal 104 provides excellent performance across a wide range of power levels. For example, the reverse injection provides a relatively large fundamental voltage swing (V BE ), and maintains a more consistent DC voltage as power increases. In this way, the anti-phase injection better compensates for voltage drops in the differential amplifier stage 106 due to high current consumption, thermal issues, or the like.

[0067] Figure 5A is a simulated graph of amplitude modulation to amplitude modulation (AMAM) characteristics of an amplifier using various bias control techniques according to one or more embodiments of the present disclosure. Figure 5B is a simulated graph of amplitude modulation to phase modulation (AMPM) characteristics of an amplifier using various bias control techniques according to one or more embodiments of the present disclosure.

[0068] This paper has considered Figure 5A and 5B The AMAM and AMPM characteristics described in are some of the main factors in determining the linearity of the amplifier, wherein linear operation is achieved when these characteristics are stable (or at least substantially stable within a given tolerance). In addition, these characteristics are closely related to the voltage applied at the base node of the voltage follower transistor 122, such as but not limited to an HBT.

[0069] like Figure 5A and 5B As described, the anti-phase bias control based on cross-coupling injection of the opposite differential input signal 104 into the bias circuit 116 of the differential amplifier stage 106 provides excellent AMAM and AMPM characteristics with relatively stable performance across a wide power level range. Specifically, Figure 5B The significant improvement based on the disclosed technique over conventional bias control without anti-injection through cross-coupling is illustrated, most notably at relatively high powers, as indicated by the substantially reduced peak near 30 dBm. These results indicate that the bias control via anti-injection through cross-coupling disclosed herein more effectively maintains the base voltage of the cross-coupled differential amplifier 100 than conventional techniques.

[0070] Reference now Fig. 6A and 6B, illustrating an envelope simulation of the actual operation of the voltage follower transistor 122 in the bias circuit 116. Fig. 6A φ is an envelope simulation of the base voltage of the differential amplifier stage 106 as a function of the supply voltage (Vcc) according to one or more embodiments of the present disclosure. Figure 6B 1 is a simulation of the envelope of the base voltage of the differential amplifier stage 106 as a function of the power of the differential output signal 102 according to one or more embodiments of the present disclosure. These simulation results illustrate the use of the differential amplifier stage 106 as disclosed herein (e.g., see Figure 1C ) based on cross-coupling between the bias circuit 116 of the differential amplifier stage 106 and the opposite differential input signal 104 to more effectively maintain the base voltage of the differential amplifier stage 106 and thereby provide better linearity than conventional bias control techniques.

[0071] Reference now Figures 7A to 7C , various non-limiting examples of using the RF amplifier 100 in a multi-stage amplification system are described according to one or more embodiments of the present disclosure. It is contemplated herein that many advanced RF amplification systems utilize multi-stage amplification, and it is further contemplated herein that the cross-coupled differential amplifier 100 disclosed herein may be implemented as any type of amplifier stage.

[0072] Fig. 7A is a conceptual diagram of a multi-stage amplifier 702 including a main amplifier stage 704 and a driver amplifier stage 706 in accordance with one or more embodiments of the present disclosure. Figure 7B 1 is a conceptual diagram of a fully differential multi-stage amplifier 702 illustrating multiple differential amplifier stages 106 according to one or more embodiments of the present disclosure. In a general sense, the multi-stage amplifier 702 may have multiple amplifier stages. As an illustration, Figure 7C 7 is a conceptual diagram of a three-stage amplifier 702 according to one or more embodiments of the present disclosure. For example, the three-stage amplifier 702 includes a main amplifier stage 704 and two driver amplifier stages 706 (eg, a pre-driver stage and a driver stage).

[0073] like Figures 7A to 7C As illustrated, the multi-stage amplifier 702 may include matching circuitry between the various amplifier stages and at the input and output to provide impedance matching both within the multi-stage amplifier 702 and between the multi-stage amplifier 702 and external devices. Figures 7A to 7C Inter-stage matching circuit 708, input matching circuit 710, and output matching circuit 712 are illustrated. Figures 7B to 7CAdditionally depicted are input transformer 714 and output transformer 716, which can further facilitate impedance matching with external components. Additionally, one terminal of both input transformer 714 and output transformer 716 is tied to ground. In this configuration, multi-stage amplifier 702 can accept a single input signal 718 and provide a single output signal 720, but each of the amplifier stages can operate on a differential input signal 104.

[0074] It is contemplated herein that the main amplifier stage 704 may generally draw a greater current than the driver amplifier stage 706, such that the base voltage of the main amplifier stage 704 may change faster than the driver amplifier stage 706. In addition, the base voltage of the main amplifier stage 704 decreases as the power of the input signal 202 increases, which may be at least partially due to thermal issues. Therefore, it may be particularly advantageous to implement the main amplifier stage 704 as a cross-coupled differential amplifier 100 disclosed herein. However, any amplifier stage of the multi-stage amplifier 702 may be implemented as a cross-coupled differential amplifier 100. For example, one or more of the driver amplifier stages 706 may consume sufficient current to cause a drop in the base voltage at higher power levels. Therefore, implementing the multi-stage amplifier 702 (where multiple amplifier stages are implemented as a cross-coupled differential amplifier 100 with bias control based on anti-phase injection using cross-coupling as disclosed herein) may achieve high linear performance over a wide power range.

[0075] Reference now Figure 8 , Figure 8 is a block diagram illustration of a cross-coupled differential amplifier 100 implemented in a communication device 802 according to one or more embodiments of the present disclosure. It is contemplated herein that the cross-coupled differential amplifier 100 may be used in any communication device 802, including but not limited to a mobile phone, a laptop computer, or a tablet computer.

[0076] In some embodiments, the communication device 802 includes an antenna 804 coupled to one or more transmitters 806 and receivers 808 to facilitate transmission and / or reception of RF signals 810. The RF signals 810 may have any frequency or frequency range, such as, but not limited to, MHz to GHz frequencies. Furthermore, the RF signals 810 may be within any specified frequency band, such as, but not limited to, a 5G band or an LTE band.

[0077] In some embodiments, the communication device 802 further includes one or more cross-coupled differential amplifiers 100 coupled to the antenna 804 to provide amplification of the RF signal 810. For example, the communication device 802 may include one or more cross-coupled differential amplifiers 100 to amplify the RF signal 810 from the transmitter 806 before being transmitted by the antenna 804.

[0078] As an illustration, the communication device 802 may include a transmitter 806 that generates an RF signal 810 for transmission (e.g., an input transmit signal) and one or more cross-coupled differential amplifiers 100 that receive and amplify the input transmit signal. For example, the communication device 802 may include an input transformer (e.g., such as Figure 1B , 7B 7C) to receive the input transmission signal and generate differential input signals 104 (e.g., first input signal and second input signal). Then, the cross-coupled differential amplifier 100 can provide amplification of these differential input signals 104 based on the reverse bias control disclosed herein to generate differential output signals 102 (e.g., first and second amplified output signals). Then, the communication device 802 can include an output transformer (e.g., as Figures 1B to 1F , 7B and 7C) to provide an amplified transmit signal for broadcasting by antenna 804.

[0079] As another example, the communication device 802 may include multiple cross-coupled differential amplifiers 100 that are customized to amplify different frequencies or bands of RF signals 810. It is contemplated herein that the cross-coupled differential amplifiers 100 as disclosed herein may provide highly linear operation across a wide range of power levels and may therefore be suitable for use in advanced communication systems.

[0080] Additionally, it is contemplated herein that the cross-coupled differential amplifier 100 is not limited to mobile communication applications and may generally be used in any communication system. Therefore, references herein to mobile communication systems are provided for illustrative purposes only and do not limit the present disclosure.

[0081] The subject matter described herein sometimes illustrates different components contained in or connected to other components. It should be understood that such architectures depicted are exemplary only, and in fact, many other architectures that realize the same functionality can be implemented. Conceptually, any configuration of components for realizing the same functionality is effectively "associated" so as to realize the desired functionality. Therefore, any two components combined to realize a specific functionality herein can be regarded as "associated with each other" so as to realize the desired functionality, regardless of the architecture or intermediate components. Similarly, any two components so associated can also be regarded as "connected" or "coupled" to each other to realize the desired functionality, and any two components that can be so associated can also be regarded as "couplable" to each other to realize the desired functionality. Specific examples that can be coupled include, but are not limited to, physically interactive and / or physically interactive components and / or wirelessly interactive and / or wirelessly interactive components and / or logically interactive and / or logically interactive components.

[0082] It is believed that the present disclosure and many of its attendant advantages will be appreciated from the foregoing description, and it will be appreciated that various changes may be made in the form, construction, and arrangement of components without departing from the disclosed subject matter or sacrificing its full material advantages. The forms described are illustrative only, and it is intended that such changes be covered and included by the appended claims. Furthermore, it will be understood that the invention is defined by the appended claims.

Claims

1. An amplifier, comprising: a first input terminal configured to receive a first input signal; a second input terminal configured to receive a second input signal; A differential amplifier, which provides differential amplification of the first input signal and the second input signal, wherein the differential amplifier comprises: a first differential amplifier stage for receiving the first input signal; and a second differential amplifier stage for receiving the second input signal; a first bias circuit comprising a first buffer for biasing the first differential amplifier stage, wherein the first bias circuit is connected to the second input terminal to provide an inverting bias control of the first differential amplifier stage based on the second input signal; and A second bias circuit includes a second buffer for biasing the second differential amplifier stage, wherein the second bias circuit is connected to the first input terminal to provide an inverting bias control of the second differential amplifier stage based on the first input signal.

2. The amplifier of claim 1 , wherein at least one of the first buffer of the first bias circuit or the second buffer of the second bias circuit comprises: One or more transistors in a voltage follower configuration.

3. The amplifier of claim 2, wherein the one or more transistors comprise: At least one of a heterojunction bipolar transistor (HBT), a bipolar transistor, a field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET), or a pseudomorphic high electron mobility transistor (PHEMT).

4. The amplifier of claim 2 , wherein the first bias circuit is connected to the second input terminal in at least one of a common collector configuration, a common drain configuration, a common base configuration, or a common gate configuration to provide an inverting bias control of the first differential amplifier stage, wherein the second bias circuit is connected to the first input terminal in at least one of a common collector configuration, a common drain configuration, a common base configuration, or a common gate configuration to provide an inverting bias control of the second differential amplifier stage.

5. The amplifier of claim 1 , wherein the first bias circuit is connected to the second input terminal via one or more first capacitors to provide the inverting bias control of the first differential amplifier stage, wherein the second bias circuit is connected to the first input terminal via one or more second capacitors to provide the inverting bias control of the second differential amplifier stage.

6. The amplifier of claim 1 , wherein the first bias circuit is connected to the second input terminal via at least one of a first additional amplifier or a first phase shifter to provide the inverting bias control of the first differential amplifier stage, wherein the second bias circuit is connected to the first input terminal via at least one of a second additional amplifier or a second phase shifter to provide the inverting bias control of the second differential amplifier stage.

7. A multi-stage amplifier comprising: Two or more amplifier stages, wherein at least one of the two or more amplifier stages comprises: a first input terminal configured to receive a first input signal; a second input terminal configured to receive a second input signal; A differential amplifier, which provides differential amplification of the first input signal and the second input signal, wherein the differential amplifier comprises: a first differential amplifier stage comprising one or more transistors and configured to receive the first input signal; and a second differential amplifier stage comprising one or more transistors and configured to receive the second input signal; a first bias circuit comprising a first buffer for biasing the first differential amplifier stage, wherein the first bias circuit is connected to the second input terminal to provide an inverting bias control of the first differential amplifier stage; and A second bias circuit includes a second buffer for biasing the second differential amplifier stage, wherein the second bias circuit is connected to the first input terminal to provide an inverting bias control of the second differential amplifier stage.

8. The multi-stage amplifier of claim 7, wherein at least one of the first buffer of the first bias circuit or the second buffer of the second bias circuit comprises: One or more transistors in a voltage follower configuration.

9. The multi-stage amplifier of claim 8, wherein the one or more transistors comprise: At least one of a heterojunction bipolar transistor (HBT), a bipolar transistor, a field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET), or a pseudomorphic high electron mobility transistor (PHEMT).

10. The multi-stage amplifier of claim 8, wherein the first bias circuit is connected to the second input terminal in at least one of a common collector configuration, a common drain configuration, a common base configuration, or a common gate configuration to provide an inverting bias control of the first differential amplifier stage, wherein the second bias circuit is connected to the first input terminal in at least one of a common collector configuration, a common drain configuration, a common base configuration, or a common gate configuration to provide an inverting bias control of the second differential amplifier stage.

11. The multi-stage amplifier of claim 7, wherein the first bias circuit is connected to the second input terminal via one or more first capacitors to provide the inverting bias control of the first differential amplifier stage, wherein the second bias circuit is connected to the first input terminal via one or more second capacitors to provide the inverting bias control of the second differential amplifier stage.

12. The multi-stage amplifier of claim 7 , wherein the first bias circuit is connected to the second input terminal via at least one of a first additional amplifier or a first phase shifter to provide the inverting bias control of the first differential amplifier stage, wherein the second bias circuit is connected to the first input terminal via at least one of a second additional amplifier or a second phase shifter to provide the inverting bias control of the second differential amplifier stage.

13. The multi-stage amplifier of claim 7, further comprising: One or more matching circuits between at least two of the two or more amplifier stages.

14. A communication device, comprising: A transmitter for generating an input transmission signal; one or more amplifiers configured to receive the input transmit signal, wherein at least one of the one or more amplifiers comprises: An input transformer, configured to receive the input transmission signal and generate a first input signal and a second input signal; a first input terminal configured to receive the first input signal; a second input terminal configured to receive the second input signal; A differential amplifier, which provides differential amplification of the first input signal and the second input signal, wherein the differential amplifier comprises: a first differential amplifier stage comprising one or more transistors and configured to receive the first input signal; and a second differential amplifier stage comprising one or more transistors and configured to receive the second input signal; a first bias circuit comprising a first buffer for biasing the first differential amplifier stage, wherein the first bias circuit is connected to the second input terminal to provide an inverting bias control of the first differential amplifier stage; and a second bias circuit including a second buffer biasing the second differential amplifier stage, wherein the second bias circuit is connected to the first input terminal to provide an inverting bias control of the second differential amplifier stage, wherein the first and second differential amplifiers provide first and second amplified output signals; an output transformer configured to receive the first and second amplified output signals and generate an amplified transmit signal; and An antenna is configured to broadcast the amplified transmit signal.

15. The communication device of claim 14, wherein at least one of the first buffer of the first bias circuit or the second buffer of the second bias circuit comprises: One or more transistors in a voltage follower configuration.

16. The communication device of claim 15, wherein the one or more transistors comprise: At least one of a heterojunction bipolar transistor (HBT), a bipolar transistor, a field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET), or a pseudomorphic high electron mobility transistor (PHEMT).

17. A communication device according to claim 15, wherein the first bias circuit is connected to the second input terminal in at least one of a common collector configuration, a common drain configuration, a common base configuration or a common gate configuration to provide an inverting bias control of the first differential amplifier stage, and wherein the second bias circuit is connected to the first input terminal in at least one of a common collector configuration, a common drain configuration, a common base configuration or a common gate configuration to provide an inverting bias control of the second differential amplifier stage.

18. The communication device of claim 14, wherein the first bias circuit is connected to the second input terminal via one or more first capacitors to provide the inverting bias control of the first differential amplifier stage, wherein the second bias circuit is connected to the first input terminal via one or more second capacitors to provide the inverting bias control of the second differential amplifier stage.

19. A communication device according to claim 14, wherein the first bias circuit is connected to the second input terminal via at least one of a first additional amplifier or a first phase shifter to provide the inverting bias control of the first differential amplifier stage, and wherein the second bias circuit is connected to the first input terminal via at least one of a second additional amplifier or a second phase shifter to provide the inverting bias control of the second differential amplifier stage.

20. The communication device of claim 14, wherein the one or more amplifiers comprise: Two or more amplifiers are configured for different frequencies associated with the input transmit signal.

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