Novel integrated programmable gain amplifier (PGA) and protection circuit

Abstract

Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier "PGA" and protection circuit. In various embodiments, a circuit is provided that includes a PGA, an analog-to-digital converter "ADC", and a protection circuit, all disposed on the same semiconductor chip. The PGA is configured to receive a wireless signal received from an antenna as input, and to output an amplified wireless signal at its output based on amplifying the wireless signal by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold magnitude, control a reduction in the programmable gain amount to bring the resulting signal at the output of the PGA below the threshold magnitude. A normally open switch can also be added at the differential output of the PGA to further clamp the PGA output.

Description

[0001] Copyright Notice

[0002] A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. TECHNICAL FIELD

[0003] In general, this disclosure relates to methods, systems, and apparatuses for implementing wireless receiver applications, and more particularly to methods, systems, and apparatuses for implementing novel integrated programmable gain amplifiers ("PGAs") and protection circuits for wireless base station applications in some cases. BACKGROUND

[0004] Conventional direct-sampling receivers for wireless base stations require off-chip gain programmable components, which result in significant manufacturing cost and large power consumption. It is desirable to have an integrated approach that includes programmable gain amplifiers ("PGAs") on the same semiconductor chip as the direct-sampling high-speed analog-to-digital converters ("ADCs").

[0005] However, one technical difficulty of integrating a PGA with a high-speed ADC is the reliability issue of such advanced complementary metal-oxide-semiconductor ("CMOS") technology. Advanced CMOS technology can be less reliable, especially under high supply operation that is typically required for high linearity wireless applications. Wireless base station receiver designs need to ensure reliability and withstand large input swings (e.g., 10 dBm, etc.). Sudden jumps in the received input power will damage the front-end CMOS circuits without fast protection circuits. Off-chip gain programmable components limit the overall response time because peak detection typically involves slow digital logic and then requires slow off-chip connections to off-chip gain components for gain adjustment.

[0006] High supply voltages are typically required to meet the extremely stringent linearity requirements of wireless base station receivers, which in turn puts more pressure on the reliability of CMOS transistors. Under such high supply, it is also required to improve the inherent reliability of the receiver front-end circuits without any active protection circuits.

[0007] Therefore, there is a need for more robust and scalable solutions for implementing wireless receiver applications, and more particularly, for methods, systems, and apparatuses for implementing novel integrated PGAs and protection circuits. SUMMARY

[0008] The techniques of this disclosure generally relate to tools and techniques for implementing wireless receiver applications, and more particularly, to methods, systems, and apparatuses for implementing novel integrated PGA and protection circuits.

[0009] In an aspect, a circuit includes a programmable gain amplifier ("PGA") disposed on a semiconductor chip, the PGA configured to receive a wireless signal received directly or indirectly from an antenna as an input and output an amplified wireless signal at an output of the PGA based on amplifying the wireless signal by a programmable gain amount; an analog-to-digital converter ("ADC") disposed on the semiconductor chip, the ADC configured to convert the amplified wireless signal received directly or indirectly from the PGA to a digital signal; and a protection circuit disposed on the semiconductor chip, the protection circuit configured to control a reduction of the programmable gain amount in response to detecting a spike in gain at the output of the PGA that exceeds a first threshold magnitude to cause a resulting signal at the output of the PGA to be below the first threshold magnitude.

[0010] According to some embodiments, the protection circuit includes a detector and a gain control ("GC") circuit. In some cases, the detector is configured to send a first signal that activates the GC circuit in response to detecting a spike in gain at the output of the PGA that exceeds the first threshold magnitude, and to reset to monitor a state of the output of the PGA that occurs prior to activation of the GC circuit in response to receiving a second signal from the GC circuit. In some examples, the GC circuit is configured to control the reduction of the programmable gain amount in response to receiving the first signal, and to send the second signal to the detector after a predetermined period of time after at least one of: receiving the first signal or controlling the reduction of the programmable gain amount. By way of example only, in some cases, controlling a reduction of the programmable gain amount includes controlling the programmable gain amount to a minimum gain state.

[0011] Alternatively or in addition, the circuit further includes a normally open ("NO") switch disposed on the semiconductor chip, the NO switch bridging one of the output of the PGA and a ground or second output of the PGA, the NO switch configured to close a circuit in response to the amplified wireless signal exceeding a second threshold magnitude, thereby clamping or limiting the output of the PGA. In some examples, the NO switch includes at least one of a clamping switch, a load switch, or a combination control logic and transistor switch, and / or the like. In some cases, the second threshold magnitude is the same as the first threshold magnitude.

[0012] According to some embodiments, the semiconductor chip includes a complementary metal-oxide-semiconductor (“CMOS”) chip.

[0013] In some embodiments, the circuitry further includes a filter disposed between the PGA and the ADC. In some examples, the filter includes at least one of a resistor-inductor-capacitor (“RLC”) filter, a high-pass filter, a band-pass filter, or a low-pass filter and / or the like.

[0014] In another aspect, a device includes an antenna and circuitry. According to some embodiments, the circuitry includes: a complementary metal-oxide-semiconductor (“CMOS”) chip; a programmable gain amplifier (“PGA”) disposed on the CMOS chip, the PGA being configured to amplify a wireless signal received directly or indirectly from the antenna based on a programmable gain, and to output the amplified wireless signal at the output of the PGA; an analog-to-digital converter (“ADC”) disposed on the CMOS chip, the ADC being configured to convert the amplified wireless signal received directly or indirectly from the PGA into a digital signal; and protection circuitry integrated on the CMOS chip along with at least one of the PGA and the ADC, the protection circuitry being configured to prevent the input of an amplified wireless signal exceeding a first threshold amplitude at the ADC.

[0015] In some embodiments, the protection circuitry includes a detector and a gain control (“GC”) circuitry. In some cases, the detector is configured to send a first signal activating the GC circuitry in response to detecting a spike in the gain at the output of the PGA exceeding a first threshold amplitude, and to reset to a state monitoring the output of the PGA that occurred prior to the activation of the GC circuitry in response to receiving a second signal from the GC circuitry. In some examples, the GC circuitry is configured to control a decrease in the programmable gain amount in response to receiving the first signal, such that the resulting signal at the output of the PGA is below the first threshold amplitude, and to send the second signal to the detector after a predetermined time period following at least one of the following: receiving the first signal or controlling the decrease in the programmable gain amount. In some cases, controlling the decrease in the programmable gain amount includes controlling the programmable gain amount to a minimum gain state.

[0016] Alternatively or additionally, the protection circuit includes a normally open (“NO”) switch disposed on the CMOS chip, the NO switch bridging the output of the PGA with either ground or a second output of the PGA, the NO switch being configured to close the circuit in response to the amplified wireless signal exceeding a second threshold amplitude, thereby clamping or limiting the output of the PGA. In some examples, the NO switch includes at least one of a clamping switch, a load switch, or a combination of control logic and transistor switches and / or the like.

[0017] According to some embodiments, the circuit further includes a filter disposed between the PGA and the ADC, the filter including at least one of a resistor-inductor-capacitor (“RLC”) filter, a high-pass filter, a band-pass filter, or a low-pass filter and / or the like.

[0018] In another aspect, a method includes: using a programmable gain amplifier (“PGA”) disposed on a semiconductor chip and amplifying a wireless signal received directly or indirectly from an antenna based on a programmable gain amount; using the PGA and outputting the amplified wireless signal at the output of the PGA; in response to the amplified wireless signal exceeding a first threshold amplitude (“over-amplified wireless signal”), using protection circuitry disposed on the semiconductor chip to prevent the over-amplified wireless signal from being relayed to an analog-to-digital converter (“ADC”) disposed on the semiconductor chip; and when the amplified wireless signal does not exceed the first threshold amplitude, using the protection circuitry to allow the amplified wireless signal to be relayed to the ADC to convert the amplified wireless signal into a digital signal.

[0019] In some embodiments, the protection circuitry includes a detector and a gain control (“GC”) circuitry. In some cases, preventing the over-amplified wireless signal from being relayed to the ADC includes using the detector to send a first signal activating the GC circuitry in response to detecting a spike in the gain at the output of the PGA exceeding a first threshold amplitude; and using the GC circuitry to control a reduction in the programmable gain amount in response to receiving the first signal, so that the resulting signal at the output of the PGA is below the first threshold amplitude. According to some embodiments, the method further includes: sending a second signal to the detector using the GC circuitry after a predetermined time period following at least one of the following: receiving the first signal or controlling the reduction in the programmable gain amount; and using the detector to reset to a state monitoring the output of the PGA that occurred before the activation of the GC circuitry in response to receiving the second signal from the GC circuitry.

[0020] Alternatively or additionally, the protection circuitry includes a normally open (“NO”) switch disposed on the semiconductor chip, the NO switch bridging the output of the PGA with either ground or a second output of the PGA. In some examples, preventing the over-amplified wireless signal from being relayed to the ADC includes using the NO switch to close a circuit in response to the amplified wireless signal exceeding the first threshold amplitude, thereby clamping or limiting the output of the PGA.

[0021] Various modifications and additions can be made to the discussed embodiments without departing from the scope of the invention. For example, although the above embodiments relate to specific features, the scope of the invention also includes embodiments with different combinations of features and embodiments that do not include all of the above features.

[0022] Details of one or more aspects of this disclosure are set forth in the accompanying drawings and the following description. Other features, objectives, and advantages of the technology described in this disclosure will be apparent from the description, drawings, and claims. Attached Figure Description

[0023] A further understanding of the nature and advantages of particular embodiments can be achieved by referring to the remainder of the specification and the accompanying drawings, wherein similar reference numerals are used to refer to similar components. In some instances, sublabels are associated with reference numerals to indicate one of a plurality of similar components. When reference numerals are cited without description of existing sublabels, it is intended to refer to all such plurality of similar components.

[0024] Figure 1 This is a schematic diagram illustrating a system including a novel integrated programmable gain amplifier (“PGA”) and protection circuitry according to various embodiments.

[0025] Figure 2 This is a schematic diagram illustrating non-limiting examples of novel integrated PGA and protection circuits according to various embodiments.

[0026] Figure 3 This is a schematic diagram illustrating alternative, non-limiting examples of novel integrated PGA and protection circuits according to various embodiments.

[0027] Figure 4 This describes how, according to various embodiments, the amplified wireless signal at the output of the PGA exceeds a threshold amplitude (e.g., Figure 3 Graphical representations of non-limiting examples of the operation of novel integrated PGAs and protection circuits.

[0028] Figure 5A and 5B This is a flowchart illustrating a method for implementing a novel integrated PGA and protection circuit according to various embodiments. Detailed Implementation

[0029] SUMMARY

[0030] Various embodiments provide tools and techniques for implementing wireless receiver applications, and more specifically, methods, systems, and apparatus for implementing novel integrated programmable gain amplifiers (“PGA”) and protection circuitry.

[0031] In various embodiments, a circuit (e.g., a receiver circuit, etc.) is provided, comprising: a programmable gain amplifier (“PGA”) disposed on a semiconductor chip, the PGA being configured to receive a wireless signal received directly or indirectly from an antenna as input, and to output an amplified wireless signal at the output of the PGA based on amplifying the wireless signal to a programmable gain amount; an analog-to-digital converter (“ADC”) disposed on the semiconductor chip, the ADC being configured to convert the amplified wireless signal received directly or indirectly from the PGA into a digital signal; and a protection circuit disposed on the semiconductor chip, the protection circuit being configured to control a reduction of the programmable gain amount in response to detecting a spike in the gain at the output of the PGA exceeding a first threshold amplitude, such that the resulting signal at the output of the PGA is below the first threshold amplitude.

[0032] According to some embodiments, the protection circuit includes a detector and a gain control (“GC”) circuit. In some cases, the detector is configured to send a first signal (also referred to as an “activation signal” or similar) to activate the GC circuit in response to detecting a spike in the gain at the output of the PGA exceeding the first threshold amplitude, and to reset to a state (also referred to as an “initial monitoring state” or similar) monitoring the output of the PGA prior to the activation of the GC circuit in response to receiving a second signal (also referred to as a “release signal” or similar) from the GC circuit. In some examples, the GC circuit is configured to control a decrease in the programmable gain amount in response to receiving the first signal, and to send the second signal to the detector after a predetermined time period following at least one of the following: receiving the first signal or controlling the decrease in the programmable gain amount. By way of example only, in some cases, controlling the decrease in the programmable gain amount includes controlling the programmable gain amount to a minimum gain state.

[0033] Alternatively or additionally, the circuit further includes a normally open (“NO”) switch disposed on the semiconductor chip, the NO switch bridging the output of the PGA with either ground or a second output of the PGA, the NO switch being configured to close the circuit in response to the amplified wireless signal exceeding a second threshold amplitude, thereby clamping or limiting the output of the PGA. In some examples, the NO switch includes at least one of a clamping switch, a load switch, or a combination of control logic and a transistor switch and / or the like. In some cases, the second threshold amplitude is the same as the first threshold amplitude.

[0034] According to some embodiments, the semiconductor chip includes a complementary metal-oxide-semiconductor (“CMOS”) chip.

[0035] Among the various aspects described herein, a novel integrated programmable gain amplifier (“PGA”) and protection circuitry are provided. This allows for several advantages at the circuit, system, and product levels. For example, some circuit advantages include (but are not limited to) low power and low cost, where the integrated CMOS PGA saves significant power and offers greater cost reduction compared to conventional off-chip PGAs; and the PGA protection circuitry ensures reliability throughout the receiver path without negatively impacting receiver performance; high speed and high performance; and / or the like. Some system advantages include (but are not limited to) eliminating the off-chip PGA, thereby allowing for a more compact overall system, thus providing significant power and cost advantages; and greater operational flexibility for other off-chip components of the wireless base station receiver because the reliability of the receiver front end is protected; and / or the like. Some product advantages include (but are not limited to) significantly reduced power; integration advantages; manufacturing advantages; and / or the like.

[0036] These and other aspects of the system and method for implementing a novel integrated PGA and protection circuit are described in more detail with reference to the accompanying drawings. Although some embodiments are described in light of the implementation of the integrated PGA and protection circuit within a wireless base station application, various embodiments are not limited thereto, and the integrated PGA and protection circuit (as described herein) can generally be applied to any wireless application in which analog signal detection is used.

[0037] The following detailed description further illustrates some embodiments to enable those skilled in the art to practice such embodiments. The described examples are provided for illustrative purposes and are not intended to limit the scope of the invention.

[0038] In the following description, numerous details are set forth for purposes of explanation to provide a thorough understanding of the described embodiments. However, it will be apparent to those skilled in the art that other embodiments of the invention can be practiced without some of these details. In other instances, some structures and apparatuses are shown in block diagram form. Several embodiments are described herein, and while various features belong to different embodiments, it should be understood that a feature described with respect to one embodiment may also be incorporated into other embodiments. However, for the same reason, one or more features of any described embodiment should not be considered essential to every embodiment of the invention, as such features may be omitted in other embodiments of the invention.

[0039] Unless otherwise indicated, all figures used herein to express quantities, dimensions, etc., should be understood to be modified by the term “about” in all instances. In this application, unless expressly stated otherwise, the use of the singular includes the plural, and unless otherwise indicated, the use of the terms “and” and “or” means “and / or”. Furthermore, the use of the term “comprising” and other forms (e.g., “includes” and “included”) should be considered non-exclusive. Additionally, terms such as “element” or “component” cover elements and components comprising one unit as well as elements and components comprising more than one unit, unless expressly stated otherwise.

[0040] Some embodiments

[0041] We now turn to the embodiment illustrated in the diagram. Figure 1 Section 5 describes some of the features of methods, systems, and apparatuses for implementing wireless receiver applications, and more specifically, some of the features of methods, systems, and apparatuses for implementing novel integrated programmable gain amplifiers (“PGAs”) and protection circuits as mentioned above. Figure 1 The methods, systems, and apparatus described in paragraphs 5 relate to examples of different embodiments comprising various components and steps, which may be considered alternatives or may be used in combination with each other in various embodiments. Figure 1 The descriptions of the methods, systems, and devices illustrated in Figures 5 and 6 are provided for illustrative purposes and should not be construed as limiting the scope of the various embodiments.

[0042] Refer to the attached diagram. Figure 1 This is a schematic diagram illustrating a system 100 including a novel integrated PGA and protection circuit according to various embodiments.

[0043] exist Figure 1In a non-limiting embodiment, system 100 includes a (wireless) device 105 (e.g., but not limited to, a wireless base station, transceiver, etc.) that includes, but is not limited to, a semiconductor chip 110, an antenna 115, and a signal processor 155. In some embodiments, semiconductor chip 110 is a chip with an integrated PGA and protection circuitry, and includes, but is not limited to, a receiver 120, a PGA 125, a normally open switch 130 (optional), a fast detector 135 (which includes, but is not limited to, at least one of a detector circuit, a detector chip, a sensor circuit, a sensor chip, etc., each configured to detect jumps or spikes in an input signal over a short time period (e.g., having ns, μs, or ms, etc.) and / or instantaneously), gain control (“GC”) circuitry 140, a filter 145, and an analog-to-digital converter (“ADC”) 150, etc. In some cases, semiconductor chip 110 is a complementary metal-oxide-semiconductor (“CMOS”) chip, etc. In this document, "PGA" may refer to a gain amplifier circuit that can be configured or programmed using gain control signals from gain control circuitry, etc., while "integrated PGA" may refer to a PGA integrated on the same semiconductor chip as an ADC or other signal processing circuitry. In this document, a PGA or integrated PGA, ADC, protection circuitry, switches, and / or other circuit components may be described as being "placed" on semiconductor chip 110. This includes being mounted on semiconductor chip 110, inserted into or connected to mounting ports mounted on semiconductor chip 110, or additionally placed on semiconductor chip 110 in a permanently fixed or removably fixed manner, wherein the inputs and outputs of these circuit components are communicatively coupled or connected to other suitable circuit components or contacts via corresponding conductive traces on semiconductor chip 110.

[0044] Receiver 120 is configured to receive wireless signals from antenna 115, and PGA 125 is configured to receive wireless signals as input directly from antenna 155 or indirectly from antenna 155 via receiver 120 (and / or other intermediate circuit components or the like), and outputs amplified wireless signals at its output based on amplifying the wireless signals to a programmable gain.

[0045] To protect the ADC 150 from receiving signals that could damage or destroy it, a protection circuit is integrated on the semiconductor chip 110 along with at least one of the PGA 125 and the ADC 150. In some embodiments, the protection circuit includes a fast detector 135 and a GC circuit 140. In response to detecting a spike in the gain at the output of the PGA 125 exceeding a first threshold amplitude, the detector sends a first signal (also referred to as an "activation signal" or similar) to activate the GC circuit. In response to receiving the first (or activation) signal, the GC circuit 140 controls a reduction in the programmable gain by sending a gain control signal to bring the resulting signal at the output of the PGA below a first threshold amplitude (e.g., 100 millivolts or similar). After a predetermined time period (e.g., between a few nanoseconds and a few milliseconds or longer) following at least one of the following: receiving the first signal or controlling a reduction in the programmable gain, the GC circuit 140 sends a second signal (also referred to as a "release signal" or similar) to the fast detector 135. In response to receiving a second (or release) signal from the GC circuit 140, the fast detector 135 resets itself and the PGA 125 (i.e., the programmable gain amount) to the initial or previous state.

[0046] Alternatively or additionally, the protection circuit includes or further includes a normally open (“NO”) switch 130 that bridges the output of the PGA to ground or a second output of the PGA. In some examples, the NO switch 130 includes (but is not limited to) a clamping switch (such as... Figure 3The term "clipped switch" refers to at least one of the following: load switch (not shown), or combinational control logic and transistor switch (not shown), and / or the like. In this document, a NO switch bridging the output of a PGA may include one or more intermediate circuit components or may not include any intermediate circuit components between at least one end of the NO switch and the corresponding output terminal of the PGA. In this document, "clamped switch" may refer to circuitry configured to limit or "clamp" the output voltage (in this case, the output of the PGA) to a specified or predetermined range of the output value (in this case, to a value below a first threshold amplitude or the like). In this document, "load switch" may refer to circuitry configured to provide overcurrent protection (i.e., controlling sudden current (or voltage) spikes in a fixed or adjustable manner), which in some cases may be achieved using a fixed or adjustable rise time that controls the sudden flow of current (sometimes referred to as "inrush current" or the like) and / or the switching rate of the device (e.g., the PGA, etc.). In response to the amplified wireless signal at the output of PGA 125 exceeding a second threshold amplitude, the NO switch closes (or turns on) the circuit, thereby clamping or limiting the PGA output to a predetermined level. When the amplified wireless signal at the output of PGA 125 drops below the second threshold amplitude, the NO switch opens (or turns off) the circuit again, thereby resetting to its initial state. In some cases, the second threshold amplitude is the same as the first threshold amplitude. Alternatively, the second threshold amplitude is greater than the first threshold amplitude, in which case the NO switch 130 serves as a backup protection circuit for the combination of the fast detector 135 and the GC circuit 140 (if the combination exists).

[0047] When the amplified wireless signal output at PGA 125 is below a first threshold amplitude, in some cases, the amplified wireless signal is relayed to ADC 150 via filter 145 (or otherwise permitted to travel toward ADC 150). In some cases, filter 145 includes (but is not limited to) at least one of a resistor-inductor-capacitor (“RLC”) filter, a high-pass filter, a band-pass filter, or a low-pass filter and / or the like. ADC 150 then converts the amplified wireless signal from an analog signal to a digital signal, which is then processed by a signal processor (e.g., signal processor 155) as part of other operations of device 105 known in the art.

[0048] The following is about Figure 2 The following section describes these and other functions of system 100 (and its components) in more detail.

[0049] Figure 2 This is a schematic diagram illustrating a non-limiting example 200 of a novel integrated PGA and protection circuit according to various embodiments.

[0050] existFigure 2 In non-limiting example 200, a CMOS chip 210 with integrated PGA and reliability protection is shown for direct sampling of a base station receiver. Figure 2 As depicted, the CMOS PGA 225 is integrated together with the high-speed direct-sampling ADC 250 on the same advanced CMOS chip 210. This integration of the PGA 225 and ADC 250 on the same CMOS chip 210 offers significant integration advantages in terms of cost and power. In some cases, the PGA uses an array of input programmable resistors (not shown, but in some cases, it is part of the GC circuit 240) to achieve gain programmability. The RLC anti-aliasing filter 245 is also used to remove any out-of-band noise before Nyquist sampling at the ADC 250.

[0051] A fast detector 235 is placed at the PGA output for reliability protection. Any large input power jump (e.g., exceeding the first threshold amplitude, as mentioned above) will trigger a detection mechanism. Figure 1 The signal described above can be detected immediately by the fast detector 235 (i.e., less than 100 ns, in some cases less than 5 ns, and in others less than 0.5 ns, etc.; practically real-time or near real-time). The fast detector 235 further maximizes input attenuation to protect the receiver from large input jumps by controlling the GC circuit 240, or by sending a first signal activating the GC circuit 240, to cause a reduction in the programmable gain of the PGA, so that the resulting signal at the PGA output is below a first threshold amplitude. Compared to conventional digital detection and feedback, this short analog feedback loop provides a much faster response time (on the order of nanoseconds, e.g., as described below). Figure 4 (as described above).

[0052] In some embodiments, Figure 2 The CMOS 210, receiver 220, PGA 225, fast detector 235, GC circuit 240, RLC filter 245, and ADC 250 are respectively connected to... Figure 1 The semiconductor chip 110, receiver 120, PGA 125, fast detector 135, GC circuit 140, filter 145, and ADC 150 are similar (if not identical) and... Figure 1 The descriptions of these components also apply to Figure 2 The corresponding component in.

[0053] These and other features of Instance 200 (and its components) are discussed in this article. Figure 1 and 3 A more detailed description will follow in section 5.

[0054] Figure 3This is a schematic diagram illustrating an alternative, non-limiting example 300 of a novel integrated PGA and protection circuit according to various embodiments.

[0055] like Figure 3 As depicted in the non-limiting example 300, a fast detector 335 is located at the output of the PGA 325 to detect output oscillations of the PGA 325. Upon detection of a disruptive oscillation (e.g., a signal oscillation exceeding a first threshold amplitude or similar, as described above...), the detector... Figure 1 When described, the first signal (also known as the "activation signal"; in this case, "fdactivated" or similar) will be set high (as described). Figure 4 (As shown in the diagram), this will immediately rewrite the gain code of the digital automatic gain control (“AGC”) circuit 340, which will then place the PGA 325 in a minimum gain position or state, keeping the internal oscillation of the PGA 325 to a minimum for reliability protection. In this document, “minimum gain state” or “minimum gain position” may refer to a gain state that is the lowest gain setting of the PGA, or a gain setting within a predetermined “low” gain setting between the lowest gain setting and approximately 1%, 5%, or 10% of the maximum gain setting, or similar. After a predetermined time period (e.g., between a few nanoseconds and a few milliseconds or longer) following at least one of the following: receiving a first (or activation) signal (i.e., Figure 3 (in the context of "fd activated") or controlling the programmable gain amount (i.e., Figure 3 As the "Gain Ctrl" decreases, the digital AGC circuit 340 sends a second signal (also known as a "release signal"; in this case, "fd_release" or similar) to the fast detector 335. In response to receiving the second (or release) signal from the GC circuit 340, the fast detector 335 resets itself and the PGA 325 (i.e., the programmable gain amount) to their initial or previous state.

[0056] To further enhance the reliability of the PGA 325 and limit its output swing, a normally open (“NO”) switch 330 (also called a “normally closed switch” or similar; in this case, a clamping switch 330, etc.) is positioned differently at the output of the PGA 325. If the PGA output swing becomes very high (e.g., exceeding a first threshold amplitude or similar), the NO switch 330 will automatically turn on (or close) itself to limit the output swing. The differential NO switch 330 (or the clamping switch in this case) does not need to be a large switch; in this way, its impact on receiver performance can be minimized (compared to a large switch that has a significant impact on receiver performance). Even without protection circuitry, the differential NO switch 330 enhances the inherent receiver reliability, resulting in a longer lifespan under the same stress of high input power.

[0057] In some embodiments, Figure 3 The semiconductor chip 310, receiver 320, PGA 325, fast detector 335, digital AGC circuit 340, and ADC 350 are respectively connected to... Figure 1 The semiconductor chip 110, receiver 120, PGA 125, fast detector 135, GC circuit 140, and ADC 150 are similar (if not identical) and are for... Figure 1 The descriptions of these components also apply to Figure 3 The corresponding component in.

[0058] These and other features of Instance 300 (and its components) are discussed in this article. Figure 1 , 2 4 and 5 will be described in more detail.

[0059] Figure 4 This describes the situation according to various embodiments where the amplified wireless signal at the output of the PGA exceeds a threshold amplitude (e.g., Figure 3 A non-limiting example of the operation of a novel integrated PGA and protection circuit (e.g., 400) is illustrated in a graphic diagram.

[0060] For wireless device applications (e.g., wireless base station applications, wireless transceiver applications, etc.), the receiver needs to withstand up to 10 dBm within 10 ns (or less). Figure 4 The symbol used in the Chinese text is "Gundam P". max Large input jumps (in the presence of "or similar terms") Figure 4 The symbol "T" is used in Chinese. rise (or similar terms). Achieving reliability protection in off-chip components within such a short timeframe is difficult. Using Figures 1 to 3 The integrated PGA and protection circuits enable rapid analog signal protection.

[0061] In suchFigure 4 In the fast detector timing diagram depicted in non-limiting example 400, the fast detector (e.g., Figures 1 to 3 A fast detector such as 135, 235, or 335 monitors the PGA output oscillation (which can contain 10 mV to 100 mV or higher, especially if no protection circuitry is used). Once the oscillation reaches a certain threshold (e.g., a first threshold amplitude, as mentioned above...), the detector detects the oscillation. Figure 1 As described above, the first signal (or activation signal; in this case, "fd_activated" or similar) will be triggered high and immediately set the PGA (e.g., Figures 1 to 3 The PGA 125, 225, or 325, etc., are rewritten to minimum gain (e.g., Figure 4 The digital signal waveform “fd_activated” transitions from low to high as depicted in the image, which corresponds to the arrow representing the threshold amplitude at the receiver input corresponding to the first threshold amplitude at the PGA output, to protect receiver reliability. Simultaneously, the first (or activated) signal is sent to the back-end digital decision feedback equalizer circuit (“DFE”; similar to…). Figures 1 to 3 (GC circuits such as 140, 240, or 340). After a predefined time (e.g., between a few nanoseconds and a few milliseconds or longer), the DFE GC circuit sends a second signal (also called a "release signal"; in this case, "fd_release" or similar) to reset the fast detector to its initial position and begin monitoring the PGA output again (where the PGA is reset to its initial or previous gain state; such as...). Figure 4 The digital signal waveform “fd_release” transitions from low to high, followed by the digital signal waveform “fd_activated” transitioning from high to low, and then the digital signal waveform “fd_release” transitioning from high to low (as depicted in the diagram), until the next sudden jump in the receiver input.

[0062] Table 1 below shows the simulated reliability of the receivers.

[0063] Element 1: Comparison of the reliability of analog receivers.

[0064]

[0065] Baseline receivers—that is, receivers with integrated PGA and ADC on the same semiconductor chip but without fast detectors or clamping switches (or other normally off switches)—experience poor reliability. As shown in Table 1 above, such baseline receivers will have a lifespan of less than 0.001 years (or less than ~9 hours).

[0066] For receivers that integrate a PGA and ADC on the same semiconductor chip, as well as a clamping switch or other normally off switch located at or added to the differential output of the PGA, the maximum PGA output swing is clamped. The reliability of such receivers is significantly improved (in this case, to approximately 0.1 years or approximately 36.5 days).

[0067] As shown in Table 1, for receivers with an integrated PGA and ADC on the same semiconductor chip, and a fast detector integrated with the PGA output, the maximum PGA output swing is limited. The reliability of such receivers is further improved (in this case, improved to greater than 10 years). Similarly, for receivers with an integrated PGA and ADC on the same semiconductor chip, a fast detector integrated with the PGA output, and a clamping switch or other normally-off switch placed at or added to the differential output of the PGA, the maximum PGA output swing is clamped. The reliability of such receivers is also further improved (in this case, improved to greater than 10 years) compared to the receivers without a fast detector described above. In other words, a fully reliable receiver (with a lifespan of more than 10 years) is obtained once at least a fast detector is used, or once both a fast detector and a clamping switch (or other normally-off switch) are used.

[0068] Figure 5A and 5B (collectively referred to as "Figure 5") is a flowchart illustrating a method 500 for implementing a novel integrated PGA and protection circuit according to various embodiments. Figure 5B Method 500 returns to the circled symbol represented as "A". Figure 5A .

[0069] Although the techniques and processes are depicted and / or described in a certain order for illustrative purposes, it should be understood that certain processes may be rearranged and / or omitted within the scope of various embodiments. Furthermore, although the method 500 illustrated by FIG5 can be derived from or used by… Figure 1 , 2 Systems, instances, or embodiments 100, 200, 300, and 400 (or components thereof) of 3 and 4 are implemented respectively (and in some cases, will be described hereinafter with respect to these systems, instances, and embodiments), but such methods may also be implemented using any suitable hardware (or software) implementation. Similarly, although Figure 1 , 2 Each of the systems, instances, or embodiments 100, 200, 300, and 400 (or components thereof) can be operated according to the method 500 illustrated in FIG. 5 (e.g., by executing instructions embodied on a computer-readable medium), but Figure 1 , 2The systems, instances, or embodiments 100, 200, 300, and 400 may also operate and / or perform other suitable processes according to other operating modes.

[0070] exist Figure 5A In a non-limiting embodiment, method 500 at block 505 includes receiving wireless signals directly or indirectly from an antenna using a programmable gain amplifier (“PGA”) disposed on a semiconductor chip. In some cases, the semiconductor chip includes complementary metal-oxide-semiconductor (“CMOS”) chips, etc.

[0071] Method 500 includes using a PGA at block 510 to amplify a wireless signal received directly or indirectly from an antenna based on a programmable gain. Method 500 further includes using a PGA and outputting the amplified wireless signal at the output of the PGA (block 515).

[0072] Method 500 further includes, at block 520, in response to the amplified wireless signal exceeding a first threshold amplitude (“over-amplified wireless signal”), using protection circuitry disposed on a semiconductor chip to prevent the over-amplified wireless signal from being relayed to an analog-to-digital converter (“ADC”) disposed on the semiconductor chip. In some cases, the first threshold amplitude (e.g., 100 millivolts, etc.) includes one of a predetermined threshold amplitude value or an adjustable threshold amplitude value.

[0073] However, method 500 further includes, when the amplified wireless signal does not exceed a first threshold amplitude, using protection circuitry to allow the amplified wireless signal to be relayed to the ADC to convert the amplified wireless signal into a digital signal (block 525). Then, method 500 returns to the process at block 505 to continue receiving wireless signals from the antenna.

[0074] refer to Figure 5B In some embodiments, the protection circuitry includes a detector and a gain control (“GC”) circuitry. In this case, preventing over-amplified wireless signals from being relayed to the ADC (at block 520) includes using the detector to send a first signal activating the GC circuitry in response to detecting a spike in the gain at the PGA output exceeding a first threshold amplitude (block 530); and using the GC circuitry to control a reduction in the programmable gain amount in response to receiving the first signal so that the resulting signal at the PGA output is below the first threshold amplitude (block 535). According to some embodiments, method 500 further includes sending a second signal to the detector using the GC circuitry after a predetermined time period following at least one of the following: receiving the first signal or controlling a reduction in the programmable gain amount (block 540); and using the detector to reset the second signal to an initial monitoring state (e.g., monitoring the state of the PGA output prior to GC circuitry activation, or the like) in response to receiving the second signal from the GC circuitry (block 545).

[0075] Method 500 returns to the circled marker represented as "A". Figure 5A The process at box 505 in the diagram is to continue receiving wireless signals from the antenna.

[0076] Alternatively or additionally, the protection circuitry includes (or further includes) a normally open (“NO”) switch disposed on a semiconductor chip, which bridges the output of the PGA to either ground (terminal or point) or a second output of the PGA. In some examples, preventing over-amplified wireless signals from being relayed to the ADC (at block 520) includes using the NO switch to cause a closed circuit in response to the amplified wireless signal exceeding a first threshold amplitude, thereby clamping or limiting the output of the PGA (block 550). Method 500 further includes using the NO switch to cause a closed circuit in response to the amplified wireless signal dropping below the first threshold amplitude, thereby allowing the amplified wireless signal to be relayed to the ADC.

[0077] Method 500 returns to the circled marker represented as "A". Figure 5A The process at box 505 in the diagram is to continue receiving wireless signals from the antenna.

[0078] although Figure 1 Not shown in section 5, but instead of connecting the fast detector to the PGA output, the fast detector can be connected to the receiver output or the PGA input, and the first threshold amplitude will correspond to the receiver's threshold amplitude. Other components, features, and functions are the same as those described above. Figure 1 Similar to (if not identical to) the description in 5.

[0079] While specific features and aspects have been described with respect to some embodiments, those skilled in the art will recognize that many modifications are possible. For example, the methods and processes described herein can be implemented using hardware components, software components, and / or any combination thereof. Furthermore, while the various methods and processes described herein may be described with respect to specific structural and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any particular structural and / or functional architecture, but can be implemented on any suitable hardware, firmware, and / or software configuration. Similarly, while a particular function may be attributed to a particular system component, this function is not necessarily limited thereto unless the context otherwise indicates, and may be distributed among various other system components according to several embodiments.

[0080] Furthermore, although the processes of the methods and procedures described herein are presented in a specific order for ease of description, various processes may be reordered, added, and / or omitted according to various embodiments unless the context otherwise indicates. Moreover, the processes described with respect to a method or procedure may be incorporated into other described methods or procedures; similarly, system components described with respect to a particular architecture and / or a system may be organized in an alternative architecture and / or incorporated into other described systems. Therefore, although various embodiments with or without specific features are described for ease of description and illustration of some aspects of these embodiments, various components and / or features described herein with respect to specific embodiments may be replaced, added, and / or subtracted from other described embodiments unless the context otherwise indicates. Therefore, although several embodiments have been described above, it will be understood that the invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A circuit comprising: A programmable gain amplifier (PGA) is mounted on a semiconductor chip and is configured to receive wireless signals received directly or indirectly from an antenna as input, and to output an amplified wireless signal at the output of the PGA based on amplifying the wireless signal to a programmable gain. An analog-to-digital converter (ADC) is disposed on the semiconductor chip and is configured to convert the amplified wireless signal received directly or indirectly from the PGA into a digital signal. A protection circuit, disposed on the semiconductor chip, is configured to control a reduction in the programmable gain amount in response to detecting a spike in the gain at the output of the PGA exceeding a first threshold amplitude, so that the resulting signal at the output of the PGA is below the first threshold amplitude; and A normally open "NO" switch, disposed on the semiconductor chip, bridges the output of the PGA with either ground or a second output of the PGA. The NO switch is configured to close the circuit in response to the amplified wireless signal exceeding a second threshold amplitude, thereby clamping or limiting the output of the PGA.

2. The circuit of claim 1, wherein the protection circuit includes a detector and a gain control "GC" circuit, wherein the detector is configured to send a first signal activating the GC circuit in response to detecting a spike in the gain at the output of the PGA exceeding the first threshold amplitude, and to reset to a state monitoring the output of the PGA prior to activation of the GC circuit in response to receiving a second signal from the GC circuit, wherein the GC circuit is configured to control the reduction of the programmable gain amount in response to receiving the first signal, and to send the second signal to the detector after a predetermined time period following at least one of the following: receiving the first signal or controlling the reduction of the programmable gain amount.

3. The circuit of claim 1, wherein controlling the reduction of the programmable gain amount includes controlling the programmable gain amount to a minimum gain state.

4. The circuit according to claim 1, wherein the NO switch comprises at least one of a clamping switch, a load switch, or a combination of control logic and a transistor switch.

5. The circuit according to claim 1, wherein the second threshold amplitude is the same as the first threshold amplitude.

6. The circuit of claim 1, wherein the semiconductor chip comprises a complementary metal-oxide-semiconductor (CMOS) chip.

7. The circuit according to claim 1, further comprising: A filter is placed between the PGA and the ADC.

8. The circuit of claim 7, wherein the filter comprises at least one of a resistor-inductor-capacitor (RLC) filter, a high-pass filter, a band-pass filter, or a low-pass filter.

9. An apparatus comprising: antenna; The circuit includes: Complementary metal-oxide-semiconductor (CMOS) chips; A programmable gain amplifier "PGA" is disposed on the CMOS chip, the PGA being configured to amplify wireless signals received directly or indirectly from the antenna based on a programmable gain, and output the amplified wireless signals at the output of the PGA; An analog-to-digital converter (ADC) disposed on the CMOS chip, the ADC being configured to convert the amplified wireless signal received directly or indirectly from the PGA into a digital signal; and A protection circuit, integrated on the CMOS chip along with at least one of the PGA and the ADC, is configured to prevent an amplified wireless signal exceeding a first threshold amplitude from being input to the ADC. The protection circuit includes a normally open "NO" switch bridging one of the output of the PGA to ground or a second output of the PGA. The NO switch is configured to close the circuit in response to the amplified wireless signal exceeding a second threshold amplitude, thereby clamping or limiting the output of the PGA.

10. The device of claim 9, wherein the protection circuitry includes a detector and a gain control "GC" circuitry, wherein the detector is configured to send a first signal activating the GC circuitry in response to detecting a spike in the gain at the output of the PGA exceeding the first threshold amplitude, and to reset to a state monitoring the output of the PGA prior to activation of the GC circuitry in response to receiving a second signal from the GC circuitry, wherein the GC circuitry is configured to control a reduction in the programmable gain amount in response to receiving the first signal, such that the resulting signal at the output of the PGA is below the first threshold amplitude, and to send the second signal to the detector after a predetermined time period following at least one of the following: receiving the first signal or controlling the reduction in the programmable gain amount.

11. The device of claim 10, wherein controlling the reduction of the programmable gain amount includes controlling the programmable gain amount to a minimum gain state.

12. The device of claim 9, wherein the NO switch comprises at least one of a clamping switch, a load switch, or a combination of control logic and a transistor switch.

13. The device of claim 9, wherein the circuit further comprises: A filter disposed between the PGA and the ADC, wherein the filter comprises at least one of a resistor-inductor-capacitor (RLC) filter, a high-pass filter, a band-pass filter, or a low-pass filter.

14. A method comprising: Use a programmable gain amplifier (PGA) mounted on a semiconductor chip to amplify wireless signals received directly or indirectly from the antenna based on the programmable gain. Use the PGA and output the amplified wireless signal at the output of the PGA; In response to the amplified wireless signal exceeding a first threshold amplitude, a protection circuit disposed on the semiconductor chip is used to prevent the over-amplified wireless signal from being relayed to the analog-to-digital converter "ADC" disposed on the semiconductor chip. The protection circuit includes a normally open "NO" switch bridging one of the output of the PGA and the ground or a second output of the PGA. The NO switch is configured to close the circuit in response to the amplified wireless signal exceeding a second threshold amplitude, thereby clamping or limiting the output of the PGA. as well as When the amplified wireless signal does not exceed the first threshold amplitude, the protection circuit allows the amplified wireless signal to be relayed to the ADC to convert the amplified wireless signal into a digital signal.

15. The method of claim 14, wherein the protection circuit comprises a detector and a gain control "GC" circuit, wherein: Preventing the over-amplified wireless signal from being relayed to the ADC includes using the detector to send a first signal activating the GC circuit in response to detecting a spike in the gain at the output of the PGA that exceeds the first threshold amplitude; In response to receiving the first signal, the GC circuit is used to control the reduction of the programmable gain so that the signal obtained at the output of the PGA is lower than the first threshold amplitude; The method further includes: A second signal is sent to the detector using the GC circuit after a predetermined time period following the receipt of the first signal or the reduction of the programmable gain; and In response to receiving the second signal from the GC circuit, the detector is reset to a state that monitors the output of the PGA that occurred before the activation of the GC circuit.

16. The method of claim 14, wherein the NO switch is disposed on the semiconductor chip, the NO switch bridging the output of the PGA with one of the PGA's ground or a second output, wherein preventing the over-amplified wireless signal from being relayed to the ADC comprises using the NO switch to cause a closed circuit in response to the amplified wireless signal exceeding the first threshold amplitude, thereby clamping or limiting the output of the PGA.

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