Implementation method and device of instruction function model, electronic equipment and storage medium

Abstract

Embodiments of the present disclosure provide an implementation method and device of an instruction function model, an electronic device and a storage medium. The implementation method of the instruction function model comprises: obtaining an object instruction conforming to a first instruction set and to be translated from the first instruction set to a second instruction set, wherein the first instruction set is an extension of the second instruction set; filling, into a memory space of a target computer, a target instruction code corresponding to a system operation code and a function supported by the target computer and the object instruction, wherein the target computer supports running the second instruction set; and executing the system operation code and the target instruction code to implement simulation of a function of the object instruction. The method can implement the universality of, for example, AVX-512 instructions through binary translation, and can efficiently and quickly implement the function model of the AVX-512 instructions on more computers through binary translation.

Description

Technical Field

[0001] The embodiments of this disclosure relate to a method for implementing an instruction function model, an apparatus for implementing an instruction function model, an electronic device, and a storage medium. Background Technology

[0002] Binary translation is a method of recompiling binary machine code, translating instruction sequences from source instruction set machine code to target instruction set machine code. In functional models or instruction set simulations, the target instruction set and the source instruction set may be the same. The simulation computer uses the instruction set supported by the target instruction set to simulate the functionality of the source instruction set. For example, when implementing an x86 instruction set functional model, binary translation can be used to translate the instruction sequence to obtain the corresponding x86 instruction sequence, which is then run on a computer with an x86 microarchitecture to obtain the simulated instruction sequence result. Similarly, when implementing an ARMv9 instruction set functional model, binary translation can be used to translate the instruction sequence to obtain the corresponding ARMv9 instruction sequence, which is then run on a computer with an ARMv9 microarchitecture to obtain the simulated instruction sequence result. However, even if the source and target instruction sets are the same, binary translation still needs to handle the switching and transfer between the simulation environment and the computer environment, as well as the implementation of the instruction set system functionality. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a method for implementing an instruction function model, comprising: acquiring an object instruction that conforms to a first instruction set and is to be translated from the first instruction set to a second instruction set, wherein the first instruction set is an extension of the second instruction set; filling the memory space of a target computer with system operation code supported by the target computer and target instruction code whose functions correspond to the object instruction, wherein the target computer supports running the second instruction set; and executing the system operation code and the target instruction code to simulate the function of the object instruction.

[0004] For example, in the implementation method of the instruction function model provided in at least one embodiment of this disclosure, the step of filling the memory space of the target computer with the system operation code supported by the target computer and the target instruction code corresponding to the object instruction includes: when the vector length of the object instruction is less than the corresponding length, replacing the object instruction with one target instruction conforming to the second instruction set; when the vector length of the object instruction is equal to the corresponding length, replacing the object instruction with at least two target instructions conforming to the second instruction set.

[0005] For example, in the implementation method of the instruction function model provided in at least one embodiment of this disclosure, the implementation method of the instruction function model further includes: concatenating at least two parts of the calculation results obtained by the at least two target instructions respectively and writing them back to the target operand.

[0006] For example, in the implementation method of the instruction function model provided in at least one embodiment of this disclosure, when the object instruction is replaced by two target instructions supported by the target computer, the implementation method of the instruction function model further includes: dividing the effective bit width of the vector operand of the object instruction into a first part and a second part in half; calculating the first part using the first target instruction of the two target instructions, and temporarily storing the first calculation result; calculating the second part using the second target instruction of the two target instructions, and concatenating the second calculation result with the first calculation result to form a final calculation result; and writing the final calculation result back to the destination operand in one go.

[0007] For example, in the implementation method of the instruction function model provided in at least one embodiment of this disclosure, the step of using the second target instruction of the two target instructions to calculate the second part and concatenating the obtained second calculation result with the first calculation result to form the final calculation result includes: taking either the first calculation result or the second calculation result as the consecutive high bits of the final calculation result, and taking the other of the first calculation result and the second calculation result as the consecutive low bits of the final calculation result.

[0008] For example, in the implementation method of the instruction function model provided in at least one embodiment of this disclosure, the implementation method of the instruction function model further includes: when the object instruction enables static rounding control, rewriting the value of the register in the target computer used to store the field indicating static rounding control to the value indicating the rounding mode of static rounding control.

[0009] For example, in the implementation method of the instruction function model provided in at least one embodiment of this disclosure, the implementation method of the instruction function model further includes: when the object instruction enables anomaly suppression, rewriting the value of the register in the target computer used to store the field indicating anomaly suppression to the value indicating the anomaly suppression mode.

[0010] For example, in the implementation method of the instruction function model provided in at least one embodiment of this disclosure, the implementation method of the instruction function model further includes: decoding the object instruction to identify the object instruction and obtain the instruction information of the object instruction, wherein the instruction information includes instruction functions, and the instruction functions include extended functions of the first instruction set relative to the second instruction set.

[0011] For example, in the implementation method of the instruction function model provided in at least one embodiment of this disclosure, the extended function includes an operation mask function that prevents specified data elements from participating in calculation and exception flag updates. The execution of the system operation code and the target instruction code to simulate the function of the object instruction includes: calculating the effective range of the instruction's read and write operations based on the mask register value used by the object instruction before performing read and write operations, and performing exception checks on the read and write operations.

[0012] For example, in the implementation method of the instruction function model provided in at least one embodiment of this disclosure, the implementation method of the instruction function model further includes: if the read / write operation is a read operation on the source operand and the read operation is not abnormal, before executing the read operation, determining whether it is necessary to read each data element of the source operand according to the mask register value; or if the read / write operation is a write operation on the destination operand and the write operation is not abnormal, before executing the write operation, determining whether it is necessary to write each data element of the destination operand according to the mask register value.

[0013] For example, in the implementation method of the instruction function model provided in at least one embodiment of this disclosure, the implementation method of the instruction function model further includes: when there is a data element in the source operand that is masked by the mask register value, not reading the data element in the source operand that is masked by the mask register value; when there is a data element in the destination operand that is masked by the mask register value, not writing the data element in the destination operand that is masked by the mask register value.

[0014] For example, in the implementation method of the instruction function model provided in at least one embodiment of this disclosure, the implementation method of the instruction function model further includes: when the source operand is in floating-point format and the object instruction does not enable static rounding control or anomaly suppression, replacing the floating-point data elements covered by the mask in the source operand according to the mask register value, so that the floating-point data elements covered by the mask will not produce anomalies in the calculation.

[0015] For example, in the implementation method of the instruction function model provided in at least one embodiment of this disclosure, the implementation method of the instruction function model further includes: when the object instruction enables the embedded broadcast function, copying the operands read by the read operation to obtain the final valid operand vector.

[0016] For example, in the implementation method of the instruction function model provided in at least one embodiment of this disclosure, the object instruction conforms to the AVX-512 instruction set, and the target instruction code conforms to a vector extended instruction set that is different from the AVX-512 instruction set.

[0017] At least one embodiment of this disclosure also provides an apparatus for implementing an instruction function model, the apparatus comprising: an acquisition unit configured to acquire an object instruction conforming to a first instruction set and to be translated from the first instruction set to a second instruction set, wherein the first instruction set is an extension of the second instruction set; a filling unit configured to fill the memory space of a target computer with system operation code supported by the target computer and target instruction code whose functions correspond to the object instruction, wherein the target computer supports running the second instruction set; and an execution unit configured to execute the system operation code and the target instruction code to simulate the function of the object instruction.

[0018] At least one embodiment of this disclosure also provides an electronic device, the electronic device comprising: a memory configured to store computer-executable instructions; and a processor configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the method as described in any of the foregoing embodiments.

[0019] At least one embodiment of this disclosure also provides a non-transitory storage medium for non-transitory storage of computer-executable instructions, wherein, when the computer-executable instructions are executed by a processor, the method described in any of the above embodiments is implemented. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0021] Figure 1 A schematic diagram of a binary translation process is shown.

[0022] Figure 2 A schematic diagram of the memory space code for binary translation is shown.

[0023] Figure 3 A flowchart illustrating an implementation method of an instruction function model provided in at least one embodiment of this disclosure is shown.

[0024] Figure 4 A schematic diagram of a binary translation process provided by at least one embodiment of the present disclosure is shown.

[0025] Figure 5A schematic diagram illustrating the modeling of memory access functionality in binary translation provided by at least one embodiment of this disclosure is shown.

[0026] Figure 6 A schematic diagram illustrating instruction function modeling in binary translation is provided in at least one embodiment of this disclosure.

[0027] Figure 7 A schematic diagram of an implementation apparatus for an instruction function model provided in at least one embodiment of the present disclosure is shown.

[0028] Figure 8 A schematic diagram of an electronic device provided in at least one embodiment of the present disclosure is shown.

[0029] Figure 9 A schematic diagram of a non-transitory storage medium provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0031] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0032] To keep the following description of embodiments of the present disclosure clear and concise, detailed descriptions of certain known functions and components are omitted.

[0033] Functional models are a crucial component of circuit design verification. In hardware simulation, the functional model runs alongside the simulated circuit, and the results are compared to verify the design's correctness. Functional models can also be used in software simulation to model software execution and verify its correctness. The functional model of a Central Processing Unit (CPU) typically simulates the CPU's functionality at the instruction set architecture level, encompassing the instruction behaviors of different instruction sets.

[0034] Different CPUs support different instruction sets. The major categories of computer instruction sets on the market include x86, ARM, and MIPS. Each major instruction set category contains different instruction subsets, which cover different categories of instructions. However, different instruction subsets can share the same major instruction set system programming functions (e.g., segment and page table protection, system register control, operating modes, etc.).

[0035] For example, the AVX, AVX2, and AVX-512 instruction sets are all subsets of the x86 instruction set, with the AVX-512 instruction set being an extension of the AVX and AVX2 instruction sets. The AVX-512 instruction set provides extended functionality not found in the AVX and AVX2 instruction sets themselves. This extended functionality includes features such as larger bit widths and more vector registers, embedded broadcast, vector element operation masks, static rounding mode, suppress all exceptions, and compressed Disp8*N encoding. The AVX-512 instructions also provide extensions to most of the functionality already present in the AVX and AVX2 instructions. For example, AVX-512 instructions provide instructions with the same operational capabilities as the AVX and AVX2 instructions, but with different encoding prefixes. For example, AVX-512 instructions implement an extension from 256 bits to 512 bits and other new features (e.g., AVX-512 instructions can have vector element operation masks).

[0036] Figure 1 A schematic diagram of a binary translation process is shown. For example, as... Figure 1 As shown, the method for implementing the instruction function model through binary translation includes the following steps S1-S4.

[0037] Step S1: The machine code of the object instruction to be translated in the decoding and parsing program is identified, and all necessary instruction information such as the instruction function, instruction set, and operands of the object instruction is obtained.

[0038] Step S2: Fill the memory space of the target computer on which the instruction function model will eventually run with the system-related function code or system operation code that the target computer supports running. The system-related function code or system operation code is used to implement functions such as memory access, page table translation, and exception checking.

[0039] Step S3: Fill the target instruction code corresponding to the function of the object instruction (or source instruction) into the memory space of the target computer, so as to implement the basic function of the object instruction (e.g., addition, subtraction, multiplication, division, etc.) using the target instructions supported by the target computer.

[0040] Step S4 causes the program to jump to the target computer's memory space and execute the code filled in steps S2 and S3 to complete the simulation of the object instruction function.

[0041] The simulation ends after executing the code filled in steps S2 and S3 in the target computer's memory space.

[0042] Figure 2 A schematic diagram of memory space code for binary translation is shown. For example, Figure 1 The memory space code obtained from steps S2 and S3 of the binary translation is as follows: Figure 2 As shown. The translated system operation code may include a series of function calls (e.g., Figure 2 The system operation code in the target instruction set includes calls to functions A, B, and a series of other functions. These functions implement the system operation functions of the target instruction (such as memory access, page table translation, and exception checking). These functions are compiled into the main program of the functional model and are called in the memory space of the target computer. For example, the translated target instruction code includes switching between the simulation environment and the computer environment. When the computer supports the source instruction set, this binary translation often includes instructions with the same instruction names as the source instructions (such as...). Figure 2 The ADD in the code may be used, but the operands and addressing modes may differ. For example, ... Figure 2As shown, the RAX register used by the source instruction is stored at the address addr_rax in the simulation environment. When the "MOV RAX, [addr_rax]" instruction is executed on the computer, the value of the RAX register in the simulation environment is copied to the computer environment. The RBX register used by the source instruction is stored at the address addr_rbx in the simulation environment. When the "MOV RBX, [addr_rbx]" instruction is executed on the computer, the value of the RBX register in the simulation environment is copied to the computer environment. For example, the target instruction may contain the source instruction. For example, the translated target instruction "ADD RAX,RBX" is exactly the same as the source instruction. The final "MOV [addr_rax],RAX" instruction of the target instruction stores the final result obtained by the computer executing the code back into the RAX register of the simulation environment.

[0043] The inventors of this disclosure noted during their research that existing binary translation relies on the computer instruction set used. If the source instruction is not supported by the computer, it cannot be directly executed on that computer, which has certain limitations. For example, the AVX-512 instruction set is a relatively new instruction set, currently only supported by some x86 processors, while other x86 processors do not support it. With existing binary translation technology, AVX-512 instructions can only be directly translated and executed on computers with these specific x86 processors, but functional emulation cannot be quickly and efficiently achieved through binary translation on other computers.

[0044] At least one embodiment of this disclosure provides a method for implementing an instruction function model, comprising: acquiring an object instruction that conforms to a first instruction set and is to be translated from the first instruction set to a second instruction set, wherein the first instruction set is an extension of the second instruction set; filling the memory space of a target computer with system operation code supported by the target computer and target instruction code whose functions correspond to the object instruction, wherein the target computer supports running the second instruction set; and executing the system operation code and the target instruction code to simulate the function of the object instruction.

[0045] The instruction function model implementation method provided in the above embodiments of this disclosure is used for binary translation. It can simulate the extended instruction set on the target computer using the instruction set before the extension, and can quickly and efficiently achieve function simulation through binary translation.

[0046] For example, in at least one embodiment, a vector extended instruction set (e.g., AVX and / or AVX2 instruction sets) that is different from the AVX-512 instruction set but from which the AVX-512 instruction set is extended is used as the target instruction to replace the AVX-512 instruction. This achieves AVX-512 instruction function simulation based on binary translation, without requiring computer support for the AVX-512 instruction set, thus improving the versatility of binary translation technology in achieving AVX-512 instruction function simulation. Furthermore, the binary translation technology provided in at least one embodiment of this disclosure is indiscriminately applicable to most AVX-512 instructions, eliminating the need for separate development and debugging for each instruction, and offering advantages such as low development workload and fast development speed.

[0047] For example, in at least one embodiment, a vector extended instruction set (e.g., ARMv8 instruction set) that is different from the ARMv9 instruction set but from which the ARMv9 instruction set is extended is used as the target instruction to replace the ARMv9 instruction. This achieves ARMv9 instruction function simulation based on binary translation, without requiring computer support for the ARMv9 instruction set, thus improving the versatility of binary translation technology in ARMv9 instruction function simulation. Furthermore, the binary translation technology provided in at least one embodiment of this disclosure is indiscriminately applicable to most ARMv9 instructions, eliminating the need for separate development and debugging for each instruction, and offering advantages such as low development workload and fast development speed.

[0048] The embodiments disclosed herein do not limit the specific implementation of the first instruction set and the second instruction set.

[0049] At least one embodiment of this disclosure also provides an apparatus for implementing an instruction function model. The apparatus includes an acquisition unit, a filling unit, and an execution unit. For example, the acquisition unit is configured to acquire object instructions that conform to a first instruction set and are to be translated from the first instruction set to a second instruction set, wherein the first instruction set is an extension of the second instruction set; the filling unit is configured to fill the memory space of a target computer with system operation codes supported by the target computer and target instruction codes whose functions correspond to the object instructions, wherein the target computer supports running the second instruction set; the execution unit is configured to execute the system operation codes and the target instruction codes to simulate the function of the object instructions.

[0050] The technical effect of the instruction function model implementation device in this embodiment is the same as the technical effect of the instruction function model implementation method described above.

[0051] Several embodiments of this disclosure will now be described with reference to specific examples.

[0052] Figure 3 A flowchart illustrating an implementation method for an instruction function model provided in at least one embodiment of this disclosure is shown. Figure 3As shown, in some embodiments of this disclosure, the method for implementing the instruction function model includes the following steps S101-S103.

[0053] Step S101: Obtain object instructions that conform to the first instruction set and need to be translated from the first instruction set to the second instruction set, wherein the first instruction set is an extension of the second instruction set.

[0054] Step S102: Fill the memory space of the target computer with the system operation codes supported by the target computer and the target instruction codes corresponding to the functions and object instructions. The target computer supports running the second instruction set.

[0055] Step S103: Execute system operation code and target instruction code to simulate the function of the object instruction.

[0056] Figure 4 A schematic diagram of a binary translation process provided by at least one embodiment of this disclosure is shown. For example, as Figure 4 As shown, object instructions (e.g., AVX-512 instructions) conforming to a first instruction set (e.g., AVX-512 instruction set) and to be translated from the first instruction set to a second instruction set are obtained. For example, the first instruction set is the AVX-512 instruction set, which is an extension of the second instruction set. For example, the second instruction set can be, but is not limited to, the AVX instruction set, the AVX2 instruction set, the SSE instruction set (StreamingSIMD Extensions), etc. For example, the second instruction set of this disclosure can include any other vector extension instruction set different from the AVX-512 instruction set.

[0057] For simplicity, the following embodiments use AVX-512 instruction set as the first instruction set and AVX instruction set and / or AVX2 instruction set as the second instruction set for non-limiting explanation.

[0058] For example, such as Figure 4 As shown, after obtaining instructions that conform to the AVX-512 instruction set (hereinafter referred to as AVX-512 instructions, and instructions that conform to other instruction sets are referred to by type below), in the process of binary translation to implement the AVX-512 instruction functional model, it is necessary to execute steps S01-S04 on the AVX-512 instructions to realize the functional simulation of the AVX-512 instructions.

[0059] For example, Figure 4 Steps S01-S04 in the above are respectively with Figure 1 The steps S1-S4 are basically the same. The difference is that... Figure 4The binary translation technology also adds AVX-512-specific features to the system operation code, while using a vector extended instruction set (VLES) different from the AVX-512 instruction set as replacement instructions in the target instruction code. For example, AVX instructions or AVX2 instructions replace AVX-512 instructions in the target instruction code. Since it is not a direct translation using AVX-512 instructions, the special functions related to AVX-512 instructions that are missing from the original instructions are implemented in the system code and target code sections.

[0060] Step S01: Decode and parse the AVX-512 instruction machine code to identify the AVX-512 instruction and obtain all necessary instruction information, such as instruction function, instruction set, and operands. For example, decode the AVX-512 instruction to identify it and obtain its instruction information. This instruction information may include, for example, the instruction function, which includes the extended functionality of the AVX-512 instruction set relative to a second instruction set (e.g., the AVX instruction set or the AVX2 instruction set).

[0061] Steps S02 and S03 involve filling the target computer's memory space with the system operation codes supported by the target computer and the target instruction codes corresponding to the functions and target instructions (e.g., AVX-512 instructions). For example, the target computer supports running a second instruction set, such as AVX, AVX2, or SSE (Streaming SIMD Extensions). In this embodiment, the target computer supports the x86 instruction set, and accordingly, the target computer may include a processor that supports the x86 instruction set. Of course, in other embodiments, depending on specific examples, the target computer may support the ARM or MIPS instruction sets, and accordingly, the target computer may include a processor that supports the ARM or MIPS instruction sets.

[0062] It should be noted that, although Figure 4 The diagram shows that step S02 is performed before step S03, but this order is only exemplary. In embodiments of this disclosure, step S03 may also be performed before step S02 or simultaneously with step S02.

[0063] Step S04 involves executing system operation code and target instruction code to simulate the functionality of the target instruction (e.g., AVX-512 instruction). For example, this simulation is achieved by executing system operation code supported by the target computer and target instruction code (e.g., AVX instruction code, AVX2 instruction code, or SSE instruction code) whose functions correspond to the AVX-512 instruction, stored in the memory space of the target computer (e.g., a target computer supporting the x86 instruction set). For instance, executing system operation code and target instruction code can simulate the computational functions and other new or extended functions of the AVX-512 instruction.

[0064] For example, the functions provided by the AVX-512 instruction set can be implemented by executing system operation code and target instruction code, including but not limited to: larger bit width and more vector registers, embedded broadcast, vector element operation mask, static rounding control, exception suppression and compressed Disp8*N encoding, which will be illustrated with specific examples below.

[0065] Figure 5 This illustration shows a schematic diagram of memory access function modeling in binary translation according to at least one embodiment of this disclosure. For example, in terms of implementing system operation simulation of AVX-512 instructions, the AVX-512 instruction-specific features (e.g., features specific to AVX and AVX2 instructions) differ primarily in memory access operations. For example, embodiments of this disclosure model the relevant functions in memory access simulation of AVX-512 instructions as follows: Figure 5 The diagram includes steps S10-S50.

[0066] For example, before performing a memory access operation (e.g., a read / write operation), the valid range of the instruction's read / write operation is calculated based on the mask register value used by the object instruction (e.g., an AVX-512 instruction), and exception checking is performed on the read / write operation. For example, the valid range of the instruction's read / write operation is calculated based on the mask register value used by the AVX-512 instruction, and exception checking is performed on the read / write operation. For example, in Figure 5 In this process, step S10 is exception checking, which occurs before memory operations (e.g., read / write operations). When AVX-512 instructions have an opmask, memory access exception checking needs to take the AVX-512 instruction's opmask into account. For example, based on the opmask register value used by the AVX-512 instruction, the instruction type, the data element width (e.g., the number of elements) of the instruction's memory access operands, and the number of data elements, the valid range of the instruction's memory access is calculated, and segment, page table, and alignment exceptions are checked based on this valid range.

[0067] For example, in the AVX-512 instruction set, the operation mask is implemented using a mask register (e.g., the K register). The mask register can be, but is not limited to, a 64-bit register, where each bit corresponds to a data element and can be used to control how the instruction processes that data element. For example, each bit of the mask register can be set to 0 or 1, indicating whether the corresponding data element is processed. When executing AVX-512 instructions, the operation mask function can be implemented by passing the mask register as an instruction parameter. The instruction will determine whether to process each data element based on the settings of the mask register. This method can avoid calculating unnecessary data when processing large amounts of data, improving instruction efficiency.

[0068] For example, in masked instructions in the AVX-512 instruction set, if the i-th bit of the k register is 0, the i-th data element is not processed; if the i-th bit of the k register is 1, the i-th data element is processed. Therefore, the data elements to be calculated can be selected by setting the mask register. For example, if you want to calculate the first 16 data elements, you can set the lower 16 bits of the mask register to 1 and the remaining bits to 0. In this way, the AVX-512 instruction will only calculate the lower 16 bits of the data element. It should be noted that although 1 and 0 are used here to represent whether a data element is processed, this is only one example of this embodiment. Any value can be used to represent the corresponding data element that needs to participate in the calculation, and another different value can be used to represent the corresponding data element that does not need to participate in the calculation.

[0069] For example, if the read / write operation is a read operation on the source operand and there is no exception in the read operation, before performing the read operation, the value of the mask register is used to determine whether it is necessary to read every data element of the source operand. Or, if the read / write operation is a write operation on the destination operand and there is no exception in the write operation, before performing the write operation, the value of the mask register is used to determine whether it is necessary to write every data element of the destination operand.

[0070] For example, such as Figure 5 As shown, if the access type of the AVX-512 instruction is a read operation, step S20 reads the source operand that needs to be read. When the AVX-512 instruction has an operation mask, based on the mask register value of the AVX-512 instruction and the width of the source operand elements, each data element of the memory access source operand is checked one by one to determine whether it needs to be read. For example, as... Figure 5As shown, if the access type of the AVX-512 instruction is a write operation, step S50 writes the destination operand that needs to be written. When the AVX-512 instruction has an operation mask, the mask register value of the AVX-512 instruction and the width of the destination operand element are used to determine whether each data element of the memory access destination operand needs to be written.

[0071] For example, if there are data elements in the source operand that are masked by the value of the mask register, the data elements masked by the value of the mask register in the source operand are not read; if there are data elements in the destination operand that are masked by the value of the mask register, the data elements masked by the value of the mask register in the destination operand are not written.

[0072] The MXCSR is a special register in the x86 architecture used to control and handle exceptions in floating-point operations. This register contains multiple control flags and exception flags, which can be used to control the precision, rounding method, and exception handling of floating-point operations. The exception flags indicate whether an exception has occurred during floating-point operations, such as division by zero, overflow, or invalid operations.

[0073] For example, when the source operand is in floating-point format and the object instruction does not have static rounding control or exception suppression enabled, the floating-point data elements in the source operand that are covered by the mask are replaced according to the mask register value, so that the floating-point data elements covered by the mask will not cause exceptions during calculation. For example, Figure 5 Step S30 in the text involves floating-point data element replacement. When the AVX-512 instruction operand is in floating-point format and an arithmetic mask is used without static rounding control or exception suppression enabled, floating-point data replacement of the source operand is required. For example, the AVX-512 arithmetic mask prevents specified data elements from participating in the calculation and update of exception flags (e.g., the MXCSR exception flag in this paper), while all data elements of the AVX instruction or AVX2 instruction used to replace the AVX-512 instruction participate in the calculation and update of the MXCSR exception flag.

[0074] To simulate the function of the computation mask, step S30 replaces floating-point data elements that do not need to participate in the calculation with 1s of the corresponding floating-point format, so as to avoid the elements that do not need to participate in the calculation affecting the calculation result of the MXCSR anomaly flag. It should be noted that although floating-point data elements that do not need to participate in the calculation are replaced with 1s of the corresponding floating-point format, the embodiments of this disclosure are not limited to this, as long as the replaced value can avoid the elements that do not need to participate in the calculation affecting the calculation result of the MXCSR anomaly flag.

[0075] The built-in broadcast function in the AVX-512 instruction set is a highly efficient data copying technique that can broadcast a data element to multiple target locations. This technique can greatly improve the efficiency of vector computation, especially when the same operation needs to be performed on large amounts of data.

[0076] For example, when an object instruction has inline broadcast enabled, the operands read in a read operation are copied to obtain the final valid operand vector. For example, when an AVX-512 instruction has inline broadcast enabled, the operands read in a read operation are copied to obtain the final valid operand vector. For example, Figure 5 Step S40 in the process simulates the function of AVX-512 embedded broadcast. When the AVX-512 instruction enables embedded broadcast, the data obtained from memory access is copied to obtain the final valid operand vector.

[0077] Static rounding control and exception suppression refer to controlling the precision of calculation results and handling of abnormal situations by setting rounding modes and exception handling methods during floating-point calculations. Static rounding control controls the precision of calculation results by setting rounding modes. Rounding modes can be set to round up, round down, round to zero, and round to the nearest whole number. This control method is static, meaning it is determined at the time of program writing and will not change due to changes in the runtime environment. Exception suppression controls the handling of abnormal situations by setting exception handling methods. Floating-point calculations may encounter various abnormal situations, such as overflow, division by zero, and infinity. Exception handling methods can be set to ignore exceptions, throw exceptions, or return a specific value. This control method is also static, meaning it is determined at the time of program writing and will not change due to changes in the runtime environment. Static rounding control and exception suppression help programmers control the precision of floating-point calculations and the handling of abnormal situations, improving the reliability and stability of the program.

[0078] For example, when an object instruction enables static rounding control, it rewrites the value of a register in the target computer that stores the field indicating static rounding control to the value indicating the rounding mode of static rounding control. For example, when an AVX-512 instruction enables static rounding control, it can rewrite the value of a register in a target computer that supports, for example, AVX or AVX2 instructions that stores the field indicating static rounding control to the value indicating the rounding mode of static rounding control.

[0079] For example, when an object instruction enables exception suppression, the value of a register in the target computer that stores a field indicating exception suppression is overwritten with a value indicating the exception suppression mode. When an AVX-512 instruction enables exception suppression, the value of a register in a target computer that supports, for example, AVX or AVX2 instructions that stores a field indicating exception suppression is overwritten with a value indicating the exception suppression mode.

[0080] Figure 6 A schematic diagram illustrating instruction function modeling in binary translation is shown, according to at least one embodiment of this disclosure. For example, as... Figure 6 As shown, when the vector length of the object instruction (e.g., an AVX-512 instruction) is less than the corresponding length, the object instruction is replaced by one target instruction (e.g., an AVX instruction or an AVX2 instruction) conforming to the second instruction set. When the vector length of the object instruction is equal to the corresponding length (e.g., 512 bits), the object instruction is replaced by at least two target instructions conforming to the second instruction set. For example, refer again... Figure 4 AVX instructions or AVX2 instructions can be used as target instructions to replace AVX-512 instructions. For example, when the vector length of an AVX-512 instruction is less than 512 bits, the target instruction is replaced by one AVX instruction or AVX2 instruction conforming to the second instruction set. Conversely, when the vector length of an AVX-512 instruction is equal to 512 bits, the target instruction is replaced by at least two AVX instructions or AVX2 instructions conforming to the second instruction set.

[0081] For example, when an AVX-512 instruction vector is 128 bits or 256 bits long, an AVX instruction or AVX2 instruction with the corresponding vector length (e.g., 128 bits or 256 bits) is used to replace that AVX-512 instruction. The execution steps of the relevant target instruction (e.g., an AVX instruction or AVX2 instruction used to replace the AVX-512 instruction) to simulate the object instruction (e.g., the AVX-512 instruction) are as follows: Figure 6 Steps S11-S33 are shown in the figure.

[0082] Step S11 prepares the source operands. Building upon the general binary translation operations on source operands, the binary translation in this embodiment of the disclosure also includes support for features specific to AVX-512 instructions. For example, with... Figure 5 Similar to step S30, when preparing the source operand for the target instruction, the source operand is a floating-point element and the source operand is stored in a register, the floating-point data elements of the source operand that do not need to participate in the calculation under the AVX-512 instruction mask are replaced with the corresponding floating-point format value 1 to form the prepared source operand.

[0083] Step S22 uses an AVX instruction or AVX2 instruction with corresponding function (e.g., addition, subtraction, multiplication, division, etc.) and vector length as the target instruction to translate the AVX-512 instruction, thereby implementing the basic computational functions of the AVX-512 instruction. The AVX instruction or AVX2 instruction with corresponding function and vector length has a different prefix format than the AVX-512 instruction, but shares the same opcode, modrm, and immediate value encoding.

[0084] After simulating the function of AVX-512 instructions by executing AVX instructions or AVX2 instructions with corresponding functions and vector lengths, step S33 writes back the calculation results of AVX instructions or AVX2 instructions with corresponding functions and vector lengths to the corresponding storage location or simulation environment register.

[0085] For example, when the AVX-512 instruction enables static rounding control or exception suppression, the MXCSR calculation result of the AVX instruction or AVX2 instruction with the corresponding function and vector length is discarded, and the MXCSR in the simulation environment is not updated; when the AVX-512 instruction enables the operation mask, the part of the destination register that is masked is not written back to the new calculation result, and the original value of the data element masked in the destination register is retained or the data element masked in the destination register is cleared, depending on whether the mask clearing is enabled.

[0086] For example, when an AVX-512 instruction uses a 512-bit vector, and the corresponding AVX or AVX2 instruction has a 256-bit vector, two corresponding AVX or AVX2 instructions can be used to simulate and replace one AVX-512 instruction for binary translation. For example, the high 256 bits and low 256 bits of the 512-bit vector of the AVX-512 instruction can be calculated separately. For example, when an AVX-512 instruction uses a 512-bit vector, and the corresponding AVX or AVX2 instruction has a 128-bit or 256-bit vector, three or four corresponding AVX or AVX2 instructions can be used to simulate and replace one AVX-512 instruction for binary translation. For example, one corresponding 256-bit vector AVX or AVX2 instruction plus two corresponding 128-bit vector AVX or AVX2 instructions can be used to simulate and replace one AVX-512 instruction for binary translation. For example, four corresponding 128-bit vector-length AVX instructions or AVX2 instructions can be used to simulate and replace one AVX-512 instruction for binary translation.

[0087] For example, the results of at least two separate calculations obtained from at least two target instructions can be concatenated and written back to the destination operand. For example, at least two AVX instructions or AVX2 instructions used to replace AVX-512 instructions can be calculated separately, and the results can be concatenated together and then written back to the corresponding storage location as the destination operand.

[0088] For example, when replacing an object instruction with two target instructions supported by the target computer, the implementation method of the instruction function model may further include: dividing the effective bit width of the vector operand of the object instruction into a first part and a second part; using the first target instruction of the two target instructions to calculate the first part, and temporarily storing the first calculation result; using the second target instruction of the two target instructions to calculate the second part, and concatenating the second calculation result with the first calculation result to form the final calculation result; and writing the final calculation result back to the destination operand in one go. In one example, the relevant target instructions (e.g., two AVX instructions or AVX2 instructions used for replacement) are used to simulate the execution steps of the object instruction (e.g., AVX-512 instructions) as follows: Figure 6 S44-S99 are shown in the figure.

[0089] For example, when replacing a 512-bit AVX-512 instruction with two 256-bit vector-length AVX instructions or AVX2 instructions supported by the target computer, the effective bit width of the vector operand of the 512-bit vector-length AVX-512 instruction can be divided in half into a continuous high-order bit portion and a continuous low-order bit portion. For example, Figure 6 Steps S44 and S77 prepare operands for two AVX instructions or AVX2 instructions. For example, this preparation operation includes dividing the effective bit width of the vector operand of a 512-bit vector-length AVX-512 instruction in half into consecutive high-order bits and consecutive low-order bits, and processing the resulting consecutive high-order bits and consecutive low-order bits separately according to the specific functions of the AVX-512 instruction (e.g., compared to AVX and AVX2 instructions) (e.g., preparing operands). For example, the source operand preparation method in steps S44 and S77 is the same as the source operand preparation method in step S11, and will not be repeated here.

[0090] For example, one of the two AVX instructions and AVX2 instructions is used to calculate the continuous high-order part, and the first calculation result is temporarily stored. The other of the two AVX instructions and AVX2 instructions is used to calculate the continuous low-order part, and the second calculation result is concatenated with the first calculation result to form the final calculation result.

[0091] For example, one of the first and second calculation results can be used as consecutive high-order bits of the final calculation result, and the other can be used as consecutive low-order bits of the final calculation result. For example, the final calculation result can be composed of consecutive high-order bits of the first calculation result and consecutive low-order bits of the second calculation result. For example, the final calculation result, formed by concatenating the first and second calculation results, can be written back to the corresponding storage location as the calculation result (or destination operand) of the simulated AVX-512 instruction.

[0092] For example, in Figure 6 Steps S55 and S88 in the process each use at least two AVX instructions or AVX2 instructions as target instructions to translate the AVX-512 instructions. The substitution operations in steps S55 and S88 (e.g., ...) Figure 6 As shown, replacing AVX-512 instructions with AVX or AVX2 instructions is similar to the replacement operation in step S22, and will not be described again here. For example, two AVX or AVX2 instructions have the same format, instruction name, and opcode.

[0093] For example, such as Figure 6 As shown, step S66 temporarily stores the result of the first part of the AVX instruction or AVX2 instruction calculated in step S55, thereby preventing the first part of the calculation result generated in step S55 from affecting the source operand of the second part (e.g., the half of the source operand needed in step S77) or from being overwritten during the second part of the calculation. For example, the bit width of the temporarily stored first part of the calculation result is half the bit width of the final destination register written back by the AVX-512 instruction.

[0094] For example, step S99 concatenates the calculation results from steps S66 and S88 and writes them back to the destination operand. For example, the two calculation results generated in steps S66 and S88 have the same bit width, representing the consecutive high and low bits of the final destination operand result, respectively. It should be noted that although... Figure 6 The diagram shows that when the vector length of the AVX-512 instruction is 512 bits, the operation steps for simulating AVX-512 instructions using AVX instructions or AVX2 instructions are performed in the order of steps S44-S99, but... Figure 6 This is merely one embodiment of the present disclosure, and the embodiments in the present disclosure are not limited thereto. For example, steps S44 and S77 can be performed simultaneously, and finally steps S55 and S88 can be concatenated to form the final calculation result and written back to the destination storage location or destination register.

[0095] The instruction function model implementation method provided in the above embodiments of this disclosure is used for binary translation. It uses a vector extended instruction set, which is different from the AVX-512 instruction set but from which the AVX-512 instruction set is extended, as the target instruction to replace the AVX-512 instruction. This achieves AVX-512 instruction function simulation based on binary translation, without requiring computer support for the AVX-512 instruction set, thus improving the versatility of binary translation technology in AVX-512 instruction function simulation. Furthermore, the binary translation technology provided in at least one embodiment of this disclosure is indiscriminately applicable to most instructions in the AVX-512 instruction set, eliminating the need for separate development and debugging for each instruction, and offering advantages such as low development workload and fast development speed.

[0096] Figure 7 A schematic diagram of an implementation apparatus for an instruction function model provided in at least one embodiment of the present disclosure is shown. For example, referring to... Figure 7 At least one embodiment of this disclosure provides an instruction function model implementation apparatus 60.

[0097] The implementation apparatus 60 for the instruction function model includes an acquisition unit 605, a filling unit 606, and an execution unit 607. For example, the acquisition unit 605 is configured to acquire object instructions (e.g., AVX-512 instruction set) that conform to a first instruction set (e.g., AVX-512 instruction set) and are to be translated from the first instruction set to a second instruction set (e.g., AVX instruction set, AVX2 instruction set, or SSE instruction set). For example, the first instruction set is an extension of the second instruction set. For example, the filling unit 606 is configured to fill the target computer's memory space with system operation codes supported by the target computer and target instruction codes whose functions correspond to the object instructions. For example, the target computer supports running the second instruction set. For example, the execution unit 607 is configured to execute the system operation codes and target instruction codes to simulate the function of the object instructions.

[0098] For example, the filling unit 606 is also configured to: when the vector length of the object instruction is less than the corresponding length, replace the object instruction with one target instruction conforming to the second instruction set; when the vector length of the object instruction is equal to the corresponding length, replace the object instruction with at least two target instructions conforming to the second instruction set.

[0099] For example, execution unit 607 is also configured to concatenate at least two parts of the calculation results obtained from at least two target instructions and write them back to the target operand.

[0100] For example, when two target instructions supported by the target computer are used to replace the object instructions, the execution unit 607 is further configured to: divide the effective bit width of the vector operand of the object instructions in half into a first part and a second part; use the first target instruction of the two target instructions to calculate the first part and temporarily store the first calculation result; use the second target instruction of the two target instructions to calculate the second part and concatenate the second calculation result with the first calculation result to form the final calculation result; and write the final calculation result back to the destination operand in one go.

[0101] For example, the execution unit 607 is further configured to: use either the first calculation result or the second calculation result as the consecutive high bits of the final calculation result, and use the other of the first calculation result and the second calculation result as the consecutive low bits of the final calculation result.

[0102] For example, execution unit 607 is also configured to: when the object instruction enables static rounding control, rewrite the value of the register in the target computer used to store the field indicating static rounding control to the value indicating the rounding mode of static rounding control.

[0103] For example, execution unit 607 is also configured to: when the object instruction enables exception suppression, rewrite the value of the register in the target computer used to store the field indicating exception suppression to the value indicating the exception suppression mode.

[0104] For example, the instruction function model implementation device 60 further includes a decoding unit configured to decode the object instruction to identify the object instruction and obtain the instruction information of the object instruction, wherein the instruction information includes instruction functions, and the instruction functions include extended functions of the first instruction set relative to the second instruction set.

[0105] For example, the extended functions include an operation mask function that excludes specified data elements from calculation and exception flag updates. The execution unit 607 is also configured to: calculate the valid range of the read and write operation of the instruction based on the mask register value used by the object instruction before performing the read and write operation, and perform exception checks on the read and write operation.

[0106] For example, the execution unit 607 is further configured to: if the read / write operation is a read operation on the source operand and there is no exception in the read operation, before executing the read operation, determine whether it is necessary to read each data element of the source operand according to the mask register value; or if the read / write operation is a write operation on the destination operand and there is no exception in the write operation, before executing the write operation, determine whether it is necessary to write each data element of the destination operand according to the mask register value.

[0107] For example, execution unit 607 is also configured to: when there is a data element in the source operand that is masked by the value of the mask register, not read the data element in the source operand that is masked by the value of the mask register; when there is a data element in the destination operand that is masked by the value of the mask register, not write the data element in the destination operand that is masked by the value of the mask register.

[0108] For example, the execution unit 607 is also configured to: when the source operand is in floating-point format and the object instruction does not enable static rounding control or exception suppression, replace the floating-point data elements covered by the mask in the source operand according to the mask register value, so that the floating-point data elements covered by the mask will not produce exceptions in the calculation.

[0109] For example, execution unit 607 is also configured to: when the object instruction enables the embedded broadcast function, copy the operands read by the read operation to obtain the final valid operand vector.

[0110] For example, in at least one example, the object instructions conform to the AVX-512 instruction set, while the target instruction code conforms to a vector extended instruction set that is different from the AVX-512 instruction set.

[0111] The instruction function model implementation apparatus provided in the above embodiments of this disclosure is used for binary translation. For example, it uses a vector extended instruction set, which is different from the AVX-512 instruction set but from which the AVX-512 instruction set is extended, as the target instruction to replace the AVX-512 instruction. This achieves AVX-512 instruction function simulation based on binary translation, without requiring computer support for the AVX-512 instruction set, thus improving the versatility of binary translation technology in AVX-512 instruction function simulation. Furthermore, the binary translation technology provided in this disclosure is applicable to most instructions in the AVX-512 instruction set without distinction, eliminating the need for separate development and debugging for each instruction, and offering advantages such as low development workload and fast development speed.

[0112] At least one embodiment of this disclosure also provides an electronic device including a memory and a processor. For example, the memory is configured to store computer-executable instructions, and the processor is configured to execute the computer-executable instructions. For example, when the computer-executable instructions are executed by the processor, they implement a method for implementing the instruction function model provided in at least one embodiment of this disclosure.

[0113] Figure 8 A schematic diagram of an electronic device provided according to at least one embodiment of the present disclosure is shown. For example... Figure 8 As shown, an electronic device 500 according to an embodiment of the present disclosure includes a processor 501 and a memory 502, which can be interconnected via a bus 503.

[0114] Processor 501 can perform various actions and processes according to the program or code stored in memory 502. Specifically, processor 501 can be an integrated circuit chip with signal processing capabilities. For example, the processor 501 can be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), off-the-shelf programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the various methods and steps disclosed in the embodiments of this disclosure. The general-purpose processor can be a microprocessor or any conventional processor, and can be an x86 architecture or an ARM architecture, etc.

[0115] The memory 502 is used for non-temporary storage of computer-executable instructions, and the processor 501 is used to run the computer-executable instructions. When the computer-executable instructions are executed by the processor 501, they implement the instruction function model provided in at least one embodiment of this disclosure.

[0116] For example, memory 502 may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct memory bus random access memory (DRRAM). It should be noted that the memory of the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0117] The electronic devices provided in the embodiments of this disclosure are used for binary translation. For example, they use a vector extended instruction set, which is different from the AVX-512 instruction set but from which the AVX-512 instruction set is extended, as the target instruction to replace the AVX-512 instruction. This achieves AVX-512 instruction function simulation based on binary translation, without requiring computer support for the AVX-512 instruction set, thus improving the versatility of binary translation technology in AVX-512 instruction function simulation. Furthermore, the binary translation technology provided in this disclosure is applicable to most instructions in the AVX-512 instruction set without distinction, eliminating the need for separate development and debugging for each instruction, resulting in advantages such as low development workload and fast development speed.

[0118] At least one embodiment of this disclosure also provides a non-transitory storage medium for non-transitory storage of computer-executable instructions. For example, when the computer-executable instructions are executed by a processor, an implementation method of the instruction function model provided in at least one embodiment of this disclosure is implemented.

[0119] Figure 9 This is a schematic diagram of a non-transitory storage medium provided in some embodiments of this disclosure. For example... Figure 9 As shown, the non-temporary storage medium 600 can non-temporarily store computer-executable instructions 610, which, when executed by a computer, implement the instruction function model implementation method provided in any embodiment of this disclosure.

[0120] Similarly, the non-transitory storage medium in the embodiments of this disclosure may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. It should be noted that the memory used in the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0121] The technical effects of the aforementioned non-transitory storage medium are the same as those of the implementation method of the aforementioned instruction function model, and will not be repeated here.

[0122] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing at least one executable instruction for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0123] In general, the various exemplary embodiments of this disclosure can be implemented in hardware or dedicated circuitry, software, firmware, logic, or any combination thereof. Some aspects can be implemented in hardware, while others can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device. When aspects of embodiments of this disclosure are illustrated or described as block diagrams, flowcharts, or using some other graphical representation, it will be understood that the blocks, apparatuses, systems, techniques, or methods described herein can be implemented as non-limiting examples in hardware, software, firmware, dedicated circuitry or logic, general-purpose hardware or controllers or other computing devices, or some combination thereof.

[0124] The following points should be noted regarding this disclosure:

[0125] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0126] (2) For clarity, the thickness and dimensions of layers or structures are enlarged in the drawings used to describe embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0127] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0128] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A method for implementing an instruction function model, comprising: Obtain object instructions that conform to a first instruction set and need to be translated from the first instruction set to a second instruction set, wherein the first instruction set is an extension of the second instruction set; Fill the memory space of the target computer with the system operation codes and target instruction codes that the target computer supports and that correspond to the object instructions, wherein the target computer supports running the second instruction set; The system operation code and the target instruction code are executed to simulate the function of the object instruction; The method for implementing the instruction function model further includes: decoding the object instruction to identify the object instruction and obtain the instruction information of the object instruction, wherein the instruction information includes instruction functions, and the instruction functions include the extended functions of the first instruction set relative to the second instruction set.

2. The method for implementing the instruction function model according to claim 1, wherein, The step of filling the target computer's memory space with the system operation codes and target instruction codes corresponding to the object instructions supported by the target computer includes: When the vector length of the object instruction is less than the corresponding length, the object instruction is replaced with a target instruction that conforms to the second instruction set. When the vector length of the object instruction is equal to the corresponding length, the object instruction is replaced with at least two target instructions that conform to the second instruction set.

3. The method for implementing the instruction function model according to claim 2 further includes: The calculation results obtained from the at least two target instructions are concatenated and written back to the target operand.

4. The method for implementing the instruction function model according to claim 3, wherein, When the object instruction is replaced by two target instructions supported by the target computer, the implementation method of the instruction function model further includes: The effective bit width of the vector operand of the object instruction is divided in half into a first part and a second part; The first part is calculated using the first target instruction of the two target instructions, and the first calculation result is temporarily stored. The second part is calculated using the second target instruction of the two target instructions, and the resulting second calculation result is concatenated with the first calculation result to form the final calculation result; and Write the final calculation result back to the destination operand in one go.

5. The method for implementing the instruction function model according to claim 4, wherein, The step of using the second target instruction from the two target instructions to calculate the second part, and concatenating the obtained second calculation result with the first calculation result to form the final calculation result, includes: Either the first calculation result or the second calculation result is taken as the consecutive high-order bits of the final calculation result, and the other of the first calculation result and the second calculation result is taken as the consecutive low-order bits of the final calculation result.

6. The method for implementing the instruction function model according to any one of claims 1-5 further includes: When the object instruction enables static rounding control, the value of the register in the target computer used to store the field indicating static rounding control is rewritten to the value indicating the rounding mode of static rounding control.

7. The method for implementing the instruction function model according to any one of claims 1-5 further includes: When the object instruction enables anomaly suppression, the value of the register in the target computer used to store the field indicating anomaly suppression is rewritten to the value indicating the anomaly suppression mode.

8. The method for implementing the instruction function model according to claim 1, wherein, The extended functionality includes an operation mask function that excludes specified data elements from computation and exception flag updates. The function of executing the system operation code and the target instruction code to simulate the object instruction includes: Before performing read / write operations, the valid range of the read / write operation is calculated based on the mask register value used by the object instruction, and anomaly checks are performed on the read / write operation.

9. The method for implementing the instruction function model according to claim 8 further includes: If the read / write operation is a read operation on the source operand and the read operation is error-free, before executing the read operation, it is determined based on the mask register value whether it is necessary to read each data element of the source operand. If the read / write operation is a write operation to the destination operand and the write operation is not abnormal, before executing the write operation, it is determined whether each data element of the destination operand needs to be written based on the mask register value.

10. The method for implementing the instruction function model according to claim 9 further includes: When there are data elements in the source operand that are masked by the value of the mask register, the data elements masked by the value of the mask register in the source operand are not read. If there are data elements in the destination operand that are masked by the value of the mask register, the data elements masked by the value of the mask register will not be written to the destination operand.

11. The method for implementing the instruction function model according to claim 9 further includes: When the source operand is in floating-point format and the object instruction does not enable static rounding control or exception suppression, the floating-point data elements covered by the mask in the source operand are replaced according to the mask register value so that the floating-point data elements covered by the mask will not cause anomalies in the calculation.

12. The method for implementing the instruction function model according to claim 9 further includes: When the object instruction enables the embedded broadcast function, the operands obtained from the read operation are copied to obtain the final valid operand vector.

13. The method for implementing the instruction function model according to any one of claims 1-5, wherein, The object instructions conform to the AVX-512 instruction set, and the target instruction code conforms to a vector extended instruction set that is different from the AVX-512 instruction set.

14. An apparatus for implementing an instruction function model, comprising: The acquisition unit is configured to acquire object instructions that conform to a first instruction set and need to be translated from the first instruction set to a second instruction set, wherein the first instruction set is an extension of the second instruction set; The filling unit is configured to fill the memory space of the target computer with the system operation codes supported by the target computer and the target instruction codes corresponding to the object instructions, wherein the target computer supports running the second instruction set; An execution unit is configured to execute the system operation code and the target instruction code to simulate the function of the object instruction; The implementation device of the instruction function model further includes a decoding unit, which is configured to decode the object instruction to identify the object instruction and obtain the instruction information of the object instruction. The instruction information includes instruction functions, and the instruction functions include extended functions of the first instruction set relative to the second instruction set.

15. An electronic device comprising: Memory, configured to store computer-executable instructions; as well as The processor is configured to execute the computer-executable instructions. Wherein, when the computer-executable instructions are executed by the processor, they implement the method according to any one of claims 1-13.

16. A non-transitory storage medium for non-transitory storage of computer-executable instructions, wherein, When the computer-executable instructions are executed by a processor, the method according to any one of claims 1-13 is implemented.

Images