Wafer warpage adjustment structure and preparation method thereof
By forming dielectric layers with different coefficients of thermal expansion on the surface or underside of the wafer, the warping problem during wafer manufacturing is solved, enabling effective leveling of complex-shaped wafers and integration of multilayer wafer systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-04-26
- Publication Date
- 2026-05-19
AI Technical Summary
During wafer manufacturing, warping occurs due to differences in the coefficients of thermal expansion of various components. Existing technologies struggle to effectively adjust local warping, especially for wafers with complex shapes.
A dielectric layer is formed on the surface or underside of the wafer. Different regions of the dielectric layer use materials with different coefficients of thermal expansion. By forming protrusions and depressions in local areas, the coefficient of thermal expansion is adjusted to improve warpage. Materials such as silicon nitride, silicon carbide, and quartz are used. Multi-layered stepped coefficient of thermal expansion gradients are formed by etching and filling.
It enables flexible and rapid adjustment of any complex warped shape, is suitable for integration of different wafer systems, and improves the reliability of wafer stacking and the integration effect of multilayer wafer systems.
Smart Images
Figure CN116995034B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor process technology, and in particular to a wafer warpage adjustment structure and its preparation method. Background Technology
[0002] Warpage occurs during wafer manufacturing as wafer size increases or thickness decreases. Warpage occurs due to the differences in the coefficients of thermal expansion (CTE) between the various components that make up a chip or semiconductor package, when chips or packages are manufactured on a wafer. Warpage refers to the undesirable bending of a semiconductor chip or semiconductor package. Summary of the Invention
[0003] In view of this, the present disclosure provides a wafer warpage adjustment structure and a method for preparing the same.
[0004] According to a first aspect of the present disclosure, a wafer warpage adjustment structure is provided, comprising:
[0005] A wafer, the wafer including an upper surface and a lower surface disposed opposite each other, the upper surface being used to form a semiconductor device;
[0006] A dielectric layer located on the upper or lower surface of the wafer;
[0007] The dielectric layer includes a first region and / or a second region, and further includes other regions besides the first region and / or the second region; wherein,
[0008] The first region covers the portion of the wafer that protrudes in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer when the wafer is in an independent state; the second region covers the portion of the wafer that is recessed in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer when the wafer is in an independent state; the coefficient of thermal expansion of the material of the first region is greater than the coefficient of thermal expansion of the material of the wafer; the coefficient of thermal expansion of the material of the second region is less than the coefficient of thermal expansion of the material of the wafer.
[0009] In some embodiments, the material of the first region of the dielectric layer includes silicon nitride or silicon carbide;
[0010] The material of the second region of the dielectric layer includes quartz.
[0011] In some embodiments, the coefficient of thermal expansion of the material in the first region of the dielectric layer is greater than the coefficient of thermal expansion of the material in other regions of the dielectric layer;
[0012] The coefficient of thermal expansion of the material in the second region of the dielectric layer is less than that of the material in other regions of the dielectric layer.
[0013] In some embodiments, the thickness of the first region of the dielectric layer is greater than or equal to the thickness of other regions of the dielectric layer.
[0014] In some embodiments, the thickness of the first region of the dielectric layer is 1 to 4 times the thickness of the other regions of the dielectric layer.
[0015] In some embodiments, the dielectric layer of the first region comprises multiple dielectric layers, and the coefficient of thermal expansion of the material of each dielectric layer in the first region decreases in a stepwise manner in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer.
[0016] In some embodiments, the dielectric layer of the second region comprises multiple dielectric layers, and the coefficient of thermal expansion of the material of each dielectric layer in the second region increases in a stepwise manner in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer.
[0017] In some embodiments, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region of the dielectric layer decreases in a stepwise manner.
[0018] In some embodiments, along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region of the dielectric layer increases in a stepwise manner.
[0019] According to a second aspect of the present disclosure, a method for preparing a wafer warp adjustment structure is provided, comprising:
[0020] A wafer is provided, the wafer including a warped region; the wafer includes an upper surface and a lower surface disposed opposite to each other, the upper surface being used to form a semiconductor device;
[0021] A dielectric layer is formed on the upper or lower surface of the wafer;
[0022] The dielectric layer includes a first region and / or a second region, and further includes other regions besides the first region and / or the second region; wherein,
[0023] The first region covers the portion of the wafer warp region that protrudes in a direction perpendicular to the wafer surface and extending from the wafer into the dielectric layer, and the second region covers the portion of the wafer warp region that is recessed in a direction perpendicular to the wafer surface and extending from the wafer into the dielectric layer; the coefficient of thermal expansion of the material of the first region is greater than the coefficient of thermal expansion of the material of the wafer; the coefficient of thermal expansion of the material of the second region is less than the coefficient of thermal expansion of the material of the wafer.
[0024] In some embodiments, the coefficient of thermal expansion of the material in the first region of the dielectric layer is greater than the coefficient of thermal expansion of the material in other regions of the dielectric layer;
[0025] The coefficient of thermal expansion of the material in the second region of the dielectric layer is less than that of the material in other regions of the dielectric layer.
[0026] In some embodiments, forming a dielectric layer on the upper or lower surface of the wafer includes:
[0027] A dielectric layer pre-layer is formed on the upper or lower surface of the wafer;
[0028] Etching a portion of the dielectric prelayer in the first region to form a first trench; filling the first trench with a first material, the first material having a coefficient of thermal expansion greater than that of the wafer material; and / or
[0029] The portion of the dielectric prelayer in the second region is etched to form a second trench; the second trench is filled with a second material, the coefficient of thermal expansion of which is less than that of the material of the wafer.
[0030] In some embodiments, the warped region of the wafer is shaped like a saddle or a wave.
[0031] In some embodiments, the thickness of the first region of the dielectric layer is greater than or equal to the thickness of other regions of the dielectric layer.
[0032] In some embodiments, the thickness of the first region of the dielectric layer is 1 to 4 times the thickness of the other regions of the dielectric layer.
[0033] In some embodiments, the dielectric layer of the first region comprises multiple dielectric layers, and the coefficient of thermal expansion of the material of each dielectric layer in the first region decreases in a stepwise manner in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer.
[0034] In some embodiments, the dielectric layer of the second region comprises multiple dielectric layers, and the coefficient of thermal expansion of the material of each dielectric layer in the second region increases in a stepwise manner in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer.
[0035] In some embodiments, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region of the dielectric layer decreases in a stepwise manner.
[0036] In some embodiments, along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region of the dielectric layer increases in a stepwise manner.
[0037] In this embodiment, a dielectric layer is formed on the upper or lower surface of the wafer, and the thermal expansion coefficient of the protruding portion of the dielectric layer in the direction extending from the wafer to the dielectric layer is greater than the thermal expansion coefficient of the wafer, while the thermal expansion coefficient of the recessed portion in the direction extending from the wafer to the dielectric layer is less than the thermal expansion coefficient of the wafer. This allows for the formation of materials with different thermal expansion coefficients in local areas to improve wafer warpage. The process is simple, flexible, and fast, applicable to any complex warpage shape, and can be used in wafer stacking of different wafer systems to achieve the integration of multilayer wafer systems. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0039] Figure 1 This is a schematic diagram of the wafer warpage adjustment structure provided in an embodiment of the present disclosure;
[0040] Figure 2 This is a schematic diagram of a wafer warpage adjustment structure provided in another embodiment of the present disclosure;
[0041] Figures 3a to 3e Other examples of wafer warpage adjustment structures provided in embodiments of this disclosure;
[0042] Figure 4 This is a schematic diagram of the wafer warpage adjustment structure after leveling, provided in an embodiment of the present disclosure.
[0043] Figure 5 A schematic flowchart illustrating the fabrication method of the wafer warp adjustment structure provided in this embodiment of the disclosure;
[0044] Figures 6a to 6f This is a schematic diagram of the wafer warp adjustment structure provided in the embodiments of this disclosure during the fabrication process.
[0045] Explanation of reference numerals in the attached figures:
[0046] 10 - Wafer; 11 - Top surface; 12 - Bottom surface;
[0047] 20 - Dielectric layer; 200 - Dielectric layer pre-layer; 201 - First trench; 202 - Second trench;
[0048] 21-First region; 211-First sub-region of the first layer; 212-First sub-region of the second layer; 213-First sub-region of the third layer; 214-First sub-region of the first layer; 215-Second sub-region of the first layer; 216-Third sub-region of the first layer;
[0049] 22 - Second region; 221 - First layer, second sub-region; 222 - Second layer, second sub-region; 223 - Third layer, second sub-region; 224 - First second sub-region; 225 - Second second sub-region; 226 - Third second sub-region;
[0050] 23 - Other areas;
[0051] 30 - Mask layer; 301 - Patterned mask layer. Detailed Implementation
[0052] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0053] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0054] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.
[0055] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.
[0056] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0058] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.
[0059] During the wafer manufacturing process, the silicon wafers used to make the wafers may have irregular warping deformation beforehand, or the wafers may be cooled from a high temperature of about 400°C to a normal temperature of 25°C after the wafers are made. During this process, the coefficient of thermal expansion (CTE) of the internal dielectric materials (such as Si and SiO2) will be mismatched, which will cause the wafers to warp and deform, which is not conducive to chip manufacturing.
[0060] In some embodiments, flattening is mainly achieved by adding a dielectric layer to the wafer. However, this method can only be applied to the entire area and it is difficult to achieve "local" adjustment. This is because the same wafer chips are usually kept the same or each photomask is the same, and the dielectric layer formed is made of the same material. Therefore, it is difficult to ensure that the wafer is completely flattened. Furthermore, this method cannot flatten wafers with complex shapes (such as saddle-shaped or wavy shapes).
[0061] Based on this, the present disclosure provides a wafer warpage adjustment structure. Figure 1 This is a schematic diagram of the wafer warpage adjustment structure provided in an embodiment of this disclosure. Figure 2 This is a schematic diagram of a wafer warpage adjustment structure provided in another embodiment of the present disclosure.
[0062] See Figure 1 and Figure 2 The wafer warpage adjustment structure includes:
[0063] Wafer 10, the wafer 10 including an upper surface 11 and a lower surface 12 disposed opposite to each other, the upper surface 11 being used to form a semiconductor device;
[0064] The dielectric layer 20 is located on the upper surface 11 or the lower surface 12 of the wafer 10;
[0065] The dielectric layer 20 includes a first region 21 and / or a second region 22, and also includes other regions 23 besides the first region 21 and / or the second region 22; wherein,
[0066] The first region 21 covers the portion of the wafer 10 that protrudes in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer 20 in an independent state; the second region 22 covers the portion of the wafer 10 that is recessed in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer 20 in an independent state; the coefficient of thermal expansion of the material of the first region 21 is greater than the coefficient of thermal expansion of the material of the wafer 10; the coefficient of thermal expansion of the material of the second region 22 is less than the coefficient of thermal expansion of the material of the wafer 10.
[0067] In this embodiment, materials with different coefficients of thermal expansion are formed in local areas to improve the warpage of the wafer. The process is simple, flexible and fast, applicable to any complex warpage shape, and can be applied to wafer stacking in different wafer systems to achieve the integration of multi-layer wafer systems.
[0068] Specifically, in some embodiments, such as Figure 1 As shown, the dielectric layer 20 is located on the upper surface 11 of the wafer 10. In other embodiments, such as Figure 2 As shown, the dielectric layer 20 is located on the lower surface 12 of the wafer 10.
[0069] In one embodiment, the material of the first region 21 of the dielectric layer 20 includes silicon nitride or silicon carbide; the material of the second region 22 of the dielectric layer 20 includes quartz.
[0070] In one embodiment, the coefficient of thermal expansion of the material in the first region 21 of the dielectric layer 20 is greater than that of the material in the other regions 23 of the dielectric layer 21; the coefficient of thermal expansion of the material in the second region 22 of the dielectric layer 20 is less than that of the material in the other regions 23 of the dielectric layer 20. The coefficient of thermal expansion of the outwardly convex regions of the dielectric layer is greater than that of the other regions, while the coefficient of thermal expansion of the inwardly concave regions is smaller than that of the other regions. Thus, the coefficient of thermal expansion of the other regions of the dielectric layer falls between that of the first and second regions, allowing these other regions to also improve wafer warpage, thereby better leveraging the dielectric layer's effect on improving wafer warpage.
[0071] Specifically, the wafer is made of silicon (Si), which has a coefficient of thermal expansion of 2.7 × 10⁻⁶. -6 / ℃, the material of the dielectric layer, excluding the first region and / or the second region, is silicon dioxide (SiO2), and the coefficient of thermal expansion of silicon dioxide is 0.55×10. -6 At ℃, the coefficient of thermal expansion of silicon nitride (SiN) is 3.2 × 10⁻⁶. -6 At ℃, the coefficient of thermal expansion of silicon carbide (SiC) is 2.8 × 10⁻⁶. -6At ℃, the coefficient of thermal expansion of quartz is 0.33×10⁻⁶. -6 / ℃. This data shows that the coefficient of thermal expansion of silicon nitride or silicon carbide is greater than that of silicon and silicon dioxide, while the coefficient of thermal expansion of quartz is less than that of silicon and silicon dioxide. In other words, the coefficient of thermal expansion of the material in the first region is greater than that of the wafer material and the material in other regions of the dielectric layer besides the first and / or second regions. The coefficient of thermal expansion of the material in the second region is less than that of the wafer material and the material in other regions of the dielectric layer besides the first and / or second regions.
[0072] In one embodiment, such as Figure 3a As shown, the thickness of the first region 21 of the dielectric layer 20 is greater than or equal to the thickness of the other regions 23 of the dielectric layer 20. Because the thickness of the dielectric layer in the first region is greater than or equal to the thickness of the other regions, the dielectric layer in this region exhibits better thermal expansion and contraction performance, thus better mitigating wafer warpage.
[0073] Specifically, in one embodiment, the thickness of the first region 21 of the dielectric layer 20 is 1 to 4 times the thickness of the other regions 23 of the dielectric layer 20. Within this thickness range, the dielectric layer has the best effect on improving the warpage of the wafer. It is neither too thin to improve the wafer warpage, nor too thick to overcorrect the wafer and cause it to bend in the opposite direction.
[0074] In one embodiment, the dielectric layer of the first region 21 comprises multiple dielectric layers, and in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer 20, the coefficient of thermal expansion of the material of each dielectric layer of the first region 21 decreases in a stepwise manner.
[0075] Specifically, such as Figure 3b As shown, in a direction perpendicular to the surface of wafer 10 and extending from wafer 10 toward dielectric layer 20, the first region 21 includes a first sub-region 211, a second sub-region 212, and a third sub-region 213. The coefficients of thermal expansion of the materials of the first sub-region 211, the second sub-region 212, and the third sub-region 213 decrease in a stepwise manner.
[0076] Thus, the first sub-region 211 of the first layer has a larger difference in thermal expansion coefficient with the wafer, which can better improve the wafer warpage. The first sub-region 212 of the second layer and the first sub-region 213 of the third layer can better adjust the degree of warpage due to the decreasing thermal expansion coefficient, so as to avoid overcorrection.
[0077] Specifically, in some embodiments, the coefficients of thermal expansion of the first sub-region 211, the second sub-region 212, and the third sub-region 213 can be reduced in a stepwise manner by using materials with different coefficients of thermal expansion. In other embodiments, the first sub-region 211, the second sub-region 212, and the third sub-region 213 can be made of the same material, but different concentrations of ions can be doped into each layer to reduce the coefficients of thermal expansion of the first sub-region 211, the second sub-region 212, and the third sub-region 213 in a stepwise manner.
[0078] In one embodiment, the dielectric layer of the second region 22 comprises multiple dielectric layers, and the coefficient of thermal expansion of the material of each dielectric layer of the second region 22 increases in a stepwise manner in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer 20.
[0079] Specifically, such as Figure 3b As shown, in a direction perpendicular to the surface of wafer 10 and extending from wafer 10 toward dielectric layer 20, the second region 22 includes a first layer second sub-region 221, a second layer second sub-region 222, and a third layer second sub-region 223. The coefficients of thermal expansion of the materials of the first layer second sub-region 221, the second layer second sub-region 222, and the third layer second sub-region 223 increase in a stepwise manner.
[0080] Thus, the second sub-region 221 of the first layer has a larger difference in thermal expansion coefficient with the wafer, which can better improve the wafer warpage. The second sub-region 222 of the second layer and the second sub-region 223 of the third layer can better adjust the degree of warpage due to the increasing thermal expansion coefficient, so as to avoid overcorrection.
[0081] Specifically, in some embodiments, the coefficients of thermal expansion of the first layer second sub-region 221, the second layer second sub-region 222, and the third layer second sub-region 223 can increase in a stepwise manner by using materials with different coefficients of thermal expansion. In other embodiments, the first layer second sub-region 221, the second layer second sub-region 222, and the third layer second sub-region 223 can use the same material, but different concentrations of ions can be doped in each layer to increase the coefficients of thermal expansion of the first layer second sub-region 221, the second layer second sub-region 222, and the third layer second sub-region 223 in a stepwise manner.
[0082] In some embodiments, the dielectric layer of the first region of the wafer warp adjustment structure includes multiple dielectric layers, and the dielectric layer of the second region includes a single dielectric layer; in other embodiments, the dielectric layer of the first region includes a single dielectric layer, and the dielectric layer of the second region includes multiple dielectric layers; in still other embodiments, such as Figure 3b As shown, the dielectric layer of the first region includes multiple dielectric layers, and the dielectric layer of the second region includes multiple dielectric layers.
[0083] In one embodiment, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region 21 of the dielectric layer decreases in a stepwise manner.
[0084] Specifically, such as Figure 3c As shown, along the direction of decreasing curvature of the curve corresponding to the protrusion, the first region 21 includes a first sub-region 214, a second first sub-region 215, and a third first sub-region 216. The coefficients of thermal expansion of the materials of the first first sub-region 214, the second first sub-region 215, and the third first sub-region 216 decrease in a stepwise manner.
[0085] Because the greatest curvature makes correction more difficult, using a dielectric layer with the greatest difference in thermal expansion coefficient from the wafer can effectively solve the above problem. Furthermore, the thermal expansion coefficients of other dielectric layers change with the curvature, allowing for precise adjustment of wafer warpage.
[0086] Specifically, in some embodiments, the coefficients of thermal expansion of the first sub-region 214, the second sub-region 215, and the third sub-region 216 can be reduced in a stepwise manner by using materials with different coefficients of thermal expansion; in other embodiments, the first sub-region 214, the second sub-region 215, and the third sub-region 216 can be made of the same material, but each can be doped with different concentrations of ions, so that the coefficients of thermal expansion of the first sub-region 214, the second sub-region 215, and the third sub-region 216 can be reduced in a stepwise manner.
[0087] In one embodiment, along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region 22 of the dielectric layer increases in a stepwise manner.
[0088] Specifically, such as Figure 3cAs shown, along the direction of decreasing curvature of the curve corresponding to the depression, the second region 22 includes a first second sub-region 224, a second second sub-region 225, and a third second sub-region 226. The coefficients of thermal expansion of the materials in the first second sub-region 224, the second second sub-region 225, and the third second sub-region 226 increase in a stepwise manner.
[0089] Because the greatest curvature makes correction more difficult, using a dielectric layer with the greatest difference in thermal expansion coefficient from the wafer can effectively solve the above problem. Furthermore, the thermal expansion coefficients of other dielectric layers change with the curvature, allowing for precise adjustment of wafer warpage.
[0090] Specifically, in some embodiments, the coefficients of thermal expansion of the first second sub-region 224, the second second sub-region 225, and the third second sub-region 226 can increase in a stepwise manner by using materials with different coefficients of thermal expansion; in other embodiments, the first second sub-region 224, the second second sub-region 225, and the third second sub-region 226 can use the same material, but each can be doped with different concentrations of ions, so that the coefficients of thermal expansion of the first second sub-region 224, the second second sub-region 225, and the third second sub-region 226 increase in a stepwise manner.
[0091] In some embodiments, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region decreases in a stepwise manner, while along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region remains unchanged; in other embodiments, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region remains unchanged, while along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region increases in a stepwise manner; in still other embodiments, such as Figure 3c As shown, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region decreases in a stepwise manner, and along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region increases in a stepwise manner.
[0092] In one embodiment, the curved shape of the wafer can be saddle-shaped or wavy.
[0093] Specifically, in some embodiments, such as Figures 1 to 3c As shown, the wafer is bent in a wavy shape; in some other embodiments, such as Figure 3d and Figure 3e As shown, the wafer is bent in a saddle shape, wherein, as Figure 3d As shown, the dielectric layer 20 only includes the first region 21, such as Figure 3eAs shown, the dielectric layer 20 only includes the second region 22.
[0094] In this embodiment of the disclosure, after forming materials with different coefficients of thermal expansion in local areas of a bent wafer, the wafer can be leveled so that the wafer ultimately reaches the desired shape. Figure 4 The shape shown.
[0095] This disclosure also provides a method for fabricating a wafer warp adjustment structure; please refer to the appendix for details. Figure 5 As shown in the figure, the method includes the following steps:
[0096] Step 501: Provide a wafer, the wafer including a warped region; the wafer including an upper surface and a lower surface disposed opposite each other, the upper surface being used to form a semiconductor device;
[0097] Step 502: Form a dielectric layer on the upper or lower surface of the wafer; the dielectric layer includes a first region and / or a second region, and also includes other regions besides the first region and / or the second region; wherein, the first region covers the portion of the wafer warp region that protrudes in a direction perpendicular to the wafer surface and extending from the wafer into the dielectric layer, and the second region covers the portion of the wafer warp region that is recessed in a direction perpendicular to the wafer surface and extending from the wafer into the dielectric layer; the coefficient of thermal expansion of the material of the first region is greater than the coefficient of thermal expansion of the material of the wafer; the coefficient of thermal expansion of the material of the second region is less than the coefficient of thermal expansion of the material of the wafer.
[0098] The preparation method of the wafer warp adjustment structure provided in this disclosure will be further described in detail below with reference to specific embodiments.
[0099] Figures 6a to 6f This is a schematic diagram of the wafer warp adjustment structure provided in the embodiments of this disclosure during the fabrication process.
[0100] First, see Figure 6a Step 501 is performed, providing a wafer 10, the wafer 10 including a warped region; the wafer 10 includes an upper surface 11 and a lower surface 12 disposed opposite to each other, the upper surface 11 being used to form a semiconductor device.
[0101] Next, see Figures 6b to 6fStep 502 is performed to form a dielectric layer 20 on the upper surface 11 or lower surface 12 of the wafer 10. The dielectric layer 20 includes a first region 21 and / or a second region 22, and also includes other regions 23 besides the first region 21 and / or the second region 22. The first region 21 covers the portion of the wafer warp region that protrudes in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer 20, and the second region 22 covers the portion of the wafer warp region that is recessed in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer 20. The coefficient of thermal expansion of the material of the first region 21 is greater than the coefficient of thermal expansion of the material of the wafer 10. The coefficient of thermal expansion of the material of the second region 22 is less than the coefficient of thermal expansion of the material of the wafer 10.
[0102] In one embodiment, forming a dielectric layer 20 on the upper surface 11 or lower surface 12 of the wafer 10 includes:
[0103] A dielectric layer prelayer 200 is formed on the upper surface 11 or the lower surface 12 of the wafer 10;
[0104] Etching a portion of the dielectric prelayer 200 in the first region to form a first trench 201; filling the first trench 201 with a first material, the first material having a coefficient of thermal expansion greater than that of the material of the wafer 10; and / or,
[0105] The portion of the dielectric prelayer 200 in the second region is etched to form a second trench 202; the second trench 202 is filled with a second material, the coefficient of thermal expansion of the second material being less than the coefficient of thermal expansion of the material of the wafer 10.
[0106] Specifically, see first. Figure 6b A dielectric prelayer 200 is formed on the upper surface 11 of the wafer 10.
[0107] In practice, the dielectric prelayer 200 can be formed using one or more thin film deposition processes; specifically, the deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof.
[0108] In some embodiments, such as Figure 6b As shown, a dielectric prelayer 200 is formed on the upper surface 11 of the wafer 10, and in some other embodiments, a dielectric prelayer 200 is formed on the lower surface 12 of the wafer 10.
[0109] Next, see Figures 6c to 6eThe dielectric prelayer 200 is etched in a portion of the first region to form a first trench 201, and / or the dielectric prelayer 200 is etched in a portion of the second region to form a second trench 202.
[0110] Specifically, a mask layer 30 can be grown on the upper surface of the dielectric prelayer 200. Then, the mask layer 30 is patterned to form a patterned mask layer 301, displaying the pattern of the first trench and / or the second trench to be etched. This patterning can be achieved through photolithography. The mask layer 30 can be a photoresist mask or a hard mask patterned based on a photolithography mask. When the mask layer 30 is a photoresist mask, it is patterned through steps such as exposure, development, and resist removal. Next, the first trench 201 and / or the second trench 202 with a certain depth are etched according to the pattern of the first trench and / or the second trench to be etched.
[0111] Here, for example, a wet or dry etching process can be used to form the first trench 201 and / or the second trench 202.
[0112] Next, see Figure 6f The first trench 201 is filled with a first material, the coefficient of thermal expansion of which is greater than that of the material of the wafer 10; and / or the second trench 202 is filled with a second material, the coefficient of thermal expansion of which is less than that of the material of the wafer 10.
[0113] In one embodiment, the material of the first region 21 of the dielectric layer 20 includes silicon nitride or silicon carbide; the material of the second region 22 of the dielectric layer 20 includes quartz.
[0114] In one embodiment, the coefficient of thermal expansion of the material of the first region 21 of the dielectric layer 20 is greater than the coefficient of thermal expansion of the material of the other regions 23 of the dielectric layer 20; the coefficient of thermal expansion of the material of the second region 22 of the dielectric layer 20 is less than the coefficient of thermal expansion of the material of the other regions 23 of the dielectric layer 20.
[0115] The coefficient of thermal expansion of the outward-protruding region of the dielectric layer is greater than that of other regions of the dielectric layer, while the coefficient of thermal expansion of the inward-recessed region is smaller than that of other regions. Thus, the coefficient of thermal expansion of other regions of the dielectric layer is between that of the first and second regions. Other regions of the dielectric layer can also play a role in improving wafer warpage, thereby better leveraging the effect of the dielectric layer in improving wafer warpage.
[0116] Specifically, the wafer is made of silicon (Si), which has a coefficient of thermal expansion of 2.7 × 10⁻⁶. -6 / ℃, the material of the dielectric layer, excluding the first region and / or the second region, is silicon dioxide (SiO2), and the coefficient of thermal expansion of silicon dioxide is 0.55×10. -6 At ℃, the coefficient of thermal expansion of silicon nitride (SiN) is 3.2 × 10⁻⁶. -6 At ℃, the coefficient of thermal expansion of silicon carbide (SiC) is 2.8 × 10⁻⁶. -6 At ℃, the coefficient of thermal expansion of quartz is 0.33×10⁻⁶. -6 / ℃. This data shows that the coefficient of thermal expansion of silicon nitride or silicon carbide is greater than that of silicon and silicon dioxide, while the coefficient of thermal expansion of quartz is less than that of silicon and silicon dioxide. In other words, the coefficient of thermal expansion of the material in the first region is greater than that of the wafer material and the material in other regions of the dielectric layer besides the first and / or second regions. The coefficient of thermal expansion of the material in the second region is less than that of the wafer material and the material in other regions of the dielectric layer besides the first and / or second regions.
[0117] In one embodiment, such as Figure 3a As shown, the thickness of the first region 21 of the dielectric layer 20 is greater than or equal to the thickness of the other regions 23 of the dielectric layer 20. Because the thickness of the dielectric layer in the first region is greater than or equal to the thickness of the other regions, the dielectric layer in this region exhibits better thermal expansion and contraction performance, thus better mitigating wafer warpage.
[0118] Specifically, in one embodiment, the thickness of the first region 21 of the dielectric layer 20 is 1 to 4 times the thickness of the other regions 23 of the dielectric layer 20. Within this thickness range, the dielectric layer has the best effect on improving the warpage of the wafer. It is neither too thin to improve the wafer warpage, nor too thick to overcorrect the wafer and cause it to bend in the opposite direction.
[0119] In one embodiment, the dielectric layer of the first region 21 comprises multiple dielectric layers, and in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer 20, the coefficient of thermal expansion of the material of each dielectric layer of the first region 21 decreases in a stepwise manner.
[0120] Specifically, such as Figure 3b As shown, in a direction perpendicular to the surface of wafer 10 and extending from wafer 10 toward dielectric layer 20, the first region 21 includes a first sub-region 211, a second sub-region 212, and a third sub-region 213. The coefficients of thermal expansion of the materials of the first sub-region 211, the second sub-region 212, and the third sub-region 213 decrease in a stepwise manner.
[0121] Thus, the first sub-region 211 of the first layer has a larger difference in thermal expansion coefficient with the wafer, which can better improve the wafer warpage. The first sub-region 212 of the second layer and the first sub-region 213 of the third layer can better adjust the degree of warpage due to the decreasing thermal expansion coefficient, so as to avoid overcorrection.
[0122] Specifically, in some embodiments, the coefficients of thermal expansion of the first sub-region 211, the second sub-region 212, and the third sub-region 213 can be reduced in a stepwise manner by using materials with different coefficients of thermal expansion. In other embodiments, the first sub-region 211, the second sub-region 212, and the third sub-region 213 can be made of the same material, but different concentrations of ions can be doped into each layer to reduce the coefficients of thermal expansion of the first sub-region 211, the second sub-region 212, and the third sub-region 213 in a stepwise manner.
[0123] In one embodiment, the dielectric layer of the second region 22 comprises multiple dielectric layers, and the coefficient of thermal expansion of the material of each dielectric layer of the second region 22 increases in a stepwise manner in a direction perpendicular to the surface of the wafer 10 and extending from the wafer 10 toward the dielectric layer 20.
[0124] Specifically, such as Figure 3b As shown, in a direction perpendicular to the surface of wafer 10 and extending from wafer 10 toward dielectric layer 20, the second region 22 includes a first layer second sub-region 221, a second layer second sub-region 222, and a third layer second sub-region 223. The coefficients of thermal expansion of the materials of the first layer second sub-region 221, the second layer second sub-region 222, and the third layer second sub-region 223 increase in a stepwise manner.
[0125] Thus, the second sub-region 221 of the first layer has a larger difference in thermal expansion coefficient with the wafer, which can better improve the wafer warpage. The second sub-region 222 of the second layer and the second sub-region 223 of the third layer can better adjust the degree of warpage due to the increasing thermal expansion coefficient, so as to avoid overcorrection.
[0126] Specifically, in some embodiments, the coefficients of thermal expansion of the first layer second sub-region 221, the second layer second sub-region 222, and the third layer second sub-region 223 can increase in a stepwise manner by using materials with different coefficients of thermal expansion. In other embodiments, the first layer second sub-region 221, the second layer second sub-region 222, and the third layer second sub-region 223 can use the same material, but different concentrations of ions can be doped in each layer to increase the coefficients of thermal expansion of the first layer second sub-region 221, the second layer second sub-region 222, and the third layer second sub-region 223 in a stepwise manner.
[0127] In some embodiments, the dielectric layer of the first region of the wafer warp adjustment structure includes multiple dielectric layers, and the dielectric layer of the second region includes a single dielectric layer; in other embodiments, the dielectric layer of the first region includes a single dielectric layer, and the dielectric layer of the second region includes multiple dielectric layers; in still other embodiments, such as Figure 3b As shown, the dielectric layer of the first region includes multiple dielectric layers, and the dielectric layer of the second region includes multiple dielectric layers.
[0128] In one embodiment, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region 21 of the dielectric layer decreases in a stepwise manner.
[0129] Because the greatest curvature makes correction more difficult, using a dielectric layer with the greatest difference in thermal expansion coefficient from the wafer can effectively solve the above problem. Furthermore, the thermal expansion coefficients of other dielectric layers change with the curvature, allowing for precise adjustment of wafer warpage.
[0130] Specifically, such as Figure 3c As shown, along the direction of decreasing curvature of the curve corresponding to the protrusion, the first region 21 includes a first sub-region 214, a second first sub-region 215, and a third first sub-region 216. The coefficients of thermal expansion of the materials of the first first sub-region 214, the second first sub-region 215, and the third first sub-region 216 decrease in a stepwise manner.
[0131] Specifically, in some embodiments, the coefficients of thermal expansion of the first sub-region 214, the second sub-region 215, and the third sub-region 216 can be reduced in a stepwise manner by using materials with different coefficients of thermal expansion; in other embodiments, the first sub-region 214, the second sub-region 215, and the third sub-region 216 can be made of the same material, but each can be doped with different concentrations of ions, so that the coefficients of thermal expansion of the first sub-region 214, the second sub-region 215, and the third sub-region 216 can be reduced in a stepwise manner.
[0132] In one embodiment, along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region 22 of the dielectric layer increases in a stepwise manner.
[0133] Specifically, such as Figure 3cAs shown, along the direction of decreasing curvature of the curve corresponding to the depression, the second region 22 includes a first second sub-region 224, a second second sub-region 225, and a third second sub-region 226. The coefficients of thermal expansion of the materials in the first second sub-region 224, the second second sub-region 225, and the third second sub-region 226 increase in a stepwise manner.
[0134] Because the greatest curvature makes correction more difficult, using a dielectric layer with the greatest difference in thermal expansion coefficient from the wafer can effectively solve the above problem. Furthermore, the thermal expansion coefficients of other dielectric layers change with the curvature, allowing for precise adjustment of wafer warpage.
[0135] Specifically, in some embodiments, the coefficients of thermal expansion of the first second sub-region 224, the second second sub-region 225, and the third second sub-region 226 can be reduced in a stepwise manner by using materials with different coefficients of thermal expansion; in other embodiments, the first second sub-region 224, the second second sub-region 225, and the third second sub-region 226 can be made of the same material, but each can be doped with different concentrations of ions, so that the coefficients of thermal expansion of the first second sub-region 224, the second second sub-region 225, and the third second sub-region 226 can be reduced in a stepwise manner.
[0136] In some embodiments, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region decreases in a stepwise manner, while along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region remains unchanged; in other embodiments, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region remains unchanged, while along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region increases in a stepwise manner; in still other embodiments, such as Figure 3c As shown, along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region decreases in a stepwise manner, and along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region increases in a stepwise manner.
[0137] In one embodiment, the warped region of the wafer is saddle-shaped or wavy.
[0138] Specifically, in some embodiments, such as Figure 6f As shown, the warped region of the wafer is wavy; in some other embodiments, such as Figure 3d and Figure 3e As shown, the warped region of the wafer is saddle-shaped, wherein, as... Figure 3d As shown, the dielectric layer 20 only includes the first region 21, such as Figure 3eAs shown, the dielectric layer 20 only includes the second region 22.
[0139] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A wafer warpage adjustment structure, characterized in that, include: A wafer, the wafer including an upper surface and a lower surface disposed opposite each other, the upper surface being used to form a semiconductor device; A dielectric layer located on the upper or lower surface of the wafer; The dielectric layer includes a first region and a second region, and also includes other regions besides the first and second regions; wherein, The first region covers the portion of the wafer that protrudes in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer when the wafer is in an independent state; the second region covers the portion of the wafer that is recessed in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer when the wafer is in an independent state; the coefficient of thermal expansion of the material of the first region is greater than the coefficient of thermal expansion of the material of the wafer; the coefficient of thermal expansion of the material of the second region is less than the coefficient of thermal expansion of the material of the wafer.
2. The wafer warpage adjustment structure according to claim 1, characterized in that, The material of the first region of the dielectric layer includes silicon nitride or silicon carbide; The material of the second region of the dielectric layer includes quartz.
3. The wafer warpage adjustment structure according to claim 1, characterized in that, The coefficient of thermal expansion of the material in the first region of the dielectric layer is greater than the coefficient of thermal expansion of the material in other regions of the dielectric layer. The coefficient of thermal expansion of the material in the second region of the dielectric layer is less than that of the material in other regions of the dielectric layer.
4. The wafer warpage adjustment structure according to claim 1, characterized in that, The thickness of the first region of the dielectric layer is greater than or equal to the thickness of the other regions of the dielectric layer.
5. The wafer warpage adjustment structure according to claim 4, characterized in that, The thickness of the first region of the dielectric layer is 1 to 4 times the thickness of the other regions of the dielectric layer.
6. The wafer warpage adjustment structure according to claim 1, characterized in that, The dielectric layer of the first region comprises multiple dielectric layers, and in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer, the coefficient of thermal expansion of the material of each dielectric layer in the first region decreases in a stepwise manner.
7. The wafer warpage adjustment structure according to claim 1, characterized in that, The dielectric layer of the second region comprises multiple dielectric layers, and in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer, the coefficient of thermal expansion of the material of each dielectric layer in the second region increases in a stepwise manner.
8. The wafer warpage adjustment structure according to claim 1, characterized in that, Along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region of the dielectric layer decreases in a stepwise manner.
9. The wafer warpage adjustment structure according to claim 1, characterized in that, Along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region of the dielectric layer increases in a stepwise manner.
10. A method for preparing a wafer warp adjustment structure, characterized in that, include: A wafer is provided, the wafer including a warped region; the wafer includes an upper surface and a lower surface disposed opposite to each other, the upper surface being used to form a semiconductor device; A dielectric layer is formed on the upper or lower surface of the wafer; The dielectric layer includes a first region and a second region, and also includes other regions besides the first and second regions; wherein, The first region covers the portion of the wafer warp region that protrudes in a direction perpendicular to the wafer surface and extending from the wafer into the dielectric layer, and the second region covers the portion of the wafer warp region that is recessed in a direction perpendicular to the wafer surface and extending from the wafer into the dielectric layer; the coefficient of thermal expansion of the material of the first region is greater than the coefficient of thermal expansion of the material of the wafer; the coefficient of thermal expansion of the material of the second region is less than the coefficient of thermal expansion of the material of the wafer.
11. The method according to claim 10, characterized in that, The coefficient of thermal expansion of the material in the first region of the dielectric layer is greater than the coefficient of thermal expansion of the material in other regions of the dielectric layer. The coefficient of thermal expansion of the material in the second region of the dielectric layer is less than that of the material in other regions of the dielectric layer.
12. The method according to claim 10, characterized in that, The formation of a dielectric layer on the upper or lower surface of the wafer includes: A dielectric layer pre-layer is formed on the upper or lower surface of the wafer; Etching a portion of the dielectric prelayer in the first region to form a first trench; filling the first trench with a first material, the first material having a coefficient of thermal expansion greater than that of the wafer material; and / or The portion of the dielectric prelayer in the second region is etched to form a second trench; the second trench is filled with a second material, the coefficient of thermal expansion of which is less than that of the material of the wafer.
13. The method according to claim 10, characterized in that, The warped region of the wafer is saddle-shaped or wavy.
14. The method according to claim 10, characterized in that, The thickness of the first region of the dielectric layer is greater than or equal to the thickness of the other regions of the dielectric layer.
15. The method according to claim 14, characterized in that, The thickness of the first region of the dielectric layer is 1 to 4 times the thickness of the other regions of the dielectric layer.
16. The method according to claim 10, characterized in that, The dielectric layer of the first region comprises multiple dielectric layers, and in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer, the coefficient of thermal expansion of the material of each dielectric layer in the first region decreases in a stepwise manner.
17. The method according to claim 10, characterized in that, The dielectric layer of the second region comprises multiple dielectric layers, and in a direction perpendicular to the wafer surface and extending from the wafer toward the dielectric layer, the coefficient of thermal expansion of the material of each dielectric layer in the second region increases in a stepwise manner.
18. The method according to claim 10, characterized in that, Along the direction of decreasing curvature of the curve corresponding to the protrusion, the coefficient of thermal expansion of the material in the first region of the dielectric layer decreases in a stepwise manner.
19. The method according to claim 10, characterized in that, Along the direction of decreasing curvature of the curve corresponding to the depression, the coefficient of thermal expansion of the material in the second region of the dielectric layer increases in a stepwise manner.