A method and apparatus for generating random clock against side channel attack

Abstract

The application relates to a random clock generation method and device against side channel attacks, wherein the method comprises the following steps: S1, selecting a reference clock as an input clock of a first round of multi-path frequency multiplication to obtain frequency multiplication clocks with different frequency multiplication coefficients; S2, randomly selecting a frequency multiplication clock from the frequency multiplication clocks, performing spur filtering, and then outputting the frequency multiplication clock as a system clock; S3, performing multi-path frequency division on the randomly selected frequency multiplication clock to obtain frequency division clocks with different frequency division coefficients; S4, randomly selecting a frequency division clock from the frequency division clocks, and performing multi-path frequency multiplication on the frequency division clock as an input clock of a next round of multi-path frequency multiplication to obtain frequency multiplication clocks with different frequency multiplication coefficients; and S5, repeating steps S2 to S4, and obtaining a system clock with various and random frequencies through multiple rounds of iteration. The application effectively improves the side channel attack protection effect.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a method and apparatus for generating random clocks that resist side-channel attacks. Background Technology

[0002] In recent years, many cryptographic chips and devices have been subjected to side-channel proximity attacks. The attack mechanism involves using physical channels such as energy, electromagnetic radiation, and sound to obtain leaked physical information during cryptographic operations, thereby attacking the cryptographic system. The specific attack analysis process mainly targets the operands or operation instructions in the cryptographic operation process.

[0003] There are two main categories of existing side-channel protection methods: masking and randomization. Masking mainly aims to homogenize the physical information leaked when processing different operands during cryptographic operations, thereby weakening the correlation between the operation data and the leaked information. Randomization mainly aims to randomly change the timing of processing different operands during cryptographic operations, thereby obfuscating the execution time of operation instructions and increasing the difficulty of side-channel attacks.

[0004] The side-channel randomization protection technology of cryptographic chips is mainly implemented through a clock randomization circuit system. The main component of the clock randomization circuit system is the clock randomization unit, which generates multiple differentiated clocks and randomly selects and outputs these clocks.

[0005] In existing differentiated clock generation methods, the input clock signal is divided by a finite number of fixed coefficients before being output to the next module. Because the clock signal is processed unidirectionally in this process, the differentiation effect mainly depends on the difference in the division coefficients. Considering engineering applications, the existing designs have limited number and variation of division coefficients, resulting in a limited number of frequency points and limited protection effectiveness for the output clock. Summary of the Invention

[0006] Based on the above analysis, the present invention aims to disclose a random clock generation method and apparatus to resist side-channel attacks, which can randomize the operation time of cryptographic chips or modules and resist side-channel proximity attacks.

[0007] This invention discloses a random clock generation method resistant to side-channel attacks, comprising:

[0008] Step S1: Select a reference clock as the input clock for the first round of multi-channel frequency multiplication to obtain multiple multiplied clocks with different multiplication coefficients;

[0009] Step S2: Randomly select one frequency-multiplied clock from the multiple frequency-multiplied clocks, filter out glitches, and use it as the system clock output;

[0010] Step S3: Divide the randomly selected frequency-multiplying clock into multiple frequency-divided clocks to obtain multiple frequency-divided clocks with different frequency division coefficients;

[0011] Step S4: Randomly select one frequency divider clock from the multiple frequency divider clocks and use it as the input clock for the next round of multiple frequency multiplication to obtain multiple frequency multiplication clocks with different multiplication coefficients.

[0012] Step S5: Repeat steps S2 to S4. After multiple rounds of iterative work, a system clock with diverse and random frequencies is obtained.

[0013] Furthermore, the multi-channel frequency multiplication is achieved using a C / N fractional division method; where N = N1, N2, ..., N z1 z1 is the number of frequency multiplication channels; C is the period count value; the period count value C = f0 / f x Where f0 is the frequency of the reference clock, and during the first round of multiplication, f... x The initial value is set; during other rounds of multi-channel frequency multiplication, f x In step S4, the frequency of one frequency-divided clock is randomly selected from the multiple frequency-divided clocks.

[0014] The multi-channel frequency division uses a digital counting frequency division with a division factor of M; where M = M1, M2, ..., M z2 z2 is the number of frequency division paths.

[0015] Furthermore, a random number generation module is used to generate random first and second configuration signals, wherein,

[0016] The first configuration signal is used to configure the multiplexer that implements the multiple-to-one selection in step S2;

[0017] The second configuration signal is used to configure the multiplexer that implements the multiple-choice function in step S4.

[0018] Furthermore, under the constraint of the period count value C, the random number generation module generates a first configuration signal and a second configuration signal based on the generated random number.

[0019] Furthermore, in the constraint of the period count value C, a multi-segment interval comparison and judgment method is adopted; by setting segment thresholds, it is determined that the period count value C falls within a certain segment, and the selectable path of the corresponding segment is generated. Then, the first configuration signal and the second configuration signal are generated based on the generated random number.

[0020] The present invention also discloses a random clock generation device resistant to side-channel attacks, comprising a clock source module, a frequency multiplication module, a frequency division module, a first multiplexer, a second multiplexer, and a random number generation module;

[0021] The clock source module is used to generate a reference clock, and its output is connected to the input of the frequency multiplier module.

[0022] The frequency multiplier module is used to perform multi-channel frequency multiplication, and its output terminal is connected to the input terminal of the first multiplexer.

[0023] The first multiplexer is used to randomly select one frequency-multiplied clock from multiple frequency-multiplied clocks, and its control terminal is connected to a first configuration signal; under the configuration of the first configuration signal, it randomly selects one frequency-multiplied clock from the input multiple frequency-multiplied clocks and outputs it as the system clock output;

[0024] The frequency divider module is used to perform multi-channel frequency division. Its input terminal is connected to the output terminal of the first multiplexer, and its output terminal is connected to the input terminal of the second multiplexer. The frequency divider module divides the multiplied clock output by the first multiplexer into multiple channels, and outputs multiple frequency-divided clocks with different division coefficients.

[0025] The second multiplexer is used to randomly select one frequency divider clock from multiple frequency divider clocks, and its control terminal is connected to a second configuration signal; under the configuration of the second configuration signal, it randomly selects one frequency divider clock from the input multiple frequency divider clocks and outputs it to the input terminal of the frequency multiplier module;

[0026] The frequency multiplier module selects the output signal of the clock source module for frequency multiplication in the first round of frequency multiplication, and selects the output signal of the second multiplexer for frequency multiplication in other rounds.

[0027] The random number generation module is used to generate random first configuration signals and second configuration signals to control the first multiplexer and the second multiplexer.

[0028] Furthermore, the frequency multiplier module includes a digital period counter and a fractional frequency divider;

[0029] The first input terminal of the digital period counter is connected to the output terminal of the clock source module, the second input terminal is connected to the output terminal of the second multiplexer, and the output terminal is connected to the input terminal of the fractional frequency divider; the output terminal of the fractional frequency divider serves as the output terminal of the frequency multiplier module.

[0030] The period count value C output by the digital period counter is C = f0 / f x Where f0 is the frequency of the reference clock, and during the first round of multiplication, f... x The initial value is set; during other rounds of multi-channel frequency multiplication, f x The frequency of the divided clock output from the second multiplexer;

[0031] The fractional frequency divider uses a digital fractional frequency division of C / N to achieve frequency multiplication; where N = N1, N2, ..., N z1Where z1 is the frequency multiplier.

[0032] Furthermore, the random number generation module includes a random number generator and a constraint unit;

[0033] The output of the random number generator is connected to the input of the constraint unit. The first output of the constraint unit outputs a first selection signal to a first multiplexer, and the second output outputs a second selection signal to a second multiplexer. The control terminal is connected to the output of the digital period counter.

[0034] The random number generation module is used to generate a random number and output it to the constraint unit;

[0035] Under the control of the period count value C, the constraint unit outputs a first selection signal and a second selection signal.

[0036] Furthermore, in the constraint unit, a multi-segment interval comparison and judgment method is adopted; by setting a segment threshold, it is determined that the frequency relationship C falls within a certain segment, and a selectable path for the corresponding segment is generated. Then, a first selection signal and a second selection signal are generated according to the random number output by the random number generation module.

[0037] Furthermore, it also includes a burr filtering module and a frequency detection module;

[0038] The input of the glitch filtering module is connected to the output of the first multiplexer, and the frequency multiplier clock output by the second multiplexer is filtered for glitch and then output as the system clock.

[0039] The input terminal of the frequency detection module is connected to the output terminal of the first multiplexer, and is used to detect the frequency multiplier clock output by the second multiplexer in real time, thereby determining whether the system clock is out of control. If it is out of control, frequency correction is performed.

[0040] This invention can achieve at least one of the following beneficial effects:

[0041] Compared to existing side-channel protection circuits based on random clocks, this invention provides a random clock generation method and apparatus for resisting side-channel attacks. Through an adaptive feedback loop structure, it randomly generates a large number of diverse frequency points, overcoming the shortcomings of existing technologies such as a small number of frequency points and simple frequency point distribution, effectively improving the protection against side-channel attacks. It is highly suitable for cryptographic encryption and decryption scenarios with low clock frequency accuracy requirements, a larger number of frequency points, and faster frequency switching speeds. Attached Figure Description

[0042] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0043] Figure 1 This is a flowchart of the random clock generation method in an embodiment of the present invention;

[0044] Figure 2 This is a block diagram illustrating the principle of the random clock generation device in an embodiment of the present invention.

[0045] Figure 3 This is a block diagram illustrating the principle of the random clock generation device in an embodiment of the present invention. Detailed Implementation

[0046] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and, together with the embodiments of the present invention, serve to illustrate the principles of the present invention.

[0047] Example 1

[0048] This embodiment discloses a random clock generation method resistant to side-channel attacks. It employs an adaptive feedback loop to process the input clock signal, generating an output clock signal with random, diverse, and uniformly distributed frequencies. For example... Figure 1 As shown, the specific workflow includes the following steps:

[0049] Step S1: Select a reference clock as the input clock for the first round of multi-channel frequency multiplication to obtain multiple multiplied clocks with different multiplication coefficients;

[0050] Step S2: Randomly select one frequency-multiplied clock from the multiple frequency-multiplied clocks, filter out glitches, and use it as the system clock output;

[0051] Step S3: Divide the randomly selected frequency-multiplying clock into multiple frequency-divided clocks to obtain multiple frequency-divided clocks with different frequency division coefficients;

[0052] Step S4: Randomly select one frequency divider clock from the multiple frequency divider clocks and use it as the input clock for the next round of multiple frequency multiplication to obtain multiple frequency multiplication clocks with different multiplication coefficients.

[0053] Step S5: Repeat steps S2 to S4. After multiple rounds of iterative work, a system clock with diverse and random frequencies is obtained.

[0054] Specifically, the multi-channel frequency multiplication described in steps S1 and S4 uses a C / N fractional division to achieve frequency multiplication; where N = N1, N2, ..., N z1 N1, N2, ..., N z1 Z1 is a distinct positive integer; C is the frequency multiplication factor; C is the period counter value; the period counter value C = f0 / f x C; where f0 is the frequency of the reference clock, and f is the frequency during the first round of multiplication. xThe initial value is set before startup; during other rounds of multi-channel frequency multiplication, f x The frequency of one frequency divider clock is randomly selected from the multiple frequency divider clocks in step S4.

[0055] Before startup f x The initial value needs to be set in conjunction with the target frequency range and the frequency division and multiplication coefficients. When the coefficients are fixed, the initial f... x This will determine the range of the system's random output clock frequency. Therefore, the solution in this embodiment is applicable to different frequency range requirements and is easy to adjust and adapt.

[0056] Specifically, the multi-channel frequency division uses digital counting frequency division with a division factor of M; where M = M1, M2, ..., M z2 M = M1, M2, ..., M z2 z1 is a distinct positive integer; z2 is the number of frequency divisions.

[0057] Specifically, in step S2, randomly selecting one frequency-multiplied clock from multiple frequency-multiplied clocks can be implemented using a multiplexer; wherein the number of input channels of the multiplexer is the number of frequency multipliers z1. Similarly, in step S4, randomly selecting one frequency-divided clock from multiple frequency-divided clocks can also be implemented using a multiplexer; wherein the number of input channels of the multiplexer is the number of frequency dividers z2.

[0058] To achieve randomness in the selection of the multiplexer, this embodiment preferably employs a random number generator module to generate random first and second configuration signals, wherein...

[0059] The first configuration signal is used to configure the multiplexer that implements the multiple-to-one selection in step S2;

[0060] The second configuration signal is used to configure the multiplexer that implements the multiple-choice function in step S4.

[0061] Specifically, under the constraint of the period count value C, the random number generation module generates a first configuration signal and a second configuration signal based on the generated random number.

[0062] In the constraint of the period count value C, a multi-segment interval comparison and judgment method is adopted. By setting a segment threshold, it is determined that the period count value C falls within a certain segment, and the corresponding segment selectable path is generated. Then, the first configuration signal and the second configuration signal are generated according to the generated random number. Specifically, the correspondence between the random number and the first configuration signal and the second configuration signal can be generated by decoding.

[0063] The first configuration signal is used for selection control in the multiplexer of the multiplexer in step S2; the second configuration signal is used for selection control in the multiplexer of the multiplexer in step S4. By constraining the period count value C, the frequency of the frequency multiplication and division can be maintained in a controllable state. This avoids system clock malfunction caused by unreasonable selection of frequency multiplication and division.

[0064] In summary, compared with existing side-channel protection circuits based on random clocks, the random clock generation method for resisting side-channel attacks provided in this invention, through an adaptive feedback loop structure, randomly generates a large number of diverse frequency points, overcoming the shortcomings of existing technologies such as a small number of frequency points and simple frequency point distribution, and effectively improving the protection effect against side-channel attacks. It is highly suitable for cryptographic encryption and decryption scenarios with low clock frequency accuracy requirements, a larger number of frequency points, and faster frequency point switching speeds.

[0065] Example 2

[0066] This embodiment discloses a random clock generation device resistant to side-channel attacks, such as... Figure 2 As shown, it includes a clock source module, a frequency multiplier module, a frequency divider module, a first multiplexer, a second multiplexer, a random number generator module, a glitch filter module, and a frequency detection module;

[0067] The clock source module provides the reference clock for the input adaptive feedback loop; the frequency multiplier module, frequency divider module, frequency detection module, random number generator module, first multiplexer, and second multiplexer together constitute the adaptive feedback loop system. The adaptive feedback loop processes the input clock signal and generates an output clock signal with random, diverse, and uniform frequency distribution.

[0068] The clock source module is used to generate a reference clock, and its output is connected to the input of the frequency multiplier module.

[0069] The frequency multiplier module is used to perform multi-channel frequency multiplication, and its output terminal is connected to the input terminal of the first multiplexer.

[0070] The first multiplexer is used to randomly select one frequency-multiplied clock from multiple frequency-multiplied clocks, and its control terminal is connected to a first configuration signal; under the configuration of the first configuration signal, it randomly selects one frequency-multiplied clock from the input multiple frequency-multiplied clocks and outputs it as the system clock output;

[0071] The frequency divider module is used to perform multi-channel frequency division. Its input terminal is connected to the output terminal of the first multiplexer, and its output terminal is connected to the input terminal of the second multiplexer. The frequency divider module divides the multiplied clock output by the first multiplexer into multiple channels, and outputs multiple frequency-divided clocks with different division coefficients.

[0072] The second multiplexer is used to randomly select one frequency divider clock from multiple frequency divider clocks, and its control terminal is connected to a second configuration signal; under the configuration of the second configuration signal, it randomly selects one frequency divider clock from the input multiple frequency divider clocks and outputs it to the input terminal of the frequency multiplier module;

[0073] The frequency multiplier module selects the output signal of the clock source module for frequency multiplication in the first round of frequency multiplication, and selects the output signal of the second multiplexer for frequency multiplication in other rounds.

[0074] The random number generation module is used to generate random first configuration signals and second configuration signals to control the first multiplexer and the second multiplexer.

[0075] The input of the glitch filtering module is connected to the output of the first multiplexer, and the frequency multiplier clock output by the second multiplexer is filtered out for glitch and then output as the system clock.

[0076] The input terminal of the frequency detection module is connected to the output terminal of the first multiplexer, and is used to detect the frequency multiplier clock output by the second multiplexer in real time, thereby determining whether the system clock is out of control. If it is out of control, frequency correction is performed.

[0077] like Figure 3 As shown, in a preferred embodiment of this invention,

[0078] The frequency multiplier module includes a digital period counter and a fractional frequency divider;

[0079] The first input terminal of the digital period counter is connected to the output terminal of the clock source module, the second input terminal is connected to the output terminal of the second multiplexer, and the output terminal is connected to the input terminal of the fractional frequency divider; the output terminal of the fractional frequency divider serves as the output terminal of the frequency multiplier module.

[0080] The period count value C output by the digital period counter is C = f0 / f x Where f0 is the frequency of the reference clock, and during the first round of multiplication, f... x The initial value is set before startup; during other rounds of multi-channel frequency multiplication, f x The frequency of the divided clock output from the second multiplexer;

[0081] The fractional frequency divider uses a C / N digital fractional frequency division to achieve frequency multiplication; where N = N1, N2, ..., N z1 Where N1, N2, ..., N z1 z1 represents the number of distinct positive integers; z2 represents the frequency multiplication factor.

[0082] Before startup f xThe initial value needs to be set in conjunction with the target frequency range and the frequency division and multiplication coefficients. When the coefficients are fixed, the initial f... x This determines the range of the system's random output clock frequency, thus making it suitable for different frequency range requirements and easy to adjust and adapt.

[0083] The frequency division module uses digital counting for frequency division with a division coefficient of M; where M = M1, M2, ..., M z2 M1, M2, ..., M z2 z1 is a distinct positive integer; z2 is the number of frequency divisions.

[0084] The first multiplexer is a z1-to-1 multiplexer.

[0085] The second multiplexer is a 2-to-1 multiplexer.

[0086] The random number generation module includes a random number generator and a constraint unit;

[0087] The output of the random number generator is connected to the input of the constraint unit. The first output of the constraint unit outputs a first selection signal to a first multiplexer, and the second output outputs a second selection signal to a second multiplexer. The control terminal is connected to the output of the digital period counter.

[0088] The random number generation module is used to generate a random number and output it to the constraint unit;

[0089] Under the control of the period count value C, the constraint unit outputs a first selection signal and a second selection signal.

[0090] In the constraint unit, a multi-segment interval comparison and judgment method is adopted; by setting a segment threshold, it is determined that the frequency relationship C falls within a certain segment, and a selectable path for the corresponding segment is generated. Then, a first selection signal and a second selection signal are generated according to the random number output by the random number generation module.

[0091] By constraining the period count value C, the frequency of frequency multiplication and division can be maintained in a controllable state. This avoids system clock malfunction caused by unreasonable selection of frequency multiplication and division.

[0092] In summary, compared with existing side-channel protection circuits based on random clocks, the random clock generation device for resisting side-channel attacks provided in this embodiment of the invention, through an adaptive feedback loop structure, randomly generates a large number of diverse frequency points, overcoming the shortcomings of existing technologies such as a small number of frequency points and simple frequency point distribution, and effectively improving the protection effect against side-channel attacks. It is highly suitable for cryptographic encryption and decryption scenarios with low clock frequency accuracy requirements, a larger number of frequency points, and faster frequency point switching speeds.

[0093] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for generating a random clock resistant to side-channel attacks, characterized in that, include: Step S1: Select a reference clock as the input clock for the first round of multi-channel frequency multiplication to obtain multiple multiplied clocks with different multiplication coefficients; Step S2: Randomly select one frequency-multiplied clock from the multiple frequency-multiplied clocks, filter out glitches, and use it as the system clock output; Step S3: Divide the randomly selected frequency-multiplying clock into multiple frequency-divided clocks to obtain multiple frequency-divided clocks with different frequency division coefficients; Step S4: Randomly select one frequency divider clock from the multiple frequency divider clocks and use it as the input clock for the next round of multiple frequency multiplication to obtain multiple frequency multiplication clocks with different multiplication coefficients. Step S5: Repeat steps S2 to S4. After multiple rounds of iterative work, a system clock with diverse and random frequencies is obtained.

2. The random clock generation method according to claim 1, characterized in that, The multi-channel frequency multiplication is achieved using a C / N fractional division method; where N = N1, N2, ..., N z1 z1 is the number of frequency multiplication channels; C is the period count value; the period count value C = f0 / f x Where f0 is the frequency of the reference clock, and during the first round of multiplication, f... x The initial value is set; during other rounds of multi-channel frequency multiplication, f x In step S4, the frequency of one frequency-divided clock is randomly selected from the multiple frequency-divided clocks. The multi-channel frequency division uses a digital counting frequency division with a division factor of M; where M = M1, M2, ..., M z2 z2 is the number of frequency division paths.

3. The random clock generation method according to claim 2, characterized in that, A random number generator module is used to generate random first and second configuration signals, wherein, The first configuration signal is used to configure the multiplexer that implements the multiple-to-one selection in step S2; The second configuration signal is used to configure the multiplexer that implements the multiple-choice function in step S4.

4. The random clock generation method according to claim 3, characterized in that, Under the constraint of the period count value C, the random number generation module generates a first configuration signal and a second configuration signal based on the generated random number.

5. The random clock generation method according to claim 4, characterized in that, In the constraint of the period count value C, a multi-segment interval comparison and judgment method is adopted; by setting the segment threshold, it is determined that the period count value C falls within a certain segment, and the corresponding segment selectable path is generated. Then, the first configuration signal and the second configuration signal are generated according to the generated random number.

6. A random clock generation device resistant to side-channel attacks, characterized in that, It includes a clock source module, a frequency multiplier module, a frequency divider module, a first multiplexer, a second multiplexer, and a random number generator module; The clock source module is used to generate a reference clock, and its output is connected to the input of the frequency multiplier module. The frequency multiplier module is used to perform multi-channel frequency multiplication, and its output terminal is connected to the input terminal of the first multiplexer. The first multiplexer is used to randomly select one frequency-multiplied clock from multiple frequency-multiplied clocks, and its control terminal is connected to the first configuration signal; Under the configuration of the first configuration signal, one frequency-multiplied clock is randomly selected from the multiple input frequency-multiplied clocks and output as the system clock output; The frequency divider module is used to perform multi-channel frequency division. Its input terminal is connected to the output terminal of the first multiplexer, and its output terminal is connected to the input terminal of the second multiplexer. The frequency divider module divides the multiplied clock output by the first multiplexer into multiple channels, and outputs multiple frequency-divided clocks with different division coefficients. The second multiplexer is used to randomly select one frequency divider clock from multiple frequency divider clocks, and its control terminal is connected to a second configuration signal; under the configuration of the second configuration signal, it randomly selects one frequency divider clock from the input multiple frequency divider clocks and outputs it to the input terminal of the frequency multiplier module; The frequency multiplier module selects the output signal of the clock source module for frequency multiplication in the first round of frequency multiplication, and selects the output signal of the second multiplexer for frequency multiplication in other rounds. The random number generation module is used to generate random first configuration signals and second configuration signals to control the first multiplexer and the second multiplexer.

7. The random clock generating device according to claim 6, characterized in that, The frequency multiplier module includes a digital period counter and a fractional frequency divider; The first input terminal of the digital period counter is connected to the output terminal of the clock source module, the second input terminal is connected to the output terminal of the second multiplexer, and the output terminal is connected to the input terminal of the fractional frequency divider; the output terminal of the fractional frequency divider serves as the output terminal of the frequency multiplier module. The period count value C output by the digital period counter is C = f0 / f x Where f0 is the frequency of the reference clock, and during the first round of multiplication, f... x The initial value is set; during other rounds of multi-channel frequency multiplication, f x The frequency of the divided clock output from the second multiplexer; The fractional frequency divider uses a digital fractional frequency division of C / N to achieve frequency multiplication; where N = N1, N2, ..., N z Where z is the number of harmonics.

8. The random clock generating device according to claim 7, characterized in that, The random number generation module includes a random number generator and a constraint unit; The output of the random number generator is connected to the input of the constraint unit. The first output of the constraint unit outputs a first selection signal to a first multiplexer, and the second output outputs a second selection signal to a second multiplexer. The control terminal is connected to the output of the digital period counter. The random number generation module is used to generate a random number and output it to the constraint unit; Under the control of the period count value C, the constraint unit outputs a first selection signal and a second selection signal.

9. The random clock generating device according to claim 8, characterized in that, In the constraint unit, a multi-segment interval comparison and judgment method is adopted; by setting a segment threshold, it is determined that the frequency relationship C falls within a certain segment, and a selectable path for the corresponding segment is generated. Then, a first selection signal and a second selection signal are generated according to the random number output by the random number generation module.

10. The random clock generating apparatus according to any one of claims 5-9, characterized in that, It also includes a burr removal module and a frequency detection module; The input of the glitch filtering module is connected to the output of the first multiplexer, and the frequency multiplier clock output by the second multiplexer is filtered for glitch and then output as the system clock. The input terminal of the frequency detection module is connected to the output terminal of the first multiplexer, and is used to detect the frequency multiplier clock output by the second multiplexer in real time, thereby determining whether the system clock is out of control. If it is out of control, frequency correction is performed.

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