Display substrate and display panel

Abstract

The application provides a display substrate and a display panel. The display substrate comprises a display area and a first frame area; the display substrate comprises: a substrate; a plurality of first voltage lines and a plurality of second voltage lines arranged on the substrate; a second voltage line is arranged between two first voltage lines adjacent in a first direction; the plurality of first voltage lines are electrically connected to each other, and the plurality of second voltage lines are electrically connected to each other; a circuit board arranged on the substrate in the first frame area, and the circuit board is arranged on a side of the first voltage line and the second voltage line away from the display area; the circuit board is electrically connected to the plurality of first voltage lines respectively, and is used for providing a first voltage signal for the first voltage line. The application plays a shunt role on the first voltage signal, and avoids the risk of burn caused by the large current density of the first voltage signal on the first voltage lines on the left and right sides under the high-brightness condition.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display substrate and a display panel. BACKGROUND

[0002] In the related art, in the lower frame area of the display product, the number of the first voltage lines is small, and in the high-brightness case, the first voltage signal on the first voltage line has a large current density, which may cause a burn risk. SUMMARY

[0003] The main purpose of the present application is to provide a display substrate and a display panel, which solve the problem that in the related art, in the lower frame area of the display product, the number of the first voltage lines is small, and in the high-brightness case, the first voltage signal on the first voltage line has a large current density, which may cause a burn risk.

[0004] In one aspect, the present application provides a display substrate, comprising a display area and a first frame area; the display substrate comprises:

[0005] a substrate substrate;

[0006] a plurality of first voltage lines and a plurality of second voltage lines arranged on the substrate substrate in the first frame area; a second voltage line is arranged between two adjacent first voltage lines in the first direction; the plurality of first voltage lines are electrically connected to each other, and the plurality of second voltage lines are electrically connected to each other;

[0007] a circuit board arranged on the substrate substrate in the first frame area, and the circuit board is arranged on the side of the first voltage line and the second voltage line away from the display area; the circuit board is electrically connected to the plurality of first voltage lines respectively, and is used for providing a first voltage signal for the first voltage line.

[0008] Optionally, the display substrate comprises at least three second voltage lines arranged in the first frame area; a first voltage line is arranged between adjacent second voltage lines in the first direction;

[0009] the circuit board is electrically connected to the at least three second voltage lines respectively, and is used for providing a second voltage signal for the second voltage line.

[0010] Optionally, the display substrate comprises at least three first voltage lines arranged in the first frame area;

[0011] The at least three first voltage lines and the plurality of second voltage lines are arranged in sequence along the first direction.

[0012] Optionally, the display substrate comprises a first voltage line, a first second voltage line, a second first voltage line, a second second voltage line and a third first voltage line arranged in the first border area along the first direction in sequence; or,

[0013] The display substrate comprises a first voltage line, a first second voltage line, a second first voltage line, a second second voltage line, a third first voltage line, a third second voltage line and a fourth first voltage line arranged in the first border area along the first direction in sequence.

[0014] Optionally, the first border area comprises a bending area and a first area; the first area is located on a side of the bending area close to the display area; the display substrate further comprises a first metal layer arranged on the substrate; the display substrate further comprises a second voltage communication line formed on the first metal layer, the second voltage communication line extends along the first direction, and the second voltage communication line is arranged in the first area.

[0015] The second voltage lines are all in communication with the second voltage communication line, so that the plurality of second voltage lines are electrically connected to each other.

[0016] Optionally, the display substrate further comprises a first side area and a second side area; the first area comprises a circular arc area;

[0017] The first side area is arranged on a first side of the display area, the second side area is arranged on a second side of the display area, the first side and the second side are opposite sides, and the circular arc area is an area of the first area close to the first side area or the second side area;

[0018] The display substrate comprises a first voltage line arranged in the circular arc area.

[0019] Optionally, the display substrate further comprises a second metal layer arranged on the first metal layer away from the substrate;

[0020] The display substrate further comprises a plurality of second voltage connection lines arranged in the circular arc area and extending along a second direction; the second voltage connection lines are formed on the second metal layer; and the first direction intersects the second direction.

[0021] The second voltage connection lines and the second voltage communication line are electrically connected through a via hole.

[0022] Optionally, the display substrate further comprises a first voltage connection line extending along the second direction, and a plurality of first conductive connection portions electrically connected to the end portion of the first voltage connection line away from the display area; the first voltage connection line and the first conductive connection portions are both arranged in the arc region; the first direction intersects the second direction; the first voltage connection line and the first conductive connection portions are both formed in the second metal layer;

[0023] The display substrate further comprises a first voltage line portion arranged in the arc region, the first voltage line portion is included in the first voltage line; the first voltage line portion extends along the first direction, the first voltage line portion is formed in the first metal layer; the orthographic projection of the first voltage line portion on the substrate substrate at least partially overlaps the orthographic projection of the first conductive connection portion on the substrate substrate;

[0024] The first conductive connection portion is electrically connected to the first voltage line portion through a via hole.

[0025] Optionally, the second voltage connection line and the first conductive connection portion are arranged alternately along the first direction.

[0026] Optionally, the display substrate further comprises a plurality of first connection lines and a plurality of second connection lines arranged in the arc region, the first connection lines and the second connection lines both extend along the second direction, and the first connection lines and the second connection lines are both formed in the second metal layer;

[0027] The second connection line is arranged on the side of the first connection line away from the display area; at least two first connection lines are electrically connected to one second connection line; the first direction intersects the second direction;

[0028] The second connection line and the second voltage communication line are electrically connected through a via hole.

[0029] Optionally, the display substrate further comprises a plurality of first voltage connection lines extending along the second direction arranged in the arc region, and a plurality of second conductive connection portions electrically connected to the end portion of the first voltage connection line away from the display area;

[0030] The first direction intersects the second direction; the first voltage connection line and the second conductive connection portion are both formed in the second metal layer;

[0031] The display substrate further comprises a first voltage line portion arranged in the arc region, the first voltage line portion is included in the first voltage line; the first voltage line portion extends along the first direction, the first voltage line portion is formed in the first metal layer; the orthographic projection of the first voltage line portion on the substrate substrate at least partially overlaps the orthographic projection of the second conductive connection portion on the substrate substrate;

[0032] The second conductive connection part is electrically connected with the first voltage line part through a via hole.

[0033] Optionally, the second connection line and the second conductive connection part are arranged alternately along a first direction.

[0034] An area of a projection of the second conductive connection part on the substrate is greater than or equal to 500 μm 2 and less than or equal to 1200 μm 2 .

[0035] Optionally, a projection of the second voltage communication line on the substrate is arranged on a side of a projection of the first voltage line part on the substrate away from the display area.

[0036] Optionally, in the arc region, the first voltage line further comprises a second voltage line part formed in the second metal layer, a third voltage line part formed in the first metal layer, and a fourth voltage line part formed in the conductive layer.

[0037] The second voltage line part is electrically connected with the first voltage line part through a via hole, and a projection of the first voltage line part on the substrate and a projection of the second voltage line part on the substrate at least partially overlap.

[0038] A projection of the third voltage line part on the substrate is arranged on a side of a projection of the first voltage line part on the substrate away from the display area.

[0039] A projection of the fourth voltage line part on the substrate and a projection of the second voltage line part on the substrate at least partially overlap, a projection of the fourth voltage line part on the substrate and a projection of the third voltage line part on the substrate at least partially overlap, and the fourth voltage line part is electrically connected with the second voltage line part and the third voltage line part respectively, so that the second voltage line part and the third voltage line part are electrically connected.

[0040] Optionally, the first region comprises a middle region in addition to the arc region; in the middle region, the first voltage line comprises a fifth voltage line part, a sixth voltage line part, a seventh voltage line part, an eighth voltage line part, and a ninth voltage line part.

[0041] The fifth voltage line part, the sixth voltage line part, the seventh voltage line part, the eighth voltage line part, and the ninth voltage line part all extend along a first direction.

[0042] The fifth voltage line part and the sixth voltage line part are formed in the first metal layer, the seventh voltage line part and the eighth voltage line part are formed in the second metal layer, and the ninth voltage line part is formed in the conductive layer.

[0043] a projection of the seventh voltage line portion on the substrate substrate, a projection of the ninth voltage line portion on the substrate substrate and a projection of the second voltage communication line on the substrate substrate at least partially overlap;

[0044] the ninth voltage line portion, the seventh voltage line portion, the fifth voltage line portion and the sixth voltage line portion are electrically connected;

[0045] the seventh voltage line portion and the eighth voltage line portion are electrically connected.

[0046] Optionally, a length of the second voltage communication line along the second direction is greater than or equal to 20 μm and less than or equal to 120 μm.

[0047] Optionally, the seventh voltage line portion is electrically connected with the eighth voltage line portion through a via hole, at the via hole, the seventh voltage line portion and the eighth voltage line portion are directly contacted, an area of the direct contact between the seventh voltage line portion and the eighth voltage line portion is greater than or equal to 40000 μm 2 and less than or equal to 100000 μm 2 .

[0048] In a second aspect, the embodiment of the present application provides a display panel, comprising the display substrate.

[0049] The embodiment of the present application adds the first voltage line in the first frame area of the display substrate, at least three first voltage lines are arranged in the first frame area and are electrically connected with each other, and the at least three first voltage lines are respectively electrically connected with the circuit board and receive the first voltage signal provided by the circuit board, thereby playing a shunt role for the first voltage signal and avoiding the risk of burnout of the current density of the first voltage signal on the first voltage lines on the left and right sides in a high-brightness case. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 is a layout diagram of the first frame area of the display substrate in the embodiment of the present application;

[0051] Figure 2A is a layout diagram of the left half part in Figure 1 ;

[0052] Figure 2B is a layout diagram of the first gate metal layer in Figure 2A ;

[0053] Figure 2C is a layout diagram of the second gate metal layer in Figure 2B ;

[0054] Figure 2D is a layout diagram of the first source-drain metal layer in Figure 2A ;

[0055] Figure 2E is a layout diagram of the second source-drain metal layer in Figure 1 ;

[0056] Figure 2F is a layout diagram of the anode layer in Figure 2B ;

[0057] Figure 3 is a layout diagram of the first frame area of the display substrate according to at least one embodiment of the present application;

[0058] Figure 4A is a layout diagram of the first frame area of the display substrate according to at least one embodiment of the present application;

[0059] Figure 4B is a layout diagram of the first frame area of the display substrate according to at least one embodiment of the present application;

[0060] Figure 5 is a schematic diagram in which a first dashed box X1 and a second dashed box X2 are added on the basis of Figure 4A ;

[0061] Figure 6 is a layout diagram of a part in the first dashed box X1 of Figure 5 ;

[0062] Figure 7 is a layout diagram of the first source-drain metal layer in Figure 6 ;

[0063] Figure 8 is a layout diagram of the second source-drain metal layer in Figure 6 ;

[0064] Figure 9 is a layout diagram of the anode layer in Figure 6 ;

[0065] Figure 10 is a layout diagram of the third area Q3 in Figure 6 ;

[0066] Figure 11 is an A-A' cross-sectional view in Figure 10 ;

[0067] Figure 12 is a B-B' cross-sectional view in Figure 10 ;

[0068] Figure 13 is a layout diagram of the third area of the display substrate in the first arc area according to at least one embodiment;

[0069] Figure 14 is a layout diagram of the third area of the display substrate in the first arc area according to at least one embodiment of the present application; Figure 13Layout diagram of the first source / drain metal layer in the image;

[0070] Figure 15 yes Figure 13 Layout diagram of the second source / drain metal layer in the image;

[0071] Figure 16 yes Figure 13 Layout diagram of the anode layer in the middle;

[0072] Figure 17 yes Figure 5 The layout diagram of the portion within the second dashed box X2;

[0073] Figure 18 yes Figure 17 Layout diagram of the first source / drain metal layer in the image;

[0074] Figure 19 yes Figure 17 Layout diagram of the second source / drain metal layer in the image;

[0075] Figure 20 yes Figure 17 Layout diagram of the anode layer in the middle;

[0076] Figure 21 yes Figure 17 C-C' section view;

[0077] Figure 22 yes Figure 17 The D-D' section view in the diagram;

[0078] Figure 23 This is a layout diagram of the first border region of the display substrate according to at least one embodiment of the present invention. Detailed Implementation

[0079] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0080] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal, and the other as the second terminal.

[0081] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0082] The display substrate includes a display area and a first frame area; the display substrate includes:

[0083] a substrate substrate;

[0084] a plurality of first voltage lines and a plurality of second voltage lines arranged on the substrate substrate in the first frame area; a second voltage line is arranged between two first voltage lines adjacent in a first direction; the plurality of first voltage lines are electrically connected to each other, and the plurality of second voltage lines are electrically connected to each other;

[0085] a circuit board arranged on the substrate substrate in the first frame area, and the circuit board is arranged on a side of the first voltage line and the second voltage line away from the display area; the circuit board is electrically connected to the plurality of first voltage lines respectively, and is used to provide a first voltage signal for the first voltage line.

[0086] Optionally, the first direction can be a horizontal direction.

[0087] In at least one embodiment of the present application, the display substrate can include a substrate substrate, a plurality of first voltage lines, a plurality of second voltage lines and a circuit board.

[0088] In a display product adopting SIP (VSS In Panel, low voltage line arranged in panel) technology, in order to reduce the current density of the first voltage lines (the first voltage lines can be low voltage lines) on the left and right sides, reduce the voltage drop on the first voltage lines, and improve the brightness uniformity, the present embodiment increases the first voltage lines in the first frame area of the display substrate, arranges a plurality of first voltage lines electrically connected to each other in the first frame area, and electrically connects the plurality of first voltage lines to the circuit board respectively to receive the first voltage signal provided by the circuit board, thereby playing a shunt role for the first voltage signal and avoiding the risk of burnout of the current density of the first voltage signal on the first voltage lines on the left and right sides in the case of high brightness.

[0089] In specific implementation, the display substrate can further include a gate line arranged in the display area, and the gate line extends along a horizontal direction.

[0090] Optionally, the added first voltage lines can be arranged in the center area of the first frame area.

[0091] In the first frame area, at least one second voltage line is arranged between two adjacent first voltage lines.

[0092] In at least one embodiment of the present application, the display substrate includes at least three second voltage lines arranged in the first frame area; a first voltage line is arranged between two adjacent second voltage lines in a first direction;

[0093] The circuit board is electrically connected with the at least three second voltage lines respectively, and is used for providing a second voltage signal for the second voltage lines.

[0094] In a specific implementation, a second voltage line can be added at a center position of the first frame area, and a first voltage line can be added on each of left and right sides of the second voltage line. The added first voltage line and the second voltage line are electrically connected with the circuit board respectively. At least one embodiment of the present application can simultaneously shunt the first voltage signal and the second voltage signal, reduce the load of the first voltage line and the load of the second voltage line, and improve display brightness uniformity.

[0095] Optionally, the display substrate includes at least three first voltage lines arranged in the first frame area.

[0096] The at least three first voltage lines and the plurality of second voltage lines are arranged in sequence along a first direction.

[0097] In a specific implementation, the display substrate can include at least three first voltage lines arranged in the frame area, and the at least three first voltage lines and the plurality of second voltage lines are arranged in sequence along a first direction.

[0098] In at least one embodiment of the present application, the display substrate includes a first first voltage line, a first second voltage line, a second first voltage line, a second second voltage line, and a third first voltage line arranged in sequence along a first direction in the first frame area; or,

[0099] The display substrate includes a first first voltage line, a first second voltage line, a second first voltage line, a second second voltage line, a third first voltage line, a third second voltage line, and a fourth first voltage line arranged in sequence along a first direction in the first frame area.

[0100] In a specific implementation, in the first frame area, the display substrate can include a first first voltage line, a first second voltage line, a second first voltage line, a second second voltage line, and a third first voltage line arranged in sequence along a horizontal direction.

[0101] The first first voltage line, the second first voltage line, and the third first voltage line are electrically connected with each other, and the first second voltage line and the second second voltage line are electrically connected with each other.

[0102] The first first voltage line, the first second voltage line, the second first voltage line, the second second voltage line, and the third first voltage line are electrically connected with the circuit board respectively, and are used for receiving a voltage signal provided by the circuit board.

[0103] The second first voltage line located at the middle position is electrically connected with the circuit board through two ports respectively, and is used for receiving the first voltage signal provided by the circuit board respectively, so that the first voltage signal can be further shunted.

[0104] In the first bezel area, the display substrate can include a first first voltage line, a first second voltage line, a second first voltage line, a second second voltage line, a third first voltage line, a third second voltage line and a fourth first voltage line arranged in the first bezel area along the first direction in sequence, the first first voltage line, the second first voltage line, the third first voltage line and the fourth first voltage line are electrically connected with each other, the first second voltage line, the second second voltage line and the third second voltage line are electrically connected with each other, and the first first voltage line, the first second voltage line, the second first voltage line, the second second voltage line, the third first voltage line, the third second voltage line and the fourth first voltage line are electrically connected with the circuit board respectively, and are used for receiving the voltage signal provided by the circuit board.

[0105] The second second voltage line located at the middle part of the first bezel area is electrically connected with the circuit board through two ports respectively, and is used for receiving the first voltage signal provided by the circuit board respectively, so that the first voltage signal can be further shunted.

[0106] In at least one embodiment of the present application, the first bezel area can be a lower bezel area.

[0107] Figure 1 It is a layout diagram of the first bezel area of the display substrate in at least one embodiment of the present application.

[0108] In Figure 1 , the first first voltage line is labeled as VSS1, the first second voltage line is labeled as VDD1, the second first voltage line is labeled as VSS2, the second second voltage line is labeled as VDD2, and the third first voltage line is labeled as VSS3.

[0109] The driving integrated circuit is labeled as I0, and the flexible circuit board is labeled as F1. The flexible circuit board F1 is used to provide the first voltage signal and the second voltage signal.

[0110] In at least one embodiment of the present application, the first voltage line can be a low voltage line, and the second voltage line can be a high voltage line, but is not limited thereto.

[0111] VSS1, VSS2 and VSS3 are electrically connected with different ports of the flexible circuit board F1 respectively, and are used for receiving the first voltage signal provided by the flexible circuit board F1;

[0112] VDD1 and VDD2 are electrically connected with different ports of the flexible circuit board F1 respectively, for receiving a second voltage signal provided by the flexible circuit board F1.

[0113] Figure 2A is a layout diagram of the left half part in Figure 1 , wherein X0 is a center line of a lower frame area of the display substrate.

[0114] Figure 2B is a layout diagram of the first gate metal layer in Figure 2A Figure 2C is a layout diagram of the second gate metal layer in Figure 2B Figure 2D is a layout diagram of the first source-drain metal layer in Figure 2A Figure 2E is a layout diagram of the second source-drain metal layer in Figure 1 Figure 2F is a layout diagram of the anode layer in Figure 2B

[0115] In Figure 2B , the label GA1 is a first GOA (Gate On Array, gate driving circuit arranged on an array substrate) signal line area, and a GOA signal line is arranged in the GA1.

[0116] In Figure 2C , the label GA2 is a second GOA signal line area, and a GOA signal line is arranged in the GA2.

[0117] In Figure 2D , the label GA3 is a second GOA signal line area, and a GOA signal line is arranged in the GA3.

[0118] In Figure 2D , the label VSS11 is a first signal line part included by VSS1, the label VDD11 is a first signal line part included by VDD1, and the label VSS21 is a first signal line part included by VSS2.

[0119] In Figure 2E , the label VSS12 is a second signal line part included by VSS1, the label VDD12 is a second signal line part included by VDD1, and the label VSS22 is a second signal line part included by VSS2.

[0120] In Figure 2F , the label Y1 is an anode pattern.

[0121] ​​​​​In at least one embodiment of the present application, the first frame area includes a bending area and a first area; the first area is located at one side of the bending area close to the display area; the display substrate further includes a first metal layer disposed on the substrate;

[0122] The display substrate further includes a second voltage communication line formed on the first metal layer, the second voltage communication line extends along a first direction, and the second voltage communication line is disposed on the first area;

[0123] The second voltage lines are all in communication with the second voltage communication line, so that the plurality of second voltage lines are electrically connected with each other.

[0124] In Figure 3 , the first area is labeled as Q1, the bending area is labeled as W1, and the first frame area is labeled as B1.

[0125] Optionally, the display substrate further includes a first side edge area and a second side edge area; the first area includes a circular arc area;

[0126] The first side edge area is disposed on a first side edge of the display area, the second side edge area is disposed on a second side edge of the display area, the first side edge and the second side edge are opposite side edges, and the circular arc area is an area of the first area close to the first side edge area or the second side edge area;

[0127] The display substrate includes a first voltage line partially disposed on the circular arc area.

[0128] In Figure 4A , the first side edge area is labeled as C1, the second side edge area is labeled as C2, the first circular arc area is labeled as R1, and the second circular arc area is labeled as R2.

[0129] In Figure 4A , the first voltage line V1 is partially located in the first circular arc area R1.

[0130] In at least one embodiment of the present application, the first side edge area can be an area disposed on the left side of the display area, and the second side edge area can be an area disposed on the right side of the display area; in the first side edge area and / or the second side edge area, a GOA circuit can be disposed.

[0131] In Figure 4B , the display area is labeled as A0.

[0132] In at least one embodiment of the present application, the display substrate further includes a second metal layer disposed on the first metal layer away from the substrate;

[0133] The display substrate further comprises a plurality of second voltage connection lines arranged in the circular arc region and extending along a second direction; the second voltage connection lines are formed in a second metal layer; the first direction intersects the second direction;

[0134] The second voltage connection lines and the second voltage communication lines are electrically connected through a via.

[0135] Optionally, the first metal layer can be a first source-drain metal layer, the second metal layer can be a second source-drain metal layer, and the conductive layer can be an anode layer.

[0136] In at least one embodiment of the present application, the first direction can be a horizontal direction, and the second direction can be a vertical direction, but the present application is not limited thereto.

[0137] Figure 5 The first dashed box X1 and the second dashed box X2 are added on the basis of Figure 4A The layout diagram of the part in the first dashed box X1 of

[0138] Figure 6 The layout diagram of the part in the first dashed box X1 of Figure 5

[0139] The layout diagram of the part in the first dashed box X1 of Figure 7 The layout diagram of the first source-drain metal layer in Figure 6 The layout diagram of the second source-drain metal layer in Figure 8 The layout diagram of the second source-drain metal layer in Figure 6 The layout diagram of the anode layer in Figure 9 Figure 6 In In

[0140] In Figure 8 In the first dashed box X1 of

[0141] In the first dashed box X1 of Figure 7 In the first dashed box X1 of

[0142] The second voltage connection line L02 and the second voltage communication line T02 are electrically connected through a via.

[0143] In at least one embodiment of the present application, the display substrate further comprises a plurality of first voltage connection lines extending along a second direction and a plurality of first conductive connection parts electrically connected to the end parts of the first voltage connection lines away from the display region; the first voltage connection lines and the first conductive connection parts are arranged in the circular arc region; the first direction intersects the second direction; the first voltage connection lines and the first conductive connection parts are formed in a second metal layer;

[0144] The display substrate further comprises a first voltage line part disposed in the arc region, the first voltage line part being included in a first voltage line; the first voltage line part extends along a first direction, the first voltage line part being formed in a first metal layer; a projection of the first voltage line part on a substrate is at least partially overlapped with a projection of the first conductive connection part on the substrate;

[0145] The first conductive connection part is electrically connected with the first voltage line part through a via hole.

[0146] As shown in Figure 8 , L01 is a first voltage connection line, and DL1 is a first conductive connection part;

[0147] The first voltage connection line L01 extends along a vertical direction, the first conductive connection part DL1 is electrically connected with an end of the first voltage connection line L01 away from a display region, and L01 and DL1 are both formed in a second source-drain metal layer.

[0148] As shown in Figure 7 , L11 is a first voltage line part, and the first voltage line part L11 extends along a horizontal direction.

[0149] As shown in Figure 6-9 , a projection of the first voltage line part L11 on a substrate is at least partially overlapped with a projection of the first conductive connection part DL1 on the substrate;

[0150] L11 is electrically connected with DL1 through a via hole.

[0151] Optionally, the second voltage connection line and the first conductive connection part are alternately arranged along a first direction.

[0152] As shown in Figure 8 , the second voltage connection line L02 and the first conductive connection part DL1 are alternately arranged along a horizontal direction.

[0153] In at least one embodiment of the present application, a projection of the second voltage connection line on a substrate is disposed on a side of a projection of the first voltage line part on the substrate away from a display region.

[0154] As shown in Figure 6-9 , a projection of the second voltage connection line T02 on a substrate is disposed on a side of a projection of the first voltage line part L11 on the substrate away from a display region.

[0155] In at least one embodiment of the present application, each first voltage line can be electrically connected with each other through a voltage line part disposed in an anode layer.

[0156] In at least one embodiment of the present application, in the arc region, the first voltage line further comprises a second voltage line part formed in the second metal layer, a third voltage line part formed in the first metal layer, and a fourth voltage line part formed in the conductive layer;

[0157] The second voltage line part is electrically connected with the first voltage line part through a via, and a projection of the first voltage line part on the substrate substrate at least partially overlaps with a projection of the second voltage line part on the substrate substrate;

[0158] A projection of the third voltage line part on the substrate substrate is arranged on a side of the projection of the first voltage line part on the substrate substrate away from the display area;

[0159] A projection of the fourth voltage line part on the substrate substrate at least partially overlaps with a projection of the second voltage line part on the substrate substrate, and a projection of the fourth voltage line part on the substrate substrate at least partially overlaps with a projection of the third voltage line part on the substrate substrate, and the fourth voltage line part is respectively electrically connected with the second voltage line part and the third voltage line part, so that the second voltage line part and the third voltage line part are electrically connected.

[0160] As shown in FIG. 1, Figure 6-9 In the first arc region, the first voltage line further comprises a second voltage line part L12 formed in the second source-drain metal layer, a third voltage line part L13 formed in the first source-drain metal layer, and a fourth voltage line part L14 formed in the conductive layer;

[0161] The second voltage line part L12 is electrically connected with the first voltage line part L11 through a via, and a projection of the first voltage line part L11 on the substrate substrate at least partially overlaps with a projection of the second voltage line part L12 on the substrate substrate;

[0162] A projection of the third voltage line part L13 on the substrate substrate is arranged on a side of the projection of the first voltage line part L11 on the substrate substrate away from the display area;

[0163] A projection of the fourth voltage line part L14 on the substrate substrate at least partially overlaps with a projection of the second voltage line part L12 on the substrate substrate, and a projection of the fourth voltage line part L14 on the substrate substrate at least partially overlaps with a projection of the third voltage line part L13 on the substrate substrate, and the fourth voltage line part L14 is respectively electrically connected with the second voltage line part L12 and the third voltage line part L13, so that the second voltage line part L12 and the third voltage line part L13 are electrically connected.

[0164] Figure 10 is Figure 6 a layout diagram of the third region Q3 in FIG. 1.

[0165] Figure 11 is Figure 10 a cross-sectional view of A-A' in FIG. Figure 12 is Figure 10 a cross-sectional view of B-B' in FIG.

[0166] In Figure 11 and Figure 12 , the label 11 is the first source-drain metal layer, the label 12 is the second source-drain metal layer, the label J1 is the first insulating layer, and the label J2 is the second insulating layer.

[0167] Optionally, the first insulating layer J1 can be a passivation layer, and the second insulating layer J2 can be a planarization layer.

[0168] In Figure 7 , the label VI1 is the first initial voltage line, and the label VI2 is the second initial voltage line, and VI1 and VI2 extend along the horizontal direction.

[0169] As shown in Figure 6-9 , the second voltage connection line L02 is electrically connected across the first initial voltage line VI1, the second initial voltage line VI2, the first voltage line portion L11, and the second voltage communication line T02;

[0170] The first voltage connection line L01 is electrically connected across the first initial voltage line VI1 and the second initial voltage line VI2 and the first conductive connection portion DL1, and the DL1 formed in the second source-drain metal layer is electrically connected to the first voltage line portion L11 formed in the first source-drain metal layer through a via.

[0171] In at least one embodiment of the present application, a double SD layer process is used to realize the lapping scheme of the first voltage line and the second voltage line in the lower frame area, and one mask is reduced.

[0172] In at least one embodiment of the present application, the display substrate further comprises a plurality of first connection lines and a plurality of second connection lines arranged in the arc region, the first connection lines and the second connection lines both extend along a second direction, and the first connection lines and the second connection lines are both formed in a second metal layer;

[0173] The second connection lines are arranged on a side of the first connection lines away from the display area; at least two first connection lines are electrically connected to one second connection line; and the first direction intersects the second direction.

[0174] The second connection lines are electrically connected to the second voltage communication lines through vias.

[0175] In a specific implementation, the display substrate may include multiple first connecting lines and second connecting lines extending vertically in the arc region; both the first connecting lines and the second connecting lines are formed in the second source / drain metal layer; the second connecting lines are disposed below the first connecting lines, at least two of the first connecting lines are electrically connected to one of the second connecting lines, and the second connecting lines are electrically connected to the second voltage communication line through vias.

[0176] In actual operation, the first connecting line can be electrically connected to the signal line disposed in the display area for transmitting the second voltage signal.

[0177] In at least one embodiment of the present invention, the display substrate further includes a plurality of first voltage connection lines disposed in the arc region and extending along a second direction, and a plurality of second conductive connection portions electrically connected to the ends of the first voltage connection lines away from the display region.

[0178] The first direction intersects with the second direction; both the first voltage connection line and the second conductive connection portion are formed on the second metal layer;

[0179] The display substrate further includes a first voltage line portion disposed in the arc region, the first voltage line portion being included in a first voltage line; the first voltage line portion extends along a first direction and is formed on a first metal layer; the orthographic projection of the first voltage line portion on the substrate at least partially overlaps with the orthographic projection of the second conductive connection portion on the substrate.

[0180] The second conductive connection portion is electrically connected to the first voltage line portion through a via.

[0181] Optionally, the second connecting line and the second conductive connection portion are arranged alternately along the first direction;

[0182] The area of ​​the orthographic projection of the second conductive connection portion on the substrate is greater than or equal to 500 μm. 2 And less than or equal to 1200μm 2 For example, the area of ​​the orthographic projection of the second conductive connection portion onto the substrate can be 800 μm. 2 .

[0183] Figure 13 This is a layout diagram of at least one embodiment of the third region of the first arc region of the display substrate.

[0184] Figure 14 yes Figure 13 Layout diagram of the first source / drain metal layer in the middle. Figure 15 yes Figure 13 The layout diagram of the second source / drain metal layer in the diagram. Figure 16 yes Figure 13a layout diagram of an anode layer in the display panel.

[0185] In Figure 15 , the first connection line is labeled as LX11, the second first connection line is labeled as LX21, and the second connection line is labeled as LX2;

[0186] LX11, LX21, and LX2 all extend in a vertical direction;

[0187] LX2 is disposed on a side of LX11 and LX21 away from the display area;

[0188] LX11 and LX21 are electrically connected, and LX2 is electrically connected to LX11 and LX21, respectively.

[0189] In Figure 14 , the second voltage communication line is labeled as T02;

[0190] As shown in Figure 13-16 , LX2 is electrically connected to T02 through a via.

[0191] In Figure 14 , the first initial voltage line is labeled as VI1, and the second initial voltage line is labeled as VI2; VI1, VI2, and T02 all extend in a horizontal direction.

[0192] As shown in Figure 15 , the first voltage connection line is labeled as L01, and the second conductive connection part is labeled as DL2; the second voltage line part is labeled as L12.

[0193] DL2 is electrically connected to an end of L01 away from the display area;

[0194] L01 and DL2 are both formed in the second source-drain metal layer;

[0195] As shown in Figure 14 , the first voltage line part is labeled as L11, and the first voltage line part L11 extends in a horizontal direction;

[0196] The orthographic projection of the first voltage line part L11 on the substrate substrate at least partially overlaps the orthographic projection of the second conductive connection part DL2 on the substrate substrate;

[0197] The second conductive connection part DL2 is electrically connected to the first voltage line part L11 through a via.

[0198] As shown in Figure 15 , the area of the orthographic projection of the second conductive connection part DL2 on the substrate substrate is greater than or equal to 500 μm 2 and less than or equal to 1200 μm 2 , so as to increase the opening area of the first voltage line segment lap joint.

[0199] In Figure 16 , the label is L14 for the fourth voltage line part.

[0200] As Figure 13-16 shown, the second voltage line part L12 is electrically connected with the first voltage line part L11 through a via, and a projection of the first voltage line part L11 on the substrate substrate at least partially overlaps with a projection of the second voltage line part L12 on the substrate substrate.

[0201] The projection of the fourth voltage line part L14 on the substrate substrate at least partially overlaps with the projection of the second voltage line part L12 on the substrate substrate, and the fourth voltage line part L14 is electrically connected with the second voltage line part L12.

[0202] In Figure 13-16 at least one embodiment, the overlapping area between each connection line for transmitting the second voltage signal and the first voltage line part L11 can be reduced.

[0203] In at least one embodiment of the present application, the first area includes an intermediate area in addition to the arc area; in the intermediate area, the first voltage line includes a fifth voltage line part, a sixth voltage line part, a seventh voltage line part, an eighth voltage line part, and a ninth voltage line part.

[0204] The fifth voltage line part, the sixth voltage line part, the seventh voltage line part, the eighth voltage line part and the ninth voltage line part all extend along the first direction.

[0205] The fifth voltage line part and the sixth voltage line part are formed in the first metal layer, the seventh voltage line part and the eighth voltage line part are formed in the second metal layer, and the ninth voltage line part is formed in the conductive layer.

[0206] The projection of the seventh voltage line part on the substrate substrate, the projection of the ninth voltage line part on the substrate substrate, and the projection of the second voltage line on the substrate substrate at least partially overlap.

[0207] The ninth voltage line part, the seventh voltage line part, the fifth voltage line part and the sixth voltage line part are electrically connected.

[0208] The seventh voltage line part is electrically connected with the eighth voltage line part.

[0209] At least one embodiment of the present application can complete the lapping of the first voltage line and the second voltage line through two source-drain metal layers, and the number of masks used can be reduced.

[0210] Optionally, the length of the second voltage communication line in the second direction is greater than or equal to 20 μm and less than or equal to 120 μm. For example, the length of the second voltage communication line in the second direction can be 80 μm.

[0211] In a specific implementation, the line width of the second voltage communication line can be reduced, and the overlapping area between the first voltage line and the second voltage line can be reduced.

[0212] In at least one embodiment of the present application, the seventh voltage line part is electrically connected to the eighth voltage line part through a via, at the via, the seventh voltage line part directly contacts the eighth voltage line part, and the area of direct contact between the seventh voltage line part and the eighth voltage line part is greater than or equal to 40,000 μm 2 and less than or equal to 100,000 μm 2 . For example, the area of direct contact between the seventh voltage line part and the eighth voltage line part can be equal to 52,500 μm 2 .

[0213] In a specific implementation, at the via, the area of direct contact between the seventh voltage line part and the eighth voltage line part is large, so as to increase the overlapping area of the first source / drain metal layer and the second source / drain metal layer as much as possible on the basis of avoiding the organic clearance area inside and outside the DAM (dam).

[0214] Figure 17 is a layout diagram of the part in the second dashed box X2 in Figure 5 .

[0215] Figure 18 is a layout diagram of the first source / drain metal layer in Figure 17 , Figure 19 is a layout diagram of the second source / drain metal layer in Figure 17 , Figure 20 is a layout diagram of the anode layer in Figure 17 .

[0216] In at least one embodiment of the present application, the first region includes a middle region in addition to the arc region; in FIG. 4, Z1 is the middle region;

[0217] As shown in Figure 17-20 , in the middle region, the first voltage line includes a fifth voltage line part L15, a sixth voltage line part L16, a seventh voltage line part L17, an eighth voltage line part L18, and a ninth voltage line part L19;

[0218] The fifth voltage line part L15, the sixth voltage line part L16, the seventh voltage line part L17, the eighth voltage line part L18, and the ninth voltage line part L19 all extend in the first direction;

[0219] The fifth voltage line portion L15 and the sixth voltage line portion L16 are formed in a first source-drain metal layer, the seventh voltage line portion L17 and the eighth voltage line portion L18 are formed in a second source-drain metal layer, and the ninth voltage line portion L19 is formed in a conductive layer;

[0220] A projection of the seventh voltage line portion L17 on the substrate substrate, a projection of the ninth voltage line portion L19 on the substrate substrate, and a projection of the second voltage communication line T02 on the substrate substrate at least partially overlap;

[0221] The ninth voltage line portion L19, the seventh voltage line portion L17, the fifth voltage line portion L15, and the sixth voltage line portion L16 are electrically connected;

[0222] The seventh voltage line portion L17 and the eighth voltage line portion L18 are electrically connected.

[0223] In Figure 18 , the label L15 is the fifth voltage line portion, the label L16 is the sixth voltage line portion, the label VI1 is the first initial voltage line, and the label VI2 is the second initial voltage line; the label T02 is the second voltage communication line;

[0224] L15, L16, VI1, VI2, and T02 all extend in the horizontal direction.

[0225] In Figure 19 , the label L17 is the seventh voltage line portion, and the label L18 is the eighth voltage line portion;

[0226] In Figure 20 , the label L19 is the ninth voltage line portion.

[0227] As Figure 18 shown, the length of the second voltage communication line T02 in the vertical direction can be 80 μm.

[0228] In specific implementation, the line width of the second voltage communication line T02 can be reduced, and the overlapping area between the first voltage line and the second voltage line can be reduced.

[0229] As Figure 17-20 shown, the seventh voltage line portion L17 is electrically connected to the eighth voltage line portion L18 through a via hole, at the via hole, the seventh voltage line portion L17 directly contacts the eighth voltage line portion L18, and the area of direct contact between the seventh voltage line portion L17 and the eighth voltage line portion L18 can be 52500 μm 2 .

[0230] In the implementation, at the via, the seventh voltage line part and the eighth voltage line part directly contact each other in a large area, so as to increase the overlapping area of the first source-drain metal layer and the second source-drain metal layer as much as possible on the basis of avoiding the organic clearance area inside and outside the DAM (baffle).

[0231] Figure 21 is a cross-sectional view of C-C' in Figure 17 Figure 22 is a cross-sectional view of D-D' in Figure 17

[0232] In Figure 21 , the number 11 is the first source-drain metal layer, the number 12 is the second source-drain metal layer, the number J1 is the first insulating layer, and the number J2 is the second insulating layer; the number 13 is the anode layer, and the number J3 is the third insulating layer.

[0233] In Figure 22 , the number 11 is the first source-drain metal layer, the number 12 is the second source-drain metal layer, and the number J1 is the first insulating layer; and the number J2 is the second insulating layer.

[0234] Optionally, the first insulating layer can be a passivation layer, the second insulating layer can be a first planarization layer, and the third insulating layer can be a second planarization layer.

[0235] Figure 23 is a layout diagram of a first frame area of a display substrate according to at least one embodiment of the present application.

[0236] In Figure 23 , the number VSS1 is the first voltage line, the number VSS2 is the second voltage line, the number VSS3 is the third voltage line, and the number VSS4 is the fourth voltage line.

[0237] The number VDD1 is the first voltage line, the number VDD2 is the second voltage line, and the number VDD3 is the third voltage line.

[0238] In Figure 23 , the number I0 is a driving integrated circuit, and the number F1 is a flexible circuit board.

[0239] VSS1, VSS2, VSS3, VSS4, VDD1, VDD2, and VDD3 are respectively electrically connected with different ports of the flexible circuit board F1, and the flexible circuit board F1 is used to provide a first voltage signal for VSS1, VSS2, VSS3, and VSS4, and provide a second voltage signal for VDD1, VDD2, and VDD3.

[0240] ​​The first in-box test area is labeled as CT1, the second in-box test area is labeled as CT2, the third in-box test area is labeled as CT3, and the fourth in-box test area is labeled as CT4.

[0241] In Figure 23 In at least one embodiment shown, a second voltage line is added at the center position of the display substrate, one first voltage line is added on each side of the second voltage line at the center position, and the added voltage lines are respectively electrically connected with different ports of the flexible circuit board F1. Figure 1 The embodiment shown. Figure 23 At least one embodiment shown can simultaneously split the first voltage signal and the second voltage signal, reduce the load of the first voltage line and the second voltage line, and improve the brightness uniformity.

[0242] The display panel described in the embodiment of the present application comprises the display substrate described above.

[0243] The above is the preferred embodiment of the present application, it should be noted that for those skilled in the art, without departing from the principles of the present application, can make a number of improvements and refinements, these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A display substrate, characterized by, The display substrate comprises a display area and a first frame area; the display substrate comprises: a substrate substrate; a plurality of first voltage lines and a plurality of second voltage lines arranged on the substrate substrate in the first frame area; a second voltage line is arranged between two first voltage lines adjacent in the first direction; the plurality of first voltage lines are electrically connected to each other, and the plurality of second voltage lines are electrically connected to each other; a circuit board arranged on the substrate substrate in the first frame area, and the circuit board is arranged on one side of the first voltage line and the second voltage line away from the display area; the circuit board is electrically connected to the plurality of first voltage lines respectively, and is used for providing a first voltage signal for the first voltage line; The first frame area comprises a first area; the first area comprises a circular arc area; the display substrate further comprises a first metal layer arranged on the substrate substrate; the display substrate further comprises a second voltage communication line formed in the first metal layer; The display substrate further comprises a second metal layer arranged on the first metal layer away from the substrate substrate; the display substrate further comprises a plurality of second voltage connection lines arranged in the circular arc area and extending in a second direction; the second voltage connection lines are formed in the second metal layer; the first direction intersects the second direction; the second voltage connection lines and the second voltage connection lines are electrically connected through a via hole; or, The display substrate further comprises a plurality of first connection lines and a plurality of second connection lines arranged in the circular arc area, the first connection lines and the second connection lines both extend in the second direction, and the first connection lines and the second connection lines are both formed in the second metal layer; the second connection lines are arranged on one side of the first connection lines away from the display area; at least two first connection lines are electrically connected to a second connection line; the first direction intersects the second direction; the second connection lines and the second voltage communication lines are electrically connected through a via hole. 2.The display substrate of claim 1, wherein, The display substrate comprises at least three second voltage lines arranged in the first frame area; a first voltage line is arranged between two second voltage lines adjacent in the first direction; The circuit board is electrically connected to the at least three second voltage lines respectively, and is used for providing a second voltage signal for the second voltage line.

3. The display substrate according to claim 1 or 2, wherein The display substrate comprises at least three first voltage lines arranged in the first frame area; The at least three first voltage lines and the plurality of second voltage lines are arranged in sequence along the first direction. 4.The display substrate of claim 3, wherein, The display substrate comprises a first first voltage line, a first second voltage line, a second first voltage line, a second second voltage line and a third first voltage line arranged in sequence along the first direction in the first frame area; or, The display substrate comprises a first first voltage line, a first second voltage line, a second first voltage line, a second second voltage line, a third first voltage line, a third second voltage line and a fourth first voltage line arranged in sequence along the first direction in the first frame area. 5.The display substrate of claim 1, wherein, The first frame region comprises a bending region; the first region is located at one side of the bending region close to the display region; the second voltage communication line extends along a first direction, and the second voltage communication line is arranged in the first region; The second voltage lines are all in communication with the second voltage communication line, so that the plurality of second voltage lines are electrically connected with each other. 6.The display substrate of claim 5, wherein, The display substrate further comprises a first side region and a second side region; The first side region is arranged at a first side of the display region, the second side region is arranged at a second side of the display region, the first side and the second side are opposite sides, and the arc region is a region of the first region close to the first side region or the second side region; The display substrate comprises a first voltage line arranged in the arc region. 7.The display substrate of claim 6, wherein, When the display substrate comprises a plurality of second voltage connection lines, The display substrate further comprises a first voltage connection line extending along a second direction, and a plurality of first conductive connection portions electrically connected with an end portion of the first voltage connection line away from the display region; the first voltage connection line and the first conductive connection portions are both arranged in the arc region; the first direction intersects the second direction; the first voltage connection line and the first conductive connection portions are both formed in the second metal layer; The display substrate further comprises a first voltage line portion arranged in the arc region, the first voltage line portion being contained in the first voltage line; the first voltage line portion extends along the first direction, and the first voltage line portion is formed in the first metal layer; A projection of the first voltage line portion on the substrate substrate at least partially overlaps a projection of the first conductive connection portion on the substrate substrate; The first conductive connection portion is electrically connected with the first voltage line portion through a via hole. 8.The display substrate of claim 7, wherein, The second voltage connection lines and the first conductive connection portions are arranged alternately along the first direction. 9.The display substrate of claim 6, wherein, When the display substrate comprises a plurality of first connection lines and a plurality of second connection lines, The display substrate further comprises a plurality of first voltage connection lines arranged in the arc region and extending along a second direction, and a plurality of second conductive connection portions electrically connected with end portions of the first voltage connection lines away from the display region; The first direction intersects the second direction; the first voltage connection lines and the second conductive connection portions are both formed in the second metal layer; The display substrate further comprises a first voltage line portion arranged in the arc region, the first voltage line portion being contained in the first voltage line; The first voltage line portion extends along the first direction, and the first voltage line portion is formed in the first metal layer; A projection of the first voltage line portion on the substrate substrate at least partially overlaps a projection of the second conductive connection portion on the substrate substrate; The second conductive connection portion is electrically connected with the first voltage line portion through a via hole. 10.The display substrate of claim 9, wherein, The second connection lines and the second conductive connection portions are arranged alternately along the first direction; An area of a normal projection of the second conductive connection portion on the substrate is greater than or equal to 500 μm 2 and less than or equal to 1200 μm 2 . 11.The display substrate of claim 7 or 9, wherein, A projection of the second voltage communication line on the substrate substrate is arranged at a side of a projection of the first voltage line portion on the substrate substrate away from the display region. 12.The display substrate of claim 7 or 9, wherein, In the arc region, the first voltage line further comprises a second voltage line part formed in the second metal layer, a third voltage line part formed in the first metal layer, and a fourth voltage line part formed in the conductive layer; The second voltage line part is electrically connected to the first voltage line part through a via hole, and a projection of the first voltage line part on the substrate substrate at least partially overlaps a projection of the second voltage line part on the substrate substrate; A projection of the third voltage line part on the substrate substrate is arranged on a side of the projection of the first voltage line part on the substrate substrate away from the display region; A projection of the fourth voltage line part on the substrate substrate at least partially overlaps the projection of the second voltage line part on the substrate substrate, and a projection of the fourth voltage line part on the substrate substrate at least partially overlaps the projection of the third voltage line part on the substrate substrate, and the fourth voltage line part is electrically connected to the second voltage line part and the third voltage line part respectively, so that the second voltage line part and the third voltage line part are electrically connected.

13. The display substrate of claim 6, wherein, The first region comprises a middle region in addition to the arc region; in the middle region, the first voltage line comprises a fifth voltage line part, a sixth voltage line part, a seventh voltage line part, an eighth voltage line part, and a ninth voltage line part; The fifth voltage line part, the sixth voltage line part, the seventh voltage line part, the eighth voltage line part, and the ninth voltage line part all extend along a first direction; The fifth voltage line part and the sixth voltage line part are formed in the first metal layer, the seventh voltage line part and the eighth voltage line part are formed in the second metal layer, and the ninth voltage line part is formed in the conductive layer; A projection of the seventh voltage line part on the substrate substrate, a projection of the ninth voltage line part on the substrate substrate, and a projection of the second voltage communication line on the substrate substrate at least partially overlap; The ninth voltage line part, the seventh voltage line part, the fifth voltage line part, and the sixth voltage line part are electrically connected; The seventh voltage line part is electrically connected to the eighth voltage line part. 14.The display substrate of claim 13, wherein, The length of the second voltage communication line along the second direction is greater than or equal to 20 μm and less than or equal to 120 μm. 15.The display substrate of claim 13, wherein, The seventh voltage line portion is electrically connected with the eighth voltage line portion through a via hole, at which the seventh voltage line portion directly contacts with the eighth voltage line portion, and an area of the direct contact between the seventh voltage line portion and the eighth voltage line portion is greater than or equal to 40000 μm 2 and less than or equal to 100000 μm 2 .

16. A display panel, characterized by A display substrate comprising any one of the display substrates as claimed in any one of claims 1 to 15.

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