Solar cells and photovoltaic modules

Abstract

The application discloses a solar cell and a photovoltaic module, and relates to the technical field of cells, and comprises a first passivation contact step arranged on the surface of a crystalline silicon substrate; a second passivation contact step arranged on the side of the first passivation contact step away from the crystalline silicon substrate; a first passivation anti-reflection step arranged on the side of the first passivation contact step away from the crystalline silicon substrate; a second passivation anti-reflection step arranged on the side of the second passivation contact step away from the first passivation contact step; and an electrode, one end of which is in contact with the first passivation contact step, and the other end of which penetrates the second passivation contact step and the second passivation anti-reflection step in sequence. The scheme provided by the application arranges multiple passivation contact steps, the first passivation contact step is relatively thin in thickness, can reduce parasitic absorption of long-wave light, and effectively improves the long-wave response and double-side rate of the solar cell. The second passivation contact step is relatively thick in thickness, and can ensure that an ohmic contact is formed with metal paste in the metallization process.

Description

Technical Field

[0001] This invention relates to the field of battery technology, and more specifically, to a solar cell and a photovoltaic module. Background Technology

[0002] TOPCon (Tunnel Oxide Passivating Contacts) cells are a type of solar cell based on the selective carrier principle using tunneling oxide passivating contacts. Their back side typically employs a combination of ultrathin tunneling silicon oxide and doped polycrystalline silicon thin films to achieve the passivating contact effect.

[0003] In related technologies, to ensure the matching of metallization paste and passivation effect, the thickness of the doped polycrystalline silicon film needs to be controlled above 90nm. However, excessively thick doped polycrystalline silicon films can cause parasitic absorption in the infrared band on the back side, leading to problems such as poor long-wavelength response and low bifaciality of the battery. Summary of the Invention

[0004] In view of this, the present invention provides a solar cell that can reduce the thickness of the doped polycrystalline silicon thin film, thereby reducing parasitic absorption in the infrared band and improving the long-wavelength response and bifaciality of the solar cell.

[0005] In a first aspect, the present invention provides a solar cell, comprising a crystalline silicon substrate, a first passivated contact step, a second passivated contact step, a first passivated antireflection step, a second passivated antireflection step, and an electrode;

[0006] The first passivated contact step is disposed on the surface of the crystalline silicon substrate;

[0007] The second passivation contact step is disposed on the side of the first passivation contact step away from the crystalline silicon substrate, and is located in the region corresponding to the electrode;

[0008] The first passivation antireflection step is disposed on the side of the first passivation contact step away from the crystalline silicon substrate and in a region that does not contact the second passivation contact step;

[0009] The second passivation anti-reflection step is disposed on the side of the second passivation contact step that is away from the first passivation contact step;

[0010] One end of the electrode is in contact with the first passivation contact step, and the other end passes through the second passivation contact step and the second passivation anti-reflection step in sequence.

[0011] In one possible implementation, the first passivation contact step includes a first tunneling oxide layer and a first doped polysilicon layer;

[0012] The first tunneling oxide layer is disposed on the surface of the crystalline silicon substrate, and the first doped polycrystalline silicon layer is disposed on the side of the first tunneling oxide layer away from the crystalline silicon substrate;

[0013] The second passivation contact step includes a second tunneling oxide layer and a second doped polysilicon layer;

[0014] The second tunneling oxide layer is disposed on the side of the first doped polysilicon layer away from the first tunneling oxide layer, and is located in the region corresponding to the electrode;

[0015] The second doped polysilicon layer is disposed on the side of the second tunneling oxide layer away from the second doped polysilicon layer;

[0016] One end of the electrode is in contact with the first doped polycrystalline silicon layer.

[0017] In one possible implementation, the first tunneling oxide layer comprises at least one of phosphorus-containing silicon oxide, aluminum oxide, silicon oxynitride, and silicon oxycarbide, wherein the phosphorus concentration of the first tunneling oxide layer is not greater than 5 × 10⁻⁶. 19 cm -3 .

[0018] In one possible implementation, the thickness of the first tunneling oxide layer is 0.5 nm to 3 nm.

[0019] In one possible implementation, the phosphorus concentration after activation of the first doped polysilicon layer is 1 × 10⁻⁶. 20 cm -3 -3×10 20 cm -3 .

[0020] In one possible implementation, the thickness of the first doped polycrystalline silicon layer is 30nm-80nm.

[0021] In one possible implementation, the second tunneling oxide layer comprises at least one of phosphorus-containing silicon oxide, aluminum oxide, silicon oxynitride, and silicon carbide, wherein the phosphorus concentration of the second tunneling oxide layer is not greater than 8 × 10⁻⁶. 19 cm -3 -2×10 20 cm -3 .

[0022] In one possible implementation, the thickness of the second tunneling oxide layer is 0.5 nm to 5 nm, and the thickness of the second tunneling oxide layer is greater than the thickness of the first tunneling oxide layer.

[0023] In one possible implementation, the patterned linewidth of the second tunneling oxide layer accounts for 1%-7% of the patterned linewidth of the first doped polysilicon layer, and the patterned linewidth of the second tunneling oxide layer is not greater than 100 μm.

[0024] In one possible implementation, the phosphorus concentration after activation of the second doped polysilicon layer is 2 × 10⁻⁶. 20 cm -3 -4×10 20 cm -3 .

[0025] In one possible implementation, the thickness of the second doped polysilicon layer is 30nm-80nm, and the thickness of the second doped polysilicon layer is greater than the thickness of the first doped polysilicon layer.

[0026] In one possible implementation, the patterned linewidth of the second doped polysilicon layer is no greater than the patterned linewidth of the second tunneling oxide layer.

[0027] In one possible implementation, the first passivation antireflection step includes at least one passivation antireflection layer, the thickness of the first passivation antireflection step being 70nm-110nm and not less than the thickness of the second passivation contact step.

[0028] In one possible implementation, the thickness of the second passivation antireflection step is 50 nm to 110 nm.

[0029] In one possible implementation, the patterned linewidth of the second passivation antireflection step is no greater than 100 μm and no less than the patterned linewidth of the second passivation contact step.

[0030] In one possible implementation, the distance from the end of the electrode that contacts the first passivation contact step to the surface of the second passivation antireflection step away from the second passivation contact step is not less than 100 nm.

[0031] In a second aspect, the present invention provides a photovoltaic module, the photovoltaic module comprising solar cells as described in the first aspect and any possible implementation thereof, wherein at least a portion of the solar cells are electrically connected in a tiling or stacking manner and encapsulated by an encapsulation material.

[0032] Compared with the prior art, the solar cell provided by the present invention achieves at least the following beneficial effects:

[0033] The embodiments provided by this invention feature multi-level passivation contact steps. A first passivation contact step is disposed on the surface of a crystalline silicon substrate to achieve surface passivation of the solar cell. The first passivation contact step is relatively thin, which reduces parasitic absorption of long-wavelength light and effectively improves the long-wavelength response and bifaciality of the solar cell. A second passivation contact step is disposed on the side of the first passivation contact step away from the crystalline silicon substrate and located in the region corresponding to the electrode. The second passivation contact step is relatively thick, which ensures good ohmic contact with the metal paste during the metallization process.

[0034] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0035] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0037] Figure 1 The diagram shown is a partial cross-sectional enlarged schematic diagram of a solar cell provided in an embodiment of the present invention;

[0038] Figure 2 The image shown is a schematic cross-sectional view of a solar cell provided in an embodiment of the present invention.

[0039] Figure 3 The image shown is a second schematic cross-sectional view of a solar cell provided in an embodiment of the present invention.

[0040] Figure 4 The figure shown is an internal quantum conversion efficiency diagram of a solar cell provided in an embodiment of the present invention;

[0041] Figure 5 The diagram shown is one of the flowcharts of a method for manufacturing a solar cell according to an embodiment of the present invention;

[0042] Figure 6 The following is a second flowchart of a method for manufacturing a solar cell according to an embodiment of the present invention. Detailed Implementation

[0043] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0044] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0045] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0046] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0047] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0048] In existing technologies, to ensure the matching of metallization paste and passivation effect, the thickness of the doped polycrystalline silicon film needs to be controlled above 90nm. Excessively thick doped polycrystalline silicon films can cause parasitic absorption in the infrared band on the back side, leading to problems such as poor long-wavelength response and low bifaciality of the battery.

[0049] To address the aforementioned problems in related technologies, embodiments of the present invention provide a solar cell that can reduce the thickness of the doped polycrystalline silicon thin film, thereby reducing parasitic absorption in the infrared band and improving the long-wavelength response and bifaciality of the solar cell.

[0050] Please refer to Figure 1 As shown, an embodiment of the present invention provides a solar cell, including: a crystalline silicon substrate 1, a first passivated contact step 2, a second passivated contact step 3, a first passivated antireflection step 4, a second passivated antireflection step 5, and an electrode 6;

[0051] The first passivated contact step 2 is disposed on the surface of the crystalline silicon substrate 1;

[0052] The second passivation contact step 3 is disposed on the side of the first passivation contact step 2 away from the crystalline silicon substrate 1, and is located in the region corresponding to the electrode 6.

[0053] The first passivation antireflection step 4 is disposed on the side of the first passivation contact step 2 away from the crystalline silicon substrate 1, and in the area that does not contact the second passivation contact step 3.

[0054] The second passivation anti-reflection step 5 is disposed on the side of the second passivation contact step 3 that is away from the first passivation contact step 2;

[0055] One end of electrode 6 is in contact with the first passivation contact step 2, and the other end passes through the second passivation contact step 3 and the second passivation anti-reflection step 5 in sequence.

[0056] It is understood that the surface of the crystalline silicon substrate 1 can be an upper surface and / or a lower surface. In some embodiments, the upper surface refers to the light incident surface, i.e., the surface facing the sun. The lower surface is the surface opposite to the upper surface. For bifacial cells, the lower surface can also serve as a light receiving surface.

[0057] Reference Figure 2 As shown, in an optional embodiment of the present invention, the first passivation contact step 2, the second passivation contact step 3, the first passivation antireflection step 4, the second passivation antireflection step 5, and the electrode 6 are disposed on the lower surface of the crystalline silicon substrate 1. In this case, the upper surface of the crystalline silicon substrate 1 is sequentially disposed with a diffusion layer 7, an interface modification layer 8, a front passivation layer 9, a transition layer 10, a front passivation antireflection layer 11, and a front electrode 12. The diffusion layer 7 can be located on either the upper or lower surface of the crystalline silicon substrate 1. When the crystalline silicon substrate 1 is an N-type crystalline silicon substrate, the element of the diffusion layer 7 is boron or other P-type dopants. The interface modification layer 8 can be an oxide layer; for example, the interface modification layer 8 can be a silicon oxide layer. The interface modification layer 8 has a relatively large thickness, ranging from 3 nm to 10 nm. The front passivation layer 9 can be at least one of silicon nitride, silicon oxynitride, silicon carbonitride, titanium oxide, hafnium oxide, and aluminum oxide. The transition layer 10 can be at least one of silicon oxide and silicon oxynitride. The front passivation antireflection layer 11 can be at least one of silicon nitride, silicon oxynitride, and silicon carbonitride. The interface modification layer 8, the front passivation layer 9, the transition layer 10, and the front passivation antireflection layer 11 constitute the front passivation antireflection structure of the solar cell. However, without being limited to the above description and figures, the front passivation antireflection structure can also be a similar single-layer or multi-layer structure.

[0058] Reference Figure 3 As shown, in an optional embodiment of the present invention, the first passivation contact step 2, the second passivation contact step 3, the first passivation antireflection step 4, the second passivation antireflection step 5, and the electrode 6 are disposed on the upper and lower surfaces of the crystalline silicon substrate 1. In this case, the passivation contact steps are respectively a front passivation contact step and a back passivation contact step, the passivation antireflection steps are respectively a front passivation antireflection step and a back passivation antireflection step, and the electrode 6 is respectively a front electrode and a back electrode.

[0059] Continue to refer to Figure 1 As shown, in an optional embodiment of the present invention, the first passivation contact step 2 includes a first tunneling oxide layer 21 and a first doped polysilicon layer 22; the first tunneling oxide layer 21 is disposed on the surface of the crystalline silicon substrate 1, and the first doped polysilicon layer 22 is disposed on the side of the first tunneling oxide layer 21 away from the crystalline silicon substrate 1.

[0060] Reference Figure 1As shown, this embodiment of the invention employs a stepped passivation contact structure, wherein the thickness of the first tunneling oxide layer 21 is 0.5 nm-3 nm, and the thickness of the first doped polycrystalline silicon layer 22 is 30 nm-80 nm. In the first passivation contact step 2, a composite film of the first tunneling oxide layer 21 and the first doped polycrystalline silicon layer 22 is used, which can effectively passivate the surface of the crystalline silicon substrate 1. Simultaneously, by forming a PN junction or a high-low junction, effective separation of photogenerated carriers is achieved.

[0061] Reference Figure 4 As shown in the figures, the internal quantum conversion efficiency (IQE) of solar cells without a stepped passivation contact structure in related technologies is represented by the dashed line, while the IQE of the solar cell with a stepped passivation contact structure provided in this invention is represented by the solid line. It can be seen that, compared with related technologies, this invention can reduce parasitic absorption in the infrared band (1000-1200nm), and the solar cell can achieve a higher IQE in the longer wavelength band. Specifically, the IQE improvement in the 1100-1150nm band can be greater than 10%.

[0062] The first tunneling oxide layer 21 includes at least one of phosphorus-containing silicon oxide, aluminum oxide, silicon oxynitride, and silicon oxycarbonate.

[0063] The doping element of the first doped polysilicon layer 22 is adapted to the crystalline silicon substrate 1. For example, when the crystalline silicon substrate 1 is an N-type crystalline silicon substrate, the doping element of the first doped polysilicon layer 22 is phosphorus or other N-type doping elements; when the crystalline silicon substrate 1 is a P-type crystalline silicon substrate, the doping element of the first doped polysilicon layer 22 is boron or other P-type doping elements.

[0064] It should be noted that when the first passivation contact step 2, the second passivation contact step 3, the first passivation antireflection step 4, the second passivation antireflection step 5, and the electrode 6 are disposed on the upper and lower surfaces of the crystalline silicon substrate 1, the doping elements of the first doped polysilicon layer 22 and the second doped polysilicon layer 32 located on the upper surface of the crystalline silicon substrate 1 are opposite to those of the first doped polysilicon layer 22 and the second doped polysilicon layer 32 located on the lower surface of the crystalline silicon substrate 1. For example, when the doping elements of the first doped polysilicon layer 22 and the second doped polysilicon layer 32 on the lower surface of the crystalline silicon substrate 1 are phosphorus or other N-type doping elements, the doping elements of the first doped polysilicon layer 22 and the second doped polysilicon layer 32 on the upper surface of the crystalline silicon substrate 1 are boron or other P-type doping elements.

[0065] When the doping element of the first doped polysilicon layer 22 is phosphorus, the phosphorus concentration of the first tunneling oxide layer 21 after phosphorus element extension is no greater than 5 × 10⁻⁶. 19 cm -3The phosphorus concentration after activation of the first doped polycrystalline silicon layer 22 is 1×10⁻⁶. 20 cm -3 -3×10 20 cm -3 .

[0066] Continue to refer to Figure 1 As shown, in an optional embodiment of the present invention, the second passivation contact step 3 includes a second tunneling oxide layer 31 and a second doped polysilicon layer 32; the second tunneling oxide layer 31 is disposed on the side of the first doped polysilicon layer 22 away from the first tunneling oxide layer 21, and is located in the region corresponding to the electrode 6; the second doped polysilicon layer 32 is disposed on the side of the second tunneling oxide layer 31 away from the second doped polysilicon layer 32; one end of the electrode 6 is in contact with the first doped polysilicon layer 22.

[0067] It is understandable that the thickness of the second tunneling oxide layer 31 is 0.5nm-5nm, and the thickness of the second tunneling oxide layer 31 is greater than the thickness of the first tunneling oxide layer 21. The thickness of the second doped polysilicon layer 32 is 30nm-80nm, and the thickness of the second doped polysilicon layer 32 is greater than the thickness of the first doped polysilicon layer 22. In the second passivation contact step 3, a composite structure of the second tunneling oxide layer 31 and the second doped polysilicon layer 32 is adopted. The thicknesses of the second tunneling oxide layer 31 and the second doped polysilicon layer 32 are respectively greater than the composite structure of the first tunneling oxide layer 21 and the first doped polysilicon layer 22. Therefore, the overall thickness of the second passivation contact step 3 is relatively large, which can ensure good ohmic contact with the metal paste during the metallization process.

[0068] Reference Figure 2 As shown, the region corresponding to the electrode 6 in the second tunneling oxide layer 31, when multiple electrodes 6 are provided, is provided with multiple second passivation contact steps 3, which include multiple second tunneling oxide layers 31. The patterned linewidth of the second tunneling oxide layer 31 accounts for 1%-7% of the patterned linewidth of the first doped polycrystalline silicon layer 22, and the patterned linewidth of the second tunneling oxide layer 31 is not greater than 100 μm, and the patterned linewidth of the second doped polycrystalline silicon layer 32 is not greater than the patterned linewidth of the second tunneling oxide layer 31. Here, the patterned linewidth refers to the width in the X direction in the cross-sectional structure of the solar cell.

[0069] The second tunneling oxide layer 31 includes at least one of phosphorus-containing silicon oxide, aluminum oxide, silicon oxynitride, and silicon oxycarbonate.

[0070] The doping element of the second doped polysilicon layer 32 is the same as that of the first doped polysilicon layer 22, and both are compatible with the crystalline silicon substrate 1. When the crystalline silicon substrate 1 is an N-type crystalline silicon substrate, the doping element of the second doped polysilicon layer 32 is phosphorus; when the crystalline silicon substrate 1 is a P-type crystalline silicon substrate, the doping element of the second doped polysilicon layer 32 is boron.

[0071] When the doping element of the second doped polysilicon layer 32 is phosphorus, the phosphorus concentration of the second tunneling oxide layer 31 after phosphorus element extension is no greater than 8 × 10⁻⁶. 19 cm -3 -2×10 20 cm -3 The phosphorus concentration after activation of the second doped polycrystalline silicon layer 32 is 2 × 10⁻⁶. 20 cm -3 -4×10 20 cm -3 .

[0072] Continue to refer to Figure 1 As shown, in an optional embodiment of the present invention, the first passivation antireflection step 4 includes at least one passivation antireflection layer, which includes at least one of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the first passivation antireflection step 4 is 70 nm-110 nm, and is not less than the thickness of the second passivation contact step 3.

[0073] Continue to refer to Figure 1 As shown, in an optional embodiment of the present invention, the second passivation antireflection step 5 includes at least one passivation antireflection layer, which includes at least one of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the second passivation antireflection step 5 is 50 nm to 110 nm. The patterned linewidth of the second passivation antireflection step 5 is not greater than 100 μm and not less than the patterned linewidth of the second passivation contact step 3.

[0074] Continue to refer to Figure 1 As shown, in an optional embodiment of the present invention, the distance from the end of the electrode 6 that contacts the first passivation contact step 2 to the surface of the second passivation antireflection step 5 that is away from the second passivation contact step 3 is not less than 100 nm.

[0075] It is understood that the material of electrode 6 includes silver, aluminum, copper, or an alloy composed of at least two of silver, aluminum, and copper. The patterned linewidth of electrode 6 is no greater than 100 nm and no greater than the patterned linewidth of the second passivation contact step 3.

[0076] In summary, the solar cell provided by this invention achieves at least the following beneficial effects:

[0077] The embodiments provided by this invention feature multi-level passivation contact steps. A first passivation contact step 2 is disposed on the surface of a crystalline silicon substrate 1 to achieve surface passivation of the solar cell. The first passivation contact step 2 is relatively thin, which reduces parasitic absorption of long-wavelength light and effectively improves the long-wavelength response and bifaciality of the solar cell. A second passivation contact step 3 is disposed on the side of the first passivation contact step 2 away from the crystalline silicon substrate 1 and located in the region corresponding to the electrode 6. The second passivation contact step 3 is relatively thick, which ensures good ohmic contact with the metal paste during the metallization process.

[0078] Based on the same inventive concept, embodiments of the present invention also provide a photovoltaic module, the photovoltaic module including the aforementioned solar cells, at least some of the solar cells being connected in a tiling or stacking manner and sealed by an encapsulation material.

[0079] In some embodiments, multiple solar cells are located on the same plane and electrically connected with a gap (small gap) or no gap to form the photovoltaic module. In some embodiments, multiple solar cells are electrically connected in a stacked manner (i.e., located on different planes) to form the photovoltaic module. The solar cells can be employed as follows: Figures 1-3 Any of the types of batteries shown.

[0080] Those skilled in the art will understand that the photovoltaic module and the aforementioned solar cell are based on the same inventive concept, and the features and advantages described above for the solar cell are also applicable to the application of the photovoltaic module. Therefore, the photovoltaic module has at least the same or similar features and advantages as the aforementioned solar cell, which will not be repeated here.

[0081] For example, the photovoltaic module may include, from bottom to top, a backsheet, encapsulation material, a cell string, encapsulation material, and glass. The encapsulation material may be a well-known encapsulation film material such as EVA or POE. The cell string may be formed by splicing or stacking the aforementioned solar cells, and when formed by splicing, there may or may not be gaps between the cells.

[0082] Based on the same inventive concept, embodiments of the present invention also provide a method for manufacturing a solar cell, referring to... Figure 5 As shown, the manufacturing method includes:

[0083] S01. Etching and cleaning are performed on the surface of the crystalline silicon substrate 1.

[0084] It is understandable that wet chemical etching can be used to etch and clean the surface of the crystalline silicon substrate 1 to obtain a smooth and flat surface morphology of the crystalline silicon substrate 1.

[0085] S02. A first tunneling oxide layer 21 is formed on the surface of the crystalline silicon substrate 1.

[0086] It is understandable that a first tunneling oxide layer 21 of 0.5 nm to 3 nm can be formed on the surface of a crystalline silicon substrate 1 by a thermal oxidation method at a temperature of 600 degrees Celsius or higher.

[0087] S03, a first undoped polycrystalline silicon layer is formed on the surface of the first tunneling oxide layer 21 away from the crystalline silicon substrate 1.

[0088] It is understood that either low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition can be used to form a first undoped polycrystalline silicon layer 22 with a thickness of 30nm-80nm on the surface of the first tunneling oxide layer 21 away from the crystalline silicon substrate 1.

[0089] S04. A second initial tunneling oxide layer is formed on the surface of the first undoped polysilicon layer away from the first tunneling oxide layer 21.

[0090] It is understandable that a second initial tunneling oxide layer with a thickness of 0.5 nm to 5 nm can be formed on the surface of the first undoped polycrystalline silicon layer 22 away from the first tunneling oxide layer 21 by a thermal oxidation method at a temperature of 600 degrees Celsius or higher, and the thickness of the second initial tunneling oxide layer is greater than that of the first tunneling oxide layer 21.

[0091] S05, a second initial undoped polysilicon layer is formed on the surface of the second initial tunneling oxide layer away from the first undoped polysilicon layer.

[0092] It is understood that either low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition can be used to form a second initial undoped polysilicon layer with a thickness of 30nm-80nm on the surface of the second initial tunneling oxide layer away from the first undoped polysilicon layer, and the thickness of the second initial undoped polysilicon layer is greater than that of the first undoped polysilicon layer.

[0093] S06. The first undoped polycrystalline silicon layer and the second initial undoped polycrystalline silicon layer are subjected to diffusion treatment to form a first phosphorus-doped polycrystalline silicon layer and a second initial phosphorus-doped polycrystalline silicon layer, respectively, and a phosphorus-sillicate glass layer (PSG) is formed on the surface of the second initial phosphorus-doped polycrystalline silicon layer.

[0094] Understandably, low-pressure diffusion can be used for the diffusion process. When the crystalline silicon substrate 1 is a P-type crystalline silicon substrate, the dopant element is phosphorus. The first phosphorus-doped polycrystalline silicon layer obtained after phosphorus diffusion is the first doped polycrystalline silicon layer 22. The phosphorus concentration of the first phosphorus-doped polycrystalline silicon layer and the second initial phosphorus-doped polycrystalline silicon layer is 1 × 10⁻⁶. 20 cm -3 -4×1020 cm -3 .

[0095] S07. Print an organic coating on the surface of the phosphosilicate glass and dry it at high temperature to form a patterned mask. The width of the patterned mask in the X direction is no more than 100 μm.

[0096] Understandably, the organic coating is prepared using a screen printing method, and the shape of the patterned mask is adapted to the shape of the second passivation contact step 3.

[0097] S08. Etching is performed on the surface of the second initial phosphorus-doped polysilicon layer away from the second initial tunneling oxide layer without patterned mask coverage, retaining the first tunneling oxide layer 21, the first phosphorus-doped polysilicon layer, the phosphorus-silicon glass layer under the patterned mask coverage, the second initial tunneling oxide layer, and the second initial phosphorus-doped polysilicon layer. The first passivation contact step 2 includes the first tunneling oxide layer 21 and the first phosphorus-doped polysilicon layer.

[0098] It is understandable that wet chemical etching can be used to perform the first selective etching on the crystalline silicon substrate 1. In the above steps, the phosphorus silicon glass layer without patterned mask coverage, the second initial tunneling oxide layer, and the second initial phosphorus-doped polysilicon layer are etched. After etching, the second initial tunneling oxide layer under the patterned mask coverage becomes the second tunneling oxide layer 31, the second initial phosphorus-doped polysilicon layer becomes the second phosphorus-doped polysilicon layer, and the second phosphorus-doped polysilicon layer becomes the second doped polysilicon layer 32.

[0099] S09. Etch the surface of the patterned mask to retain the first tunneling oxide layer 21, the first doped polysilicon layer, the second tunneling oxide layer 31, and the second phosphorus doped polysilicon layer.

[0100] Understandably, wet chemical etching can also be used to perform a second selective etching on the crystalline silicon substrate 1. In the above steps, the patterned mask and the phosphosilicate glass layer covered by the patterned mask are etched.

[0101] S10. A first passivation antireflection step 4 and a second passivation antireflection step 5 are formed on the surfaces of the first phosphorus-doped polycrystalline silicon layer and the second phosphorus-doped polycrystalline silicon layer away from the crystalline silicon substrate 1.

[0102] Understandably, the first passivation antireflection step 4 and the second passivation antireflection step 5 are prepared by plasma-enhanced chemical vapor deposition. The first passivation antireflection step 4 and the second passivation antireflection step 5 are prepared using at least one of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 70 nm to 110 nm.

[0103] S11. Electrode 6 is prepared in the region corresponding to the second passivation contact step 3 and the second passivation antireflection step 5.

[0104] It is understandable that electrode 6 is prepared using either screen printing or electroplating. The imaged linewidth of electrode 6 in the X direction is no greater than 100 nm.

[0105] This invention also provides another method for manufacturing a solar cell, see below. Figure 6 As shown, the manufacturing method includes:

[0106] S21. Etching and cleaning are performed on the surface of the crystalline silicon substrate 1.

[0107] S22. A first tunneling oxide layer 21 is formed on the surface of the crystalline silicon substrate 1.

[0108] S23. In-situ doped polycrystalline silicon is deposited on the surface of the first tunneling oxide layer 21 away from the crystalline silicon substrate 1 to form the first original phosphorus-doped polycrystalline silicon layer.

[0109] S24. A second initial tunneling oxide layer is formed on the surface of the first original phosphorus-doped polysilicon layer away from the first tunneling oxide layer 21.

[0110] S25. In-situ doped polysilicon deposition is performed on the surface of the second initial tunneling oxide layer away from the first original phosphorus-doped polysilicon layer to form the second original phosphorus-doped polysilicon layer.

[0111] S26. A silicon oxide mask is formed on the surface of the second original phosphorus-doped polysilicon layer.

[0112] Understandably, silicon oxide masks can be prepared using ion-enhanced chemical vapor deposition, with a thickness of not less than 10 nm.

[0113] S27. Print an organic coating on the surface of a silicon oxide mask and dry it at high temperature to form a patterned mask. The width of the patterned mask in the X direction is no more than 100 μm.

[0114] S28. Etch the surface of the second original phosphorus-doped polysilicon layer away from the second initial tunneling oxide layer without patterned mask coverage, retaining the first tunneling oxide layer 21, the first original phosphorus-doped polysilicon layer, the silicon oxide mask covered by the patterned mask, the second initial tunneling oxide layer, and the second original phosphorus-doped polysilicon layer.

[0115] It is understandable that the second initial tunneling oxide layer after corrosion is the second tunneling oxide layer 31.

[0116] S29. Etch the surface of the patterned mask to retain the first tunneling oxide layer 21, the first original phosphorus-doped polysilicon layer, the second initial tunneling oxide layer, and the second original phosphorus-doped polysilicon layer.

[0117] S30. Perform high-temperature annealing treatment on the solar cells.

[0118] Understandably, the annealing temperature is 750°C-950°C. After annealing, the phosphorus impurities in the first and second original phosphorus-doped polycrystalline silicon films are activated, resulting in a phosphorus concentration of 1×10⁻⁶ after activation. 20 cm -3 -4×10 20 cm -3 The activated first original phosphorus-doped polysilicon is the first phosphorus-doped polysilicon layer, which is the first doped polysilicon layer 22. The activated second original phosphorus-doped polysilicon is the second phosphorus-doped polysilicon layer, which is the second doped polysilicon layer 32.

[0119] S31. A first passivation antireflection step 4 and a second passivation antireflection step 5 are formed on the surfaces of the first phosphorus-doped polycrystalline silicon layer and the second phosphorus-doped polycrystalline silicon layer away from the crystalline silicon substrate 1.

[0120] S32. Electrode 6 is prepared in the region corresponding to the second passivation contact step 4 and the second passivation antireflection step 5.

[0121] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A solar cell, characterized in that, include: A crystalline silicon substrate, a first passivated contact step, a second passivated contact step, a first passivated anti-reflection step, a second passivated anti-reflection step, and an electrode; The first passivation contact step is disposed on the surface of the crystalline silicon substrate; the first passivation contact step includes a first tunneling oxide layer and a first doped polysilicon layer; the first tunneling oxide layer is disposed on the surface of the crystalline silicon substrate, and the first doped polysilicon layer is disposed on the side of the first tunneling oxide layer away from the crystalline silicon substrate; The second passivation contact step is disposed on the side of the first passivation contact step away from the crystalline silicon substrate and is located in the region corresponding to the electrode; the second passivation contact step includes a second tunneling oxide layer and a second doped polysilicon layer; the second tunneling oxide layer is disposed on the side of the first doped polysilicon layer away from the first tunneling oxide layer and is located in the region corresponding to the electrode; the second doped polysilicon layer is disposed on the side of the second tunneling oxide layer away from the first doped polysilicon layer; The thickness of the second tunneling oxide layer is greater than the thickness of the first tunneling oxide layer; the thickness of the second doped polysilicon layer is greater than the thickness of the first doped polysilicon layer; The first passivation antireflection step is disposed on the side of the first passivation contact step away from the crystalline silicon substrate, and in a direction perpendicular to the plane of the crystalline silicon substrate, the first passivation antireflection step and the second passivation contact step do not overlap. The second passivation anti-reflection step is disposed on the side of the second passivation contact step that is away from the first passivation contact step; One end of the electrode is in contact with the first doped polycrystalline silicon layer, and the other end passes through the second passivation contact step and the second passivation antireflection step in sequence; the distance from the end of the electrode in contact with the first passivation contact step to the surface of the second passivation antireflection step away from the second passivation contact step is not less than 100 nm. The first passivation contact step, the second passivation contact step, the first passivation antireflection step, the second passivation antireflection step, and the electrode are disposed on the upper and lower surfaces of the crystalline silicon substrate. The first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer located on the upper surface of the crystalline silicon substrate have opposite doping elements to the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer located on the lower surface of the crystalline silicon substrate.

2. The solar cell according to claim 1, characterized in that, The first tunneling oxide layer comprises at least one of phosphorus-containing silicon oxide, aluminum oxide, silicon oxynitride, and silicon oxycarbide, wherein the phosphorus concentration of the first tunneling oxide layer is not greater than [missing value]. .

3. The solar cell according to claim 2, characterized in that, The thickness of the first tunneling oxide layer is 0.5nm-3nm.

4. The solar cell according to claim 2, characterized in that, The phosphorus concentration after activation of the first doped polycrystalline silicon layer is .

5. The solar cell according to claim 2, characterized in that, The thickness of the first doped polycrystalline silicon layer is 30nm-80nm.

6. The solar cell according to claim 2, characterized in that, The second tunneling oxide layer comprises at least one of phosphorus-containing silicon oxide, aluminum oxide, silicon oxynitride, and silicon oxycarbide, wherein the phosphorus concentration of the second tunneling oxide layer is not greater than [missing value]. .

7. The solar cell according to claim 2, characterized in that, The thickness of the second tunneling oxide layer is 0.5nm-5nm.

8. The solar cell according to claim 2, characterized in that, The patterned linewidth of the second tunneling oxide layer is 1%-7% of the patterned linewidth of the first doped polysilicon layer, and the patterned linewidth of the second tunneling oxide layer is not greater than... .

9. The solar cell according to claim 2, characterized in that, The phosphorus concentration after activation of the second doped polycrystalline silicon layer is .

10. The solar cell according to claim 2, characterized in that, The thickness of the second doped polycrystalline silicon layer is 30nm-80nm.

11. The solar cell according to claim 2, characterized in that, The patterned linewidth of the second doped polysilicon layer is not greater than the patterned linewidth of the second tunneling oxide layer.

12. The solar cell according to claim 1, characterized in that, The first passivation antireflection step includes at least one passivation antireflection layer, and the thickness of the first passivation antireflection step is 70nm-110nm, and is not less than the thickness of the second passivation contact step.

13. The solar cell according to claim 1, characterized in that, The thickness of the second passivation antireflection step is 50nm-110nm.

14. The solar cell according to claim 1, characterized in that, The patterned linewidth of the second passivation anti-reflection step is no greater than [missing value]. And not less than the patterned linewidth of the second passivation contact step.

15. A photovoltaic module, characterized in that, The photovoltaic module includes the solar cells according to any one of claims 1-14, wherein at least some of the solar cells are electrically connected in a tiling or stacking manner and encapsulated by an encapsulation material.

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