High double-sided rate TOPCon battery based on Poly Finger structure and preparation method thereof

Abstract

The invention discloses a high double-sided rate TOPCon battery based on a Poly Finger structure and a preparation method thereof. The preparation method comprises the following steps: S1, performing alkali texturing treatment to form a positive pyramid textured surface; s2, performing boron diffusion to form a boron diffusion layer; s3, removing borosilicate glass on the back surface; s4, polishing the substrate; s5, sequentially depositing a silicon dioxide tunneling oxide layer, a phosphorus-doped amorphous silicon layer and a silicon dioxide mask layer on the back surface; s6, performing annealing crystallization to obtain a phosphorus-doped polycrystalline silicon layer and a phosphorosilicate glass layer; s7, the phosphorosilicate glass is loosened through picosecond laser; s8, performing surface etching to form a Poly Finger structure; s9, polishing the back surface; s10, performing ink jet etching on a non-grid line area, and cleaning to obtain an inverted pyramid light trapping structure; s11, preparing an aluminum oxide passivation layer; s12, coating the front and back surfaces; and S13, preparing an electrode. The product prepared by the invention can significantly improve the back efficiency and the cell double-sided rate.

Description

A high bifaciality TOPCon solar cell based on a Poly Finger structure and its fabrication method Technical Field

[0001] This invention belongs to the field of solar cell technology, specifically a high bifaciality TOPCon solar cell based on a Poly Finger structure and its fabrication method. Background Technology

[0002] TOPCon (Tunnel Oxide Passivated Contact) solar cell technology is a tunneling oxide passivated contact solar cell based on the selective carrier principle, first proposed by the Fraunhofer Institute for Solar Energy Research in Germany in 2014. This technology uses N-type silicon as a substrate, on which an ultrathin silicon dioxide (SiO2) tunneling layer and a phosphorus-doped polycrystalline silicon (poly-Si) layer are sequentially fabricated. These two layers constitute a composite functional layer, forming a highly efficient passivated contact structure that significantly suppresses carrier recombination losses at the surface and recombination in the metal contact region.

[0003] However, the thick polysilicon layer in the non-gate region introduces a significant parasitic absorption effect, resulting in a marked loss in short-circuit current density (Jsc). Therefore, the Poly Finger structure significantly reduces short-circuit current loss by selectively removing the polysilicon layer in the non-gate region. However, since the back of the cell typically still uses a polished surface structure, when incident light shines on this interface, it causes a large amount of light energy loss, reducing the power generation on the back side and limiting the improvement of the cell's bifaciality. Summary of the Invention

[0004] The primary objective of this invention is to provide a method for fabricating a high bifaciality TOPCon solar cell based on a Poly Finger structure. The method involves selectively modifying the polycrystalline silicon layer in the non-gate area on the back side using a laser, followed by etching away the polycrystalline silicon in that area using an alkaline solution. In the exposed silicon wafer area, an acidic etching solution is deposited using an inkjet printer to form an inverted pyramid light-trapping structure. This inverted pyramid light-trapping structure can effectively suppress parasitic absorption effects and simultaneously increase back-side light absorption.

[0005] The second objective of this invention is to provide a high bifaciality TOPCon cell based on a Poly Finger structure. Compared with conventional TOPCon cell structures, the polycrystalline silicon in the non-grid area is removed, and an inverted pyramid light-trapping structure is fabricated on the silicon substrate. This optimizes the electron transport path, increases the short-circuit current, and the inverted pyramid light-trapping structure increases back-side light absorption, thereby improving the back-side power and bifaciality of the cell, resulting in a significant improvement in cell efficiency.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] A method for fabricating high bifaciality TOPCon solar cells based on a Poly Finger structure, comprising the following steps:

[0008] S1. Textured surface treatment: Anisotropic alkaline texturing is performed on both sides of the silicon wafer to form a uniformly distributed micron-level positive pyramid textured surface on the front side of the silicon wafer.

[0009] S2. Boron diffusion: Boron diffusion is performed on the front or both sides of the silicon wafer to form a boron diffusion layer;

[0010] S3, Deborosilicate Glass: Deborosilicate glass for the back and edge areas of silicon wafers;

[0011] S4. Substrate polishing: Polish the back of the silicon wafer to form a highly flat polished surface. After cleaning, remove metal ions and ensure the surface is hydrophobic.

[0012] S5. Backside deposition: Sequentially deposit a silicon dioxide tunneling oxide layer, a phosphorus-doped amorphous silicon layer, and a silicon dioxide mask layer on the backside of the silicon wafer.

[0013] S6. Annealing and crystallization: High-temperature annealing and crystallization treatment is performed on the phosphorus-doped amorphous silicon layer to obtain a phosphorus-doped polycrystalline silicon layer. At the same time, phosphorus atoms diffuse into the silicon dioxide mask layer to form phosphorosilicate glass, which improves the density of the film.

[0014] S7. Laser modification: Using a picosecond laser to loosen the phosphosilicate glass in the non-gateline area on the back of the silicon wafer;

[0015] S8. Surface etching: Remove the loosened phosphorus silica glass, phosphorus-doped polysilicon layer and silicon dioxide tunnel oxide layer in the non-gate area and continue etching to the substrate layer to form a polyfinger structure.

[0016] S9. Backside polishing: Polish the backside of the silicon wafer to form a highly flat polished surface. After cleaning, remove metal ions and ensure the surface is hydrophobic.

[0017] S10, Inkjet Etching: Using an inkjet printer, an etched droplet array is printed on the non-grid area on the back side, and the inverted pyramid light-trapping structure is obtained by cleaning.

[0018] S11. Preparation of aluminum oxide passivation layer: An aluminum oxide passivation layer is prepared on the front and back sides of the silicon wafer using atomic layer deposition.

[0019] S12, Front and back coating: Silicon nitride antireflective coating is deposited on the outside of the aluminum oxide passivation layer;

[0020] S13. Electrode fabrication: Print paste in the reserved areas of the front and back gate lines of the silicon wafer to prepare the front metal electrode and the back metal electrode, respectively.

[0021] In step S1, the height of the pyramidal textured surface is 1-5 μm and the length of the base side is 2-7 μm; in step S2, the depth of the boron diffusion layer is 0.1-1 μm.

[0022] In step S3, the borosilicate glass is treated with an acid bath with a concentration controlled at 300-450 μs / cm. In step S4, the substrate polishing and in step S9, the back surface polishing are performed using a tank-type machine with NaOH + H2O + polishing additives to polish the back surface of the silicon wafer, forming a highly flat polished surface. Then, ozone or hydrogen peroxide with alkali is used to clean the additive residue. Finally, a combination of hydrochloric acid and dehydrating additives is used to remove metal ions and ensure surface hydrophobicity.

[0023] In step S5, the back-side deposition uses PECVD plasma-enhanced chemical vapor deposition, with the temperature controlled at 400-500℃ and the pressure controlled at 250-270Pa. On the back side of the silicon wafer, a silicon dioxide tunneling oxide layer with a thickness of 1-3nm is first deposited using N2O, then a phosphorus-doped amorphous silicon layer with a thickness of 50-150nm is deposited using SiH4 and PH3, and finally a silicon dioxide mask layer with a thickness of 8-15nm is deposited using N2O and SiH4.

[0024] The annealing and crystallization process in step S6 is as follows: The phosphorus-doped amorphous silicon layer on the back side of the silicon wafer is annealed using a vapor-phase high-temperature annealing method in a high-temperature annealing furnace. First, it is heat-treated at 860–895℃ for 20–40 minutes, followed by back-side annealing at 800–860℃ for 20–30 minutes, advancing to a junction depth of 50–150 nm and a doping concentration of 1 × 10⁻⁶ nm. 19 -1×10 21 cm -3 The n+-poly layer; during the annealing process, phosphorus atoms in the phosphorus-doped amorphous silicon layer diffuse into the surface silicon dioxide mask layer to form phosphosilicate glass.

[0025] The picosecond laser in step S7 has a single pulse energy of 50-200 μJ and a wavelength of 395-532 nm, and a mask layer for the reserved grid area is retained during laser quality modification.

[0026] The specific process of inkjet etching in step S10 is as follows: using an inkjet printer, an etch droplet array is printed on the non-grid area on the back side. The etchant is a mixed solution of AgNO3 / Cu(NO3)2 and HF / H2O2. The volume of the printed etch droplets is 1-20 pL. After etching, the droplets are cleaned. The resulting inverted pyramid light trapping structure has a bottom edge length of 2-7 μm and a depth of 1-5 μm.

[0027] The method for preparing the alumina passivation layer in step S11 is as follows: using an ALD atomic layer deposition furnace, the temperature is controlled at 180-250℃ and the pressure is controlled at 60-100Pa, and trimethylaluminum and argon are used to form an alumina passivation layer with a thickness of 3-10nm on both the front and back sides of the silicon wafer.

[0028] The front and back coating process in step S12 is as follows: using PECVD plasma-enhanced chemical vapor deposition, the temperature is controlled at 380℃~450℃, the pressure is controlled at 2300-2600Pa, and the N2O:SiH4 flow ratio is controlled at 1:3-10 for 200-350s to form a silicon nitride antireflection film with a thickness of 50-100nm on the front and back of the silicon wafer.

[0029] The electrode preparation process in step S13 is as follows: paste is printed on the front and back gate line reserved areas of the silicon wafer respectively, and sintered in a sintering furnace at 700-800℃ for 1.5-2.5 minutes to form the front metal electrode and the back metal electrode.

[0030] A solar cell fabricated using a high bifaciality TOPCon cell fabrication method based on a Poly Finger structure is used to convert received light energy into electrical energy.

[0031] The present invention has the following advantages over the prior art:

[0032] In the preparation method of this invention, during the processing of silicon wafers, the polycrystalline silicon layer in the non-gate area on the back side is modified to accelerate the etching rate of alkaline solution until it is etched to the silicon substrate. Compared with conventional TOPCon cells, this method not only ensures the silicon dioxide tunneling oxide layer structure but also reduces the parasitic absorption of the polycrystalline silicon layer, thereby increasing the short-circuit current density. At the same time, for the low bifaciality of PolyFinger structure TOPCon cells, an inverted pyramid light-trapping structure is formed by etching the non-gate area with acid using an inkjet printer. Inkjet printing allows for fine printing without the need for a mask layer to protect the polycrystalline silicon, reducing the process difficulty. It also increases the absorption of light on the back side, improves the bifaciality of the cell, and thus improves the cell efficiency. Attached Figure Description

[0033] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0034] Figure 1 is a flowchart of a high bifaciality TOPCon cell fabrication method based on a Poly Finger structure provided by the present invention;

[0035] Figure 2 is a schematic diagram of the layer structure of the high bifaciality TOPCon cell based on the Poly Finger structure provided in Embodiment 1 of the present invention;

[0036] Figure 3 is a schematic diagram of the layer structure of a conventional TOPCon-Poly Finger battery provided in Comparative Example 1 of the present invention.

[0037] Figure 4 is a schematic diagram of the layer structure of a conventional TOPCon battery provided in Comparative Example 2 of the present invention. Detailed Implementation

[0038] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0039] The terms “a,” “one,” “the,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that other elements / components / etc. may exist in addition to the listed elements / components / etc.

[0040] As shown in Figure 1-2, a method for fabricating a high bifaciality TOPCon solar cell based on a Poly Finger structure includes the following steps:

[0041] S1. Textured surface treatment: N-type monocrystalline silicon wafers are selected, and NaOH and additives are used to perform anisotropic alkaline texturing on both sides of the silicon wafers to form a uniformly distributed micron-level positive pyramid textured surface on the front side of the silicon wafer. The height of the positive pyramid textured surface is 1-5μm, and the length of the bottom edge is 2-7μm.

[0042] S2. Boron diffusion: Boron diffusion is performed on the front or both sides of the texturized silicon wafer using a low-pressure tubular boron diffusion furnace. The boron source used is BCl3, and the diffusion temperature is 850-880℃, forming a boron diffusion layer with a depth of 0.1-1μm.

[0043] S3, Borosilicate glass on the back surface: Borosilicate glass treatment is performed on the back and edge areas of the silicon wafer using a chain acid etching method, with the acid concentration controlled at 300-450μs / cm.

[0044] S4. Substrate polishing: The back of the silicon wafer is polished using a tank machine with NaOH + H2O + polishing additives to form a highly flat polished surface; then ozone or hydrogen peroxide with alkali is used to clean the additive residue; finally, hydrochloric acid with dehydrating additives is used to remove metal ions and ensure surface hydrophobicity, with the reaction amount controlled not to exceed 0.2g.

[0045] S5. Backside deposition: Using PECVD plasma-enhanced chemical vapor deposition, the temperature is controlled at 400-500℃ and the pressure is controlled at 250-270Pa. On the backside of the silicon wafer, a silicon dioxide tunneling oxide layer with a thickness of 1-3nm is first deposited using N2O, then a phosphorus-doped amorphous silicon layer with a thickness of 50-150nm is deposited using SiH4 and PH3, and finally a silicon dioxide mask layer with a thickness of 8-15nm is deposited using N2O and SiH4.

[0046] S6. Annealing and Crystallization: The phosphorus-doped amorphous silicon layer on the back side of the silicon wafer is annealed using a vapor-phase high-temperature annealing method in a high-temperature annealing furnace. First, heat treatment is performed at 860–895℃ for 20–40 min, followed by back-side annealing at 800–860℃ for 20–30 min, advancing the process to a junction depth of 50–150 nm and a doping concentration of 1×10⁻⁶ nm. 19 -1×10 21 cm -3 The n+-poly layer; during the annealing process, phosphorus atoms in the phosphorus-doped amorphous silicon layer diffuse into the surface silicon dioxide mask layer to form phosphosilicate glass;

[0047] S7. Laser modification: A picosecond laser with a single pulse energy of 50-200μJ and a wavelength of 395-532nm is used to loosen the phosphorosilicate glass layer in the non-gateline area on the back of the silicon wafer to facilitate subsequent etching.

[0048] S8. Surface etching: A chain pickling machine with hydrofluoric acid is used to etch the phosphorosilicate glass that is coated on the front and side of the silicon wafer. The polysilicon coated on the front is etched with alkaline solution to remove the loose phosphorosilicate glass layer and phosphorus-doped polysilicon layer in the non-gate area and the silicon dioxide tunnel oxide layer, and the etching continues for 1-8 μm until the base layer is formed to form a Poly Finger structure.

[0049] S9. Backside Polishing: Hydrofluoric acid is used to remove the borosilicate glass on the front side and the phosphosilicate glass in the back grid area. A tank-type machine with NaOH + H2O + polishing additives is used to polish the back side of the silicon wafer to form a highly reflective polished surface. Then, ozone or hydrogen peroxide with alkali is used to clean the additive residue. Finally, hydrochloric acid with dehydrating additives is used to remove metal ions and ensure surface hydrophobicity, with the reaction amount controlled not to exceed 0.04g.

[0050] S10. Inkjet etching of the non-grid area on the back side: Using an inkjet printer, an etchant droplet array is printed on the non-grid area on the back side. The etchant is a mixed solution of AgNO3 / Cu(NO3)2 and HF / H2O2. The volume of the printed etchant droplets is 1-20 pL. After etching, the droplets are cleaned. The resulting inverted pyramid light trapping structure has a bottom edge length of 2-7 μm and a depth of 1-5 μm.

[0051] S11. Preparation of aluminum oxide passivation layer (preparing aluminum oxide passivation layer on the front and back of silicon wafer using atomic layer deposition): using an ALD atomic layer deposition furnace, the temperature is controlled at 180-250℃ and the pressure is controlled at 60-100Pa, using trimethylaluminum and argon gas, to form an aluminum oxide passivation layer with a thickness of 3-10nm on the front and back of the silicon wafer.

[0052] S12. Front and back coating: Using PECVD plasma-enhanced chemical vapor deposition, the temperature is controlled at 380℃~450℃ and the pressure is controlled at 2300-2600Pa. The N2O:SiH4 flow ratio is controlled at 1:3-10 and the deposition time is 200-350s to form a silicon nitride antireflection film with a thickness of 50-100nm on the front and back of the silicon wafer.

[0053] S13. Electrode preparation: Print paste on the front and back gate line reserved areas of the silicon wafer respectively and sinter in a sintering furnace at 700-800℃ for 1.5-2.5 minutes to form the front metal electrode and the back metal electrode.

[0054] Example 1

[0055] A method for fabricating a high bifaciality TOPCon solar cell based on a Poly Finger structure includes the following steps:

[0056] S1. Textured surface treatment: N-type monocrystalline silicon wafers are selected, and NaOH and additives are used to perform anisotropic alkaline texturing on both sides of the silicon wafers to form a uniformly distributed micron-level positive pyramid textured surface on the front side of the silicon wafer, with a height of 2μm.

[0057] S2. Boron diffusion: Boron diffusion is performed on the front or both sides of the texturized silicon wafer using a low-pressure tubular boron diffusion furnace. The boron source used is BCl3, the diffusion temperature is 860℃, and a boron diffusion layer with a depth of 0.5μm is formed.

[0058] S3, Borosilicate glass on the back surface: Borosilicate glass treatment is performed on the back and edge areas of the silicon wafer using a chain acid etching method, with the acid concentration controlled at 400 μs / cm.

[0059] S4. Substrate polishing: The back of the silicon wafer is polished using a tank machine with NaOH + H2O + polishing additives to form a highly flat polished surface; then ozone or hydrogen peroxide with alkali is used to clean the additive residue; finally, hydrochloric acid with dehydrating additives is used to remove metal ions and ensure surface hydrophobicity, with the reaction amount controlled at 0.2g.

[0060] S5. Backside deposition: Using PECVD plasma-enhanced chemical vapor deposition, the temperature is controlled at 450℃ and the pressure is controlled at 270Pa. On the backside of the silicon wafer, a silicon dioxide tunneling oxide layer with a thickness of 1.5nm is first deposited using N2O, then a phosphorus-doped amorphous silicon layer with a thickness of 100nm is deposited using SiH4 and PH3, and finally a silicon dioxide mask layer with a thickness of 10nm is deposited using N2O and SiH4.

[0061] S6. Annealing and Crystallization: The phosphorus-doped amorphous silicon layer on the back side of the silicon wafer is annealed using a vapor-phase high-temperature annealing method in a high-temperature annealing furnace. First, it is heat-treated at 800℃ for 28 minutes, followed by a back-side annealing process at 840℃ for 25 minutes, advancing to a junction depth of 100 nm and a doping concentration of 1 × 10⁻⁶. 20 cm -3 The n+-poly layer; during the annealing process, phosphorus atoms in the phosphorus-doped amorphous silicon layer diffuse into the surface silicon dioxide mask layer to form phosphosilicate glass;

[0062] S7. Laser modification: A picosecond laser with a single pulse energy of 50-200μJ and a wavelength of 395-532nm is used to loosen the phosphorosilicate glass layer in the non-gateline area on the back of the silicon wafer to facilitate subsequent etching.

[0063] S8. Surface Etching: A chain pickling machine with hydrofluoric acid is used to etch the phosphosilicate glass layer coated on the front and side of the silicon wafer. The polysilicon coated on the front side is etched with alkaline solution to remove the loosened phosphosilicate glass layer and phosphorus-doped polysilicon layer in the non-gate area and the silicon dioxide tunnel oxide layer, and the etching continues for 3μm until the substrate layer is reached to form a polyfinger structure.

[0064] S9. Backside Polishing: Hydrofluoric acid is used to remove the borosilicate glass on the front side and the phosphosilicate glass in the back grid area. A tank-type machine with NaOH + H2O + polishing additives is used to polish the back side of the silicon wafer to form a highly reflective polished surface. Then, ozone or hydrogen peroxide with alkali is used to clean the additive residue. Finally, hydrochloric acid with dehydrating additives is used to remove metal ions and ensure surface hydrophobicity, with the reaction amount controlled not to exceed 0.04g.

[0065] S10. Backside non-grid area inkjet etching: Using an inkjet printer, an etchable droplet array is printed on the backside non-grid area. The etchant is a mixed solution of AgNO3 / Cu(NO3)2 and HF / H2O2. The volume of the printed etchable droplets is 5pL. After etching, the area is cleaned. The depth of the inverted pyramid light-trapping structure prepared is 2μm.

[0066] S11. Preparation of aluminum oxide passivation layer (aluminum oxide passivation layer is prepared on the front and back of silicon wafer using atomic layer deposition): using an ALD atomic layer deposition furnace, the temperature is controlled at 200℃ and the pressure is controlled at 75Pa, using trimethylaluminum and argon gas, to form an aluminum oxide passivation layer with a thickness of 5nm on the front and back of the silicon wafer.

[0067] S12, Front and back coating: Using PECVD plasma-enhanced chemical vapor deposition, the temperature is controlled at 400℃, the pressure is controlled at 2525Pa, and the N2O:SiH4 flow ratio is controlled at 1:5 for 250s deposition to form a silicon nitride antireflection film with a thickness of 70nm on the front and back of the silicon wafer.

[0068] S13. Electrode preparation: Print paste on the front and back gate line reserved areas of the silicon wafer respectively and sinter in a sintering furnace at 700-800℃ for 1.5-2.5 minutes to form the front metal electrode and the back metal electrode.

[0069] The preparation method provided in this embodiment is shown in Figure 1, and the layer structure diagram of the obtained high bifaciality TOPCon cell is shown in Figure 2. The front efficiency, back efficiency and bifaciality of the 30 products were tested, and the parameters are shown in Table 1. It should be explained that: Uoc is the open circuit voltage (mV), Isc is the short circuit current (A) and FF is the fill factor (%).

[0070] Table 1. Parameter detection results of the high bifaciality TOPCon battery prepared by the method provided in Example 1.

[0071]

[0072] Comparative Example 1

[0073] The difference between Comparative Example 1 and Example 1 is that the ordinary TOPCon-PolyFinger battery prepared in Comparative Example 1 does not include step S10 of Example 1. The structure of the product is shown in Figure 3, and the preparation steps are as follows:

[0074] S1. Textured surface treatment: N-type monocrystalline silicon wafers are selected, and NaOH and additives are used to perform anisotropic alkaline texturing on both sides of the silicon wafers to form a uniformly distributed micron-level positive pyramid textured surface on the front side of the silicon wafer, with a height of 3μm.

[0075] S2. Boron diffusion: Boron diffusion is performed on the front or both sides of the texturized silicon wafer using a low-pressure tubular boron diffusion furnace. The boron source used is BCl3, the diffusion temperature is 860℃, and a boron diffusion layer with a depth of 0.7μm is formed.

[0076] S3, Borosilicate glass on the back surface: Borosilicate glass treatment is performed on the back and edge areas of the silicon wafer using a chain acid etching method, with the acid concentration controlled at 400 μs / cm.

[0077] S4. Substrate polishing: The back of the silicon wafer is polished using a tank machine with NaOH + H2O + polishing additives to form a highly flat polished surface; then ozone or hydrogen peroxide with alkali is used to clean the additive residue; finally, hydrochloric acid with dehydrating additives is used to remove metal ions and ensure surface hydrophobicity, with the reaction amount controlled at 0.2g.

[0078] S5. Backside deposition: Using PECVD plasma-enhanced chemical vapor deposition, the temperature is controlled at 450℃ and the pressure is controlled at 270Pa. On the backside of the silicon wafer, a silicon dioxide tunneling oxide layer with a thickness of 2nm is first deposited using N2O, then a phosphorus-doped amorphous silicon layer with a thickness of 120nm is deposited using SiH4 and PH3, and finally a silicon dioxide mask layer with a thickness of 10nm is deposited using N2O and SiH4.

[0079] S6. Annealing and Crystallization: The phosphorus-doped amorphous silicon layer on the back side of the silicon wafer is annealed using a vapor-phase high-temperature annealing method in a high-temperature annealing furnace. First, it is heat-treated at 880℃ for 28 minutes, followed by a back-side annealing process at 840℃ for 25 minutes, advancing to a junction depth of 120 nm and a doping concentration of 1 × 10⁻⁶. 20 cm -3 The n+-poly layer; during the annealing process, phosphorus atoms in the phosphorus-doped amorphous silicon layer diffuse into the surface silicon dioxide mask layer to form phosphosilicate glass;

[0080] S7. Laser modification: A picosecond laser with a single pulse energy of 50-200μJ and a wavelength of 395-532nm is used to loosen the phosphorosilicate glass layer in the non-gateline area on the back of the silicon wafer to facilitate subsequent etching.

[0081] S8. Surface Etching: A chain pickling machine with hydrofluoric acid is used to etch the phosphosilicate glass layer coated on the front and side of the silicon wafer. The polysilicon coated on the front side is etched with alkaline solution to remove the loosened phosphosilicate glass layer and phosphorus-doped polysilicon layer in the non-gate area and the silicon dioxide tunnel oxide layer, and the etching continues for 4μm until the substrate layer is reached to form a polyfinger structure.

[0082] S9. Backside Polishing: Hydrofluoric acid is used to remove the borosilicate glass on the front side and the phosphosilicate glass in the back grid area. A tank-type machine with NaOH + H2O + polishing additives is used to polish the back side of the silicon wafer to form a highly reflective polished surface. Then, ozone or hydrogen peroxide with alkali is used to clean the additive residue. Finally, hydrochloric acid with dehydrating additives is used to remove metal ions and ensure surface hydrophobicity, with the reaction amount controlled not to exceed 0.04g.

[0083] S10. Preparation of aluminum oxide passivation layer (preparation of aluminum oxide passivation layer on the front and back of silicon wafer using atomic layer deposition): using an ALD atomic layer deposition furnace, the temperature is controlled at 200℃ and the pressure is controlled at 75Pa, using trimethylaluminum and argon gas, to form an aluminum oxide passivation layer with a thickness of 7nm on the front and back of the silicon wafer.

[0084] S11. Front and back coating: PECVD plasma-enhanced chemical vapor deposition method is adopted, with the temperature controlled at 400℃, the pressure controlled at 2525Pa, and the N2O:SiH4 flow ratio controlled at 1:5 for 280s deposition to form a silicon nitride antireflection film with a thickness of 80nm on the front and back of the silicon wafer.

[0085] S12. Electrode preparation: Print paste on the front and back gate line reserved areas of the silicon wafer respectively and sinter in a sintering furnace at 700-800℃ for 1.5-2.5 minutes to form the front metal electrode and the back metal electrode.

[0086] Figure 3 shows a schematic diagram of the layer structure of a conventional TOPCon-Poly Finger cell prepared by the method provided in Comparative Example 1. The front efficiency, back efficiency, and bifaciality of 30 products were tested, and the parameters are shown in Table 2. It should be noted that: Uoc is the open circuit voltage (mV), Isc is the short circuit current (A), and FF is the fill factor (%).

[0087] Table 2. Parameter test results of ordinary TOPCon-Poly Finger cells prepared by the method provided in Comparative Example 1.

[0088]

[0089] Comparative Example 2

[0090] The difference between Comparative Example 2 and Example 1 is that the ordinary TOPCon battery prepared in Comparative Example 2 does not include steps S7 and S10 of Example 1. The remaining steps are basically the same, and the structure of the product is shown in Figure 4. The preparation steps are as follows:

[0091] S1. Textured surface treatment: N-type monocrystalline silicon wafers are selected, and NaOH and additives are used to perform anisotropic alkaline texturing on both sides of the silicon wafers to form a uniformly distributed micron-level positive pyramid textured surface on the front side of the silicon wafer, with a height of 2μm.

[0092] S2. Boron diffusion: Boron diffusion is performed on the front or both sides of the texturized silicon wafer using a low-pressure tubular boron diffusion furnace. The boron source used is BCl3, the diffusion temperature is 860℃, and a boron diffusion layer with a depth of 0.5μm is formed.

[0093] S3, Borosilicate glass on the back surface: Borosilicate glass treatment is performed on the back and edge areas of the silicon wafer using a chain acid etching method, with the acid concentration controlled at 400 μs / cm.

[0094] S4. Substrate polishing: The back of the silicon wafer is polished using a tank machine with NaOH + H2O + polishing additives to form a highly flat polished surface; then ozone or hydrogen peroxide with alkali is used to clean the additive residue; finally, hydrochloric acid with dehydrating additives is used to remove metal ions and ensure surface hydrophobicity, with the reaction amount controlled at 0.2g.

[0095] S5. Backside deposition: Using PECVD plasma-enhanced chemical vapor deposition, the temperature is controlled at 450℃ and the pressure is controlled at 270Pa. On the backside of the silicon wafer, a silicon dioxide tunneling oxide layer with a thickness of 1.5nm is first deposited using N2O, then a phosphorus-doped amorphous silicon layer with a thickness of 100nm is deposited using SiH4 and PH3, and finally a silicon dioxide mask layer with a thickness of 10nm is deposited using N2O and SiH4.

[0096] S6. Annealing and Crystallization: The phosphorus-doped amorphous silicon layer on the back side of the silicon wafer is annealed using a vapor-phase high-temperature annealing method in a high-temperature annealing furnace. First, it is heat-treated at 880℃ for 28 minutes, followed by a back-side annealing process at 840℃ for 25 minutes, advancing to a junction depth of 100 nm and a doping concentration of 5 × 10⁻⁶. 20 cm -3 The n+-poly layer; during the annealing process, phosphorus atoms in the phosphorus-doped amorphous silicon layer diffuse into the surface silicon dioxide mask layer to form phosphosilicate glass;

[0097] S7. Surface Etching: A chain pickling machine with hydrofluoric acid is used to etch the phosphosilicate glass layer coated on the front and side of the silicon wafer. The polysilicon coated on the front side is etched with alkaline solution to remove the loosened phosphosilicate glass layer and phosphorus-doped polysilicon layer in the non-gate area and the silicon dioxide tunnel oxide layer, and the etching continues for 4μm until the substrate layer is reached to form a polyfinger structure.

[0098] S8. Backside Polishing: Hydrofluoric acid is used to remove the borosilicate glass on the front side and the phosphosilicate glass in the back grid area. A tank-type machine with NaOH + H2O + polishing additives is used to polish the back side of the silicon wafer to form a highly reflective polished surface. Then, ozone or hydrogen peroxide with alkali is used to clean the additive residue. Finally, hydrochloric acid with dehydrating additives is used to remove metal ions and ensure surface hydrophobicity, with the reaction amount controlled not to exceed 0.04g.

[0099] S9. Backside non-grid area inkjet etching: Using an inkjet printer, an etchable droplet array is printed on the backside non-grid area. The etchant is a mixed solution of AgNO3 / Cu(NO3)2 and HF / H2O2. The volume of the printed etchable droplets is 5pL. After etching, the area is cleaned. The depth of the inverted pyramid light-trapping structure prepared is 2μm.

[0100] S10. Preparation of aluminum oxide passivation layer (aluminum oxide passivation layer is prepared on the front and back of silicon wafer by atomic layer deposition): using an ALD atomic layer deposition furnace, the temperature is controlled at 200℃ and the pressure is controlled at 75Pa, using trimethylaluminum and argon gas, to form an aluminum oxide passivation layer with a thickness of 5nm on the front and back of the silicon wafer.

[0101] S11. Front and back coating: PECVD plasma-enhanced chemical vapor deposition method is adopted, with the temperature controlled at 400℃, the pressure controlled at 2525Pa, and the N2O:SiH4 flow ratio controlled at 1:5 for 250s deposition to form a silicon nitride antireflection film with a thickness of 70nm on the front and back of the silicon wafer.

[0102] S12. Electrode preparation: Print paste on the front and back gate line reserved areas of the silicon wafer respectively and sinter in a sintering furnace at 700-800℃ for 1.5-2.5 minutes to form the front metal electrode and the back metal electrode.

[0103] Figure 4 shows a schematic diagram of the layer structure of a conventional TOPCon battery prepared by the method provided in Comparative Example 2. The front efficiency, back efficiency, and bifaciality of 30 products were tested, and the parameters are shown in Table 3. It should be noted that: Uoc is the open circuit voltage (mV), Isc is the short circuit current (A), and FF is the fill factor (%).

[0104] Table 3. Parameter test results of ordinary TOPCon batteries prepared by the method provided in Comparative Example 2.

[0105]

[0106] Therefore, by comparing the data of Example 1, Comparative Example 1 and Comparative Example 2, it was found that the back efficiency of the battery obtained by the preparation method provided by the present invention is significantly improved, and thus the bifaciality is greatly improved.

[0107] In the preparation method of this invention, during the processing of silicon wafers, the polycrystalline silicon layer in the non-gate area on the back side is modified to accelerate the etching rate of alkaline solution until it is etched to the silicon substrate. Compared with conventional TOPCon cells, this method not only ensures the silicon dioxide tunneling oxide layer structure but also reduces the parasitic absorption of the polycrystalline silicon layer, thereby increasing the short-circuit current density. At the same time, for the low bifaciality of PolyFinger structure TOPCon cells, an inverted pyramid light-trapping structure is formed by etching the non-gate area with acid using an inkjet printer. Inkjet printing allows for fine printing without the need for a mask layer to protect the polycrystalline silicon, reducing the process difficulty. It also increases the absorption of light on the back side, improves the bifaciality of the cell, and thus improves the cell efficiency.

[0108] In this embodiment of the invention, the term "multiple" refers to two or more, unless otherwise explicitly defined. The terms "install," "connect," and "fix" should be interpreted broadly. For example, "connect" can mean a fixed connection, a detachable connection, or an integral connection. Those skilled in the art can understand the specific meaning of the above terms in this embodiment of the invention based on the specific circumstances.

[0109] In the description of the embodiments of the present invention, it should be understood that the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the present invention.

[0110] In the description of this specification, the terms "an embodiment," "a preferred embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0111] The above embodiments are merely illustrative of the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solutions based on the technical concept proposed in this invention shall fall within the scope of protection of this invention. Technologies not covered in this invention can be implemented using existing technologies.

Claims

1. A method for fabricating a high bifaciality TOPCon battery based on a Poly Finger structure, characterized in that: The preparation method involves the following steps: S1, texturing: anisotropic alkaline texturing is performed on both sides of the silicon wafer to form a uniformly distributed micron-sized pyramidal texture on the front side of the wafer; S2, boron diffusion: boron diffusion is performed on the front or both sides of the silicon wafer to form a boron diffusion layer; S3, borosilicate glass removal: borosilicate glass is removed from the back side and edge areas of the silicon wafer; S4, substrate polishing: the back side of the silicon wafer is polished to form a highly flat polished surface, and after cleaning, metal ions are removed while ensuring surface hydrophobicity; S5, back side deposition: sequential deposition is performed on the back side of the silicon wafer. S6. Annealing and crystallization: The phosphorus-doped amorphous silicon layer is subjected to high-temperature annealing and crystallization treatment to obtain a phosphorus-doped polycrystalline silicon layer. At the same time, phosphorus atoms diffuse into the silicon dioxide mask layer to form phosphosilicate glass; S7. Laser modification: The phosphosilicate glass in the non-gateway area on the back of the silicon wafer is loosened using a picosecond laser; S8. Surface etching: The loosened phosphosilicate glass, phosphorus-doped polycrystalline silicon layer and silicon dioxide tunneling oxide layer in the non-gateway area are removed and etching continues to the substrate layer to form Poly Finger structure; S9, Backside polishing: Polish the backside of the silicon wafer to form a highly flat polished surface, clean it to remove metal ions and ensure the surface is hydrophobic; S10, Inkjet etching: Use an inkjet printer to print an etch droplet array on the non-gateline area on the backside, clean it to obtain an inverted pyramid light-trapping structure; S11, Alumina passivation layer preparation: Prepare an alumina passivation layer on the front and back sides of the silicon wafer using atomic layer deposition; S12, Front and back side coating: Deposit a silicon nitride antireflection film on the outside of the alumina passivation layer; S13, Electrode preparation: Print paste on the front and back gateline reserved areas of the silicon wafer to prepare the front metal electrode and the back metal electrode, respectively.

2. The method for fabricating a high bifaciality TOPCon cell based on a Poly Finger structure according to claim 1, characterized in that: In step S1, the height of the pyramidal textured surface is 1-5 μm and the length of the base side is 2-7 μm; in step S2, the depth of the boron diffusion layer is 0.1-1 μm.

3. The method for fabricating a high bifaciality TOPCon battery based on a Poly Finger structure according to claim 1, characterized in that: In step S3, the borosilicate glass is treated with an acid bath with a concentration controlled at 300-450 μs / cm. In step S4, the substrate polishing and in step S9, the back surface polishing are performed using a tank-type machine with NaOH + H2O + polishing additives to polish the back surface of the silicon wafer, forming a highly flat polished surface. Then, ozone or hydrogen peroxide with alkali is used to clean the additive residue. Finally, a combination of hydrochloric acid and dehydrating additives is used to remove metal ions and ensure surface hydrophobicity.

4. The method for fabricating a high bifaciality TOPCon battery based on a Poly Finger structure according to claim 1, characterized in that: In step S5, the back-side deposition uses PECVD plasma-enhanced chemical vapor deposition, with the temperature controlled at 400-500℃ and the pressure controlled at 250-270Pa. On the back side of the silicon wafer, a silicon dioxide tunneling oxide layer with a thickness of 1-3nm is first deposited using N2O, then a phosphorus-doped amorphous silicon layer with a thickness of 50-150nm is deposited using SiH4 and PH3, and finally a silicon dioxide mask layer with a thickness of 8-15nm is deposited using N2O and SiH4.

5. The method for fabricating a high bifaciality TOPCon battery based on a Poly Finger structure according to claim 1, characterized in that: The annealing and crystallization process in step S6 is as follows: The phosphorus-doped amorphous silicon layer on the back side of the silicon wafer is annealed using a vapor-phase high-temperature annealing method in a high-temperature annealing furnace. First, it is heat-treated at 860–895℃ for 20–40 minutes, followed by back-side annealing at 800–860℃ for 20–30 minutes, advancing to a junction depth of 50–150 nm and a doping concentration of 1 × 10⁻⁶ nm. 19 -1×10 21 cm -3 The n+-poly layer; during the annealing process, phosphorus atoms in the phosphorus-doped amorphous silicon layer diffuse into the surface silicon dioxide mask layer to form phosphosilicate glass.

6. The method for fabricating a high bifaciality TOPCon battery based on a Poly Finger structure according to claim 1, characterized in that: The picosecond laser in step S7 has a single pulse energy of 50-200 μJ and a wavelength of 395-532 nm, and retains the phosphorosilicon glass layer in the reserved grid area during laser quality modification.

7. The method for fabricating a high bifaciality TOPCon battery based on a Poly Finger structure according to claim 1, characterized in that: The specific process of inkjet etching in step S10 is as follows: using an inkjet printer, an etch droplet array is printed on the non-grid area on the back side. The etchant is a mixed solution of AgNO3 / Cu(NO3)2 and HF / H2O2. The volume of the printed etch droplets is 1-20 pL. After etching, the droplets are cleaned. The resulting inverted pyramid light trapping structure has a bottom edge length of 2-7 μm and a depth of 1-5 μm.

8. The method for fabricating a high bifaciality TOPCon battery based on a Poly Finger structure according to claim 1, characterized in that: The method for preparing the alumina passivation layer in step S11 is as follows: using an ALD atomic layer deposition furnace, the temperature is controlled at 180-250℃ and the pressure is controlled at 60-100Pa, and trimethylaluminum and argon are used to form an alumina passivation layer with a thickness of 3-10nm on both the front and back sides of the silicon wafer.

9. The method for fabricating a high bifaciality TOPCon cell based on a Poly Finger structure according to claim 1, characterized in that: The front and back coating process in step S12 is as follows: using PECVD plasma-enhanced chemical vapor deposition, the temperature is controlled at 380℃~450℃, the pressure is controlled at 2300-2600Pa, and the N2O:SiH4 flow ratio is controlled at 1:3-10 for 200-350s to form a silicon nitride antireflection film with a thickness of 50-100nm on the front and back of the silicon wafer.

10. The method for fabricating a high bifaciality TOPCon battery based on a Poly Finger structure according to claim 1, characterized in that: The electrode preparation process in step S13 is as follows: paste is printed on the front and back gate line reserved areas of the silicon wafer respectively, and sintered in a sintering furnace at 700-800℃ for 1.5-2.5 minutes to form the front metal electrode and the back metal electrode.

11. A solar cell prepared by the high bifaciality TOPCon cell preparation method based on the Poly Finger structure as described in any one of claims 1-10, the solar cell being used to convert received light energy into electrical energy.

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