Passivation contact battery structure

Abstract

The utility model discloses a passivation contact cell structure comprising a silicon substrate, and the back surface of the silicon substrate comprises a metal contact area and a non-metal contact area. A metal contact area on the back face of the silicon substrate is of a suede structure, and a first back face tunneling oxide layer, a first back face doped polycrystalline silicon layer, a second back face tunneling oxide layer, a second back face doped polycrystalline silicon layer, a back face aluminum oxide layer, a back face silicon nitride layer and a back face electrode are sequentially arranged on the metal contact area on the back face of the silicon substrate in a stacked mode from inside to outside. A non-metal contact area on the back face of the silicon substrate is of a polished face structure, and a back face first tunneling oxide layer, a back face first doped polycrystalline silicon layer, a back face aluminum oxide layer and a back face silicon nitride layer are sequentially arranged on the non-metal contact area on the back face of the silicon substrate in a stacked mode from inside to outside. The cell structure provided by the utility model can reduce parasitic absorption and inhibit silver ion diffusion, brings current gain, improves metal compounding, improves interface contact resistance, and is beneficial to improvement of cell efficiency.

Description

Technical Field

[0001] This utility model belongs to the field of passivated contact batteries, and specifically relates to a passivated contact battery structure. Background Technology

[0002] Tunnel oxide passivated contact (TOPCon) solar cells are a mainstream type of solar cell. These cells consist of an ultrathin tunnel oxide layer and a doped polycrystalline silicon layer sequentially fabricated on the back side. Together, they form a passivated contact structure, providing excellent interface passivation for the back of the silicon wafer. The tunnel oxide layer contacts the silicon substrate, neutralizing dangling bonds on the silicon surface and achieving excellent chemical passivation. The doped polycrystalline silicon, due to the Fermi level difference with the silicon substrate, creates band bending on the silicon substrate surface, allowing electrons to pass through while blocking holes, thus providing field passivation and enabling selective collection of charge carriers. This reduces current loss caused by metal contact recombination and improves cell conversion efficiency.

[0003] However, doped polycrystalline silicon exhibits parasitic absorption of light, leading to short-circuit current loss. Therefore, from the perspective of improving short-circuit current, the thinner the doped polycrystalline silicon layer, the better. However, silver paste has a more severe corrosive and destructive effect on thinner doped polycrystalline silicon layers, resulting in a significant increase in metal recombination and a larger on-state voltage loss. Furthermore, excessive corrosion of the polycrystalline silicon film by the paste can cause the interfacial tunneling contact mechanism to fail, thereby affecting the interfacial contact resistance. Therefore, achieving both lower parasitic absorption and better interfacial contact is crucial for further improving battery efficiency.

[0004] To address the aforementioned shortcomings, for example, CN106449800A discloses a passivation contact structure for selective polycrystalline silicon thin films. A silicon dioxide layer with a thickness of <2 nm is prepared on the surface of crystalline silicon. A doped polycrystalline silicon thin film is then prepared on the surface of the silicon dioxide layer. The doped polycrystalline silicon thin film has a first thickness in the region without metal contact and a second thickness in the region with metal contact, with the first thickness being less than the second thickness. A metal electrode is formed on the surface of the second thickness region of the polycrystalline silicon thin film. This invention also discloses a method for preparing the aforementioned passivation contact structure for selective polycrystalline silicon thin films, effectively combining traditional screen printing technology with passivation contact technology. This facilitates the mass production of passivation contact technology and effectively improves the efficiency of solar cells. This invention involves printing a mask on the polycrystalline silicon surface, then using etching to thin the polycrystalline silicon in the unmasked region to form the first thickness region. After removing the mask layer, the unetched polycrystalline silicon thin film region below the mask layer becomes the second thickness region, on which the metal electrode is printed.

[0005] However, the above-mentioned battery structure has the following technical defects: In the metal electrode contact area, the polycrystalline silicon thin film is a single layer, which cannot effectively suppress the longitudinal diffusion and corrosion of silver ions, thus failing to suppress metal recombination. Secondly, as the reflection angle decreases, the surface recombination of the tunnel oxide layer / doped polycrystalline silicon passivation contact gradually decreases, and the implicit open circuit voltage (iVoc) gradually increases. However, the interfacial contact resistivity between the electrode paste and the tunnel oxide layer / doped polycrystalline silicon passivation contact structure gradually increases. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings and deficiencies in the existing technology by providing a passivated contact battery structure based on the existing technology.

[0007] The objective of this utility model can be achieved through the following measures:

[0008] A passivated contact battery structure includes a silicon substrate, and a metal contact region and a non-metal contact region are included on the back side of the silicon substrate; wherein...

[0009] The metal contact area on the back side of the silicon substrate has a textured structure. From the inside to the outside, the metal contact area on the back side of the silicon substrate is provided with a first tunneling oxide layer, a first doped polysilicon layer, a second tunneling oxide layer, a second doped polysilicon layer, an aluminum oxide layer, a silicon nitride layer, and a back electrode.

[0010] The non-metallic contact area on the back of the silicon substrate is a polished surface structure. From the inside to the outside, the non-metallic contact area on the back of the silicon substrate is stacked with a first tunneling oxide layer, a first doped polysilicon layer, an aluminum oxide layer, and a silicon nitride layer.

[0011] In a preferred embodiment, a front emitter, a front alumina layer, a front silicon nitride layer, and a front electrode are sequentially stacked from the inside to the outside on the front side of the silicon substrate.

[0012] In a preferred embodiment, the height of the pyramid formed in the textured structure of the metal contact area on the back side of the silicon substrate is 0.5–2 μm.

[0013] In a preferred embodiment, the thickness of the first tunneling oxide layer on the back side is 1–2 nm.

[0014] In a preferred embodiment, the first doped polycrystalline silicon layer on the back side is a first in-situ phosphorus-doped amorphous silicon layer with a thickness of 50–80 nm and a phosphorus atom doping concentration of 1.0–2.5 × 10⁻⁶. 20 / cm 3 .

[0015] In a preferred embodiment, the thickness of the second tunneling oxide layer on the back side is 1–2 nm.

[0016] In a preferred embodiment, the second doped polycrystalline silicon layer on the back side is a second in-situ phosphorus-doped amorphous silicon layer with a thickness of 40–70 nm and a phosphorus atom doping concentration of 3.0–4.0 × 10⁻⁶. 20 / cm 3 .

[0017] In a preferred embodiment, the thickness of the back alumina layer is 2–10 nm.

[0018] In a preferred embodiment, the thickness of the back silicon nitride layer is 70–80 nm, and the refractive index of the silicon nitride is 2.1–2.2.

[0019] In a preferred embodiment, the front emitter is a boron-doped emitter with a thickness of 0.7–1.0 μm.

[0020] In a preferred embodiment, the thickness of the front alumina layer is 2–10 nm.

[0021] In a preferred embodiment, the thickness of the front silicon nitride layer is 70–80 nm.

[0022] The passivated contact battery structure provided by this invention has the following advantages:

[0023] 1. The non-metallic contact area on the back is a single layer of polycrystalline silicon with a first thickness, and the metallic contact area is a double layer of polycrystalline silicon with a second thickness. The first thickness is smaller than the second thickness, which can reduce parasitic absorption and bring current gain.

[0024] 2. By adopting a double-layer polycrystalline silicon structure in the contact area of ​​the back metal electrode, the diffusion of silver ions in the electrode paste can be suppressed, the metal composite can be improved, and the excessive corrosion of the polycrystalline silicon film by the paste can be avoided, which would lead to the failure of the interface tunneling contact mechanism and improve the interface contact resistance.

[0025] 3. The bottom of the metal electrode contact area on the back side has a textured surface, which improves interfacial contact resistance, while the non-electrode contact area has a polished surface, reducing surface recombination and improving carrier lifetime. This differentiation achieves low interfacial contact resistivity and low surface recombination, which is beneficial to improving battery efficiency. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the passivated contact battery structure of this utility model;

[0027] Figure 2 This is a schematic diagram of the preparation process of Embodiment 1 of this utility model;

[0028] Figure 3 This is a schematic diagram of the passivated contact battery structure obtained in Comparative Example 1 of this utility model;

[0029] Figure 4 This is a schematic diagram of the passivated contact battery structure obtained in Comparative Example 2 of this utility model;

[0030] Figure 5 This is a schematic diagram of the passivated contact battery structure obtained in Comparative Example 3 of this utility model;

[0031] Figure 6 This is a schematic diagram of the passivated contact battery structure obtained in Comparative Example 4 of this utility model;

[0032] In the figure, 1-silicon substrate, 2-first tunneling oxide layer on the back side, 3-first doped polysilicon layer on the back side, 4-second tunneling oxide layer on the back side, 5-second doped polysilicon layer on the back side, 6-alumina layer on the back side, 7-silicon nitride layer on the back side, 8-back electrode, 9-front emitter, 10-alumina layer on the front side, 11-silicon nitride layer on the front side, 12-front electrode. Detailed Implementation

[0033] The present invention will be further described below with reference to the accompanying drawings and embodiments, but the scope of protection of the present invention is not limited to the following examples.

[0034] Example 1

[0035] like Figure 1 As shown, the passivated contact battery structure of this invention includes a silicon substrate, and on the back side of the silicon substrate, there are metal contact regions and non-metal contact regions. Wherein,

[0036] The metal contact area on the back side of the silicon substrate has a textured surface. From the inside out, the following layers are stacked sequentially on the metal contact area: a first back-side tunneling oxide layer, a first back-side doped polysilicon layer, a second back-side tunneling oxide layer, a second back-side doped polysilicon layer, a back-side aluminum oxide layer, a back-side silicon nitride layer, and a back-side electrode. The non-metallic contact area on the back side of the silicon substrate has a polished surface. From the inside out, the following layers are stacked sequentially on the non-metallic contact area: a first back-side tunneling oxide layer, a first back-side doped polysilicon layer, a back-side aluminum oxide layer, and a back-side silicon nitride layer.

[0037] The front emitter, the front alumina layer, the front silicon nitride layer, and the front electrode are stacked sequentially from the inside to the outside on the front side of the silicon substrate.

[0038] The thicknesses and requirements for each layer in the back and front sides of the silicon substrate are as follows: In the textured structure of the metal contact area on the back side of the silicon substrate, the height of the pyramid formed is 0.5–2 μm; the thickness of the first tunneling oxide layer on the back side is 1–2 nm; the first doped polycrystalline silicon layer on the back side is the first in-situ phosphorus-doped amorphous silicon layer, with a thickness of 50–80 nm and a phosphorus atom doping concentration of 1.0–2.5 × 10⁻⁶. 20 / cm 3The thickness of the second tunneling oxide layer on the back side is 1–2 nm; the second doped polycrystalline silicon layer on the back side is a second in-situ phosphorus-doped amorphous silicon layer with a thickness of 40–70 nm and a phosphorus atom doping concentration of 3.0–4.0 × 10⁻⁶. 20 / cm 3 The thickness of the back alumina layer is 2–10 nm; the thickness of the back silicon nitride layer is 70–80 nm, and the refractive index of silicon nitride is 2.1–2.2; the front emitter is a boron-doped emitter with a thickness of 0.7–1.0 μm, a front alumina layer thickness of 2–10 nm, and a front silicon nitride layer thickness of 70–80 nm.

[0039] like Figure 2 As shown, the method for fabricating the passivated contact battery structure in this example includes the following steps:

[0040] S1: Select an N-type monocrystalline silicon wafer for surface cleaning and perform the first texturing. Specifically, at a reaction temperature of 80-85℃, in a solution with a ratio of texturing additive: sodium hydroxide: water = 1:3:250, for a treatment time of 6-10 minutes, perform double-sided texturing on the silicon wafer, forming a pyramid with a height range of 0.5-2μm;

[0041] S2: A single-sided boron diffusion process is performed on the texturized silicon wafer to form a boron-doped emitter on the front side. The boron source is BCl3 or BBr3, the peak temperature of diffusion is 1000-1100℃, and the sheet resistance after diffusion is 280-360Ω / sq.

[0042] S3: Place the silicon wafer face up in the chain machine and remove the BSG on the back and edges of the boron-expanded silicon wafer in a 15% to 30% HF solution. Then polish the back side with sodium hydroxide and polishing additive. The mass ratio is approximately additive:sodium hydroxide:water = 1:5:90. The reaction temperature is 60 to 70°C and the reaction time is 3 to 6 minutes.

[0043] S4: A silicon oxide mask layer is deposited on the entire back side of a silicon wafer using PECVD. Specifically, at a temperature of 400–600°C, a pressure of 150–250 Pa, a silane flow rate of 800–2500 sccm, and a nitrous oxide flow rate of 7000–12000 sccm, the reaction time is controlled to generate a mask layer thickness of 30–100 nm. Then, a laser is used to pattern the mask by laser laser cutting. The laser source is green or violet light with a power of 20–100 W. The pattern is a grid of equidistant lines with a linewidth of 50–100 μm and a cutting spacing of 0.8–1.5 mm.

[0044] S5: Secondary texturing is performed on the silicon wafer's open-film area. Specifically, at a reaction temperature of 80–85°C, in a solution with a texturing additive: sodium hydroxide: water ratio of approximately 1:3:250, the treatment time is 6–10 minutes, resulting in a pyramid height ranging from 0.5 to 2 μm. Then, the remaining mask on the back side is removed using a 3%–10% HF solution.

[0045] S6: A first tunneling oxide layer, a first in-situ phosphorus-doped amorphous silicon layer, a second tunneling oxide layer, and a second in-situ phosphorus-doped amorphous silicon layer are sequentially deposited on the entire back side of a silicon wafer by PECVD. Specifically, (1) oxygen is introduced at a temperature of 400-600℃, and SiO2 is generated on the surface of the silicon wafer by reacting with oxygen as the first tunneling oxide layer. The reaction time is controlled to obtain a thickness of 1-2 nm for the first tunneling oxide layer; (2) phosphine, silane, and hydrogen are introduced at a temperature of 450-650℃ as reaction sources to generate a first in-situ phosphorus-doped amorphous silicon layer on the surface of the silicon wafer. The reaction time is controlled to obtain a thickness of 50-80 nm for the first in-situ phosphorus-doped amorphous silicon layer. The ratio between different reaction gases (phosphine:silane:hydrogen ≈ 1:20:80) is controlled to ensure a phosphorus atom doping concentration of 1.0-2.5*10 20 / cm 3 (3) Oxygen is introduced at a temperature of 400-600℃, and SiO2 is generated on the surface of the silicon wafer as the second tunneling oxide layer. The reaction time is controlled to obtain a thickness of 1-2 nm for the second tunneling oxide layer. (4) Phosphine, silane and hydrogen are introduced as reaction sources at a temperature of 450-650℃ to generate a second in-situ phosphorus-doped amorphous silicon layer on the surface of the silicon wafer. The reaction time is controlled to obtain a thickness of 40-70 nm for the second in-situ phosphorus-doped amorphous silicon layer. The ratio between different reaction gases (phosphine:silane:hydrogen ≈ 1:15:60) is controlled to ensure a phosphorus atom doping concentration of 3.0-4.0*10 20 / cm 3 ;

[0046] S7: Laser crystallization is performed on the texturized area on the back of the silicon wafer to transform the amorphous silicon in this area into polycrystalline silicon. Some phosphorus atoms are activated, giving it electrical activity. A green light source is used, and the laser energy is set to transform the amorphous silicon into polycrystalline silicon. The scanning area is the texturized area on the back, and the scanning pattern is the same as the opening pattern in S4. The scanning method is line-by-line scanning, with a line width of 50–100 μm, a scanning interval of 0.8–1.5 mm, a spot overlap rate of 30%–75%, and a scanning speed of 3000 mm / s–4000 mm / s. This process crystallizes the amorphous silicon in the scanned area, which is the metal electrode contact area.

[0047] S8: Perform alkaline etching treatment. Utilize the difference in alkaline etching resistance between the polycrystalline silicon in the metal contact area and the amorphous silicon in the non-metal contact area on the back side. At a reaction temperature of 50-60°C, use a sodium hydroxide solution with a volume fraction of 2-3% for a treatment time of 1.5-3 minutes to remove the amorphous silicon thin film layer in the non-metal contact area on the back side.

[0048] S9: Use a 5% to 8% HF solution to remove the second tunneling oxide layer corresponding to the non-metallic contact area on the back side, and then anneal the silicon wafer at 800 to 900°C.

[0049] S10: A passivation antireflection coating is formed on the front and back sides of the silicon wafer. The passivation antireflection coating adopts a stacked design of aluminum oxide and silicon nitride, wherein the thickness of aluminum oxide is 2-10 nm, the thickness of silicon nitride is 70-80 nm, and the refractive index of silicon nitride is 2.1-2.2;

[0050] S11: Print front and back electrodes, with the back electrode printed on the textured area.

[0051] Comparative Example 1: Backside fully polished + single-layer doped polycrystalline silicon cell structure

[0052] like Figure 3 As shown, the passivated contact battery structure involved in Comparative Example 1 includes a silicon substrate (1), a back tunneling oxide layer (2), a back doped polycrystalline silicon layer (3), a back aluminum oxide layer (4), a back silicon nitride layer (5), a back electrode (6), a front emitter (7), a front aluminum oxide layer (8), a front silicon nitride layer (9), and a front electrode (10).

[0053] The preparation steps are as follows:

[0054] S1 to S3 are the same as in Example 1.

[0055] S4: A tunneling oxide layer and an in-situ phosphorus-doped amorphous silicon layer are sequentially deposited on the entire back side of a silicon wafer using PECVD. Specifically, (1) oxygen is introduced at a temperature of 400–600°C, and SiO2 is generated on the surface of the silicon wafer as a tunneling oxide layer by reacting with oxygen. The reaction time is controlled to obtain a tunneling oxide layer thickness of 1–2 nm; (2) phosphine, silane, and hydrogen are introduced at a temperature of 450–650°C as reaction sources to generate an in-situ phosphorus-doped amorphous silicon layer on the surface of the silicon wafer. The reaction time is controlled to obtain an in-situ phosphorus-doped amorphous silicon layer thickness of 90–150 nm. The ratio between different reaction gases (phosphine:silane:hydrogen ≈ 1:15:60) is controlled to ensure a phosphorus atom doping concentration of 3.0–4.0 × 10⁻⁶. 20 / cm 3 ;

[0056] S5: Anneal the silicon wafer to transform the amorphous silicon on the back side into polycrystalline silicon. Some phosphorus atoms are activated and become electrically active. The annealing temperature is 800-900℃ and the time is 15-60min.

[0057] S6: Forming a passivation antireflection coating. The passivation antireflection coating adopts a stacked design of aluminum oxide and silicon nitride, wherein the thickness of aluminum oxide is 2-10 nm, the thickness of silicon nitride is 70-80 nm, and the refractive index of silicon nitride is 2.1-2.2;

[0058] S7: Printed front and back electrodes.

[0059] Comparative Example 2: Backside texturing + single-layer doped polycrystalline silicon solar cell structure

[0060] like Figure 4 As shown, the passivated contact battery structure involved in Comparative Example 2 includes a silicon substrate (1), a back tunneling oxide layer (2), a back doped polycrystalline silicon layer (3), a back aluminum oxide layer (4), a back silicon nitride layer (5), a back electrode (6), a front emitter (7), a front aluminum oxide layer (8), a front silicon nitride layer (9), and a front electrode (10).

[0061] The preparation steps are as follows:

[0062] S1 to S5 are the same as in Example 1.

[0063] S6: A tunneling oxide layer and an in-situ phosphorus-doped amorphous silicon layer are sequentially deposited on the entire back side of a silicon wafer using PECVD. Specifically, (1) oxygen is introduced at a temperature of 400–600°C, and SiO2 is generated on the surface of the silicon wafer as a tunneling oxide layer by reacting with oxygen. The reaction time is controlled to obtain a tunneling oxide layer thickness of 1–2 nm; (2) phosphine, silane, and hydrogen are introduced as reaction sources at a temperature of 450–650°C to generate an in-situ phosphorus-doped amorphous silicon layer on the surface of the silicon wafer. The reaction time is controlled to obtain an in-situ phosphorus-doped amorphous silicon layer thickness of 90–150 nm. The ratio between different reaction gases (phosphine:silane:hydrogen ≈ 1:15:60) is controlled to ensure a phosphorus atom doping concentration of 3.0–4.0 × 10⁻⁶. 20 / cm 3 ;

[0064] S7: Anneal the silicon wafer to transform the amorphous silicon on the back side into polycrystalline silicon. Some phosphorus atoms are activated and become electrically active. The annealing temperature is 800-900℃ and the time is 15-60min.

[0065] S8: Forming a passivation antireflection coating layer. The passivation antireflection coating layer adopts a stacked design of aluminum oxide + silicon nitride, wherein the thickness of aluminum oxide is 2-10 nm, the thickness of silicon nitride is 70-80 nm, and the refractive index of silicon nitride is 2.1-2.2;

[0066] S9: Print front and back electrodes, with the back electrode printed on the textured area.

[0067] Comparative Example 3: Backside fully polished + locally double-layer doped polycrystalline silicon solar cell structure

[0068] like Figure 5 As shown, the passivated contact battery structure involved in Comparative Example 3 includes a silicon substrate (1), a first tunneling oxide layer (2) on the back side, a first doped polycrystalline silicon layer (3) on the back side, a second tunneling oxide layer (4) on the back side, a second doped polycrystalline silicon layer (5) on the back side, an aluminum oxide layer (6) on the back side, a silicon nitride layer (7) on the back side, a back electrode (8), a front emitter (9), a front aluminum oxide layer (10), a front silicon nitride layer (11) on the front side, and a front electrode (12).

[0069] The preparation steps are as follows:

[0070] S1 to S3 are the same as in Example 1.

[0071] S4: A first tunneling oxide layer, a first in-situ phosphorus-doped amorphous silicon layer, a second tunneling oxide layer, and a second in-situ phosphorus-doped amorphous silicon layer are sequentially deposited on the entire back side of a silicon wafer by PECVD. Specifically, (1) oxygen is introduced at a temperature of 400-600℃, and SiO2 is generated on the surface of the silicon wafer by reacting with oxygen as the first tunneling oxide layer. The reaction time is controlled to obtain a thickness of 1-2 nm for the first tunneling oxide layer; (2) phosphine, silane, and hydrogen are introduced at a temperature of 450-650℃ as reaction sources to generate a first in-situ phosphorus-doped amorphous silicon layer on the surface of the silicon wafer. The reaction time is controlled to obtain a thickness of 50-80 nm for the first in-situ phosphorus-doped amorphous silicon layer. The ratio between different reaction gases (phosphine: silane: hydrogen ≈ 1:20:80) is controlled to ensure a phosphorus atom doping concentration of 1.0-2.5*10 20 / cm 3 (3) Oxygen is introduced at a temperature of 400-600℃, and SiO2 is generated on the surface of the silicon wafer as the second tunneling oxide layer. The reaction time is controlled to obtain a thickness of 1-2 nm for the second tunneling oxide layer. (4) Phosphine, silane and hydrogen are introduced as reaction sources at a temperature of 450-650℃ to generate a second in-situ phosphorus-doped amorphous silicon layer on the surface of the silicon wafer. The reaction time is controlled to obtain a thickness of 40-70 nm for the second in-situ phosphorus-doped amorphous silicon layer. The ratio between different reaction gases (phosphine:silane:hydrogen ≈ 1:15:60) is controlled to ensure a phosphorus atom doping concentration of 3.0-4.0*10 20 / cm 3 ;

[0072] S5: Anneal the silicon wafer to transform the amorphous silicon on the back side into polycrystalline silicon. Some phosphorus atoms are activated, making them electrically active. The annealing temperature is 800–900℃, and the time is 15–60 min. Then, use a laser to scan the polycrystalline silicon in the corresponding area of ​​the textured back side. The laser source is violet light, with a power of 2–20 W, a scanning linewidth of 50–100 μm, a gate spacing of 0.8–1.5 mm, and the resulting oxide mask thickness is 1–4 nm.

[0073] S6: At a reaction temperature of 60-70°C, a sodium hydroxide solution with a volume fraction of 3-5% is used to remove the polysilicon thin film layer in the non-metallic contact area on the back side. Since there is a laser oxide layer on the surface of the scanning area, the polysilicon layer in this area will not be etched. After the polysilicon layer in other areas is etched, when the polysilicon layer in the area without the laser oxide layer mask is removed by alkaline etching, the reaction rate and activity of the tunneling oxide layer with the alkali are relatively slow, thus preventing the alkaline solution from etching the polysilicon layer.

[0074] S7: Use a 5% to 8% HF solution to remove the tunneling oxide layer corresponding to the non-metallic contact area on the back side and the oxide layer mask corresponding to the metallic contact area.

[0075] S8: Forming a passivation antireflection coating layer. The passivation antireflection coating layer adopts a stacked design of aluminum oxide + silicon nitride, wherein the thickness of aluminum oxide is 2-10 nm, the thickness of silicon nitride is 70-80 nm, and the refractive index of silicon nitride is 2.1-2.2;

[0076] S9: Print front and back electrodes, wherein the back electrode is printed on a double-layer polysilicon region.

[0077] Comparative Example 4: Backside full textured surface + single-layer doped polycrystalline silicon cell structure

[0078] like Figure 6 As shown, the passivated contact battery structure involved in Comparative Example 4 includes a silicon substrate (1), a back tunneling oxide layer (2), a back doped polycrystalline silicon layer (3), a back aluminum oxide layer (4), a back silicon nitride layer (5), a back electrode (6), a front emitter (7), a front aluminum oxide layer (8), a front silicon nitride layer (9), and a front electrode (10).

[0079] The preparation steps are as follows:

[0080] S1 to S2 are the same as in Example 1.

[0081] S3: Place the silicon wafer face up in the chain machine and remove the BSG from the back and edges of the boron-expanded silicon wafer in a 15% to 30% HF solution;

[0082] S4: A tunneling oxide layer and an in-situ phosphorus-doped amorphous silicon layer are sequentially deposited on the entire back side of a silicon wafer using PECVD. Specifically, (1) oxygen is introduced at a temperature of 400–600°C, and SiO2 is generated on the surface of the silicon wafer as a tunneling oxide layer by reacting with oxygen. The reaction time is controlled to obtain a tunneling oxide layer thickness of 1–2 nm; (2) a certain proportion of phosphine, silane, and hydrogen are introduced at a temperature of 450–650°C as a reaction source to generate an in-situ phosphorus-doped amorphous silicon layer on the surface of the silicon wafer. The reaction time is controlled to obtain an in-situ phosphorus-doped amorphous silicon layer thickness of 90–150 nm. The ratio between different reaction gases (phosphine:silane:hydrogen ≈ 1:15:60) is controlled to ensure a phosphorus atom doping concentration of 3.0–4.0 × 10⁻⁶. 20 / cm 3 ;

[0083] S5: Anneal the silicon wafer to transform the amorphous silicon on the back side into polycrystalline silicon. Some phosphorus atoms are activated and become electrically active. The annealing temperature is 800-900℃ and the time is 15-60min.

[0084] S6: Forming a passivation antireflection coating. The passivation antireflection coating adopts a stacked design of aluminum oxide and silicon nitride, wherein the thickness of aluminum oxide is 2-10 nm, the thickness of silicon nitride is 70-80 nm, and the refractive index of silicon nitride is 2.1-2.2;

[0085] S7: Printed front and back electrodes.

[0086] Performance test examples

[0087] The batteries obtained in Example 1 and Comparative Examples 1-4 were subjected to the following performance tests: The photoelectric conversion efficiency and related electrical performance parameters of the batteries under standard illumination power were tested using an IV tester under simulated solar light (and the electrical performance data were the average values ​​of 100Pcs batteries from various samples). Specific test results are shown in Table 1 (Eta: conversion efficiency, Voc: open-circuit voltage, Isc: short-circuit current, FF: fill factor). 1

[0089]

[0090] Based on the data in Table 1, it can be seen that Example 1 has the following advantages compared with Comparative Examples 1 to 4:

[0091] (1) As can be seen from Example 1 and Comparative Examples 1 & 3, when a local texturing structure is used in the metal contact area on the back side, the contact resistivity of the contact area decreases by 0.34-0.6 mΩ·cm. 2As can be seen from Example 1 and Comparative Example 4, the use of a full back-side texturing structure reduces Voc and Isc. This is because the increased back-side surface area brings more recombination centers, while the density of the back-side passivation film is also affected, resulting in a decrease in passivation effect. Although the increased metal contact area improves interface contact and promotes the improvement of FF, there is still a significant loss in efficiency. The present invention uses a partial back-side texturing structure to balance these two points well.

[0092] (2) As can be seen from Example 1 and Comparative Example 2, the back metal contact area is a double layer of heavily doped polysilicon, and the non-metal contact area is a single layer of shallowly doped polysilicon. This improves metal composite while reducing parasitic absorption in the non-metal contact area, resulting in a Voc increase of 2.9mV and an Isc increase of 50mA.

[0093] Based on the above analysis, the overall efficiency of Example 1 can be improved by 0.24% compared to the conventional TOPCon battery in Comparative Example 1.

[0094] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and inventive concept of the present utility model, should be included within the protection scope of the present utility model.

Claims

1. A passivated contact battery structure, comprising a silicon substrate (1), wherein the back surface of the silicon substrate (1) includes a metal contact region and a non-metal contact region, characterized in that, The metal contact area on the back side of the silicon substrate (1) has a textured surface structure. The metal contact area on the back side of the silicon substrate (1) is provided with the following layers stacked from the inside to the outside: a first tunneling oxide layer (2), a first doped polysilicon layer (3), a second tunneling oxide layer (4), a second doped polysilicon layer (5), an aluminum oxide layer (6), a silicon nitride layer (7), and a back electrode (8). The non-metallic contact area on the back of the silicon substrate (1) is a polished surface structure. From the inside to the outside, the non-metallic contact area on the back of the silicon substrate (1) is provided with a back first tunneling oxide layer (2), a back first doped polysilicon layer (3), a back aluminum oxide layer (6) and a back silicon nitride layer (7).

2. The passivated contact battery structure according to claim 1, characterized in that... A front emitter (9), a front alumina layer (10), a front silicon nitride layer (11) and a front electrode (12) are stacked sequentially from the inside to the outside on the front side of the silicon substrate (1).

3. The passivated contact battery structure according to claim 1, characterized in that... The height of the pyramid formed in the textured surface structure of the metal contact area on the back side of the silicon substrate (1) is 0.5 to 2 μm.

4. The passivated contact battery structure according to claim 1, characterized in that... The thickness of the first tunneling oxide layer on the back side is 1–2 nm.

5. The passivated contact battery structure according to claim 1, characterized in that... The first doped polycrystalline silicon layer (3) on the back side is a first in-situ phosphorus-doped amorphous silicon layer with a thickness of 50-80 nm and a phosphorus atom doping concentration of 1.0-2.5 × 10⁻⁶. 20 / cm 3 .

6. The passivated contact battery structure according to claim 1, characterized in that... The thickness of the second tunneling oxide layer on the back side is 1–2 nm.

7. The passivated contact battery structure according to claim 1, characterized in that... The second doped polycrystalline silicon layer (5) on the back side is a second in-situ phosphorus-doped amorphous silicon layer with a thickness of 40-70 nm and a phosphorus atom doping concentration of 3.0-4.0 × 10⁻⁶. 20 / cm 3 .

8. The passivated contact battery structure according to claim 1, characterized in that... The thickness of the back alumina layer (6) is 2-10 nm.

9. The passivated contact battery structure according to claim 1, characterized in that... The thickness of the back silicon nitride layer (7) is 70-80 nm, and the refractive index of silicon nitride is 2.1-2.

2.

10. The passivated contact battery structure according to claim 2, characterized in that... The front emitter (9) is a boron-doped emitter, and the thickness of the front emitter is 0.7 to 1.0 μm; the thickness of the front alumina layer (10) is 2 to 10 nm; and the thickness of the front silicon nitride layer (11) is 70 to 80 nm.

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