Solar cell and photovoltaic module

Abstract

The embodiment of the present application relates to the technical field of solar cells, in particular to a solar cell and a photovoltaic module, the solar cell comprising: a substrate; a tunneling dielectric layer located on a first surface of the substrate; a plurality of doped conductive layers located on a surface of the tunneling dielectric layer away from the substrate, and the plurality of doped conductive layers are arranged at intervals; a plurality of first electrodes arranged at intervals, the first electrodes extend along a first direction, the first electrodes are arranged on a side of the doped conductive layers away from the substrate, and the first electrodes are electrically connected with the doped conductive layers; and at least one conductive transfer layer located between adjacent doped conductive layers and in contact with side surfaces of the doped conductive layers. The embodiment of the present application is conducive to improving the photoelectric conversion efficiency of the solar cell.

Description

Technical Field

[0001] This application relates to the field of solar cells, and particularly to a solar cell and a photovoltaic module. Background Technology

[0002] Solar cells exhibit good photoelectric conversion efficiency. Typically, a tunneling dielectric layer and a doped conductive layer are fabricated on the substrate surface to suppress carrier recombination and enhance passivation. The tunneling dielectric layer provides good chemical passivation, while the doped conductive layer provides good field passivation. Furthermore, electrodes are fabricated on parts of the substrate surface to transport and collect photogenerated carriers generated by the solar cell. However, current solar cells suffer from low photoelectric conversion efficiency. Summary of the Invention

[0003] This application provides a solar cell and a photovoltaic module, which at least helps to improve the photoelectric conversion efficiency of the solar cell.

[0004] This application provides a solar cell, comprising: a substrate; a tunneling dielectric layer located on a first surface of the substrate; a plurality of doped conductive layers located on the surface of the tunneling dielectric layer away from the substrate, and the plurality of doped conductive layers being spaced apart; a plurality of spaced first electrodes extending along a first direction, the first electrodes being disposed on the side of the doped conductive layer away from the substrate and electrically connected to the doped conductive layer; and at least one conductive transport layer located between adjacent doped conductive layers and in contact with the side of the doped conductive layer.

[0005] In addition, there are multiple conductive transport layers, which are arranged at intervals along the first direction.

[0006] In addition, the array of multiple conductive transport layers includes: multiple columns of conductive transport layers spaced apart along a second direction, wherein multiple conductive transport layers in each column of conductive transport layers are spaced apart along a first direction, and at least one first electrode is present between two adjacent columns of conductive transport layers along the second direction, wherein the second direction is perpendicular to the first direction.

[0007] In addition, the conductive transport layer is present between all adjacent first electrodes.

[0008] In addition, one column of the conductive transport layers is staggered with the adjacent column of the conductive transport layers along the first direction.

[0009] In addition, each of the conductive transport layers in one column corresponds one-to-one with each of the conductive transport layers in an adjacent column, and the corresponding two conductive transport layers are arranged at intervals along the second direction.

[0010] Additionally, it includes: a plurality of second electrodes arranged at intervals, the second electrodes extending along the second direction and electrically connected to a plurality of first electrodes arranged at intervals along the second direction.

[0011] In addition, in a column of conductive transport layers, there is at least one second electrode between two adjacent conductive transport layers.

[0012] In addition, in a column of conductive transport layers, there are two second electrodes between two adjacent conductive transport layers.

[0013] In addition, one column of the conductive transport layer is staggered with an adjacent column of the conductive transport layer along the first direction, and the two staggered conductive transport layers belonging to different columns are located on opposite sides of the second electrode.

[0014] In addition, the substrate includes a peripheral region and a central region. The outer side of the second electrode located on the outermost side is the peripheral region, and the region of the substrate other than the peripheral region is the central region. The spacing of the conductive transport layer located in the peripheral region in the first direction is smaller than the spacing of the conductive transport layer located in the central region in the first direction.

[0015] Furthermore, in each column of the conductive transport layers located in the central region, the spacing between each conductive transport layer in the first direction is equal.

[0016] In addition, in each column of the conductive transport layer in the central region, the spacing between each conductive transport layer is 0.01mm to 20mm; in each column of the conductive transport layer in the peripheral region, the spacing between each conductive transport layer is 0.005mm to 18mm.

[0017] Additionally, it includes a connecting portion located between adjacent conductive transport layers spaced apart along the first direction, and electrically contacting the sides of two adjacent conductive transport layers.

[0018] In addition, the top surface of the conductive transport layer is lower than or flush with the top surface of the doped conductive layer.

[0019] In addition, the top surface of the conductive transport layer has a light-trapping structure.

[0020] In addition, the material of the conductive transport layer is the same as the material of the doped conductive layer.

[0021] In addition, the material of the doped conductive layer is at least one of doped amorphous silicon, doped polycrystalline silicon, or doped microcrystalline silicon.

[0022] Additionally, it includes: a first passivation layer, a portion of which covers the first surface of the substrate, and the remaining portion of which covers the top surface of the doped conductive layer and the conductive transport layer.

[0023] Accordingly, this application also provides a photovoltaic module, including a battery string, which is formed by connecting a plurality of solar cells as described in any one of the above claims; and an encapsulation layer, which is used to cover the surface of the battery string, and the cover is used to cover the surface of the encapsulation layer away from the battery string.

[0024] The technical solution provided in this application has at least the following advantages: In the solar cell technical solution provided in this application embodiment, multiple doped conductive layers are arranged at intervals. Thus, when incident light irradiates the region between two adjacent doped conductive layers, since no doped conductive layer is present in this region, the incident light is not absorbed by the doped conductive layer. This reduces parasitic absorption of the incident light by the doped conductive layer and improves the utilization rate of the substrate for the incident light. Furthermore, a conductive transport layer is located between two adjacent doped conductive layers and is in contact with them. This allows majority carriers in the substrate to be transported to the doped conductive layer through the conductive transport layer, thereby improving the lateral transport of majority carriers in the substrate and increasing the fill factor of the solar cell. This achieves both improved utilization of incident light and improved transport capability of majority carriers in the substrate, ultimately improving the overall photoelectric conversion efficiency of the solar cell. Attached Figure Description

[0025] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0026] Figure 1 A top view of a solar cell provided in an embodiment of this application; Figure 2 for Figure 1 A magnified view of one of the components in section 1; Figure 3 This is a schematic diagram of carrier transport in a solar cell provided in one embodiment of this application; Figure 4 A top view of another solar cell provided in an embodiment of this application; Figure 5A top view of another solar cell provided in an embodiment of this application; Figure 6 A top view of another solar cell provided in an embodiment of this application; Figure 7 for Figure 1 Another magnified view of part 1; Figure 8 for Figure 1 Another magnified view of part 1; Figure 9 for Figure 1 Another magnified view of part 1; Figure 10 This is a schematic diagram of a photovoltaic module provided in an embodiment of this application. Detailed Implementation

[0027] As is known from the background technology, current solar cells suffer from low photoelectric conversion efficiency.

[0028] Analysis reveals that one reason for the low photoelectric conversion efficiency of current solar cells is that, to reduce light absorption by the doped conductive layer, it is typically placed in the metallized region, while the doped conductive layer in the non-metallized region is removed. However, this results in a lack of lateral transport channels for charge carriers in the substrate. More charge carriers are transported to the areas covered by the doped conductive layer, while very few are transported to areas without a doped conductive layer. This significantly reduces the fill factor of the solar cell, leading to low overall power generation efficiency.

[0029] This application provides a solar cell with multiple doped conductive layers arranged at intervals. These doped conductive layers are disposed in localized areas on the substrate surface, reducing parasitic absorption of incident light by the doped conductive layers and improving the substrate's utilization rate of incident light. To enhance the lateral transport capability of charge carriers in the substrate, a conductive transport layer is positioned between two adjacent doped conductive layers and in contact with them. This allows majority carriers in the substrate to be transported to the doped conductive layers via the conductive transport layer, thereby improving the lateral transport of majority carriers in the substrate and increasing the fill factor of the solar cell. This achieves both improved utilization of incident light and enhanced transport capability of majority carriers in the substrate, ultimately improving the overall photoelectric conversion efficiency of the solar cell.

[0030] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0031] Figure 1 A top view of a solar cell provided in an embodiment of this application; Figure 2 for Figure 1 A magnified view of one of the components in section 1; Figure 3 This is a schematic diagram of carrier transport in a solar cell provided in one embodiment of this application.

[0032] refer to Figures 1 to 3 The solar cell includes: a substrate 100; a tunneling dielectric layer 101 located on a first surface of the substrate 100; a plurality of doped conductive layers 102 located on the surface of the tunneling dielectric layer 101 away from the substrate 100, and the plurality of doped conductive layers 102 are spaced apart; a plurality of spaced first electrodes 103 extending along a first direction X, the first electrodes 103 being disposed on the side of the doped conductive layers 102 away from the substrate 100 and electrically connected to the doped conductive layers 102; and at least one conductive transport layer 104 located between adjacent doped conductive layers 102 and in contact with the side of the doped conductive layers 102.

[0033] The conductive transport layer 104 is positioned between two adjacent doped conductive layers 102 and in contact with them. This allows majority carriers in the substrate 100 to be transported to the doped conductive layers 102 via the conductive transport layer 104, thereby improving the lateral transport of majority carriers in the substrate 100, increasing the fill factor of the solar cell, and simultaneously improving the utilization rate of incident light while enhancing the transport capability of majority carriers in the substrate 100, ultimately improving the overall photoelectric conversion efficiency of the solar cell. For details, please refer to... Figure 3 , Figure 3 This is a schematic diagram of carrier transport in a solar cell provided in an embodiment of this application. Due to the provision of a conductive transport layer 104, carriers in the substrate 100 can move laterally to the lateral transport layer 104, and then be transported to the doped conductive layer 102 through the lateral transport layer 104, thereby increasing the carrier transport capacity in the substrate 100 and increasing the carrier concentration in the doped conductive layer 102.

[0034] The substrate 100 is used to receive incident light and generate photogenerated carriers. In some embodiments, the substrate 100 may be a substrate 100, and the material of the substrate 100 may include at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In other embodiments, the material of the substrate 100 may also be silicon carbide, organic materials, or multi-component compounds. Multi-component compounds may include, but are not limited to, materials such as perovskite, gallium arsenide, cadmium telluride, and copper indium selenide.

[0035] In some embodiments, the substrate 100 contains dopant elements of either N-type or P-type. N-type elements can be Group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), while P-type elements can be Group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In). For example, when the substrate 100 is a P-type substrate 100, its internal dopant element type is P-type. Alternatively, when the substrate 100 is an N-type substrate 100, its internal dopant element type is N-type. Specifically, in some embodiments, the substrate 100 can be an N-type substrate 100, and the substrate 100 can be doped with N-type dopant ions, such as any one of phosphorus ions, bismuth ions, antimony ions, or arsenic ions.

[0036] In some embodiments, the solar cell is a TOPCON (Tunnel Oxide Passivated Contact) cell, and the substrate 100 further includes a second surface disposed opposite to the first surface. Both the first and second surfaces of the substrate 100 can be used to receive incident light or reflect light. In some embodiments, the first surface can be the back surface of the substrate 100, and the second surface can be the front surface of the substrate 100. In other embodiments, the first surface can also be the front surface of the substrate 100, in which case the second surface is the back surface of the substrate 100.

[0037] In some embodiments, the first surface of the substrate 100 can be configured as a non-pyramidal textured surface, such as a layered stepped morphology, to give the tunneling dielectric layer 101 located on the first surface of the substrate 100 higher density and uniformity, thereby enabling the tunneling dielectric layer 101 to have a good passivation effect on the first surface of the substrate 100. The second surface of the substrate 100 can be configured as a pyramidal textured surface to give the second surface of the substrate 100 lower reflectivity to incident light, thereby increasing the light absorption and utilization rate.

[0038] In some embodiments, the tunneling dielectric layer 101 and the doped conductive layer 102 can be used to form a passivation contact structure on the surface of the substrate 100. By forming the tunneling dielectric layer 101 and the doped conductive layer 102, the recombination of charge carriers on the surface of the substrate 100 can be reduced, thereby increasing the open-circuit voltage of the solar cell and improving the photoelectric conversion efficiency of the solar cell. Specifically, the tunneling dielectric layer 101 can reduce the defect state concentration on the first surface of the substrate 100, thereby reducing the recombination centers on the first surface of the substrate 100 and thus reducing the recombination rate of charge carriers.

[0039] The doped conductive layer 102 is used to form a field passivation layer, allowing minority carriers to escape from the interface, thereby reducing the minority carrier concentration and resulting in a lower carrier recombination rate at the interface of the substrate 100. This leads to a larger open-circuit voltage, short-circuit current, and fill factor of the solar cell, thus improving the photoelectric conversion performance of the solar cell. In some embodiments, the doped conductive layer 102 and the substrate 100 have doping elements of the same conductivity type.

[0040] Multiple doped conductive layers 102 extend along a first direction X, and are spaced apart along a second direction Y, which is perpendicular to the first direction X. In some embodiments, the first electrode 103 and the doped conductive layer 102 have a one-to-one correspondence, that is, one first electrode 103 is electrically connected to one doped conductive layer 102. In other words, the doped conductive layer 102 is only disposed in the region corresponding to the first electrode 103, thereby reducing parasitic light absorption in the region where the first electrode 103 is not disposed and improving the light utilization efficiency of the substrate 100. In some embodiments, the material of the first electrode 103 can be at least one of silver, aluminum, copper, tin, gold, lead, or nickel.

[0041] The tunneling dielectric layer 101 and the doped conductive layer 102 are stacked. Specifically, in some embodiments, the tunneling dielectric layer 101 can cover the entire first surface of the substrate 100, and multiple doped conductive layers 102 are spaced apart on the top surface of the tunneling dielectric layer 101. In other embodiments, the tunneling dielectric layer 101 and the doped conductive layer 102 are correspondingly arranged, that is, the tunneling dielectric layer 101 is disposed between the doped conductive layer 102 and the substrate 100, and the tunneling dielectric layer 101 is also located between the conductive transport layer 104 and the substrate 100, so that this part of the tunneling dielectric layer 101 can reduce carrier recombination on the first surface of the substrate 100, thereby increasing the carrier concentration transported to the conductive transport layer 104.

[0042] In some embodiments, the material of the tunneling dielectric layer 101 may include, but is not limited to, dielectric materials with tunneling properties such as alumina, silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, and intrinsic polycrystalline silicon. Specifically, the tunneling dielectric layer 101 may be formed of a silicon oxide layer including silicon oxide (SiOx), which has good passivation properties and allows charge carriers to easily tunnel through the silicon oxide layer.

[0043] In some embodiments, the material of the conductive transport layer 104 is the same as the material of the doped conductive layer 102. By using the same material for the conductive transport layer 104 and the doped conductive layer 102, the number of material types in the entire production process can be reduced, facilitating management. Furthermore, using the same material for the conductive transport layer 104 and the doped conductive layer 102 ensures good contact between them, resulting in better carrier transport at the interface and reducing transport losses. Additionally, it allows the carrier transport rates in the conductive transport layer 104 and the doped conductive layer 102 to be similar or the same, thereby improving the transport efficiency of carriers from the conductive transport layer 104 to the doped conductive layer 102. It is worth noting that "same material" here refers to the conductive transport layer 104 having the same type and concentration of dopant ions as the doped conductive layer 102.

[0044] Specifically, in some embodiments, the material of the doped conductive layer 102 is at least one of doped amorphous silicon, doped polycrystalline silicon, or doped microcrystalline silicon. Correspondingly, the material of the conductive transport layer 104 may also be one of doped amorphous silicon, doped polycrystalline silicon, or doped microcrystalline silicon.

[0045] It is understood that in other embodiments, the material of the conductive transport layer 104 may also be different from the material of the doped conductive layer 102. For example, the material of the conductive transport layer 104 may be one of doped amorphous silicon, doped polycrystalline silicon, or doped microcrystalline silicon, and the material of the doped conductive layer 102 may be another of doped amorphous silicon, doped polycrystalline silicon, or doped microcrystalline silicon.

[0046] In some embodiments, when the material of the conductive transport layer 104 is different from the material of the doped conductive layer 102, the absorption coefficient of the material of the conductive transport layer 104 to the incident light can be set to be smaller than the absorption coefficient of the conductive transport layer 104 to the incident light. This can improve the lateral transport capability of charge carriers while reducing the absorption capability of the conductive transport layer 104 to the incident light, thereby improving the utilization rate of the solar cell to the incident light.

[0047] In some embodiments, the material of the conductive transport layer 104 is the same as the material of the doped conductive layer 102, and the actual process for preparing the doped conductive layer 102 and the conductive transport layer 104 can be as follows: An initial tunneling dielectric layer 101 and an initial doped conductive layer 102 are formed on the first surface of a substrate 100 using a deposition process. The initial tunneling dielectric layer 101 covers the entire first surface of the substrate 100, and the initial doped conductive layer 102 covers the entire first surface of the tunneling dielectric layer 101.

[0048] The top surface of the initial doped conductive layer 102 is patterned to define the shape of the spaced doped conductive layer 102 and the shape of the conductive transport layer 104.

[0049] An etching process is performed on the patterned initial doped conductive layer 102 to remove part of the initial doped conductive layer 102, forming spaced doped conductive layers 102 and conductive transport layers 104 located between adjacent doped conductive layers 102.

[0050] In some embodiments, laser etching can be used to etch the initial doped conductive layer 102, which simplifies the etching process and eliminates the need for patterning the initial doped conductive layer 102, thus simplifying the fabrication process.

[0051] In some embodiments, when the tunneling dielectric layer 101 can cover the entire first surface of the substrate 100, and multiple doped conductive layers 102 are spaced apart on the top surface of the tunneling dielectric layer 101, in the etching process, only the initial doped conductive layer 102 is etched, and the initial tunneling dielectric layer 101 serves as the tunneling dielectric layer 101.

[0052] In some other embodiments, the tunneling dielectric layer 101 is disposed correspondingly to the doped conductive layer 102, that is, the tunneling dielectric layer 101 is disposed between the doped conductive layer 102 and the substrate 100, and the tunneling dielectric layer 101 is also located between the conductive transport layer 104 and the substrate 100. In the process of etching the initial doped conductive layer 102, the initial tunneling dielectric layer 101 can be etched at the same time to form the tunneling dielectric layer 101 corresponding to the doped conductive layer 102 and the conductive transport layer 104.

[0053] In some embodiments, there are multiple conductive transport layers 104, which are arranged at intervals along a first direction X. The multiple conductive transport layers 104 are disposed between two adjacent doped conductive layers 102, allowing majority carriers in the substrate 100 to be transported to the doped conductive layers 102 through the multiple conductive transport layers 104, thereby enhancing the lateral transport capability of majority carriers in the substrate 100. Furthermore, the multiple conductive transport layers 104 are arranged at intervals, meaning that the conductive transport layers 104 do not cover the entire area between two adjacent doped conductive layers 102, but are disposed in localized areas between two adjacent doped conductive layers 102. Thus, when the material of the conductive transport layers 104 is the same as the material of the doped conductive layers 102, the overall area of ​​the conductive transport layers 104 is not excessively large, thereby preventing the substrate 100 from having low utilization of incident light due to excessive absorption of incident light by the conductive transport layers 104.

[0054] In some embodiments, a plurality of conductive transport layers 104 are arranged in an array, including multiple columns of conductive transport layers 104 spaced apart along a second direction Y. In each column of conductive transport layers 104, the plurality of conductive transport layers 104 are spaced apart along a first direction X, and at least one first electrode 103 is present between two adjacent columns of conductive transport layers 104 along the second direction Y. The second direction Y is perpendicular to the first direction X. That is, in some embodiments, when there is only one first electrode 103 between adjacent conductive transport layers 104, a conductive transport layer 104 is present between every two adjacent first electrodes 103. In other embodiments, multiple first electrodes 103 may also be present between two adjacent columns of conductive transport layers 104, such that a conductive transport layer 104 is present between some adjacent two first electrodes 103, and a conductive transport layer 104 is not present between some adjacent first electrodes 103. For example, in the first direction X, there is a conductive transport layer 104 between the first electrode 103 and the second electrode 103, but no conductive transport layer 104 between the second electrode 103 and the third electrode 103. It is understood that when the material of the conductive transport layer 104 is the same as the material of the doped conductive layer 102, the more conductive transport layers 104 there are, the stronger the absorption capacity of incident light while enhancing the lateral capacity of charge carriers. Therefore, the connection relationship between the conductive transport layer 104 and the doped conductive layer 102 can be flexibly set based on the total number of first electrodes 103 and the requirement for the current collection capacity of the first electrodes 103, so that while improving the charge carrier transport capacity, the conductive transport layer 104 does not have a strong absorption effect on incident light.

[0055] refer to Figure 1In some embodiments, a conductive transport layer 104 is provided between all adjacent first electrodes 103. Providing a conductive transport layer 104 between every two first electrodes 103 can improve the lateral transport capability between adjacent first electrodes 103, thereby improving the current collection capability of each first electrode 103.

[0056] refer to Figure 4 as well as Figure 5 , Figure 4 This is a top view schematic diagram of another solar cell structure provided in an embodiment of this application. Figure 5 This is a top view of another solar cell provided in an embodiment of the present application. In some embodiments, a column of conductive transport layers 104 is staggered with an adjacent column of conductive transport layers 104 along a first direction X.

[0057] Specifically, in some embodiments, each conductive transport layer 104 in the first column of conductive transport layers 104 is not directly aligned with each conductive transport layer 104 in the second column of conductive transport layers 104 in the second direction Y; that is, each conductive transport layer 104 in the first column of conductive transport layers 104 and each conductive transport layer 104 in the second column of conductive transport layers 104 are staggered in the first direction X. This staggered arrangement of multiple conductive transport layers 104 serves two purposes: firstly, it prevents the number of conductive transport layers 104 from becoming excessive, thereby avoiding excessive absorption of incident light by the conductive transport layers 104; secondly, it allows for a smaller number of conductive transport layers 104 while ensuring uniform distribution of the conductive transport layers 104 on the first surface of the substrate 100, thereby enhancing the lateral transport capability of charge carriers at different locations in the substrate 100.

[0058] refer to Figure 1 In other embodiments, each conductive transport layer 104 in a column of conductive transport layers 104 corresponds one-to-one with each conductive transport layer 104 in an adjacent column of conductive transport layers 104, and the corresponding two conductive transport layers 104 are spaced apart along the second direction Y. For example, each conductive transport layer 104 in the first column of conductive transport layers 104 and the corresponding conductive transport layer 104 in the second column of conductive transport layers 104 are aligned and distributed in the second direction Y, and each column of conductive transport layers 104 is regularly arranged. This results in a large number of conductive transport layers 104, thereby forming more lateral transport channels for the lateral transport of charge carriers in the substrate 100. Furthermore, since each column of conductive transport layers 104 is regularly arranged, the process of forming the conductive transport layers 104 can be simplified in the actual fabrication process.

[0059] refer to Figure 1 , Figure 4 as well as Figure 5In some embodiments, the system further includes: a plurality of spaced-apart second electrodes 106 extending along a second direction Y and electrically connected to a plurality of spaced-apart first electrodes 103 arranged along the second direction Y. The plurality of second electrodes 106 are spaced-apart along a first direction X, and are electrically connected to the first electrodes 103 for collecting and channeling current from the first electrodes 103 into the solar cell. It is understood that the second electrodes 106 are not only in electrical contact with the first electrodes 103 but also in electrical contact with a portion of the doped conductive layer 102. This allows charge carriers in the doped conductive layer 102 to be directly transferred to the second electrodes 106 without passing through the first electrodes 103, thereby improving the current collection capability of the second electrodes 106.

[0060] In some embodiments, in a row of conductive transport layers 104, at least one second electrode 106 is provided between two adjacent conductive transport layers 104. That is, the second electrode 106 is spaced apart from the conductive transport layers 104. In this way, the second electrode 106 can be limited by the conductive transport layers 104, so that the position of the second electrode 106 can be determined without additional positioning processing during the fabrication process of the second electrode 106, which facilitates the printing of the second electrode 106 and simplifies the process flow.

[0061] refer to Figures 4 to 5 Specifically, in some embodiments, in a row of conductive transport layers 104, there are two second electrodes 106 between two adjacent conductive transport layers 104. That is, the conductive transport layers 104 are sparsely distributed, thereby preventing the problem of excessive absorption of incident light due to an excessive number of conductive transport layers 104.

[0062] It is understandable that, since the conductive transport layer 104 serves as a lateral transport channel for charge carriers, the doped conductive layer 102 adjacent to the conductive transport layer 104 has a higher charge carrier concentration. This results in a higher charge carrier concentration in the portion of the first electrode 103 electrically connected to the doped conductive layer 102 adjacent to the conductive transport layer 104. Based on this, in some embodiments, a column of conductive transport layers 104 is staggered with an adjacent column of conductive transport layers 104 along the first direction X. Two staggered conductive transport layers 104 belonging to different columns are located on opposite sides of the second electrode 106, and the conductive transport layers 104 on both sides of the second electrode 106 are not directly opposite each other in the first direction X. This allows for a limited number of conductive transport layers 104 to be uniformly distributed on both sides of the second electrode 106. The placement of conductive transport layers 104 on both sides of the second electrode 106 means that the second electrode 106 is electrically connected to the portion of the first electrode 103 with a higher carrier concentration. This improves the overall ability of the second electrode 106 to collect current from the first electrode 103. Furthermore, since the number of conductive transport layers 104 is relatively small, the problem of excessive absorption of incident light by the conductive transport layers 104 can be avoided, thereby improving the overall photoelectric conversion performance of the solar cell.

[0063] It is understood that, in some embodiments, the projection of a portion of the second electrode 106 onto the first surface of the substrate 100 may also coincide with a portion of the conductive transport layer 104. This allows the second electrode 106 to cover a portion of the top surface of the conductive transport layer 104, partially blocking it and reducing the parasitic light absorption capacity of the conductive transport layer 104 to incident light, thereby further improving the photoelectric conversion efficiency of the solar cell. In some embodiments, the second electrode 106 is also in direct electrical contact with the covered connection portion 105. The connection portion 105 can serve as a lateral transport channel between adjacent second electrodes, allowing charge carriers in the connection layer 105 and the conductive transport layer 104 to be directly transported to the second electrode 106, further improving the current collection capacity of the second electrode 106.

[0064] Understandably, in the lamination process of solar cells, to prevent the cells from being crushed, the second electrode 106 is usually positioned far from the edge of the cell, meaning there is a significant space between the edge of the substrate 100 and the second electrode 106. This results in a smaller number of second electrodes 106 at the edge of the substrate 100, leading to a weaker carrier collection capability for the outermost second electrode 106 at the edge of the substrate 100. Therefore, in some embodiments, the substrate 100 includes a peripheral region and a central region. The region outside the outermost second electrode 106 is the peripheral region, and the region of the substrate 100 excluding the peripheral region is the central region. The spacing of the conductive transport layers 104 in the first direction X in the peripheral region is smaller than the spacing of the conductive transport layers 104 in the first direction X in the central region. This results in a higher density of the conductive transport layer 104 on the first surface of the substrate 100 in the peripheral region compared to the central region. This means that the lateral transport capability of the charge carriers in the substrate 100 in the peripheral region is stronger, resulting in a higher charge carrier concentration in the first electrode 103 in the peripheral region. This compensates for the number of charge carriers collected by the outermost second electrode 106, thereby improving the ability of the outermost second electrode 106 to collect current.

[0065] In some embodiments, in each column of conductive transport layers 104, there are multiple conductive transport layers 104 located in the peripheral region, while in the central region, there are either one or zero conductive transport layers 104 between two adjacent second electrodes 106. That is, the conductive transport layers 104 are more sparsely distributed in the central region, thereby reducing the parasitic light absorption capacity of the conductive transport layers 104 on incident light, while the conductive transport layers 104 are more densely distributed in the peripheral region, improving the current collection capacity of the outermost second electrode 106, thereby further improving the overall photoelectric conversion performance of the solar cell.

[0066] Specifically, refer to Figure 4 In some embodiments, in the first column of conductive transport layers 104 in the peripheral region, the number of conductive transport layers 104 located on the outermost side of the second electrode 106 can be two, and in the second column of conductive transport layers 104 in the peripheral region, the number of conductive transport layers 104 located on the outermost side of the second electrode 106 can be one. The conductive transport layers 104 in the first column and the conductive transport layers 104 in the second column are arranged alternately. Only the arrangement of the first and second columns of conductive transport layers 104 is shown here; the arrangement of the third, fourth, fifth, and sixth columns of conductive transport layers 104 can be referenced from the first and second columns.

[0067] refer to Figure 5In other embodiments, in the first column of conductive transport layers 104 in the peripheral region, there may be one conductive transport layer 104 located on the side of the outermost second electrode 106; in the second column of conductive transport layers 104 in the peripheral region, there may be one conductive transport layer 104 located on the side of the outermost second electrode 106; and in the third column of conductive transport layers 104 in the peripheral region, there may be one conductive transport layer 104 located on the side of the outermost second electrode 106. The three adjacent columns of conductive transport layers 104 are staggered along the first direction X. Only the arrangement of the first, second, and third columns of conductive transport layers 104 is shown here; the arrangement of the remaining columns of conductive transport layers 104 can be referenced from the first, second, and third columns.

[0068] In some embodiments, in each column of conductive transport layers 104 located in the central region, the spacing between each conductive transport layer 104 in the first direction X is equal. Setting the spacing between adjacent conductive transport layers 104 in each column of conductive transport layers 104 equal facilitates the use of laser ablation processes during formation; that is, it eliminates the need to adjust the spacing between adjacent conductive transport layers 104, thereby simplifying production. Furthermore, setting the spacing between adjacent conductive transport layers 104 in the central region to be equal ensures a uniform distribution of the conductive transport layers 104 in the central region, thereby uniformly improving the carrier collection capability of the second electrode 106 at different locations.

[0069] In some embodiments, in each conductive transmission layer 104 in the central region, the spacing between each conductive transmission layer 104 is 0.01mm to 20mm, for example, it can be 0.01mm to 0.1mm, 0.1mm to 0.5mm, 0.5mm to 2mm, 2mm to 5mm, 5mm to 10mm, 10mm to 15mm, or 15mm to 20mm; in each column of conductive transmission layers 104 in the peripheral region, the spacing between each conductive transmission layer 104 can be 0.005mm to 18mm, for example, it can be 0.005mm to 0.01mm, 0.01mm to 0.1mm, 0.1mm to 0.5mm, 0.5mm to 2mm, 2mm to 5mm, 5mm to 10mm, 10mm to 15mm, or 15mm to 18mm. Within this range, on the one hand, the spacing between adjacent conductive transport layers 104 is not too small, preventing the conductive transport layers 104 from being too densely packed, which would result in the conductive transport layers 104 having an excessively strong light absorption effect on the incident light. On the other hand, within this range, the spacing between adjacent conductive transport layers 104 is not too small, thereby forming more lateral transport channels, which can significantly improve the lateral transport capability of charge carriers in the substrate 100.

[0070] refer to Figure 6 , Figure 6 This is a top view schematic diagram of another solar cell provided in an embodiment of this application. In some embodiments, it further includes a connecting portion 105, which is located between adjacent conductive transport layers 104 spaced apart along a first direction X, and is in electrical contact with the sides of two adjacent conductive transport layers 104. It is understood that the width of the connecting portion 105 in the second direction Y is smaller than the spacing between two adjacent doped conductive layers 102 in the second direction Y, that is, the side of the connecting portion 105 does not contact the side of the two adjacent doped conductive layers 102. Thus, when incident light irradiates the gap between the doped conductive layer 102 and the connecting portion 105, it will not be absorbed by the connecting portion 105 or the doped conductive layer 102. In some embodiments, the material of the connecting portion 105 can be the same as the material of the conductive transport layer 104, so that the connecting portion 105 can also serve to provide a lateral transport channel for charge carriers in the substrate 100. Specifically, charge carriers in the substrate 100 corresponding to the connection portion 105 can be transported to the connection portion 105, and then the charge carriers in the connection portion 105 are transported to the conductive transport layer 104, and then reach the doped conductive layer 102 via the conductive transport layer 104. It is easy to see that, due to the addition of the connection portion 105, more charge carriers in the substrate 100 can be transported to the conductive transport layer 104 and finally reach the doped conductive layer 102, thereby increasing the lateral transport capability of charge carriers in the substrate 100, resulting in a larger charge carrier concentration in the doped conductive layer 102, thereby increasing the current collection capability of the first electrode 103.

[0071] refer to Figure 2 In some embodiments, the top surface of the conductive transport layer 104 is lower than or flush with the top surface of the doped conductive layer 102. Setting the top surface of the conductive transport layer 104 to be no higher than the top surface of the doped conductive layer 102 prevents the absorption of incident light by the sides of the conductive transport layer 104 due to the top surface of the conductive transport layer 104 protruding from the top surface of the doped conductive layer 102, thereby reducing the parasitic absorption capacity of the conductive transport layer 104 for incident light. It is understood that when the top surface of the conductive transport layer 104 is lower than the top surface of the doped conductive layer 102, the top surface of the doped conductive layer 102 will partially block incident light rays incident obliquely into the top surface of the conductive transport layer 104, further reducing the transmission capacity of the conductive transport layer 104 for incident light. When the top surface of the conductive transport layer 104 is flush with the top surface of the doped conductive layer 102, the manufacturing process of the solar cell can be simplified, allowing the conductive transport layer 104 and the doped conductive layer 102 to be formed in the same step using laser ablation.

[0072] In some embodiments, the height of the conductive transport layer 104 in the direction perpendicular to the surface of the substrate 100 can be 0.5 to 1.2 times the height of the doped conductive layer 102, specifically 0.5, 0.6, 0.7, 0.8, 0.9, 1, or 1.2. Within this range, the thickness of the conductive transport layer 104 is not too thin, ensuring that the lateral transport capability of the conductive transport layer 104 for charge carriers is not too poor. On the other hand, within this range, the thickness of the conductive transport layer 104 is also not too large, thereby preventing the problem of excessive absorption of incident light due to excessively large trenches in the conductive transport layer 104.

[0073] refer to Figures 7 to 9 In some embodiments, the top surface of the conductive transport layer 104 has a light-trapping structure 108. The light-trapping structure 108 can enhance the reflectivity of the top surface of the conductive transport layer 104 to incident light, thereby allowing incident light illuminating the top surface of the conductive transport layer 104 to be reflected away and prevented from being absorbed by the conductive transport layer 104. This portion of the reflected incident light can also be reflected back, for example, to areas not covered by the doped conductive layer 102 and the conductive transport layer 104, and thus absorbed and utilized by the substrate 100. In this way, the absorption and utilization rate of the substrate 100 for incident light can be enhanced.

[0074] Specifically, refer to Figure 7 In some embodiments, the light-trapping structure 108 may include multiple pyramid structures, each having a base and sides connected to the base. Incident light can be reflected multiple times between the sides of adjacent pyramid structures, thereby reflecting the incident light that illuminates the top surface of the conductive transport layer 104 and reducing the absorption of incident light by the conductive transport layer 104. Furthermore, since the pyramid structure has multiple sides, the reflection probability of incident light is further increased, further reducing the absorption of incident light by the conductive transport layer 104. The reflected incident light can be reflected again to the first surface of the substrate 100 that is not covered by the doped conductive layer 102 and the conductive transport layer 104, thereby increasing the utilization rate of the substrate 100 for incident light, increasing the open-circuit voltage and short-circuit current, and improving the photoelectric conversion efficiency of the solar cell.

[0075] In other embodiments, the light-trapping structure 108 may also include a recessed structure facing the substrate 100. This recessed structure not only ensures that the top surface of the conductive transport layer 104 is lower than the top surface of the doped conductive layer 102, thus allowing the doped conductive layer 102 to partially block incident light rays illuminating the top surface of the conductive transport layer 104, but also allows the incident light rays to undergo multiple reflections on the sidewalls of the recessed structure, thereby reducing parasitic absorption of the incident light rays by the top surface of the conductive doped layer.

[0076] Specifically, in some embodiments, the height of the recessed structure gradually decreases in the direction from which the doped conductive layer 102 points to the center of the recessed structure. See details. Figure 8 The recessed structure has two opposing sidewalls, with their tops spaced apart and their bottoms joined. That is, the two sidewalls of the recessed structure are inclined relative to the first surface of the substrate 100. Thus, when incident light shines on one sidewall surface, a portion of the incident light will be reflected from that sidewall surface to the other sidewall surface. Then, of the incident light reflected to the other sidewall surface, some will be reflected back out, and some will be reflected again from that sidewall surface to the original sidewall surface. In this way, the incident light undergoes multiple reflections before exiting to the outside, thus increasing the probability that the incident light exiting to the outside will be reflected back to the first surface of the substrate 100 that is not covered by the doped conductive layer 102 and the conductive transport layer 104.

[0077] In other embodiments, reference is made to... Figure 9 In the direction from the doped conductive layer 102 to the substrate 100, the cross-sectional shape of the recessed structure can also be rectangular. That is, the recessed structure has two opposing sidewalls and a bottom wall. The two opposing sidewalls are perpendicular to the first surface of the substrate 100, and the bottom wall can be arranged parallel to the surface of the substrate 100.

[0078] It is understood that in other embodiments, the recessed structure may also be of other shapes, as long as it satisfies the feature that the recessed structure is recessed toward the substrate 100.

[0079] refer to Figure 2In some embodiments, the system further includes a first passivation layer 107, a portion of which covers the first surface of the substrate 100, and the remaining portion of which covers the top surface of the doped conductive layer 102 and the conductive transport layer 104. That is, the tunneling dielectric layer 101 is correspondingly disposed to the doped conductive layer 102, and is disposed between the doped conductive layer 102 and the substrate 100, and between the conductive transport layer 104 and the substrate 100. This allows the tunneling dielectric layer 101 to cover only a portion of the surface of the substrate 100, thus allowing a portion of the first passivation layer 107 to directly contact the first surface of the substrate 100. Because the conductive transport layer 104 is disposed between adjacent doped conductive layers 102, multiple lateral transport channels are formed in the substrate 100 directly in contact with the first passivation layer 107. Charge carriers in the substrate 100 can move laterally into the doped conductive layer 102, thereby reducing carrier consumption during transport and increasing the transport rate. Meanwhile, because the doped conductive layers 102 are spaced apart and only disposed in the metallized region (the region corresponding to the first electrode 103), the probability of incident light being absorbed when it irradiates the region between the doped conductive layers 102 is greatly reduced, thus reducing the parasitic absorption of incident light by the doped conductive layers 102 as a whole. Therefore, the solar cell provided in this embodiment not only improves the utilization rate of incident light in the solar cell but also maintains a high carrier transport efficiency in the solar cell.

[0080] In some embodiments, the first passivation layer 107 may be a single layer or a multilayer structure, and the material of the first passivation layer 107 may be at least one of magnesium fluoride, silicon oxide, aluminum oxide, silicon oxynitride, silicon nitride, and titanium oxide.

[0081] In other embodiments, the tunneling dielectric layer 101 may also be disposed on the first surface of the substrate 100. Based on this, a first passivation layer 107 may be disposed to partially cover the top surface of the doped conductive layer 102 and the conductive transport layer 104, with the remaining portion of the first passivation layer 107 covering the top surface of the doped dielectric layer.

[0082] In some embodiments, after forming the doped conductive layer 102 and the conductive transport layer 104, a first passivation layer 107 may be formed using PECVD (Plasma Enhanced Chemical Vapor Deposition).

[0083] The first electrode 103 penetrates the first passivation layer 107 and is electrically connected to the doped conductive layer 102. The first passivation layer 107 is used to reduce the reflection of incident light by the substrate 100. In some embodiments, after the first passivation layer 107 is formed, a plurality of spaced-apart first electrodes 103 may be formed on the side of the doped conductive layer 102 away from the substrate 100. The first electrodes 103 extend along a first direction X and are electrically connected to the doped conductive layer 102.

[0084] In some embodiments, the second surface of the substrate 100 may have an emitter, the type of doped ions in the emitter being different from the type of doped ions in the conductive layer 102. In some embodiments, the surface of the emitter away from the substrate 100 may also have an antireflection layer, which serves to reduce the reflection of incident light. In some embodiments, the antireflection layer may be a silicon nitride layer, which may include silicon nitride material. In other embodiments, the antireflection layer may also be a multilayer structure, such as a stacked structure made of one or more materials selected from silicon nitride, silicon oxide, or silicon oxynitride.

[0085] In other embodiments, the second surface of the substrate 100 may also have a structure similar to that of the first surface of the substrate 100. For example, the second surface of the substrate 100 may have a second tunneling dielectric layer and a second doped conductive layer stacked sequentially along the distance from the second surface of the substrate 100, wherein the dopant ion type in the second doped conductive layer is different from the dopant ion type in the doped conductive layer 102.

[0086] In some embodiments, a third electrode (not shown) is also included, located on the second surface of the substrate 108. When the second surface of the substrate 100 has an emitter, the third electrode penetrates the antireflection layer and is electrically connected to the emitter. When the second surface of the substrate 100 has a structure similar to that of the first surface of the substrate 100, the third electrode is electrically connected to the second doped conductive layer.

[0087] In the solar cell provided in the above embodiment, a conductive transport layer 104 is disposed between two adjacent doped conductive layers 102 and in contact with the doped conductive layers 102, so that majority carriers in the substrate 100 can be transported to the doped conductive layers 102 through the conductive transport layer 104, thereby improving the lateral transport of majority carriers in the substrate 100, increasing the fill factor of the solar cell, and improving the transport capability of majority carriers in the substrate 100 while improving the utilization rate of incident light, thus improving the overall photoelectric conversion efficiency of the solar cell.

[0088] Accordingly, embodiments of this application also provide a photovoltaic module, with reference to... Figure 10The photovoltaic module includes a battery string, which is formed by connecting multiple solar cells 110 provided in the above embodiments; an encapsulation layer 120 for covering the surface of the battery string; and a cover plate 130 for covering the surface of the encapsulation layer 120 away from the battery string. The solar cells 110 are electrically connected in a whole or in multiple segments to form multiple battery strings, and the multiple battery strings are electrically connected in series and / or parallel.

[0089] Specifically, in some embodiments, multiple battery strings can be electrically connected via conductive strips 140. The encapsulation layer 120 covers the front and back of the solar cell 110. Specifically, the encapsulation layer 120 can be an organic encapsulation film such as ethylene-vinyl acetate copolymer (EVA) film, polyethylene octene copolymer elastomer (POE) film, or polyethylene terephthalate (PET) film. In some embodiments, the cover plate 130 can be a light-transmitting cover plate such as a glass cover plate or a plastic cover plate. Specifically, the surface of the cover plate 130 facing the encapsulation layer 120 can be an uneven surface, thereby increasing the utilization rate of incident light.

[0090] Although this application discloses preferred embodiments as described above, it is not intended to limit the claims. Any person skilled in the art can make several possible changes and modifications without departing from the concept of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

[0091] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A solar cell, characterized by, include: Base; A tunneling medium layer, the tunneling medium layer being located on a first surface of the substrate; Multiple doped conductive layers are located on the surface of the tunneling dielectric layer away from the substrate, and the multiple doped conductive layers are spaced apart along a second direction; Multiple first electrodes are arranged at intervals, the first electrodes extend along a first direction, the first electrodes are disposed on the side of the doped conductive layer away from the substrate, and are electrically connected to the doped conductive layer; At least one conductive transport layer is located in the spacer region between two adjacent doped conductive layers along the second direction and is in contact with the side of the doped conductive layer; the conductive transport layer is one of doped amorphous silicon, doped polycrystalline silicon, or doped microcrystalline silicon material.

2. The solar cell according to claim 1, characterized in that, There are multiple conductive transport layers, and the multiple conductive transport layers are arranged at intervals along the first direction.

3. The solar cell according to claim 2, characterized in that, The array of multiple conductive transport layers includes: multiple columns of conductive transport layers spaced apart along a second direction, wherein multiple conductive transport layers in each column are spaced apart along a first direction, and at least one first electrode is present between two adjacent columns of conductive transport layers along the second direction, wherein the second direction is perpendicular to the first direction.

4. The solar cell according to claim 3, characterized in that, The conductive transport layer is present between all adjacent first electrodes.

5. The solar cell according to claim 3, characterized in that, One column of the conductive transport layers is staggered with an adjacent column of the conductive transport layers along the first direction.

6. The solar cell of claim 3, wherein Each of the conductive transport layers in one column corresponds one-to-one with each of the conductive transport layers in an adjacent column, and the corresponding two conductive transport layers are arranged at intervals along the second direction.

7. The solar cell of claim 3, wherein Also includes: A plurality of second electrodes are spaced apart, the second electrodes extending along the second direction and electrically connected to a plurality of first electrodes spaced apart along the second direction.

8. The solar cell of claim 7, wherein, In a column of conductive transport layers, there is at least one second electrode between two adjacent conductive transport layers.

9. The solar cell of claim 8, wherein, In a column of conductive transport layers, there are two second electrodes between two adjacent conductive transport layers.

10. The solar cell of claim 9, wherein, One column of conductive transport layers is staggered with an adjacent column of conductive transport layers along the first direction, and the two staggered conductive transport layers belonging to different columns are located on opposite sides of the second electrode.

11. The solar cell of claim 7, wherein, The substrate includes a peripheral region and a central region. The peripheral region is located outside the outermost second electrode. The central region is the area of ​​the substrate other than the peripheral region. The spacing of the conductive transport layers in the first direction in the peripheral region is smaller than the spacing of the conductive transport layers in the first direction in the central region.

12. The solar cell of claim 11, wherein, In each column of the conductive transport layers located in the central region, the spacing between each conductive transport layer in the first direction is equal.

13. The solar cell of claim 12, wherein, In each column of the conductive transport layer in the central region, the spacing between each conductive transport layer is 0.01mm to 20mm; in each column of the conductive transport layer in the peripheral region, the spacing between each conductive transport layer is 0.005mm to 18mm.

14. The solar cell according to claim 2 or 7, characterized in that, Also includes: A connecting portion is located between adjacent conductive transport layers spaced apart along the first direction and is in electrical contact with the sides of two adjacent conductive transport layers.

15. The solar cell of claim 1, wherein, The top surface of the conductive transport layer is lower than or flush with the top surface of the doped conductive layer.

16. The solar cell of claim 15, wherein, The top surface of the conductive transport layer has a light-trapping structure.

17. The solar cell of claim 1, wherein, The material of the conductive transport layer is the same as the material of the doped conductive layer.

18. The solar cell of claim 17, wherein, The material of the doped conductive layer is at least one of doped amorphous silicon, doped polycrystalline silicon, or doped microcrystalline silicon.

19. The solar cell of claim 1, wherein, Also includes: A first passivation layer, a portion of which covers the first surface of the substrate, and the remaining portion of which covers the top surface of the doped conductive layer and the conductive transport layer.

20. A photovoltaic module, characterized by, include: A battery string, wherein the battery string is formed by connecting a plurality of solar cells according to any one of claims 1 to 19; Encapsulation layer, the encapsulation layer being used to cover the surface of the battery string; A cover plate for covering the surface of the encapsulation layer away from the battery string.

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