Thermo-oxidative protective layer low-loss laser patterning method
By growing thermally oxidized silicon and amorphous silicon layers on the surface of crystalline silicon solar cells, and combining laser patterning and selective etching, the problems of laser damage and process compatibility are solved, enabling the manufacture of high-efficiency and low-cost crystalline silicon solar cells.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- YANGZHOU UNIV
- Filing Date
- 2026-04-29
- Publication Date
- 2026-07-28
AI Technical Summary
Existing laser patterning technology has problems in the manufacturing of crystalline silicon solar cells, such as laser damage, uneven contact area, silicon wafer thinning, and poor process compatibility, making it difficult to achieve efficient mass production and cost control.
The low-loss laser patterning method using a thermal-oxidative protective layer is adopted. By growing a thermal-oxidative silicon oxide layer and an amorphous silicon layer on the surface of the silicon wafer, and combining step-by-step laser patterning and selective etching processes, high-precision patterning is achieved while avoiding silicon wafer damage, and it is also compatible with multiple battery routes.
It improves the photoelectric conversion efficiency and reliability of batteries, reduces production costs and breakage rate, and is compatible with various battery manufacturing processes without large-scale modification.
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Figure CN122476705A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of crystalline silicon solar cell manufacturing technology, and in particular to a low-loss laser patterning method for a thermal-oxidative protective layer. Background Technology
[0002] In the fabrication of crystalline silicon solar cells, the preparation of textured diffusion and locally passivated contact structures are crucial steps in improving photoelectric conversion efficiency and reducing production costs. Currently, the mainstream laser patterning technology in the industry primarily uses lasers to directly apply to the textured surface of silicon wafers to achieve patterning. However, this type of technology generally suffers from the following unresolved problems, severely restricting the mass production quality and cost control of high-efficiency solar cells: 1. Direct laser irradiation of the textured silicon wafer surface can easily cause melting or lattice defects due to the light-trapping effect of the textured surface, thereby increasing the recombination rate of the silicon wafer surface, reducing the open-circuit voltage (Voc) and fill factor (FF) of the cell, and ultimately affecting the photoelectric conversion efficiency of the cell. Although existing technologies have attempted to reduce damage by using methods such as reduced-power lasers, the effect is limited and cannot maintain the patterning accuracy. 2. Conventional laser patterning combined with wet etching processes to address laser damage issues can lead to a significant height difference between the metal and non-metal contact areas. This height difference can easily cause silicon wafer breakage during subsequent cell encapsulation and module lamination, increasing the fragmentation rate and affecting the lamination adhesion, thus reducing the reliability and lifespan of the module. 3. Traditional wet etching processes remove redundant layers after laser processing, which involves etching the entire silicon wafer, resulting in additional wafer thinning. This contradicts the current industry trend of thinner silicon wafers (120μm and below), increasing not only silicon material loss but also the production cost of silicon wafers. 4. Existing laser patterning processes are mostly designed for specific battery routes (such as only BC or only TOPCon), making it difficult to be compatible with multiple generations of high-efficiency battery routes. If companies want to switch battery production types, they need to carry out large-scale transformation of production lines, which is costly, time-consuming, and not conducive to large-scale mass production and technology upgrades.
[0003] In view of the shortcomings of the existing technologies, there is currently no laser patterning technology in the industry that can simultaneously solve problems such as laser damage, contact area height difference, silicon wafer thinning and poor process compatibility. Therefore, the development of a laser patterning technology with low damage, no height difference, zero additional thinning and high compatibility has become an urgent need in the current solar cell manufacturing field.
[0004] The information disclosed in this background section is intended only to enhance the understanding of the general background of this disclosure and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0005] This invention provides a low-loss laser patterning method for thermo-oxidative protective layers, effectively solving the problems in the background art.
[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A low-loss laser patterning method for thermal-oxidative protective layers includes the following steps: S1 provides a textured crystalline silicon wafer. A thermally oxidized silicon oxide layer with a thickness of 5-20 nm is grown on the textured surface of the crystalline silicon wafer. Then, an amorphous silicon layer with a thickness of 20-30 nm is deposited on the surface of the thermally oxidized silicon oxide layer. More specifically, the 5-20 nm thermally oxidized silicon oxide layer is not only a low-loss buffer layer for laser processing, but also plays a role in blocking doping in subsequent diffusion processes. Its thickness has been verified by a large number of experiments. If the thickness is less than 5 nm, it cannot effectively buffer laser energy and will still cause damage to the silicon wafer. If the thickness is greater than 20 nm, on the one hand, the anti-reflection effect will cause additional laser damage. On the other hand, it will affect the deposition and bonding of the subsequent amorphous silicon layer and increase the transition of diffusion blocking, affecting the battery performance. The thickness of the 20-30nm amorphous silicon layer used as an acid-resistant mask needs to be precisely controlled. If it is too thin, the acid resistance will be insufficient and it will be partially dissolved during the HF etching process, affecting the patterning accuracy. If it is too thick, it will increase the difficulty of laser processing and increase the time and cost of subsequent low-temperature dilute alkali etching. S2 uses a laser to perform localized patterning on the amorphous silicon layer, defining the laser-processed area as the processed area and the unprocessed area as the unprocessed area, so that the amorphous silicon layer in the processed area undergoes film opening or oxidation modification. More specifically, the laser-processed area is defined as the area that needs to be re-diffused or retain the conventional passivated contact structure in the future, while the unprocessed area is the area that needs to be lightly diffused or without a passivated contact structure in the future. More specifically, amorphous silicon itself has an amorphous structure with short-range order and long-range disorder. It has an extremely high absorption rate for the photon energy of the green and ultraviolet lasers used in this process. In the ultra-short action time of nanoseconds / picoseconds, the captured photon energy can be rapidly converted into a localized instantaneous high-temperature field. The temperature can instantly break through the crystallization, melting and even vaporization threshold of amorphous silicon. On the one hand, the amorphous silicon in the processing area can be directly melted and vaporized by high-power laser to achieve physical film removal. On the other hand, the amorphous silicon can be oxidized with ambient oxygen at local high temperature by precisely controlled laser to generate silicon dioxide. At the same time, it causes the silicon-silicon covalent bond breakage and structural crystallization modification inside the amorphous silicon, completely destroying its original dense amorphous structure and acid corrosion resistance. Moreover, this effect is limited to the local area of laser irradiation, the heat-affected zone is extremely small and will not penetrate the thermal oxygen oxide silicon layer below the damage. S3 uses HF etching solution to selectively etch the laser-processed crystalline silicon wafer, removing the amorphous silicon layer and the underlying thermal oxidation silicon layer in the processed area, exposing the textured substrate of the crystalline silicon wafer, while the amorphous silicon layer and thermal oxidation silicon layer in the unprocessed area are completely preserved. More specifically, HF etching solution has the ability to complex and dissolve silicon dioxide. It can break silicon-oxygen bonds through chemical reaction and generate soluble fluorosilicic acid complexes. Therefore, during the etching process, the amorphous silicon layer that has been oxidized or structurally damaged in the processing area, along with the underlying thermo-oxidized silicon dioxide layer, will be dissolved and removed by HF etching solution. The amorphous silicon layer in the unprocessed area will protect the underlying thermo-oxidized silicon dioxide layer from being etched. Finally, only the textured silicon wafer substrate is exposed in the laser-preset processing area, completing the transfer of the patterned structure. S4 performs selective removal processing on the crystalline silicon wafer after HF etching, removing only the amorphous silicon layer in the unprocessed area while completely preserving the thermally oxidized silicon layer in the unprocessed area. More specifically, dilute alkali has a high etching efficiency for amorphous silicon, but has almost no corrosive effect on the thermally oxidized silicon layer. This step will remove the intact amorphous silicon layer remaining in the unprocessed area without damaging the thermally oxidized silicon layer below the area.
[0007] This invention utilizes a dual-layer protection system constructed from a thermally oxidized silicon layer and an amorphous silicon layer, combined with step-by-step laser patterning and selective etching processes. This achieves high-precision patterning of the silicon wafer surface while effectively avoiding structural damage caused by direct laser irradiation. It also eliminates the etching consumption of the silicon wafer body in traditional processes, preventing significant structural height differences on the silicon wafer surface. This not only significantly improves product yield but also has strong process adaptability, compatible with the fabrication processes of various mainstream batteries, allowing for production switchover without large-scale modifications to the production line.
[0008] Furthermore, the method for preparing the thermally oxidized silicon layer is as follows: using dry oxygen thermal oxidation or wet oxygen thermal oxidation, the thermally oxidized silicon layer is grown on the textured surface of the crystalline silicon wafer at a temperature of 800~1000℃. More specifically, this step is carried out in a thermal oxidation furnace, and the oxidation time is adjusted according to the target thickness.
[0009] Furthermore, the amorphous silicon layer is prepared by depositing an amorphous silicon layer on the surface of a thermally oxidized silicon layer at a temperature of 400~600℃ using any one of low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or plasma-enhanced chemical vapor deposition. More specifically, the above preparation method can be flexibly adapted to the mature deposition equipment of existing mainstream production lines in the photovoltaic industry, and can be implemented without large-scale production line modification. The deposition temperature range of 400~600℃ can control the density and film quality of the amorphous silicon layer, forming an amorphous silicon film with excellent adhesion, uniform and dense structure and no pinhole peeling defects on the surface of the thermally oxidized silicon layer, which fully ensures its performance stability as an acid-resistant mask. At the same time, the three deposition methods can be flexibly matched with the process temperature and film formation requirements of different battery technology routes, thus broadening the process adaptability range of the present invention.
[0010] Furthermore, in step S2, the laser is any one of a green nanosecond laser, a green picosecond laser, or an ultraviolet picosecond laser.
[0011] More specifically, green nanosecond, green picosecond, and ultraviolet picosecond lasers can all achieve localized film opening or oxidation of amorphous silicon layers. Among them, green picosecond lasers have the smallest heat-affected zone and the highest processing precision, making them suitable for high-precision patterning requirements; ultraviolet picosecond lasers are suitable for fine line patterning; and green nanosecond lasers are suitable for mass production. Enterprises can choose flexibly according to their production needs.
[0012] Furthermore, the laser processing power is 5~20W, and the scanning speed is 10000~50000mm / s; More specifically, the above parameters can ensure that the amorphous silicon layer can achieve sufficient film opening or oxidation modification, ensuring the accuracy and integrity of patterning, and can also effectively control the thermally affected range of the laser.
[0013] Furthermore, the etching temperature of the HF etching solution is 20~30℃, and the etching time is 10~30s; The concentration of HF etching solution is 1-3%.
[0014] The above parameters can ensure that the amorphous silicon layer and the thermally oxidized silicon layer in the laser processing area are completely and uniformly removed, exposing the textured silicon wafer substrate, and can also effectively avoid damage to the silicon wafer body and additional thinning caused by over-etching.
[0015] Furthermore, the selective removal process is a low-temperature dilute alkaline etching process, with an etching temperature of 40~60℃ and an etching time of 20~40s; More specifically, by using the above parameters, the difference in etching rates between dilute alkali and thermal oxidation silicon can be fully utilized, which can not only completely remove the intact amorphous silicon layer remaining in the unprocessed area, but also avoid damaging the underlying thermal oxidation silicon layer.
[0016] Furthermore, the low-temperature dilute alkaline etching process uses a sodium hydroxide solution with a concentration of 0.3~0.8% and a temperature of 42~52℃. Etching with a dilute sodium hydroxide solution of the above concentration and temperature can gently and selectively remove the amorphous silicon layer with almost no erosion of the underlying thermally oxidized silicon layer.
[0017] Furthermore, the crystalline silicon wafer is either a P-type crystalline silicon wafer or an N-type crystalline silicon wafer.
[0018] Further, after step S4 is completed, the following processing is performed on one of the crystalline silicon wafers: (1) Phosphorus diffusion or boron diffusion treatment is performed on the crystalline silicon wafer to form a highly doped region in the processed area and a low doped region in the unprocessed area; More specifically, this processing method is applicable to structures such as selective emitters and localized back fields. It involves phosphorus or boron diffusion processes on silicon wafers that have undergone the above steps. In this process, the laser-processed area (the area with the exposed substrate) can achieve heavy diffusion to form a highly doped region; in the unprocessed area (the area with the thermally oxidized silicon layer), the thermally oxidized silicon layer can block the diffusion of dopants, achieving light diffusion to form a low-doped region. Through this method, patterned diffusion with a textured surface can be achieved, improving the photoelectric conversion efficiency of the battery. (2) Prepared into TOPCon, HJT, PERC or IBC batteries (2) A tunneling oxide layer and a doped polycrystalline silicon layer are sequentially deposited on the surface of a crystalline silicon wafer to prepare the passivation contact structure of the TOPCon cell; More specifically, the TOPCon cell fabrication method is as follows: on the silicon wafer surface treated by the above steps, a tunneling oxide layer and a doped polycrystalline silicon layer are deposited to complete the fabrication of the conventional TOPCon passivation contact structure; wherein, the laser-processed area forms a conventional tunneling oxide layer + doped polycrystalline silicon passivation contact structure; the un-laser-processed area is covered with a layer of doped polycrystalline silicon or amorphous silicon on a 5-20nm thermally oxidized silicon oxide layer.
[0019] The method for fabricating HJT cells is as follows: On the surface of a silicon wafer processed by the above steps, an intrinsic amorphous silicon layer, a doped amorphous silicon layer, and a transparent conductive layer are deposited to complete the fabrication of a conventional HJT passivation contact structure; wherein, the laser-processed area forms a conventional intrinsic amorphous silicon + doped amorphous silicon passivation contact structure; the unprocessed area is covered with a layer of doped amorphous silicon on a 5-20nm thermally oxidized silicon layer.
[0020] Furthermore, after completing the above corresponding processing, subsequent pattern adjustments can be made: for the unprocessed areas, laser film opening or oxidation is used again, combined with HF acid etching, to remove the doped polycrystalline / amorphous silicon layer and the underlying 5~20nm thermal oxidation silicon layer in the area, and the structure can be flexibly adjusted according to the battery design requirements.
[0021] Furthermore, after completing all the above process steps, metallization, annealing, passivation and other subsequent steps are completed according to the conventional preparation process of solar cells, and finally a high-efficiency crystalline silicon solar cell is prepared.
[0022] Furthermore, texturing also includes steps of cleaning and drying the crystalline silicon wafer to remove surface impurities and oxide layers.
[0023] The technical solution of this invention can achieve the following technical effects: (1) No additional chemical or physical mask is required. By utilizing the acid resistance of the amorphous silicon layer and the selective etching characteristics after laser processing, the precise definition of the pattern can be achieved, simplifying the process flow, reducing the cost of mask consumables, and improving the patterning accuracy. (2) The same process flow can be seamlessly adapted to mainstream high-efficiency battery routes such as TOPCon, HJT, PERC, and IBC. There is no need to make large-scale modifications to the production line. Only the laser patterning parameters and subsequent functional structure preparation steps need to be adjusted according to the battery type, which reduces the investment in production line modification and production switching costs for enterprises. (3) The 5~20nm thermal oxidation silicon layer can effectively buffer laser energy and reduce the lattice damage and heat-affected zone of the laser on the textured silicon wafer. According to experimental tests, the open circuit voltage (Voc), photoelectric conversion efficiency and fill factor (FF) of the battery using the present invention can be improved, which is significantly better than the existing laser patterning technology. (4) The final battery surface has high flatness and no obvious height difference between the metal contact area and the non-metal contact area, which can reduce the silicon wafer breakage rate, improve the bonding during the module lamination process, reduce lamination bubbles, delamination and other defects, and improve the reliability and service life of the module. (5) The entire process does not involve etching of the silicon wafer itself, achieving zero additional thinning of the silicon wafer, which can perfectly adapt to thin silicon wafers of 120μm and below; at the same time, it reduces silicon material loss and lowers silicon material cost, and long-term large-scale mass production can significantly reduce the production cost of enterprises. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 A flowchart illustrating a low-loss laser patterning method for thermal-oxidative protective layers; Figure 2 This is a schematic diagram showing the structural changes of a crystalline silicon wafer processed using the technology of this invention at each process step; Figure 3 Image a shows the morphology of the textured surface after laser processing without the thermal oxidation silicon layer; image b shows the morphology of the textured surface after laser processing with a 5-20 nm thermal oxidation silicon layer. Figure 4 This figure shows the effect of thermal oxidation of silicon layer on the minority carrier lifetime of textured surface. Detailed Implementation
[0026] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.
[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0028] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Example 1:
[0029] This embodiment provides a method for fabricating TOPCon solar cells. Some steps employ the low-loss laser patterning method for the thermal-oxidative protective layer of this invention. The specific steps are as follows: (1) Select an N-type monocrystalline silicon wafer with a thickness of 120μm and perform texturing using a conventional alkaline texturing process to form a pyramid textured surface (pyramid size 2~5μm) on the silicon wafer surface; after texturing, use SC1 (ammonia water-hydrogen peroxide-deionized water) and SC2 (hydrochloric acid-hydrogen peroxide-deionized water) cleaning solutions in sequence to remove surface impurities and natural oxide layer, and then dry for later use; (2) Preparation of thermal oxidation silicon layer: The dried silicon wafer is placed in a thermal oxidation furnace and oxidized at 850°C for 30 minutes using a dry oxygen thermal oxidation method to grow a 10nm thick thermal oxidation silicon (SiO2) layer on the textured surface; after oxidation, it is naturally cooled to room temperature. (3) Mask layer deposition: LPCVD is used to deposit an amorphous silicon layer with a thickness of 25nm on the surface of the thermally oxidized silicon layer; the deposition temperature is 550℃, the deposition pressure is 10Pa, and the deposition time is 20min to ensure that the amorphous silicon layer and the thermally oxidized silicon layer are tightly bonded and free from defects such as peeling and pinholes. (4) Laser patterning: Green picosecond laser with a power of 12W and a scanning speed of 30000mm / s was selected. According to the design requirements of local passivation contact of TOPCon battery, the amorphous silicon layer was locally oxidized to define the metal contact area (laser processing area) and the non-contact area (unprocessed area). The laser processing pattern is strip-shaped with a width of 100μm and a spacing of 500μm. (5) HF selective etching: The laser-patterned silicon wafer is placed in a 2% HF etching solution and etched for 20 seconds at 25°C. The amorphous silicon layer in the laser-processed area has been oxidized to silicon dioxide by laser irradiation and can be completely dissolved by the HF etching solution. At the same time, the 10nm thermal oxidation silicon layer below the area is also etched away, finally exposing the clean silicon wafer textured substrate. In the area that has not been laser-processed, the amorphous silicon layer has excellent resistance to HF acid and has no significant loss under this etching condition. It can completely cover the surface of the thermal oxidation silicon layer, thereby achieving precise patterning etching. (6) Low-temperature dilute alkaline etching: The silicon wafer after HF etching is placed in a 0.5% NaOH dilute alkaline etching solution and etched at 50°C for 30s; the amorphous silicon layer in the unprocessed area is removed, and the 10nm thermal oxidation silicon layer in the area is retained; after etching, it is rinsed with deionized water and dried for later use. (7) TOPCon passivation contact preparation: A 1.2 nm thick tunneling oxide layer (SiO2) is deposited on the silicon wafer surface using PECVD, and then an 80 nm thick phosphorus-doped polycrystalline silicon layer is deposited using LPCVD; wherein, the laser-processed area (metal contact area) forms a conventional tunneling oxide layer + phosphorus-doped polycrystalline silicon passivation contact structure; the unprocessed area (non-contact area) forms a special passivation contact structure of a 10 nm thermally oxidized silicon oxide layer + phosphorus-doped polycrystalline silicon layer; (8) Post-patterning: Using a picosecond ultraviolet laser, the phosphorus-doped polysilicon layer in the unprocessed area is locally opened, and then placed in a 2% HF etching solution for 15 seconds to remove the phosphorus-doped polysilicon layer and the underlying 10nm thermal oxidation silicon layer, forming a flat non-contact area.
[0030] (9) Subsequent processes: Silver electrodes are prepared in the laser processing area using conventional photolithography and metallization processes; then annealing is performed (temperature 800℃, time 30min) to complete passivation and metal contact; finally, TOPCon solar cells are prepared.
[0031] Using a solar cell tester, the photoelectric performance and yield of the TOPCon solar cell prepared in this embodiment and the comparative solar cell prepared using traditional laser patterning technology were tested. The test results showed that the solar cell prepared in this embodiment had an increased open-circuit voltage (Voc) of 6mV, an increased fill factor (FF) of 1.2%, and an increased photoelectric conversion efficiency of 0.35%. The patterning processing accuracy error was controlled within ±3μm. There was no obvious height difference on the surface of the solar cell, and the fragmentation rate was reduced by 22%. Example 2:
[0032] This embodiment provides a method for fabricating crystalline silicon solar cells. Some steps employ the low-loss laser patterning method for the thermo-oxidative protective layer of this invention. The specific steps are as follows: (1) Substrate preparation: P-type single crystal silicon wafers with a thickness of 110μm were selected and texturing was carried out using conventional acid texturing process to form a pyramid textured surface on the silicon wafer; after texturing, the wafers were cleaned and dried for later use. (2) Preparation of thermal oxidation silicon layer: The thermal oxidation method was used to oxidize at 900℃ for 25 min to grow a thermal oxidation silicon layer with a thickness of 8 nm on the textured surface; it was then cooled to room temperature for later use. (3) Mask layer deposition: A 20 nm thick amorphous silicon layer is deposited on the surface of the thermally oxidized silicon layer using PECVD; the deposition temperature is 450 °C, the deposition pressure is 50 Pa, and the deposition time is 15 min. (4) Laser patterning: Ultraviolet picosecond laser with a power of 8W and a scanning speed of 40000mm / s is selected. The re-diffusion region (laser processing region, corresponding to the metal contact area of the battery emitter) is defined. The laser processing pattern is dot-shaped with a diameter of 80μm and a spacing of 400μm. (5) HF selective etching: The laser-patterned silicon wafer is placed in a 1.5% HF etching solution and etched for 15s at a constant temperature of 23°C. In this step, the amorphous silicon layer in the laser-processed area has been oxidized to silicon dioxide by laser irradiation and loses its resistance to HF acid. It can be completely dissolved by the etching solution. At the same time, the 8nm thermal oxidation silicon layer below the area is also etched away, finally exposing the clean textured silicon wafer substrate. In the area that has not been laser-processed, the amorphous silicon layer has excellent resistance to HF acid. Under this etching condition, there is no significant loss, and it can completely cover the surface of the thermal oxidation silicon layer, thereby achieving precise selective patterning etching. (6) Low-temperature alkaline etching: Immerse in a 0.4% NaOH dilute alkaline etching solution and etch for 25 seconds at 45°C; remove the amorphous silicon layer in the unprocessed area and retain an 8nm thermal oxidation silicon layer; clean and dry for later use.
[0033] (7) Patterned diffusion: The silicon wafer is placed in a diffusion furnace and a phosphorus diffusion process is adopted. The diffusion temperature is 850℃ and the diffusion time is 40min. Among them, the laser processing area (exposed thermal oxidation silicon layer) is re-diffused with a phosphorus doping concentration of 1×10 20 cm -3 Light diffusion is achieved in the unprocessed area (where the thermally oxidized silicon layer is retained), with a phosphorus doping concentration of 5 × 10⁻⁶. 18 cm -3 This forms a selective emitter structure.
[0034] (8) Subsequent processes: Remove the phosphosilicate glass from the surface of the silicon wafer, and then perform conventional processes such as passivation, metallization, and annealing to prepare crystalline silicon solar cells.
[0035] Using a solar cell tester, the selective emitter solar cell prepared in this embodiment was compared with that prepared by a conventional process. The results showed that the open-circuit voltage of the solar cell prepared in this embodiment was increased by 5mV, the fill factor was increased by 1.0%, the photoelectric conversion efficiency was increased by 0.3%, the patterning accuracy was within ±4μm, and the fragmentation rate was reduced by 20%. Example 3:
[0036] This embodiment provides a method for fabricating TOPCon solar cells. Some steps employ the low-loss laser patterning method for the thermal-oxidative protective layer of this invention. The specific steps are as follows: (1) Substrate preparation: Select an N-type single crystal silicon wafer with a thickness of 120μm, and perform texturing using a conventional alkaline texturing process to form a pyramid textured surface on the silicon wafer; clean and dry after texturing for later use. (2) Preparation of thermal oxidation silicon layer: The thermal oxidation method was used to oxidize at 860℃ for 28 min to grow a 10 nm thick thermal oxidation silicon layer on the textured surface; it was then cooled to room temperature for later use. (3) Mask layer deposition: An amorphous silicon layer with a thickness of 25 nm was deposited on the surface of the thermally oxidized silicon layer using LPCVD; the deposition temperature was 520℃, the deposition pressure was 12 Pa, and the deposition time was 22 min. (4) Laser patterning: Green nanosecond laser with a power of 10W and a scanning speed of 25000mm / s is selected. The re-diffusion region (laser processing region, corresponding to the metal contact area of the battery emitter) is defined. The laser processing pattern is dotted with a line width of 100μm and a line spacing of 500μm. Control sample settings: A control sample was set up synchronously. Except for omitting the above-mentioned thermal oxidation silicon layer preparation steps, the process parameters, equipment models and environmental conditions of substrate preparation, mask layer deposition and laser patterning were completely consistent with those of this embodiment. It was used to verify the low-loss effect of the thermal oxidation silicon layer of the present invention. (5) HF selective etching: The silicon wafer of this embodiment and the silicon wafer of the comparative example after laser patterning are placed in HF etching solution with a mass fraction of 2% and etched for 20s at a constant temperature of 25°C. In this step, the amorphous silicon layer in the laser-processed area has been oxidized to silicon dioxide by laser irradiation and loses its resistance to HF acid. It can be completely dissolved by the etching solution. At the same time, the 10nm thermal oxidation silicon layer below the area is also etched away, and finally the clean silicon wafer textured substrate is exposed. In the area that has not been laser-processed, the amorphous silicon layer has excellent resistance to HF acid. Under this etching condition, there is no significant loss and it can completely cover the surface of the thermal oxidation silicon layer, thereby achieving precise selective patterning etching. (6) Low-temperature alkaline etching: Immerse in a 0.5% NaOH dilute alkaline etching solution and etch for 30 seconds at 50°C; remove the amorphous silicon layer in the unprocessed area and retain a 10nm thermal oxidation silicon layer; clean and dry for later use.
[0037] (7) TOPCon passivation contact structure preparation: A 1.2 nm thick tunneling oxide layer is deposited on the entire surface of the silicon wafer using PECVD, and then an 80 nm thick phosphorus-doped polycrystalline silicon layer is deposited using LPCVD; In the laser-processed metal contact area, the tunneling oxide layer directly contacts the exposed textured silicon wafer substrate to form a conventional tunneling oxide layer + phosphorus-doped polycrystalline silicon passivation contact structure; In the unprocessed passivation area, the tunneling oxide layer is deposited on the surface of the retained 10 nm thermally oxidized silicon oxide layer to form a composite passivation structure of 10 nm thermally oxidized silicon oxide layer + phosphorus-doped polycrystalline silicon layer. (8) Post-patterning: Ultraviolet picosecond laser is used to perform local film opening treatment on the phosphorus-doped polycrystalline silicon layer in the unprocessed passivation area. Then, the silicon wafer is placed in 2% HF etching solution for 15s to remove the phosphorus-doped polycrystalline silicon layer and the bottom 10nm thermal oxidation silicon layer in the corresponding area, forming a flat non-contact area to meet the battery structure design requirements. (9) Subsequent processes: Following the conventional preparation process of N-type TOPCon solar cells, the back passivation, front antireflection film deposition, screen printing of metal electrodes and annealing are completed in sequence to finally prepare high-efficiency TOPCon solar cells.
[0038] The TOPCon solar cell prepared in this embodiment showed a 0.38% improvement in photoelectric conversion efficiency, a 7mV improvement in open-circuit voltage, and a 1.3% improvement in fill factor compared to the comparative example. The silicon wafer was not thinned further, and the silicon material loss was reduced by 6% compared to the traditional process.
[0039] The surface morphology of the textured silicon wafers after laser processing in this embodiment and the comparative example was characterized using scanning electron microscopy (SEM). The results are as follows: Figure 3 As shown; where Figure 3a shows the morphology of the textured surface after laser processing, which is a comparative example. It can be seen that the textured pyramid structure exhibits obvious melting and collapse, lattice damage, and a large number of pits and defects caused by laser ablation. Figure 3 b shows the morphology of the textured surface after laser processing in this embodiment. The textured pyramid structure is intact and undamaged, with no obvious melting marks or lattice defects, which fully verifies the buffering and protective effect of the 5~20nm thermal oxidation silicon layer of this invention on laser processing, and can effectively avoid direct damage to the textured surface of the silicon wafer by the laser.
[0040] Microwave photoconductivity attenuation method (μ-PCD) was used, with a concentration of 0.08-0.7 J / cm. 2 Under a laser energy density gradient, the minority carrier lifetime of textured silicon wafers with and without thermally oxidized silicon oxide layers in this embodiment and the comparative example were tested. Using the minority carrier lifetime of the unprocessed, un-laser-processed textured silicon wafer as a baseline of 100%, the minority carrier lifetime retention rate under different laser energy densities was calculated. The test results are as follows: Figure 4 As shown, the results indicate that, within the full range of tested laser energy densities, silicon wafers with a thermally oxidized silicon layer (i.e., a protective film) exhibit significantly lower minority carrier lifetime loss compared to silicon wafers without a protective layer. With increasing laser energy density, the minority carrier lifetime of unprotected silicon wafers drops drastically, while silicon wafers with a thermally oxidized silicon layer maintain a high minority carrier lifetime retention rate. This fully demonstrates that the thermally oxidized silicon layer of this invention can effectively reduce lattice damage to silicon wafers caused by laser processing, significantly reduce the surface recombination rate of silicon wafers, and provide a foundation for improving the photoelectric conversion efficiency of batteries.
[0041] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of the application as defined herein, and are to be considered as covering any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from its scope. Thus, if such modifications and modifications fall within the scope of this application and its equivalents, this application intends to include such modifications and modifications.
Claims
1. A low-loss laser patterning method for a thermo-oxidative protective layer, characterized in that, Includes the following steps: S1 provides a texturized crystalline silicon wafer, wherein a thermally oxidized silicon layer with a thickness of 5-20 nm is grown on the texturized surface of the crystalline silicon wafer, and then an amorphous silicon layer with a thickness of 20-30 nm is deposited on the surface of the thermally oxidized silicon layer. S2 uses a laser to perform localized patterning on the amorphous silicon layer, defining the laser-processed area as the processed area and the unprocessed area as the unprocessed area, thereby causing the amorphous silicon layer in the processed area to undergo film opening or oxidation modification. S3 uses HF etching solution to selectively etch the laser-processed crystalline silicon wafer to remove the amorphous silicon layer and the underlying thermal oxidation silicon layer in the processed area, exposing the textured substrate of the crystalline silicon wafer, while the amorphous silicon layer and thermal oxidation silicon layer in the unprocessed area are completely preserved. S4 performs selective removal processing on the crystalline silicon wafer after HF etching, removing only the amorphous silicon layer in the unprocessed area while completely retaining the thermally oxidized silicon layer in the unprocessed area.
2. The low-loss laser patterning method for thermal-oxidative protective layers according to claim 1, characterized in that, The method for preparing the thermo-oxidized silicon layer is as follows: the thermo-oxidized silicon layer is grown on the textured surface of the crystalline silicon wafer at a temperature of 800~1000℃ using dry or wet thermo-oxidation.
3. The low-loss laser patterning method for thermal-oxidative protective layers according to claim 1, characterized in that, The amorphous silicon layer is prepared by depositing the amorphous silicon layer on the surface of the thermally oxidized silicon layer at a temperature of 400~600℃ using any one of low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or plasma-enhanced chemical vapor deposition.
4. The low-loss laser patterning method for thermal-oxidative protective layers according to claim 1, characterized in that, In step S2, the laser is any one of a green nanosecond laser, a green picosecond laser, or an ultraviolet picosecond laser.
5. The low-loss laser patterning method for the thermo-oxidative protective layer according to claim 4, characterized in that, The laser has a processing power of 5~20W and a scanning speed of 10000~50000mm / s.
6. The low-loss laser patterning method for thermal-oxidative protective layers according to claim 1, characterized in that, The etching temperature of the HF etching solution is 20~30℃, and the etching time is 10~30s; The concentration of the HF etching solution is 1-3%.
7. The low-loss laser patterning method for thermal-oxidative protective layers according to claim 1, characterized in that, The selective removal process is a low-temperature dilute alkali etching process, with an etching temperature of 40~60℃ and an etching time of 20~40s.
8. The low-loss laser patterning method for thermal-oxidative protective layers according to claim 7, characterized in that, The low-temperature dilute alkali etching process uses a sodium hydroxide solution with a concentration of 0.3-0.8% and a temperature of 42-52°C.
9. The low-loss laser patterning method for thermal-oxidative protective layers according to claim 1, characterized in that, The crystalline silicon wafer is a P-type crystalline silicon wafer or an N-type crystalline silicon wafer.
10. The low-loss laser patterning method for thermal-oxidative protective layers according to claim 1, characterized in that, After step S4 is completed, one of the crystalline silicon wafers is selected to undergo the following processing: (1) The crystalline silicon wafer is subjected to phosphorus diffusion or boron diffusion treatment to form a highly doped region in the processed region and a low doped region in the unprocessed region; (2) Prepared into TOPCon, HJT, PERC or IBC batteries.