Preparation method of solar cell and solar cell
By preparing silicon slurry layers with different doping types on the back side of a silicon substrate and converting them into polycrystalline silicon layers, the problems of complex and high cost in TBC cell fabrication processes have been solved, enabling the production of high-efficiency and low-cost solar cells.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 扬州阿特斯太阳能电池有限公司
- Filing Date
- 2024-10-30
- Publication Date
- 2026-05-01
AI Technical Summary
The existing TBC battery manufacturing process is difficult and costly, and cannot be simplified.
A tunneling layer is prepared on the back side of a silicon substrate, and N-type silicon paste layers and P-type silicon paste layers with different doping types are prepared on the back side of the substrate respectively. The layers are then converted into N-type doped polycrystalline silicon layers and P-type doped polycrystalline silicon layers by annealing to form a selective emitter, thus simplifying the process steps.
It reduces the production cost of solar cells, increases open-circuit voltage and fill factor, enhances cell efficiency, avoids metal electrode burn-through, and simplifies the process.
Smart Images
Figure CN121968765A_ABST
Abstract
Description
A method for preparing a solar cell and the solar cell Technical Field
[0001] This invention relates to the field of photovoltaic cells, and in particular to a method for preparing a solar cell and the solar cell itself. Background Technology
[0002] Back contact (BC) cells are a general term for various types of crystalline silicon solar cells with back contact structures.
[0003] The BC battery has spaced P-regions and N-regions on its back side, and a first electrode and a second electrode are formed on these regions, respectively. Both the positive and negative electrodes of the BC battery are located on the back side, eliminating the need for metal grid lines on the front side to block light, thus avoiding light loss due to metal electrode shading. This significantly improves the battery's optical absorption and achieves good short-circuit current. Furthermore, the BC battery eliminates the front surface emitter, reducing front surface recombination losses.
[0004] TOPCon solar cells are constructed by depositing a 1-2 nm tunneling layer on the back of a silicon substrate, followed by a layer of doped polycrystalline silicon. These two layers together form a passivation contact structure, providing excellent interface passivation for the back of the silicon wafer. The ultrathin oxide layer allows electrons to tunnel into the polycrystalline silicon layer while blocking hole transport, reducing recombination current. The lateral transport properties of the doped polycrystalline silicon layer reduce series resistance. These two characteristics together improve the open-circuit voltage, fill factor, and conversion efficiency of the solar cell.
[0005] While TBC batteries incorporate the advantages of both TOPCon and BC batteries, their fabrication process requires repeated laser processing, etching, and mask technology, which significantly increases the complexity of the process and production costs. Summary of the Invention
[0006] The purpose of this invention is to provide a method for preparing a solar cell and a solar cell in order to overcome the shortcomings of the prior art, thereby reducing the difficulty and cost of the process.
[0007] To achieve one of the above objectives, the present invention provides a method for preparing a solar cell, comprising the following steps:
[0008] A tunneling layer is fabricated on the back side of a silicon substrate;
[0009] An N-type silicon slurry layer and a P-type silicon slurry layer are respectively prepared in a first region on the back side of the tunneling layer and in a second region spaced apart from the first region;
[0010] Annealing converts the N-type silicon slurry layer and the P-type silicon slurry layer into N-type doped polycrystalline silicon layer and P-type doped polycrystalline silicon layer, respectively.
[0011] A first electrode and a second electrode are formed on the back side of the N-type doped polycrystalline silicon layer and the P-type doped polycrystalline silicon layer, respectively.
[0012] As a further improvement of one embodiment of the present invention, a first silicon paste is prepared in the gate line region of the first region to form a first N-type silicon paste layer, and a second silicon paste is prepared in the non-gate line region of the first region to form a second N-type silicon paste layer, wherein the doping concentration of the N-type dopant source in the first silicon paste is greater than the doping concentration of the N-type dopant source in the second silicon paste.
[0013] And / or, a third silicon paste is prepared in the gate region of the second region to form a first P-type silicon paste layer, and a fourth silicon paste is prepared in the non-gate region of the second region to form a second P-type silicon paste layer, wherein the doping concentration of the P-type dopant source in the third silicon paste is greater than the doping concentration of the P-type dopant source in the fourth silicon paste.
[0014] As a further improvement of one embodiment of the present invention, the first N-type silicon slurry layer is doped with phosphorus, and the phosphorus doping content is 5wt% to 8wt%.
[0015] And / or, the second N-type silicon slurry layer is doped with phosphorus, and the phosphorus doping content is 1wt% to 4wt%;
[0016] And / or, the first P-type silicon slurry layer is doped with boron, and the boron doping content is 5wt% to 8wt%;
[0017] And / or, the second P-type silicon slurry layer is doped with boron, with a boron doping content of 1wt% to 4wt%.
[0018] As a further improvement of one embodiment of the present invention, the doping concentration of the N-type doped polysilicon layer located in the gate region is 1E21 atoms / cm. 3 ~5E21atoms / cm 3 ;
[0019] And / or, the doping concentration of the N-type doped polysilicon layer located in the non-gate region is 3E20 atoms / cm. 3 ~8E20atoms / cm 3 ;
[0020] And / or, the doping concentration of the P-type doped polysilicon layer located in the gate region is 1E19 atoms / cm². 3 ~5E19 atoms / cm 3 ;
[0021] And / or, the doping concentration of the P-type doped polysilicon layer located in the non-gate region is 3E18 atoms / cm.3 ~8E18atoms / cm 3 .
[0022] As a further improvement of one embodiment of the present invention, the thickness of the N-type doped polysilicon layer located in the gate line region is greater than the thickness of the N-type doped polysilicon layer located in the non-gate line region.
[0023] And / or, the thickness of the P-type doped polysilicon layer located in the gate region is greater than the thickness of the P-type doped polysilicon layer located in the non-gate region;
[0024] And / or, the N-type doped polysilicon layer located in the gate line region and the P-type doped polysilicon layer located in the gate line region have the same thickness;
[0025] And / or, the N-type doped polysilicon layer located in the non-gate region and the P-type doped polysilicon layer located in the non-gate region have the same thickness.
[0026] As a further improvement of one embodiment of the present invention, the thickness of the N-type doped polysilicon layer in the gate region is 1.1 to 3.1 times the thickness of the N-type doped polysilicon layer in the non-gate region;
[0027] And / or, the thickness of the P-type doped polysilicon layer in the gate region is 1.1 to 3.1 times the thickness of the P-type doped polysilicon layer in the non-gate region.
[0028] As a further improvement of one embodiment of the present invention, the tunneling layer is a silicon oxide layer or a silicon carbide layer, and the thickness of the tunneling layer is 0.5 nm to 2 nm.
[0029] As a further improvement of one embodiment of the present invention, the first region and the second region are separated by an interval, the width of which is 1-500 μm.
[0030] As a further improvement of one embodiment of the present invention, the method for preparing a solar cell further includes the following steps: before forming the first electrode and the second electrode, depositing a passivation layer and / or a reflective layer on the back side, or the front side, or both sides.
[0031] To achieve one of the above objectives, the present invention provides a solar cell prepared by the aforementioned preparation method.
[0032] Compared with existing technologies, this invention prepares first N-type silicon slurry layers and second N-type silicon slurry layers with different doping types in the first and second regions of a silicon substrate, respectively, and then completes the preparation of N-type doped polycrystalline silicon layers and P-type doped polycrystalline silicon layers through annealing. A spacer region is naturally formed between the first and second regions, eliminating the need for multiple masking processes and laser grooving. This simplifies the fabrication process of solar cells, reduces the production cost of solar cells, and facilitates the adjustment of parameters such as doping concentration and thickness in the grid and non-grid regions.
[0033] In both N-type and P-type doped polysilicon layers, the doping concentration in the gate region is higher than that in the non-gate region, forming an SE structure in both regions. This improves the cell's open-circuit voltage and fill factor. The gate region forms a highly doped polysilicon layer, reducing the contact resistance between the metal electrode and the doped polysilicon layer, and further enhancing the fill factor. The non-gate region consists of a less doped polysilicon layer, reducing Auger recombination and increasing the open-circuit voltage.
[0034] In both N-type and P-type doped polysilicon layers, the thickness of the gate region is greater than that of the non-gate region, which prevents the metal electrode from burning through during sintering, thus ensuring the efficiency and yield of the battery. The thin doped polysilicon layer in the non-gate region reduces the parasitic absorption of long-wavelength light by the doped polysilicon layer, increases the short-circuit current of the battery, and improves the battery performance. Attached Figure Description
[0035] Figure 1 is a flowchart of a solar cell fabrication method in this embodiment;
[0036] Figure 2 shows the structure of a silicon substrate after double-sided texturing in the fabrication method of a solar cell;
[0037] Figure 3 shows the structure of the back side of the silicon substrate after polishing in the fabrication method of solar cells;
[0038] Figure 4 shows the structure after a tunneling layer is prepared on the back side of a silicon substrate in the fabrication method of a solar cell.
[0039] Figure 5 shows the structure after the first N-type silicon slurry layer and the second N-type silicon slurry layer are prepared on the back side in the method of preparing a solar cell;
[0040] Figure 6 shows the structure of a solar cell after annealing in the fabrication process.
[0041] Figure 7 shows the structure of a solar cell after double-sided coating in the fabrication method.
[0042] Figure 8 is a schematic diagram of the structure of a solar cell obtained by the solar cell preparation method of the present invention.
[0043] Figure label:
[0044] 10. Silicon substrate; 20. Tunneling layer; 31. N-type silicon slurry layer; 32. P-type silicon slurry layer; 41. N-type doped polycrystalline silicon layer; 42. P-type doped polycrystalline silicon layer; 50. Passivation film; 60. Antireflection film; 71. First electrode; 72. Second electrode. Detailed Implementation
[0045] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0046] Please refer to Figures 1-8. The present invention aims to provide a method for preparing solar cells, which simplifies the process steps of TBC cells and reduces production costs.
[0047] The method for preparing the solar cell includes at least the following steps:
[0048] S1 forms a tunneling layer 20 on the back side of the silicon substrate 10;
[0049] S2 prepares an N-type silicon paste layer 31 and a P-type silicon paste layer 32 in a first region on the back side of the tunneling layer 20 and a second region spaced apart from the first region, respectively, while forming an interval region between the first region and the second region;
[0050] S3 annealing converts the N-type silicon slurry layer 31 and the P-type silicon slurry layer 32 into N-type doped polycrystalline silicon layer 41 and P-type doped polycrystalline silicon layer 42, respectively.
[0051] S4 forms a first electrode 71 and a second electrode 72 on the back sides of the N-type doped polysilicon layer 41 and the P-type doped polysilicon layer 42, respectively.
[0052] This invention prepares silicon slurry layers of different doping types on the back side of the tunneling layer 20, eliminating the need for multiple masking processes, laser grooving, secondary diffusion, and laser propulsion. After annealing, N-type silicon slurry layers 31 and P-type silicon slurry layers 32 can be formed. This simplifies the fabrication process of solar cells and reduces their production costs.
[0053] In S1, the silicon substrate 10 is an N-type silicon wafer with a resistivity of 0.3Ω·cm to 7Ω·cm, preferably 0.5Ω·cm to 3.5Ω·cm.
[0054] The silicon substrate 10 can be a silicon wafer that has already undergone surface treatment, or the silicon substrate 10 can be surface treated first and then subsequent steps can be performed.
[0055] The surface treatment of the silicon substrate 10 includes the following steps:
[0056] Surface cleaning. The silicon substrate 10 is cleaned, for example, to remove surface oil and to remove the damaged layer on the surface of the silicon substrate 10 using a mixed solution of potassium hydroxide solution (KOH) and hydrogen peroxide (H2O2).
[0057] The silicon substrate 10 is textured on both sides. Any texturing process commonly used in the art can be used to form a textured structure on the surface of the silicon substrate 10. For example, texturing can be performed in a sodium hydroxide solution or a potassium hydroxide solution to form a pyramid textured surface on the silicon wafer. The size of the pyramid textured surface is controlled within 2 μm, and the reflectivity is controlled within 10%, preferably 7% to 10%.
[0058] The back side of the silicon substrate 10 is polished. This invention utilizes a chain-type machine to apply polishing alkali solution for single-sided polishing of the back side of the silicon substrate 10. The polishing alkali solution can be a sodium hydroxide solution or a potassium hydroxide solution, with added polishing additives. After alkali polishing, the reflectivity of the back side of the silicon substrate 10 is no greater than 40%, such as 30%–40%; the substrate size is 15 μm or larger.
[0059] It should be noted that this step is single-sided polishing, and the front side of the silicon substrate 10 retains its textured surface. Of course, polishing is not a necessary step. Without polishing, both sides of the silicon substrate 10 have a textured surface; after polishing, the back side of the silicon substrate 10 has a flat surface.
[0060] The tunneling layer 20 can be prepared using any conventional technique in the art. As an example, the tunneling layer 20 can be a silicon oxide layer (SiOx) or a silicon carbide layer (SiC); the thickness of the tunneling layer 20 is 0.5 nm to 2 nm, preferably 1 nm to 1.5 nm; it can be formed by deposition using an LPCVD process.
[0061] For ease of description, the back side of the tunnel layer 20 is divided into: a first region, a second region spaced apart from the first region, and an interval region located between the first region and the second region.
[0062] In step S2, an N-type silicon paste layer 31 is prepared in the first region, and a P-type silicon paste layer 32 is prepared in the second region. No silicon paste layer is prepared in the gap between the first region and the second region, so as to naturally separate the N-type silicon paste layer 31 and the P-type silicon paste layer 32 to prevent short circuit between them.
[0063] Step S2 includes the following steps:
[0064] S21 prepares an N-type silicon slurry layer 31 in the first region.
[0065] The N-type silicon slurry layer 31 is a silicon slurry layer doped with an N-type dopant source. The N-type dopant source can be, but is not limited to, phosphorus, arsenic, carbon, nitrogen, etc. In this embodiment, the N-type dopant source is phosphorus. The phosphorus-doped silicon slurry includes silicon powder, a phosphorus source, and an organic carrier. The phosphorus source is one or more of phosphoric acid, ammonium dihydrogen phosphate, diammonium hydrogen phosphate, and polyphosphoric acid. The organic carrier includes acrylic resin, ethyl cellulose, diethylene glycol monobutyl ether acetate, ethylene glycol, tributyl citrate, polyamide wax, etc.
[0066] The first region includes a gate line region and a non-gate line region. A first silicon paste is prepared in the gate line region to form a first N-type silicon paste layer, and a second silicon paste is prepared in the non-gate line region to form a second N-type silicon paste layer. Both the first silicon paste and the second silicon paste are silicon pastes doped with N-type dopant sources. The first N-type silicon paste layer and the second N-type silicon paste layer together constitute an N-type silicon paste layer 31.
[0067] In one embodiment, the doping concentration of the N-type dopant source in the first silicon slurry is greater than the doping concentration of the N-type dopant source in the second silicon slurry; therefore, the doping concentration of the first N-type silicon slurry layer is greater than the doping concentration of the second N-type silicon slurry layer. As an example, the first N-type silicon slurry layer is phosphorus-doped with a phosphorus content of 5% to 8%, preferably 6%; the second N-type silicon slurry layer is phosphorus-doped with a phosphorus content of 1% to 4%, preferably 3%.
[0068] In one embodiment, the thickness of the first N-type silicone slurry layer is greater than the thickness of the second N-type silicone slurry layer. Specifically, the thickness of the first N-type silicone slurry layer is 1.1 to 3.1 times the thickness of the second N-type silicone slurry layer.
[0069] In one specific embodiment, the thickness of the first N-type silicon paste layer is 90–130 nm, preferably 120 nm, and the width of the first N-type silicon paste layer is 1–100 μm, preferably 50 μm; the thickness of the second N-type silicon paste layer is 40–80 nm, preferably 60 nm, and the width of the second N-type silicon paste layer is 1–1000 μm, preferably 500 μm.
[0070] A first N-type silicon paste layer of any doping concentration and a second N-type silicon paste layer of any thickness can be used in combination to form different solar cells. In one specific embodiment, the first N-type silicon paste layer in the grid region and the second N-type silicon paste layer in the non-grid region have different doping concentrations and different thicknesses.
[0071] S22 prepares a P-type silicon slurry layer 32 in the second region.
[0072] The P-type silicon slurry layer is a silicon slurry layer doped with a P-type dopant source. The P-type dopant source can be, but is not limited to, phosphorus, arsenic, carbon, nitrogen, etc. In this embodiment, the P-type dopant source is boron. The boron-doped silicon slurry includes silicon powder, a boron source, and an organic carrier. The boron source is one or more of boric acid, elemental boron, methylboric acid, ethylboric acid, and phenylboronic acid. The organic carrier includes acrylic resin, ethyl cellulose, diethylene glycol monobutyl ether acetate, ethylene glycol, tributyl citrate, polyamide wax, etc.
[0073] The second region includes a gate line region and a non-gate line region. A third silicon paste is prepared in the gate line region to form a first P-type silicon paste layer, and a fourth silicon paste is prepared in the non-gate line region to form a second P-type silicon paste layer. Both the third and fourth silicon pastes are silicon pastes doped with P-type dopant sources. The first and second P-type silicon paste layers together constitute the P-type silicon paste layer 32.
[0074] In one embodiment, the doping concentration of the P-type dopant source in the third silicon slurry is greater than that in the fourth silicon slurry, therefore the doping concentration of the first P-type silicon slurry layer is greater than that of the second P-type silicon slurry layer. As an example, the first P-type silicon slurry layer is boron-doped with a boron content of 5% to 8%, preferably 6%; the second P-type silicon slurry layer is boron-doped with a boron content of 1% to 4%, preferably 3%.
[0075] In one embodiment, the thickness of the first P-type silicone slurry layer is greater than the thickness of the second P-type silicone slurry layer. Specifically, the thickness of the first P-type silicone slurry layer is 1.1 to 3.1 times the thickness of the second P-type silicone slurry layer.
[0076] In one specific embodiment, the thickness of the first P-type silicon paste layer is 90-130 nm, preferably 120 nm, and the width of the first P-type silicon paste layer is 1-100 μm, preferably 50 μm; the thickness of the second P-type silicon paste layer is 40-80 nm, preferably 60 nm, and the width of the second P-type silicon paste layer is 1-1000 μm, preferably 500 μm.
[0077] A first P-type silicon paste layer of any doping concentration and a second P-type silicon paste layer of any thickness can be used in combination to form different solar cells. In one specific embodiment, the first P-type silicon paste layer in the grid region and the second P-type silicon paste layer in the non-grid region have different doping concentrations and different thicknesses.
[0078] In one embodiment, the first N-type silicon slurry layer has the same width and thickness as the first P-type silicon slurry layer, and the second N-type silicon slurry layer has the same width and thickness as the second P-type silicon slurry layer. This not only facilitates the preparation of silicon slurry layers in the first and second regions, but also ensures that the thicknesses of the N-type doped polycrystalline silicon layer 41 and the P-type doped polycrystalline silicon layer 42 formed in the first and second regions are the same or tend to be the same during subsequent preparation processes, thus facilitating electrode preparation.
[0079] A first N-type silicon paste layer and a second N-type silicon paste layer are prepared in the gate line region and the non-gate line region of the first region, respectively. Similarly, a first P-type silicon paste layer and a second P-type silicon paste layer are prepared in the gate line region and the non-gate line region of the second region, respectively. The second N-type and second P-type silicon paste layers are relatively thin, reducing parasitic absorption of amorphous silicon in the non-gate line region. The first N-type and first P-type silicon paste layers are relatively thick, preventing burn-through during electrode formation.
[0080] Therefore, this invention achieves heavy doping in the gate region and light doping in the non-gate region by preparing silicon slurry layers of different doping types, concentrations, and thicknesses on the back side of the tunneling layer 20 without the need for secondary diffusion or laser propulsion processes. Furthermore, it can simultaneously form P-type and N-type silicon slurry layers while achieving different thicknesses of the doped polycrystalline silicon layers in the gate and non-gate regions. The process is simple, highly feasible, and low-cost.
[0081] In optional embodiments, the silicone paste layer can be prepared by coating, printing, or transfer. As an example, in this embodiment, the silicone paste layer is formed on the back side of the tunneling layer 20 by printing. It should be noted that since the first N-type silicone paste layer, the second N-type silicone paste layer, the first P-type silicone paste layer, and the second P-type silicone paste layer are different, multiple printing processes are required to print the first silicone paste in the gate area, the second silicone paste in the non-gate area, the third silicone paste in the gate area, and the fourth silicone paste in the non-gate area, respectively.
[0082] By printing silicon paste layers with different doping concentrations and thicknesses, the process steps for preparing solar cells are simplified. The operation is simple and the production cost is low. It can also form interdigitated P-type and N-type silicon paste layers.
[0083] It is relatively easy to understand that no silicone paste is printed in the spacer area, and the width of the spacer area is 1 to 500 μm, for example, 100 μm. The smaller the spacing, the better, provided that the N-type silicone paste layer 31 and the P-type silicone paste layer 32 can be separated.
[0084] S3 annealing.
[0085] The silicon substrate coated with silicon slurry is annealed in an annealing equipment to crystallize the silicon slurry layer and activate the doping source, so that the silicon slurry layer is converted into a doped polycrystalline silicon layer; that is, the N-type silicon slurry layer 31 is converted into an N-type doped polycrystalline silicon layer 41, and the P-type silicon slurry layer 32 is converted into a P-type doped polycrystalline silicon layer 42.
[0086] In this invention, the annealing time is 1800s to 10800s, and the annealing temperature is 800℃ to 1050℃. This time and temperature range is applicable to the annealing of common P-type and N-type doped sources. Of course, the annealing temperature and time are usually slightly adjusted according to the specific type of dopant source being incorporated.
[0087] In one embodiment, when the doping source of the N-type silicon slurry layer is phosphorus and the doping source of the P-type silicon slurry layer is boron, the annealing temperature is 900°C and the annealing time is 2300s.
[0088] After the annealing step is completed, in the first region, the phosphorus doping concentration of the N-type doped polysilicon layer 41 located in the gate region is 1E21 atoms / cm. 3 ~5E21atoms / cm 3 The preferred phosphorus doping concentration is 3E21 atoms / cm³. 3 The doping concentration of the N-type doped polysilicon layer 41 located in the non-gate region is 3E20 atoms / cm. 3 ~8E20atoms / cm 3 The preferred phosphorus doping concentration is 5E20 atoms / cm³. 3 .
[0089] In the second region, the doping concentration of the P-type doped polysilicon layer 42 located in the gate region is 1E19 atoms / cm². 3 ~5E19 atoms / cm 3 The preferred boron doping concentration is 4E19 atoms / cm³. 3 The doping concentration of the P-type doped polysilicon layer 42 located in the non-gate region is 3E18 atoms / cm. 3 ~8E18atoms / cm 3 The preferred boron doping concentration is 6E18 atoms / cm³. 3 .
[0090] As shown above, the gate line regions of both the first and second regions are heavily doped, while the non-gate line regions are lightly doped. Both regions constitute an SE structure.
[0091] The solar cell fabrication method of the present invention further includes, before forming the first electrode 71 and the second electrode 72, depositing a film on the back side, the front side, or both sides to form a passivation film 50 and / or an antireflection film 60.
[0092] The passivation film 50 is made of alumina and formed using the ALD process.
[0093] In one embodiment, an aluminum oxide film is deposited only on the front side of the silicon substrate 10 to passivate the front side of the solar cell.
[0094] In one embodiment, a passivation film 50 is formed on both sides.
[0095] The antireflective film 60 is made of silicon nitride and formed using a PECVD process.
[0096] In one embodiment, a silicon nitride film is deposited on both sides using a PECVD device to reduce the light reflectivity on both sides. In one embodiment, the thickness of the silicon nitride film is 80 nm.
[0097] S4 forms a first electrode 71 and a second electrode 72 on the back sides of the N-type doped polysilicon layer 41 and the P-type doped polysilicon layer 42, respectively.
[0098] Specifically, the electrodes are formed by screen printing and sintering. The first electrode 71 passes through the back passivation film 50 and the back antireflection film 60 and contacts the N-type doped polysilicon layer 41. The second electrode 72 passes through the back passivation film 50 and the back antireflection film 60 and contacts the P-type doped polysilicon layer 42.
[0099] The first electrode 71 and the second electrode 72 are formed within the gate line regions of the first and second regions, respectively. As mentioned above, the doped polycrystalline silicon layer in the gate line region has a relatively large thickness, thus preventing the gate line region from being burned through during the sintering process of the first electrode 71 and the second electrode 72, ensuring the yield of the battery fabrication. Furthermore, the doped polycrystalline silicon layer in the first and second regions has the same thickness, allowing the metal electrodes to be printed on the same plane, facilitating operation.
[0100] The first electrode 71 and the second electrode 72 form ohmic contacts with the N-type doped polycrystalline silicon layer 41 and the P-type doped polycrystalline silicon layer 42 in the grid region, respectively, reducing the series resistance of the solar cell and increasing the fill factor FF. The solar cell can be fabricated by screen printing, forming interdigitated first electrodes 71 and second electrodes 72 in the first and second regions, respectively.
[0101] The N-type doped polycrystalline silicon layer 41 and the P-type doped polycrystalline silicon layer 42 in the non-gate region have low doping concentrations, both being lightly doped. This reduces the probability of carrier recombination at the surface, thereby increasing the open-circuit voltage Voc and short-circuit current Isc of the solar cell. Furthermore, the heavily doped and lightly doped regions can create a P++ / P+ and N++ / N+ high-low junction laterally, which is beneficial for improving carrier collection and further increasing the short-circuit current Isc.
[0102] The following specific embodiments will be provided to describe in detail the method for preparing the solar cell of the present invention.
[0103] Example
[0104] The method for preparing a solar cell includes the following steps:
[0105] Double-sided texturing is performed on the silicon substrate 10; an N-type monocrystalline silicon wafer is selected, and the front and back sides of the silicon substrate are texturized using a grooved texturing device.
[0106] In this embodiment, the damaged layer on the surface of the silicon wafer is first removed in a mixed solution of KOH and H2O2, and then texturing is performed in a sodium hydroxide solution or potassium hydroxide solution to form a pyramid textured surface on the silicon wafer. The size of the pyramid textured surface is controlled at 2μm and the reflectivity is controlled at 8%.
[0107] The back side of the silicon substrate is polished. A chain-type alkaline polishing device is used to polish the back side of the silicon substrate on one side only. In this embodiment, the alkaline polishing solution is a sodium hydroxide solution or a potassium hydroxide solution. After alkaline polishing, the reflectivity of the back side of the silicon wafer is 40%, and the tower size is 15 μm.
[0108] A 1.5 nm thick tunnel oxide layer was prepared on the back side of a silicon wafer using the LPCVD process.
[0109] A silicon paste layer is prepared on the back of the solar cell. In this embodiment, the silicon paste layer is prepared by printing.
[0110] Specifically, phosphorus-doped silicon paste is printed in the gate line area of the first region, wherein the phosphorus content is 6%, the height of the silicon paste is 120nm, and the width of the gate line area of the first region is 50μm; phosphorus-doped silicon paste is printed in the non-gate line area of the first region, wherein the phosphorus content is 3%, the height of the silicon paste is 60nm, and the width of the non-gate line area of the first region is 500μm.
[0111] The second region's gate line area is printed with boron-doped silicon paste, wherein the boron doping content is 6%, the paste height is 120nm, and the width of the gate line area in the second region is 50μm; the non-gate line area of the second region is printed with boron-doped silicon paste, wherein the boron doping content is 3%, the paste height is 60nm, and the width of the non-gate line area in the second region is 500μm.
[0112] The spacer area is not printed with silicone paste, and the width of the spacer area is 100μm.
[0113] Annealing is performed using a tubular high-temperature annealing device to achieve doping and crystallization of the silicon slurry.
[0114] In this embodiment, the high-temperature annealing temperature is 920℃, and the phosphorus doping concentration of the gate line region in the first region after annealing is 3E21 atoms / cm². 3The phosphorus doping concentration in the non-gate region of the first area is 5E20 atoms / cm². 3 The boron doping concentration in the gate region of the second region is 4E19 atoms / cm². 3 The boron doping concentration in the non-gateline region of the second region is 6E18 atoms / cm². 3 .
[0115] In this embodiment, a silicon nitride film with a thickness of 80 nm is deposited on both the front and back sides of an N-type single crystal silicon wafer using a PECVD device.
[0116] A first electrode 71 and a second electrode 72 are formed by screen printing on the back of an N-type monocrystalline silicon wafer, thus producing a TBC monocrystalline solar cell.
[0117] Comparative Example
[0118] The method for preparing solar cells differs from the steps described in the above embodiments in the following steps:
[0119] A 1.5 nm thick tunneling layer and a 120 nm thick poly silicon layer were fabricated on the back side of a silicon wafer using the LPCVD process.
[0120] Phosphorus and boron atoms were implanted into the polysilicon in the first region and the polysilicon in the second region respectively to achieve doping.
[0121] Using tubular high-temperature annealing, polysilicon undergoes crystallization and doping, transforming into a doped polysilicon layer. After annealing, the phosphorus doping concentration in the first region is 8E20 atoms / cm². 3 The boron doping concentration in the second region is 1E19 atoms / cm². 3 .
[0122] Solar cell structures were fabricated using the above embodiments and comparative examples, and various electrical parameters of the two solar cells were obtained, as shown in the table below.
[0123]
[0124]
[0125] Note: VOC represents open-circuit voltage, Jsc represents current density, FF represents fill factor, and Eff represents conversion efficiency.
[0126] The experimental results show that the solar cell fabrication method of this invention, using the method described in this embodiment, fabricates doped polycrystalline silicon layers with high and low doping concentrations in the grid region and non-grid region, respectively, forming a selective emitter and effectively improving the open-circuit voltage and fill factor. Simultaneously, doped polycrystalline silicon layers of different thicknesses are fabricated in the grid region and non-grid region. The thicker doped polycrystalline silicon layer in the grid region prevents burn-through during electrode sintering, while the thinner doped polycrystalline silicon layer in the non-grid region effectively reduces parasitic absorption of the solar spectrum by the doped polycrystalline silicon layer, thereby increasing the current density.
[0127] The comparative process cannot directly fabricate doped polycrystalline silicon layers of different thicknesses and doping concentrations in the grid line region and the non-grid line region. Therefore, the TBC solar cell fabricated in this embodiment has a much higher conversion efficiency than the TBC solar cell fabricated in the comparative example.
[0128] This application provides a solar cell prepared using the method described above.
[0129] In one embodiment, the solar cell includes a silicon substrate 10, a tunneling layer 20 located on the back side of the silicon substrate 10, an N-type doped polycrystalline silicon layer 41 and a P-type doped polycrystalline silicon layer 42 located on the back side of the tunneling layer 20, a first electrode 71 located on the back side of the N-type doped polycrystalline silicon layer 41, and a second electrode 72 located on the back side of the P-type doped polycrystalline silicon layer 42.
[0130] By placing both the first electrode 71 and the second electrode 72 on the back side, and eliminating the obstruction of metal electrodes on the front side, the solar cell has a large light-receiving area, thus improving its efficiency.
[0131] N-type doped polysilicon layers 41 and P-type doped polysilicon layers 42 are alternately disposed, with a gap between them. The doping concentration of the N-type doped polysilicon layer 41 in the gate region is greater than that in the non-gate region, and the thickness of the N-type doped polysilicon layer 41 in the gate region is greater than that in the non-gate region. The first electrode 71 is in contact only with the N-type doped polysilicon layer 41 in the gate region.
[0132] The doping concentration of the P-type doped polysilicon layer 42 in the gate region is greater than that in the non-gate region, and the thickness of the P-type doped polysilicon layer 42 in the gate region is greater than that in the non-gate region. The second electrode 72 is in contact only with the P-type doped polysilicon layer 42 in the gate region.
[0133] Therefore, the gate region and the non-gate region are respectively doped polysilicon layers with high and low doping concentrations, forming a selective emitter, which effectively improves the open-circuit voltage and fill factor. At the same time, the thick doped polysilicon layer in the gate region avoids burn-through during the electrode sintering process, while the thin doped polysilicon layer in the non-gate region effectively reduces the parasitic absorption of the solar spectrum by the doped polysilicon layer, thereby increasing the current density.
[0134] The back of the solar cell is also provided with a back passivation layer and a back anti-reflection layer. The first electrode 71 and the second electrode 72 pass through the back anti-reflection layer and the back passivation layer to contact the doped polycrystalline silicon layer of the grid line region.
[0135] The solar cell also includes a front passivation layer and a front antireflection layer sequentially disposed on the front side of the silicon substrate to passivate surface defects on the front side.
[0136] The above description, based on the embodiments shown in the figures, details the structure, features, and effects of the present invention. The above description is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the figures. Any changes made in accordance with the concept of the present invention, or equivalent embodiments modified to have equivalent changes, that do not exceed the spirit covered by the specification and figures, should be within the protection scope of the present invention.
Claims
1. A method for preparing a solar cell, characterized in that, The process includes the following steps: preparing a tunneling layer (20) on the back side of a silicon substrate (10); preparing an N-type silicon paste layer (31) and a P-type silicon paste layer (32) in a first region and a second region spaced apart from the first region on the back side of the tunneling layer (20); annealing the N-type silicon paste layer (31) and the P-type silicon paste layer (32) to convert them into an N-type doped polycrystalline silicon layer (41) and a P-type doped polycrystalline silicon layer (42), respectively; and forming a first electrode (71) and a second electrode (72) on the back side of the N-type doped polycrystalline silicon layer (41) and the P-type doped polycrystalline silicon layer (42), respectively.
2. The method for preparing a solar cell according to claim 1, characterized in that: A first N-type silicon paste layer is formed by preparing a first silicon paste in the gate region of the first region, and a second N-type silicon paste layer is formed by preparing a second silicon paste in the non-gate region of the first region, wherein the doping concentration of the N-type dopant source in the first silicon paste is greater than the doping concentration of the N-type dopant source in the second silicon paste; and / or, a third silicon paste layer is formed by preparing a first P-type silicon paste layer in the gate region of the second region, and a fourth silicon paste layer is formed by preparing a second P-type silicon paste layer in the non-gate region of the second region, wherein the doping concentration of the P-type dopant source in the third silicon paste is greater than the doping concentration of the P-type dopant source in the fourth silicon paste.
3. The method for preparing a solar cell according to claim 2, characterized in that: The first N-type silicon slurry layer is doped with phosphorus, and the phosphorus doping content is 5 wt% to 8 wt%; and / or, the second N-type silicon slurry layer is doped with phosphorus, and the phosphorus doping content is 1 wt% to 4 wt%; and / or, the first P-type silicon slurry layer is doped with boron, and the boron doping content is 5 wt% to 8 wt%; and / or, the second P-type silicon slurry layer is doped with boron, and the boron doping content is 1 wt% to 4 wt%.
4. The method for preparing a solar cell according to claim 2, characterized in that: The doping concentration of the N-type doped polysilicon layer (41) located in the gate region is 1E21 atoms / cm. 3 ~5E21atoms / cm 3 ; and / or, the doping concentration of the N-type doped polysilicon layer (41) located in the non-gate region is 3E20 atoms / cm. 3 ~8E20atoms / cm 3 ; and / or, the doping concentration of the P-type doped polysilicon layer (42) located in the gate region is 1E19 atoms / cm 3 ~5E19 atoms / cm 3 ; and / or, the doping concentration of the P-type doped polysilicon layer (42) located in the non-gate region is 3E18 atoms / cm 3 ~8E18atoms / cm 3 .
5. The method for preparing a solar cell according to any one of claims 2-4, characterized in that: The thickness of the N-type doped polysilicon layer (41) located in the gate region is greater than the thickness of the N-type doped polysilicon layer (41) located in the non-gate region; and / or, the thickness of the P-type doped polysilicon layer (42) located in the gate region is greater than the thickness of the P-type doped polysilicon layer (42) located in the non-gate region; and / or, the thicknesses of the N-type doped polysilicon layer (41) located in the gate region and the P-type doped polysilicon layer (42) located in the gate region are the same; and / or, the thicknesses of the N-type doped polysilicon layer (41) located in the non-gate region and the P-type doped polysilicon layer (42) located in the non-gate region are the same.
6. The method for preparing a solar cell according to claim 5, characterized in that: The thickness of the N-type doped polysilicon layer (41) in the gate region is 1.1 to 3.1 times the thickness of the N-type doped polysilicon layer (41) in the non-gate region; and / or, the thickness of the P-type doped polysilicon layer (42) in the gate region is 1.1 to 3.1 times the thickness of the P-type doped polysilicon layer (42) in the non-gate region.
7. The method for preparing a solar cell according to claim 1, characterized in that: The tunneling layer (20) is a silicon oxide layer or a silicon carbide layer, and the thickness of the tunneling layer (20) is 0.5 nm to 2 nm.
8. The method for preparing a solar cell according to claim 1, characterized in that: The first region and the second region are separated by an interval, the width of which is 1-500 μm.
9. The method for preparing a solar cell according to claim 1, characterized in that: It also includes the following steps: before forming the first electrode (71) and the second electrode (72), a passivation layer and / or a reflective layer are deposited on the back side, or the front side, or both sides.
10. A solar cell, characterized in that: The solar cell is prepared using the preparation method described in any one of claims 1-9.