Gallium nitride semiconductor device having vertical jfet and lateral hemt

Abstract

A semiconductor device (100) for controlling an electric current flowing between a source terminal (102) and a drain terminal (104) and a method for forming such a device are disclosed. The semiconductor device is formed from a layer stack of GaN layers, wherein a vertical junction field effect transistor JFET structure (120) and a lateral high electron mobility transistor HEMT structure (130) are provided to control the electric current.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more particularly to a GaN-based semiconductor device including a junction field-effect transistor (JFET) and a high electron mobility transistor (HEMT). Background Technology

[0002] GaN-based semiconductor devices have attracted increasing attention in the field of power electronics because they can operate at relatively higher voltages and currents compared to traditional silicon-based devices. Therefore, GaN-based transistors are increasingly used in applications such as power converters, inverters, and high-frequency switching systems.

[0003] Typically, the ability of transistors to achieve high-voltage operation is largely attributed to the presence of a thick drift region capable of withstanding high electric fields. However, this drift region is usually associated with an increased gate-to-drain distance, resulting in a larger device footprint. This trade-off between high voltage capability and compactness also presents design challenges for GaN-based transistors. Furthermore, with increasing gate-to-drain distance, challenges such as higher parasitic capacitance and reduced switching speed may arise, negatively impacting device performance in high-frequency applications.

[0004] Therefore, improved device design is needed to facilitate high voltage handling capabilities while reducing device footprint, thereby enabling more efficient and compact GaN-based power devices. Summary of the Invention

[0005] The purpose of this disclosure is to provide techniques for solving at least some of the problems described above. Further and alternative objectives can be understood from the following.

[0006] According to a first aspect, a semiconductor device configured to control a current path between a source terminal and a drain terminal is provided. The semiconductor device includes a layer stack disposed between the source terminal and the drain terminal, and a vertical junction field-effect transistor (JFET) structure and a lateral high electron mobility transistor (HEMT) structure formed in the layer stack. The layer stack includes an n-type GaN drift layer disposed thereon and electrically connected to the drain terminal, a p-type GaN first gate layer disposed above the drift layer, an undoped GaN channel layer disposed above the first gate layer, a barrier layer disposed above the channel layer, a p-type GaN second gate layer disposed above the barrier layer, and an n-type GaN channel region extending vertically through the channel layer and the first gate layer and electrically connected to the drift layer. The JFET structure includes a channel structure formed by the channel region and a gate structure formed by the first gate layer, wherein the channel structure is configured to form a current conduction path between the drift layer and the channel layer. The HEMT structure includes a channel structure formed at the interface between the channel layer and the barrier layer, and a gate structure formed by the gate layer, wherein the channel structure is configured to form a current conduction path between the channel region and the source terminal. Furthermore, an interconnect structure is provided, configured to electrically connect the gate structure of the JFET structure to the source terminal.

[0007] According to a second aspect, a method for forming a semiconductor device according to the first aspect is provided, the method comprising a vertical junction field-effect transistor (JFET) structure and a lateral high electron mobility transistor (HEMT) structure. The method includes forming an opening in a layer stack including an n-type GaN drift layer, a p-type GaN first gate layer above the drift layer, an unintentionally doped GaN channel layer above the first gate layer, a barrier layer above the channel layer, and a second gate layer above the barrier layer. The opening extends at least through the channel layer and the first gate layer into the drift layer. The method further includes forming an n-type GaN channel region in the opening by epitaxial growth. Furthermore, a drain terminal and a source terminal electrically connected to the first gate layer and the channel layer are formed below the drift layer. The JFET structure includes a channel structure formed by the channel region and a gate structure formed by the first gate layer, wherein the channel structure is configured to form a current conduction path between the drift layer and the channel layer. The HEMT structure includes a channel structure formed at the interface between the channel layer and the barrier layer, and a gate structure formed by a second gate layer, wherein the channel structure is configured to form a current conduction path between the channel region and the source terminal.

[0008] According to a third aspect, a power conversion device is provided, including a semiconductor device according to the first aspect. Examples of such a power conversion device include converters (DC / DC, AC / DC, AC / AC), inverters, and motor drivers.

[0009] Layer stacking allows for the formation of JFETs and HEMTs, which together control the current flowing between the drain and source terminals of the semiconductor device. The drain of the JFET is electrically connected to the drain terminal of the semiconductor device, the source of the JFET is electrically connected to the drain of the HEMT, and the source of the HEMT is electrically connected to the source terminal of the semiconductor device. Furthermore, the gate of the JFET is electrically connected to the source of the HEMT, which in turn is connected to the source terminal of the semiconductor device.

[0010] Advantageously, a JFET can be a normally-on device due to the behavior of the pn junction at its gate, while a HEMT can be a normally-off device due to the p-type GaN second gate layer being located above the barrier layer. This configuration allows the entire semiconductor device to be normally-off, remaining non-conductive for gate voltages below the HEMT threshold voltage. This allows the semiconductor device to meet safety standards typically required in power conversion systems, designed to prevent unexpected currents in the event of control signal failure.

[0011] HEMTs can be used to control the on / off state of semiconductor devices. When the HEMT is turned off and the drain terminal potential of the semiconductor device increases, the potential of the common node connecting the source of the JFET and the drain of the HEMT may increase accordingly. This increase may continue until the (negative) gate-to-source voltage of the JFET drops below its threshold voltage, at which point the JFET may turn off. As the drain terminal voltage continues to increase, this behavior causes the voltage at the common node to be fixed at the inverse of the JFET threshold voltage. Therefore, the maximum drain voltage that the HEMT must maintain in order to keep the entire semiconductor device in a non-conductive state can be limited to the inverse of the JFET threshold voltage. This design allows the HEMT to be relatively compact because it does not need to maintain a drain voltage exceeding the JFET threshold voltage, thus reducing its contribution to the on-resistance of the semiconductor device.

[0012] In the on state, current can flow through the semiconductor device via the JFET and HEMT connected in series. Specifically, current can flow from the drain terminal through the JFET channel, and further through the two-dimensional electron gas (2DEG) channel region formed at the heterojunction between the channel layer and the barrier layer of the HEMT, and finally reach the source terminal.

[0013] This configuration (where the JFET's channel is formed by a vertically extending n-type GaN channel region, and the HEMT is a lateral device formed at the interface between the channel layer and the barrier layer) allows the top surface of the layer stack to shield the high potential at the drain terminal. Advantageously, this reduces the risk of adverse surface effects caused by electric field congestion and electron buildup within the dielectric layer of the semiconductor device.

[0014] Furthermore, the vertical design of the JFET allows the drain terminal of the semiconductor device to be positioned on the back side of the layer stack, i.e., below the JFET and HEMT. Therefore, the device's voltage blocking capability, or breakdown voltage, may be proportional to the thickness of the layer stack, and more specifically, to the thickness of the drift layer.

[0015] Monolithic integration of JFETs and HEMTs within a shared GaN epitaxial layer stack offers several advantages. By forming two transistors within the same stack, parasitic effects are reduced, leading to improved high-frequency performance and lower switching losses. This integration also reduces the need for external interconnects between the JFET and HEMT, resulting in more compact devices with a smaller footprint. Furthermore, using a single epitaxial layer stack simplifies the manufacturing process, as the same growth and processing steps can be applied to both the JFET and HEMT.

[0016] JFETs and HEMTs can include complementary characteristics; JFETs provide high-voltage blocking capability, while HEMTs provide precise and fast switching. Therefore, a JFET can be referred to as a high-voltage device, and an HEMT can be referred to as a low-voltage device arranged in a cascode configuration. For example, the breakdown voltage of a JFET can be at least 600V, such as in the range of 650-1200V. As mentioned above, the breakdown voltage can be determined at least in part by the thickness of the drift layer. The drift layer can be a lightly doped layer configured to withstand high electric fields by distributing voltage across its thickness. A thicker drift layer allows the depletion region to expand further, thereby reducing the peak electric field at any given point. By increasing the thickness of the drift layer, the device can maintain a higher voltage before the electric field exceeds the material's critical electric field, leading to avalanche breakdown.

[0017] The channel region forming the vertical channel structure of a JFET can be formed in an opening or via etched into the channel layer and the first gate layer of the layer stack. This channel region can be formed using an n-type GaN epitaxial regeneration process. The conductivity of this channel region can be modulated by depleting the pn junction formed between the n-type GaN channel region and the p-type GaN first channel layer. Therefore, the size of the channel region, its doping, and the doping of the first channel layer can determine the threshold voltage of the JFET.

[0018] The layer stack may also include one or more heavily doped n-type GaN contact layers to facilitate low-resistance ohmic contacts between adjacent layers. In some examples, such heavily doped contact layers may be disposed between the drain terminal and the drift layer to reduce the contact resistance between the drift layer and the drain terminal. In other examples, a heavily doped intermediate layer may be disposed between the first gate layer and the channel layer to reduce channel layer depletion. In the context of this disclosure, “heavily doped” generally refers to a sufficiently high doping concentration (typically 10⁻⁶). 18 cm -3 (or higher) semiconductor layers that dominate the electrical behavior of materials.

[0019] HEMTs can include a p-type GaN gate formed by a p-doped GaN layer above a barrier layer to create a depletion region that suppresses 2DEG at zero gate voltage. This design allows HEMTs to be normally-off devices. However, other gate designs are also possible, such as metal-insulator-semiconductor (MIS) gates. MIS gates can utilize a dielectric insulating layer (such as silicon nitride or aluminum oxide) between the gate metal and the barrier layer. This insulating layer can reduce gate leakage by providing electrical isolation. While MIS gates can also achieve normally-off operation, they typically require additional design elements, such as recessed gate structures, to suppress 2DEG at zero gate voltage.

[0020] The semiconductor device may also include a field plate structure disposed above a barrier layer and transversely between the gate layer and the channel region. This field plate structure can be used to shape and control the electric field distribution within the semiconductor device. The field plate structure may include a metal extension connected to the source terminal and may be placed on an insulating layer to alter the electric field within the device. More specifically, the field plate structure can be configured to reduce electric field congestion in the region between the channel region and the HEMT gate by redistributing the electric field over a larger area. The field plate structure may be electrically connected to the source terminal and extend on the gate of the HEMT.

[0021] It should be noted that relative spatial terms such as “vertical,” “up,” “above,” “below,” “below,” “stacked on,” etc., should be understood as indicating a position or direction relative to the normal direction of the substrate, or a position or direction relative to the bottom-up direction of the layer stack. Accordingly, terms such as “lateral” and “horizontal” should be understood as parallel to the substrate, that is, parallel to the upper surface or main extension plane of the substrate. Attached Figure Description

[0022] The foregoing, as well as the additional objects, features, and advantages, can be better understood through the following illustrative and non-limiting detailed description with reference to the accompanying drawings. Unless otherwise stated, the same reference numerals will be used for the same elements in the drawings.

[0023] Figure 1A It is a schematic cross-section based on some examples of semiconductor devices.

[0024] Figure 1B It is a circuit diagram depicting the electrical connections of JFETs and HEMTs based on some examples of semiconductor devices.

[0025] Figure 2A -D is a schematic representation of the depletion region of a JFET at different drain voltages, based on cross-sections of some example semiconductor devices.

[0026] Figure 3A -G is a schematic cross-section illustrating various processing steps according to some examples of methods for manufacturing semiconductor devices. Detailed Implementation

[0027] The following description, with reference to the accompanying drawings, includes examples of semiconductor devices including JFETs and HEMTs, as well as methods for forming such devices.

[0028] Figure 1A A schematic cross-section of a semiconductor device 100 according to an example is shown. The semiconductor device 100 is formed by a layer stack disposed between a source terminal 102 and a drain terminal 104. The layer stack includes multiple epitaxially formed GaN layers—in this example, from bottom to top: an n-type drift layer 112 disposed above the drain terminal, a p-type first gate layer 113 disposed above the drift layer 112, an unintentionally doped channel layer 115 disposed above the first gate layer 113, a barrier layer 116 disposed above the channel layer 115, and a p-type second gate layer 117 disposed above the barrier layer 116. Optionally, one or more highly doped contact layers may be provided to reduce the resistance between adjacent layers. In this example, a highly doped n-type contact layer 111 is disposed between the drain terminal 104 and the drift layer 112.

[0029] The layer stack also includes an n-type GaN channel region 118, which extends vertically through the channel layer 115 and the first gate layer 113 to contact the drift layer 112. The channel region 118 can be formed by epitaxially growing n-type GaN in an opening formed in the layer stack. Therefore, the size of the channel region 118 can be determined by the size of the opening, and the doping of the channel region 118 can be determined by the epitaxial growth process.

[0030] These different layers and regions in the layer stack provide junctions and regions that can be used to form the vertical JFET structure 120 and the lateral HEMT structure 130. Figure 1A The circuit diagram symbol is shown in the figure. The channel region 118, which extends vertically downward from the top of the layer stack to the drift layer 112, forms the channel region of the vertical JFET structure 120. The conductivity state of the channel region can be modulated by the pn junction depletion provided by the interface between the p-type first gate layer 113 and the n-type channel region 118, thereby allowing control of the current conduction path between the drift layer 112 and the channel layer 115.

[0031] The channel structure of the HEMT structure 130 can be formed by a two-dimensional electron gas (2DEG) at the heterojunction between the channel layer 115 and the barrier layer 116. The heterojunction can be formed by different band gaps of the channel layer 115 and the barrier layer 116. The barrier layer 116 can be formed, for example, by AlGaN used as a barrier, while the GaN of the channel layer 115 serves as a lateral channel region for conduction. In other examples, the barrier layer 116 can be formed by InAlN, InGaN, AlN, or ScAlN.

[0032] AlGaN and GaN layers can exhibit spontaneous and piezoelectric polarization effects. At the heterojunction, the polarization difference between the two materials can generate a fixed positive charge that attracts free electrons from the surrounding material to form a dense, confined electron layer. Electrons can be configured as a thin quantum well at the interface between the channel layer 115 and the barrier layer 116. This confinement can generate a 2DEG, where electrons can move laterally in two dimensions but are confined in a third dimension. This allows for the provision of a HEMT structure 130 that forms a lateral current conduction path between the source region and source terminal 102 of the JFET via the channel layer 115.

[0033] In addition, a heavily doped n-type intermediate layer 114 can be arranged between the first gate layer 113 and the channel layer 115 to prevent the 2DEG from being depleted from below.

[0034] An interconnect structure 140 may be provided to electrically connect the gate structure of the JFET structure 120 (i.e., the first gate layer 113) and the source region of the HEMT (i.e., the channel layer 115) to the source terminal 102 of the semiconductor device 100. The interconnect structure 140 may include vertical interconnects, such as via connections, extending down from the metallization layer of the device to the first gate layer 113 and the channel layer 115. As a result, the gate of the JFET structure 120 can be connected to the source of the HEMT structure 130.

[0035] A gate metal layer 119 may be formed on the gate layer 117 to form the gate structure of the HEMT structure 120. This gate structure may form the gate terminal of the entire semiconductor device 100.

[0036] In some examples, a field plate structure 142 may be provided to reduce field congestion in the semiconductor device 100. The field plate structure 142 may form part of a metallization layer and may extend from a vertical interconnect that contacts the first gate layer 113 and the channel layer 115 to the source terminal 102, and extend over the gate structure 119 to a location transverse between the gate structure 119 and the channel region 118.

[0037] Figure 1AA symmetrical layout is shown, featuring a central channel region 118 and a first HEMT structure 130 and a second HEMT structure 230 arranged laterally opposite to the channel region 118. This configuration allows two JFET structures to be formed from the same channel region 118—a first JFET structure 120 defining a current conduction path from the drain terminal 104 via the first HEMT structure 130 to the first source terminal 102, and a second JFET structure 220 defining a current conduction path from the drain terminal 104 via the second HEMT structure 230 to the second source terminal 202. Therefore, it should be understood that each of these transistors can be formed from the same stack of layers, i.e., from the same drift layer 112, first gate layer 113, vertical channel region 118, etc. Furthermore, the same metallization layer can be used to form the interconnect structure 140 of each transistor, and the corresponding gate structures 119, 219 of the first and second HEMT structures 130, 230.

[0038] In some examples, the gate structures 119, 219 of the first HEMT structure 130 and the second HEMT structure 230 can be addressed independently; in other examples, they can be electrically connected to each other and therefore addressed simultaneously. The same applies to the first and second source terminals 102, 202 of the semiconductor device 100, which can also be addressed independently or interconnected.

[0039] Semiconductor device 100 can be used in power conversion devices, such as converters and inverters. The dual-transistor arrangement of semiconductor device 100 can provide the main switching element of such power conversion device, which may include multiple switching elements arranged in a half-bridge configuration, a full-bridge configuration, and other topologies to enable voltage to be increased or decreased, or to convert direct current to alternating current.

[0040] It should be noted that Figure 1A The configuration shown is merely an illustrative example, and other configurations are possible. This disclosure is by no means limited to a symmetrical layout having a vertical channel region 118 arranged between two HEMT structures 130, 230. The semiconductor device 100 may also include a single HEMT structure 230 and a single JFET structure 120, which preferably includes a vertical channel region 118, which is sandwiched from at least both sides by a first gate layer 113 to ensure effective depletion of the channel region 18.

[0041] like Figure 1A As shown, the source of the resulting JFET 120 and the drain of the resulting HEMT 130 can be interconnected at a common node. Figure 1B An example of this layout is shown in the image. Figure 1B It is a circuit diagram that outlines the electrical relationships between the transistors and terminals of the obtained semiconductor device 100.

[0042] Figure 1B A common-source, common-gate configuration is shown, in which JFET 120 and HEMT 130 are connected in series to control the current path between the drain terminal D and the source terminal S of semiconductor device 100. The drain of JFET 120 is electrically connected to the drain terminal D, the source of JFET 120 is electrically connected to the drain of HEMT 130, and HEMT 130 and its source are electrically connected to the source terminal S. The gate of HEMT 130 forms the gate terminal G of the resulting semiconductor device 100. Furthermore, the gate of JFET 120 is electrically connected to the source of HEMT 130.

[0043] The JFET 120 can be referred to as a high-voltage transistor, configured to block high voltages, such as 600V and above, when the semiconductor device 100 is arranged in a blocking or off state. On the other hand, the HEMT 130 can be referred to as a low-voltage transistor, configured to open and close current paths. The JFET 120 can be a normally-on device, i.e., conducting current at zero gate voltage or a gate voltage below a threshold voltage, while the HEMT 130 can be a normally-off device, requiring an applied gate voltage to conduct current.

[0044] The source of JFET 120 and the drain of HEMT 130 are interconnected at a common node N. This configuration of transistors 120 and 130 allows for a voltage V at the common node N. N The threshold voltage Vt of the JFET 120 is fixed. JFET The inverse voltage (note that the threshold voltage in this configuration is negative). As a result, the maximum voltage V N That is, the maximum drain voltage that HEMT 130 must maintain in order to keep the entire semiconductor device 100 in a non-conductive state can be limited to the negative threshold voltage Vt of JFET 120. JFET The reverse voltage. Advantageously, the common node N is an internal node, fully integrated in the layer stack and requiring no interconnects or metallization.

[0045] Figure 2A -D schematically illustrates the off-state operation of semiconductor device 100, which can be coupled with... Figure 1A The semiconductor devices in the diagram are similarly configured. These figures illustrate the semiconductor device 100 when the first and second HEMTs 130, 230 are in a non-conductive state, due to a gate voltage V below a threshold voltage. G This is caused by (such as zero gate voltage) being applied to each gate terminal G of the semiconductor device 100.

[0046] Figure 2A -D represents the response to an increased drain voltage V. DA series of graphs showing the extension of the depletion region 119 of the JFET 120 by applying a load to the drain terminal D of the semiconductor device 100. On the left side of each figure, a cross-section of the device 100 is shown, indicating the depletion region 119. On the right side, a graph is shown illustrating the strain on the drain voltage V. D The voltage V of the common node N N .

[0047] Figure 2A It shows when the drain voltage V D And therefore the voltage V at the common node N N The depletion region 119 is zero. In this state, JFET 120 is in the on state and HEMT 130 is in the off state. Therefore, the depletion region 119 at the interface between drift layer 112 and first gate layer 113 is relatively small and does not extend completely through channel region 118.

[0048] exist Figure 2B In the middle, the drain voltage V D It has increased, but is still below the threshold voltage Vt. JFET The inverse voltage. The depletion region 119 is larger, but does not extend across the channel region 118. Therefore, the JFET is in the on state. In this operating mode, the drain of the HEMT 130 is exposed to the common node voltage V. N The voltage at the common node varies with the drain voltage V. D It increases with the increase of , as shown in the figure.

[0049] exist Figure 2C In the middle, the drain voltage V D Exceeding the threshold voltage Vt of JFET 120 JFET The reverse voltage causes the depletion region 119 to deplete the vertical channel region 118 from both sides. As a result, the channel of the JFET 120 enters a non-conducting state, blocking the current path and reducing the voltage V at the common node N. N Fixed to the JFET 120 threshold voltage Vt JFET The inverse voltage is shown in the figure. The increased drain voltage V D The main portion can now be carried by the JFET 120 and the enlarged depletion region 119, while the HEMT 130 remains exposed to a substantially constant voltage V at the common node N. N .

[0050] Figure 2D A semiconductor device 100 with a fully depleted drift layer 112 is shown, with a depletion region 119 spanning the entire thickness of the drift layer 112. However, throughout this phase, the common node voltage V... N It can remain essentially constant at -Vt JFET .

[0051] Now refer to Figure 3A The cross-sectional diagrams in -G discuss example methods for forming the semiconductor device 100 as shown in any of the above diagrams. Figure 3A -G indicates the various stages of manufacturing. It should be noted that the proposed method is an illustrative example, and other methods are possible depending on the specific configuration and performance requirements of the semiconductor device 100.

[0052] Figure 3A A cross-section of an example layer stack disposed on substrate 109 is shown. The layer stack is typically grown on substrate 109 using metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE) techniques. Substrate 109 provides mechanical support and can serve as a base for the epitaxial growth of various GaN layers. Examples of substrate 109 include silicon, silicon carbide, GaN, polycrystalline AlN, and sapphire substrates.

[0053] The layers can be grown sequentially, each layer having a doping distribution and thickness to form the functional regions of the resulting JFET and HEMT. The layer stack may include a highly n-doped GaN contact layer 111, which can be grown directly on the substrate 109 as the first layer of the stack. This layer 111 can be used for various purposes, such as providing a low-resistance interface for electrical connections and serving as a basis for subsequent epitaxial growth of drift layers. The contact layer 111 can typically have 10... 18 -10 19 cm -3 Doping concentration on the order of magnitude.

[0054] An n-doped GaN drift layer 112 can be grown on the contact layer 111. The thickness and doping concentration of the drift layer 111 can be designed to balance the high breakdown voltage and low on-resistance of the resulting JFET. For power transistors with breakdown voltages in the range of 600-1200V, the thickness is typically between 7-15µm. In some examples, the doping concentration can be as high as 10µm. 15 -10 16 cm -3 Within the range.

[0055] The layer stack may also include a first gate layer 113, which may be a p-doped GaN layer forming the gate region of the JFET. The first gate layer 113 may be doped with acceptor impurities, typically magnesium, to introduce holes as majority carriers. The doping level can be selected to balance conductivity and device stability; the doping level is typically 10. 17 and 10 20 cm -3 between.

[0056] Optionally, the layer stack may include an intermediate layer 114 formed on the first gate layer 113. The intermediate layer 114 may be a heavily doped n-type GaN layer configured to prevent 2DEG depletion from below and allow control of the conduction state via locally induced depletion by the second gate layer 117. The intermediate layer 114 may include 10 18 cm -3 Or a higher doping concentration.

[0057] The layer stack may also include an unintentionally doped GaN channel layer 115 disposed above the first gate layer 113. The unintentionally doped channel layer 115 may be grown on the intermediate layer 114 and may be configured to form a current conduction path for HEMT. The channel layer 115 can be formed without intentionally adding dopants. However, due to impurities or defects inherent in the growth process, in some examples it may exhibit light n-type conductivity, allowing the formation of a 2DEG without introducing excessive electron scattering. The thickness of the channel layer 115 is typically about 100-500 nm.

[0058] A barrier layer 116 may be formed on the channel layer 115. The barrier layer 116 may be formed of a wide bandgap material (such as AlGaN) and configured to form a heterojunction that generates a 2DEG. The barrier layer 116 may be relatively thin, such as in the range of 10-30 nm.

[0059] The gate of the HEMT 130 can be formed from a p-type GaN second gate layer 117. The first gate layer 113 helps deplete the 2DEG of the HEMT, preventing the HEMT from conducting at zero gate bias. Including a p-GaN gate can locally suppress 2DEG at zero gate voltage, thus providing normally-off operation of the HEMT 130. The thickness and doping concentration of the second gate layer 117 can be selected to determine the threshold voltage Vt of the HEMT 130. HEMT In some examples, this threshold voltage can be in the range of 1-3V. The second gate layer 117 is approximately 100 nanometers thick and is doped with Mg. The doping concentration is typically in the range of 10. 18 -10 20 cm -3 Within the range.

[0060] Figure 3A The example method shown in -G can be used to form similar... Figure 1A and 2A Semiconductor device 100 as shown in -D. Therefore, example device 100 may include a symmetrical configuration with HEMTs arranged on either side of the central JFET structure. It should be noted that the appended claims are by no means limited to this configuration. Other configurations include, for example... Figure 1B The single JFET and single HEMT shown are also possible.

[0061] Figure 3B The layer stack is shown after the second gate layer 117 is patterned to form the gate regions of the first and second HEMTs.

[0062] like Figure 3C As shown, an opening or via 151 can be formed between the gate regions. The opening 151 can be etched into the layer stack, through the barrier layer 116, the channel layer 115, the intermediate layer 114 (if any), and the first gate layer 113, all the way down to the drift layer 112.

[0063] Subsequently, opening 151 can be regrowed with n-type GaN material to form a vertical channel region 118, which provides the channel for the resulting JFET. The channel region 118 is allowed to be electrically connected to the drift layer 112 by etching opening 151 at least until the drift layer 112 is exposed. The channel region 118 can be selectively grown in the opening or grown via blanket regeneration. In the latter case, a removal step is performed to remove excess n-type GaN. The resulting structure... Figure 3D As shown in the image.

[0064] exist Figure 3E In this configuration, a passivation layer 142 has been formed over the layer stack. The passivation layer 142 is further patterned to form an opening at the gate layer 117, thereby defining the gate metal of the HEMT.

[0065] exist Figure 3F In this configuration, gate metals 119 and 219 have been formed to allow control over the conductivity state of each HEMT (and thus the resulting semiconductor device). Furthermore, trenches or contact openings 152 and 153 have been opened for contact with the first gate layer 113 and the channel layer 115. The trenches 152 and 153 are positioned such that the gate structures of the respective HEMTs formed by the gate layers 113 and the gate metals 119 and 219 are arranged between the trenches 152 and 154.

[0066] These trenches 152, 153 can be formed sequentially, wherein the deeper trench 152 exposing the first gate layer 113 can be formed first, followed by the shallower trench 153 exposing the channel layer 115. The trenches 152, 153 can be filled with metal to form a vertical interconnect and allow electrical access from above to the gate layer 113 and the channel layer 115.

[0067] The resulting device is as follows Figure 3GAs shown, a first interconnect structure 140 is formed at a first HEMT, a second interconnect structure 240 is formed at a second HEMT, and a drain terminal 104 contacts the drift layer 112 from below. During operation, current can flow from the drain terminal 104 through the drift layer 112 and the JFET channel formed by the channel region 118, and further laterally through the 2DEG in the channel layer 115 to the source terminals formed at the interconnect structures 140 and 240.

[0068] Conclusion

[0069] In the foregoing, the inventive concept has been described primarily with reference to a limited number of examples. However, as will be readily understood by those skilled in the art, other examples besides those disclosed above are equally possible within the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device configured to control a current flowing between a source terminal and a drain terminal, said semiconductor device comprising: A layer stack disposed between the source terminal and the drain terminal, the layer stack comprising: An n-type GaN drift layer is disposed above the drain terminal and electrically connected to the drain terminal. A p-type GaN first gate layer disposed above the drift layer. An unintentionally doped GaN channel layer disposed above the first gate layer. A barrier layer arranged above the channel layer, A p-type GaN second gate layer is disposed above the barrier layer. It extends vertically through the channel layer and the first gate layer and is electrically connected to the n-type GaN channel region of the drift layer; The semiconductor device further includes: A vertical junction field-effect transistor (JFET) structure includes a channel structure formed by the channel region and a gate structure formed by the first gate layer, wherein the channel structure is configured to form a current conduction path between the drift layer and the channel layer. A lateral high electron mobility transistor (HEMT) structure includes a channel structure formed at a heterojunction between the channel layer and the barrier layer, and a gate structure formed by the gate layer, wherein the channel structure is configured to form a current conduction path between the channel region and the source terminal; and The gate structure of the JFET structure is electrically connected to the interconnect structure of the source terminal.

2. The semiconductor device of claim 1, wherein the JFET structure has a breakdown voltage of at least 600V.

3. The semiconductor device of claim 1, wherein the channel region is formed in an opening etched into the channel layer and the first gate layer.

4. The semiconductor device of claim 1, further comprising: A heavily doped n-type GaN contact layer is disposed between the drain terminal and the drift layer.

5. The semiconductor device of claim 1, further comprising: A heavily doped n-type GaN intermediate layer is disposed between the first gate layer and the channel layer.

6. The semiconductor device of claim 1, wherein the gate layer is a p-type GaN layer.

7. The semiconductor device of claim 1, wherein the barrier layer is formed of AlGaN.

8. The semiconductor device of claim 1, further comprising: A field plate structure is disposed above the barrier layer and transversely between the gate layer and the channel region.

9. A method for forming a semiconductor device, said semiconductor device comprising a vertical junction field-effect transistor (JFET) structure and a lateral high electron mobility transistor (HEMT) structure, said method comprising: A layer stack is provided, the layer stack including an n-type GaN drift layer, a p-type GaN first gate layer above the drift layer, an unintentionally doped GaN channel layer above the first gate layer, a barrier layer above the channel layer, and a second gate layer disposed above the barrier layer. An opening is formed in the layer stack, the opening extending through the channel layer and the first gate layer into the drift layer; An n-type GaN channel region is formed in the opening by epitaxial growth; A drain terminal is formed below the drift layer; as well as Forming a source terminal electrically connected to the first gate layer and the channel layer; The JFET structure includes a channel structure formed by the channel region and a gate structure formed by the first gate layer, wherein the channel structure is configured to form a current conduction path between the drift layer and the channel layer; as well as The HEMT structure includes a channel structure formed at the interface between the channel layer and the barrier layer, and a gate structure formed by the gate layer, wherein the channel structure is configured to form a current conduction path between the channel region and the source terminal.

10. The method of claim 9, wherein the gate layer is a p-type GaN layer.

11. The method of claim 9, wherein the barrier layer is an AlGaN layer.

12. The method of claim 9, further comprising forming a heavily doped n-type GaN contact layer on the drift layer.

13. The method of claim 9, further comprising forming a heavily doped n-type GaN intermediate layer on the channel layer.

14. The method of claim 9, wherein the layers are epitaxially grown on a Si substrate or a SiC substrate.

15. An electrical power conversion device comprising a semiconductor device as claimed in any one of claims 1-8.

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