Low-power state synchronization control method and system, and electric appliance

Abstract

This invention relates to the field of synchronization control technology, and discloses a low-power state synchronization control method, system, and electrical equipment. The method includes: when the low-power state synchronization control system detects that it meets the conditions for entering low-power mode, starting a low-power countdown; sending first communication data with a low-power state flag to each second chip at preset time intervals until the low-power countdown ends, so that each second chip controls itself to enter a low-power state based on the received first communication data with the low-power state flag and the corresponding reception time, wherein the preset time interval is less than the low-power countdown; and controlling the first chip to enter a low-power state after the low-power countdown ends. This achieves the function of all chips synchronously entering low power mode, improves the problem of low-power state synchronization lag between chips, eliminates the need for a state synchronization port, reduces I / O port occupation, is unaffected by I / O port level fluctuations, and has higher reliability in low-power synchronization control.

Description

Technical Field

[0001] This invention relates to the field of synchronization control technology, and more specifically to low-power state synchronization control methods, systems and electrical equipment. Background Technology

[0002] With the diversification of product functions, control systems require more control chips to implement corresponding product functions. Furthermore, the demand for low power consumption has led many control systems to implement low-power functionality. In related technologies, taking a control system composed of multiple MCUs as an example, to synchronize the low-power states of each MCU, an I / O port of the master MCU is used as a status synchronization port to inform the other MCUs of their own status, thus enabling all MCUs to synchronously enter the low-power state. However, this method requires a certain amount of time for status detection, resulting in significant synchronization lag, and is easily affected by external interference such as I / O port level fluctuations, leading to low reliability. Therefore, improving the synchronous control of the low-power state in the control system has become an urgent problem to be solved. Summary of the Invention

[0003] In view of this, the present invention provides a low-power state synchronization control method, system and electrical equipment to solve the problem of low-power state synchronization lag in the control chip of the control system in the related art.

[0004] In a first aspect, the present invention provides a low-power state synchronization control method, applied to a first chip in a low-power state synchronization control system composed of at least two chips with low-power and communication functions, wherein the first chip is the chip that controls all chips in the low-power state synchronization control system to enter a low-power state, and the method includes:

[0005] When the low-power state synchronization control system detects that it meets the low-power entry condition, it starts the low-power entry countdown.

[0006] According to a preset time interval, first communication data with a low power status flag is sent to each second chip until the low power countdown ends, so that each second chip controls each second chip to enter a low power state based on the received first communication data with a low power status flag and the corresponding receiving time. The second chip is a chip other than the first chip in the low power state synchronization control system. The preset time interval is less than or equal to the low power countdown.

[0007] After the low-power countdown ends, the first chip is controlled to enter a low-power state.

[0008] By continuously sending communication data with a low-power status flag to the second chip during the low-power countdown, the first chip can detect whether the first chip is about to enter a low-power state. When it is determined that the first chip is about to enter a low-power state after the low-power countdown ends, the second chip is synchronously controlled to enter a low-power state, and the first chip also enters a low-power state after the low-power countdown ends. This achieves the function of all chips in the low-power state synchronization control system entering low power synchronously, greatly improving the problem of low-power state synchronization lag between chips. It can meet the product's requirements for low-power synchronization performance, and there is no need to set up a status synchronization port, reducing the occupation of I / O ports. It is not affected by I / O port level fluctuations, and the reliability of low-power synchronization control is higher.

[0009] In an optional implementation, the method further includes:

[0010] When the low-power state synchronization control system detects that it does not meet the conditions for entering low power, it sends second communication data with a non-low-power state flag to each of the second chips at the preset time interval.

[0011] Thus, the first chip sends communication data with different flags to the second chip based on whether the low-power state synchronous control system has entered the low-power state condition, so as to further improve the accuracy of the second chip in judging whether the first chip has entered the low-power state and further improve the accuracy of synchronous low-power control.

[0012] In one optional implementation, after controlling the first chip to enter a low-power state, the method further includes:

[0013] The transmitting port of the first chip is set to output a fixed level, and the receiving port of the first chip is set to a low-power wake-up port, so as to control the first chip to exit the low-power state by detecting the level signal received by the low-power wake-up port.

[0014] After entering low power mode, the first chip sets its own transmitting port to a fixed level to distinguish it from the normal high and low level communication signals, thereby improving the accuracy of the second chip's judgment of the first chip's current state. It also sets the receiving port to a low power wake-up port to realize the external wake-up function of the first chip.

[0015] In one optional implementation, after controlling the first chip to enter a low-power state, the method further includes:

[0016] Upon detecting the first wake-up signal, the first chip is controlled to exit the low-power state and sends third communication data to each of the second chips, so that each of the second chips, upon receiving the third communication data, controls itself to exit the low-power state. The first wake-up signal is a signal that controls all chips in the low-power state synchronization control system to exit the low-power state.

[0017] Thus, by waking up the first chip when it detects a wake-up signal and sending communication data with a non-low power flag to the second chip, the synchronous wake-up function of the second chip and the first chip can be achieved.

[0018] In an optional implementation, the method further includes:

[0019] The system receives fourth communication data sent by the second chip, which is communication data fed back by the second chip after receiving the third communication data.

[0020] Thus, by receiving the third communication data sent by the first chip and feeding back the corresponding data, the second chip can determine that it is about to be woken up. After knowing the status of the second chip, the first chip can communicate with it normally.

[0021] In an optional implementation, the method further includes:

[0022] The system receives fifth communication data sent by the second chip. The fifth communication data is the communication data sent by the second chip when it detects a second wake-up signal. The second wake-up signal is a signal that controls all chips in the low-power state synchronization control system to exit the low-power state.

[0023] Based on the fifth communication data, the first chip is controlled to exit the low-power state, and the sixth communication data is sent to each of the second chips, so that the second chip enters the normal communication state when it receives the sixth communication data, and the remaining second chips are controlled to exit the low-power state when they receive the sixth communication data.

[0024] Thus, when the first chip receives communication data from the second chip, it determines that the second chip has received a wake-up signal, automatically controls the first chip to exit the low-power state, realizes the external wake-up function of the first chip, and synchronously controls the other second chips to exit the low-power state by sending communication data to the second chip. This realizes the synchronous wake-up control of all first chips and second chips, so as to ensure the state synchronization of each chip in the low-power state synchronous control system and meet the synchronization requirements of the product.

[0025] Secondly, the present invention provides a low-power state synchronization control method, applied to a second chip in a low-power state synchronization control system composed of at least two chips with low-power and communication functions, wherein the second chip is a chip that is synchronously controlled by the first chip in the low-power state synchronization control system to enter a low-power state, the method comprising:

[0026] Receive the first communication data sent by the first chip;

[0027] Determine whether the first communication data contains a low power state flag. The low power state flag is a flag that the first chip sends to each second chip at a preset time interval during the low power countdown period when it detects that the low power state synchronization control system meets the low power entry conditions. The preset time interval is less than or equal to the low power countdown.

[0028] When the first communication data contains a low-power status flag, record the time when the first communication data is received.

[0029] Based on the receiving time, if it is detected that the first communication data with a low power status flag sent by the first chip is continuously received within the first preset receiving time period according to the preset time interval, the second chip is controlled to enter the low power status, and the first preset receiving time period is not less than the low power countdown.

[0030] Therefore, the second chip determines whether the first chip has entered a low-power countdown by detecting whether the communication data sent by the first chip within a certain period of time contains a low-power status flag. After the low-power countdown of the first chip ends, the second chip is synchronously controlled to also enter a low-power state. This realizes the function of all chips in the low-power state synchronization control system entering low power synchronously, which greatly improves the problem of low-power state synchronization lag between chips. It can meet the product's requirements for low-power synchronization performance, and there is no need to set up a status synchronization port, reducing the occupation of I / O ports. It is not affected by I / O port level fluctuations, and the reliability of low-power synchronization control is higher.

[0031] In an optional implementation, the method further includes:

[0032] Upon receiving the third communication data sent by the first chip, the second chip is controlled to exit the low-power state. The third communication data is the communication data sent by the first chip to the second chip when it detects the first wake-up signal.

[0033] Thus, when the second chip receives the communication data sent by the first chip after it is woken up, it synchronously controls the second chip to exit the low-power state, thereby achieving synchronous control of the first chip and the second chip exiting the low-power state. This further improves the accuracy of the second chip in judging whether the first chip is entering the low-power state and further improves the precision of synchronous low-power control.

[0034] In an optional implementation, upon receiving third communication data sent by the first chip, the method further includes:

[0035] Send the fourth communication data to the first chip.

[0036] When the second chip receives the communication data that wakes up the first chip, it sends a corresponding communication signal back to the first chip, so that the first chip knows whether the second chip has been woken up. This further ensures that the first chip and the second chip exit the low-power state synchronously, thus achieving wake-up synchronization control.

[0037] In an optional implementation, the method further includes:

[0038] Based on the receiving time, if it is detected that communication data with a low-power status flag is continuously received from the first chip within the second preset receiving time period according to the preset time interval, the sending of communication data to the first chip is stopped, and the output of the sending port of the second chip is set to a fixed level. The second preset receiving time period is not less than the preset time interval and not greater than the low-power countdown.

[0039] Therefore, when the second chip determines that the first chip is about to enter a low-power state, it avoids erroneously waking up the first chip by stopping sending communication data to the first chip and setting the output of the sending port to a fixed level.

[0040] In an optional implementation, the method further includes:

[0041] When the second wake-up signal is detected, the second chip is controlled to exit the low-power state and sends the fifth communication data to the first chip, so that the first chip controls the first chip to exit the low-power state after receiving the fifth communication data. The second wake-up signal is a signal that controls all chips in the low-power state synchronization control system to exit the low-power state.

[0042] Thus, when the second chip detects the wake-up signal, the first chip is simultaneously woken up by sending communication data to the first chip.

[0043] In an optional implementation, the method further includes:

[0044] The sixth communication data sent by the first chip is communication data fed back by the first chip after receiving the fifth communication data.

[0045] Control the second chip to enter normal communication state.

[0046] By utilizing the communication data fed back by the first chip when it receives the communication data sent by the second chip to wake up the first chip, the second chip is controlled to enter the normal communication state, thereby realizing normal communication between the second chip and the first chip and further ensuring the synchronization and reliability of their states.

[0047] In one optional implementation, controlling the second chip to enter a low-power state includes:

[0048] The second chip is controlled to enter a low-power state after a fixed delay.

[0049] Therefore, by delaying its entry into the low-power state, the second chip avoids the problem of the first chip being woken up again immediately after entering the low-power state, which would cause the second chip to frequently switch states. This ensures that the second chip enters the low-power state synchronously only after the first chip has ensured that it has entered the low-power state, further improving the reliability of the product and enhancing the user experience.

[0050] Thirdly, the present invention provides a low-power state synchronization control system, comprising: a first chip and at least one second chip, wherein the first chip and the second chip are both chips with low power consumption and communication functions, the first chip is a chip that controls all chips in the low-power state synchronization control system to enter a low-power state, and the second chip is a chip in the low-power state synchronization control system other than the first chip.

[0051] When the first chip detects that the low-power state synchronization control system meets the low-power entry conditions, it starts the low-power entry countdown; it sends first communication data with a low-power state flag to each second chip at a preset time interval until the low-power countdown ends, and the preset time interval is less than or equal to the low-power countdown.

[0052] The second chip receives the first communication data sent by the first chip; determines whether the first communication data contains a low-power state flag; when the first communication data contains a low-power state flag, records the reception time of the first communication data; based on the reception time, if it is detected that the first communication data with a low-power state flag sent by the first chip is continuously received within a first preset reception duration according to the preset time interval, the second chip is controlled to enter a low-power state, and the first preset reception duration is not less than the low-power countdown.

[0053] After the low-power countdown ends, the first chip controls itself to enter a low-power state.

[0054] By utilizing the low-power status flag carried in the communication data sent by the first chip to the second chip during the low-power countdown, the second chip can accurately detect whether the first chip is about to enter a low-power state. This enables all chips in the low-power state synchronization control system to enter low-power state synchronously, greatly improving the problem of low-power state synchronization lag between chips. It can meet the product's requirements for low-power synchronization performance, and there is no need to set up a status synchronization port, reducing the occupation of I / O ports. It is not affected by I / O port level fluctuations, and the reliability of low-power synchronization control is higher.

[0055] In one alternative implementation, the first chip and the second chip communicate via a serial port.

[0056] By utilizing serial communication between the first and second chips for low-power state synchronization control, and using the transmit / receive ports as the medium for mutual wake-up of low power, the I / O port resources required for state synchronization can be saved.

[0057] In one alternative implementation, both the first chip and the second chip are MCUs.

[0058] Fourthly, the present invention provides an electrical device, comprising: a low-power state synchronization control system according to the third aspect or any corresponding embodiment thereof.

[0059] In one alternative implementation, the electrical device is an electric fan. Attached Figure Description

[0060] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0061] Figure 1 This is a structural block diagram of a low-power state synchronization control system according to an embodiment of the present invention;

[0062] Figure 2 This is a structural block diagram of an electrical device according to an embodiment of the present invention;

[0063] Figure 3 This is a schematic diagram of the interaction process of a low-power state synchronization control system according to an embodiment of the present invention;

[0064] Figure 4 This is a schematic diagram of another interaction process of the low-power state synchronization control system according to an embodiment of the present invention;

[0065] Figure 5 This is a schematic diagram of another interaction process of the low-power state synchronization control system according to an embodiment of the present invention;

[0066] Figure 6 This is a schematic diagram illustrating the specific working process of a low-power state synchronization control system according to an embodiment of the present invention. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0068] According to embodiments of the present invention, a low-power state synchronization control system is provided, such as... Figure 1 As shown, the low-power state synchronization control system includes a first chip 101 and a second chip 102. Both the first chip 101 and the second chip 102 are chips with low-power and communication functions. The first chip 101 controls all chips in the low-power state synchronization control system to enter a low-power state, and the second chip 102 is any chip in the low-power state synchronization control system other than the first chip 101. It should be noted that this embodiment of the invention uses a low-power state synchronization control system containing one second chip 102 as an example. In practical applications, the low-power state synchronization control system may also include two, three, or more second chips 102. The specific number of second chips 102 is related to the functional requirements of the actual low-power state synchronization control system, and this invention is not limited thereto.

[0069] When the first chip 101 detects that the low-power state synchronization control system meets the low-power entry conditions, it starts the low-power entry countdown; and sends first communication data with low-power state flags to each second chip 102 at preset time intervals until the low-power countdown ends, and the preset time interval is less than or equal to the low-power countdown.

[0070] The second chip 102 receives the first communication data sent by the first chip 101; determines whether the first communication data contains a low-power state flag; if the first communication data contains a low-power state flag, records the reception time of the first communication data; based on the reception time, if it is detected that the first communication data with a low-power state flag sent by the first chip 101 is continuously received within a preset reception duration at a preset time interval, the second chip 102 is controlled to enter a low-power state, and the first preset reception duration is not less than the low-power countdown.

[0071] After the low-power countdown ends, the first chip 101 is controlled to enter a low-power state.

[0072] The low-power state synchronization control system provided in this embodiment of the invention utilizes a low-power state flag sent by the first chip 101 to the second chip 102 during the low-power countdown. This facilitates the second chip 102's accurate detection of whether the first chip 101 is about to enter a low-power state, enabling all chips in the low-power state synchronization control system to enter low-power synchronously. This significantly improves the problem of low-power state synchronization lag between chips, meets the product's requirements for low-power synchronization performance, eliminates the need for a state synchronization port, reduces I / O port occupation, is unaffected by I / O port level fluctuations, and has higher reliability in low-power synchronization control.

[0073] The specific working principles and processes of the first chip 101 and the second chip 102 are described in the relevant descriptions of the method embodiments below, and will not be repeated here.

[0074] In some optional implementations, the first chip 101 and the second chip 102 communicate via a serial port. This allows for low-power state synchronization control through serial communication between the first chip 101 and the second chip 102, and uses the transmit / receive port as a medium for mutual wake-up, thus saving I / O port resources required for state synchronization.

[0075] Specifically, in this embodiment of the invention, the first chip 101 and the second chip 102 are both MCUs, wherein the first chip 101 is the main MCU and the second chip 102 is the secondary MCU. In practical applications, the first chip 101 and the second chip 102 can also be other chips with specific low power consumption and communication functions, such as microcontrollers, etc. The invention is not limited thereto.

[0076] In existing multi-MCU systems, to synchronize the low-power states of each MCU, an I / O port is needed as a status synchronization port to inform the other MCUs of their own status (via the high or low level of this I / O port). This method requires a certain amount of time for status detection, is easily affected by external interference (I / O port level fluctuations), has low reliability, and requires redundant I / O port resources.

[0077] The low-power state synchronization control scheme provided by this invention uses serial communication for low-power state synchronization. When the countdown for the main MCU to enter low-power mode is less than T1, it sends a low-power state flag bit to the secondary MCU until it enters low-power mode itself. If the secondary MCU detects the low-power flag bit continuously for T2 (T2≥T1), it considers the main MCU to be in low-power mode and controls itself to also enter low-power mode, thereby achieving synchronized control of the low-power states of multiple MCUs.

[0078] According to embodiments of the present invention, an electrical device is provided, such as... Figure 2 As shown, the electrical equipment includes: Figure 1 The low-power state synchronization control system 201 is shown. Exemplarily, this embodiment of the invention uses an electric fan as an example for explanation. In practical applications, the electrical device can also be other electrical devices composed of multiple chips requiring low-power state synchronization control, such as air conditioners, etc. The invention is not limited thereto.

[0079] Specifically, taking an electric fan as an example, the first chip 101 mentioned above is a chip on the main board of the electric fan, and the second chip 102 is a chip on the display board of the electric fan. In low power mode, the main board controls the main board and the display board to enter low power mode. When the user operates the display board, the display board and the main board are woken up, and the electric fan exits the low power mode.

[0080] The electrical equipment provided in this invention, by setting up a low-power state synchronization control system, utilizes a low-power state flag carried in the communication data sent by the first chip 101 to the second chip 102 during the low-power countdown. This facilitates the second chip 102's accurate detection of whether the first chip 101 is about to enter a low-power state, achieving the function of all chips in the low-power state synchronization control system entering low power synchronously. This significantly improves the problem of low-power state synchronization lag between chips, meets the product's requirements for low-power synchronization performance, and eliminates the need for a separate state synchronization port, reducing I / O port occupation and being unaffected by I / O port level fluctuations, resulting in higher reliability of low-power synchronization control. Furthermore, it improves the user experience of the electrical equipment and enhances the product performance.

[0081] According to an embodiment of the present invention, a low-power state synchronization control method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0082] This embodiment provides a low-power state synchronization control method, which can be used for, for example... Figure 1 The first chip 101 and the second chip 102 shown are, for example, MCUs, microcontrollers, etc. Figure 3 This is a schematic diagram of the interaction process of a low-power state synchronization control system according to an embodiment of the present invention. The first chip 101 is used to execute steps S101 to S103, and the second chip 102 is used to execute steps S201 to S204. The specific interaction process between the first chip 101 and the second chip 102 is as follows:

[0083] Step S101: When the low-power state synchronization control system is detected to meet the low-power entry conditions, start the low-power entry countdown.

[0084] Specifically, entering the low-power condition can be a user-operated low-power command, or it can be based on pre-set low-power conditions, such as determining that the low-power condition is met if no user operation is detected within a certain time. This is just one example, and the present invention is not limited thereto. The specific duration of the aforementioned low-power countdown T1 can be flexibly set according to the requirements of the low-power response time, such as T1 = 3s, etc., and the present invention is not limited thereto.

[0085] Step S102: Send first communication data with a low-power status flag to each second chip at preset time intervals until the low-power countdown ends.

[0086] The preset time interval can be flexibly set according to the detection requirements of the second chip. The preset time interval t is less than or equal to the low power countdown T1, such as t = 0.5s, etc. The present invention is not limited thereto.

[0087] Specifically, the low-power status flag can be carried in the normal communication data between the first chip and the second chip by setting a low-power status flag, so that it is not necessary to send separate communication data to enter low power mode. For example, if the low-power status flag is 1, it means that the first chip starts the countdown to enter low power mode, and if the low-power status flag is 0, it means that the first chip is in normal operation mode.

[0088] Step S201: Receive the first communication data sent by the first chip.

[0089] Step S202: Determine whether the first communication data contains a low-power status flag.

[0090] Specifically, the presence of a low-power status flag can be determined by detecting whether the low-power status flag bit in the communication data is 1.

[0091] Step S203: When the first communication data contains a low-power state flag, record the time when the first communication data is received.

[0092] Step S204: Based on the receiving time, if it is detected that the first communication data with a low power state flag sent by the first chip is continuously received within a preset time interval within a first preset receiving duration, the second chip is controlled to enter a low power state, and the first preset receiving duration is not less than the low power countdown.

[0093] Wherein, the first preset receiving time T2 is not less than the low-power countdown T1. For example, to avoid the influence of the preset time interval t, T2 can be slightly larger than T1, such as T2 = 3.5s. This is just an example, and the present invention is not limited thereto. This achieves the goal that the second chip knows as soon as the first chip enters the low-power state, so as to control the second chip to enter the low-power state synchronously with the first chip.

[0094] Step S103: After the low-power countdown ends, control the first chip to enter the low-power state.

[0095] Specifically, the first chip automatically enters the low-power state after the low-power countdown ends, so as to achieve the synchronization of the first chip and the second chip into the low-power state. It should be noted that due to the difference between T1 and T2, the first chip and the second chip may not enter the low-power state in absolute synchronization. However, the time difference between the two entering the low-power state is negligible relative to the product's synchronization control requirements, and can meet the product's requirements for low-power synchronous control.

[0096] By continuously sending communication data with a low-power status flag to the second chip during the low-power countdown, the first chip can detect whether the first chip is about to enter a low-power state. When it is determined that the first chip is about to enter a low-power state after the low-power countdown ends, the second chip is synchronously controlled to enter a low-power state, and the first chip also enters a low-power state after the low-power countdown ends. This achieves the function of all chips in the low-power state synchronization control system entering low power synchronously, greatly improving the problem of low-power state synchronization lag between chips. It can meet the product's requirements for low-power synchronization performance, and there is no need to set up a status synchronization port, reducing the occupation of I / O ports. It is not affected by I / O port level fluctuations, and the reliability of low-power synchronization control is higher.

[0097] This embodiment provides a low-power state synchronization control method, which can be used for, for example... Figure 1 The first chip 101 and the second chip 102 shown are, for example, MCUs, microcontrollers, etc. Figure 4 This is a schematic diagram of the interaction process of a low-power state synchronization control system according to an embodiment of the present invention. The first chip 101 is used to execute steps S301 to S307, and the second chip 102 is used to execute steps S401 to S407. The specific interaction process between the first chip 101 and the second chip 102 is as follows:

[0098] Step S301: When the low-power state synchronization control system detects that the low-power state entry condition is met, the low-power entry countdown is started. For details, please refer to... Figure 3 The specific description of step S101 shown will not be repeated here.

[0099] In some alternative implementations, when the low-power state synchronization control system is detected to not meet the conditions for entering low power, second communication data with a non-low-power state flag is sent to each second chip at preset time intervals.

[0100] For example, the low-power status flag can be carried in the normal communication data between the first chip and the second chip by setting a low-power status flag bit, so that it is not necessary to send separate communication data to enter low power. For example, assuming the low-power status flag bit is 1, it means that the first chip starts the countdown to enter low power, and the low-power status flag bit is 0, it means that the first chip does not meet the conditions to enter low power and it is in normal operation mode.

[0101] Thus, the first chip sends communication data with different flags to the second chip based on whether the low-power state synchronous control system has entered the low-power state condition, so as to further improve the accuracy of the second chip in judging whether the first chip has entered the low-power state and further improve the accuracy of synchronous low-power control.

[0102] Step S302: Send first communication data with a low-power status flag to each second chip at preset time intervals until the low-power countdown ends. For details, please refer to... Figure 3 The specific description of step S102 shown will not be repeated here.

[0103] Step S401: Receive the first communication data sent by the first chip. For details, please refer to... Figure 3 The specific description of step S201 shown will not be repeated here.

[0104] Step S402: Determine whether the first communication data contains a low-power status flag. For details, please refer to... Figure 3The specific description of step S202 shown will not be repeated here.

[0105] Step S403: If the first communication data contains a low-power state flag, record the reception time of the first communication data. For details, please refer to... Figure 3 The specific description of step S203 shown will not be repeated here.

[0106] Step S404: Based on the reception time, if it is detected that first communication data with a low-power state flag sent by the first chip is continuously received at preset time intervals within a first preset reception duration, the second chip is controlled to enter a low-power state. The first preset reception duration is not less than the low-power countdown. For details, please refer to... Figure 3 The specific description of step S204 shown will not be repeated here.

[0107] In some optional embodiments, controlling the second chip to enter a low-power state in step S404 above includes: controlling the second chip to enter a low-power state after a fixed delay.

[0108] The fixed delay time can be flexibly set according to the communication time interval between the first chip and the second chip and the product's requirements for synchronization control accuracy, so as to avoid the problem of frequent and unstable state switching of the second chip when the first chip is woken up just as the second chip enters the low power state. For example, the fixed delay time is 0.5s.

[0109] Therefore, by delaying its entry into the low-power state, the second chip avoids the problem of the first chip being woken up again immediately after entering the low-power state, which would cause the second chip to frequently switch states. This ensures that the second chip enters the low-power state synchronously only after the first chip has ensured that it has entered the low-power state, further improving the reliability of the product and enhancing the user experience.

[0110] Step S303: After the low-power countdown ends, control the first chip to enter a low-power state. For details, please refer to... Figure 3 The specific description of step S103 shown will not be repeated here.

[0111] Step S304: Set the output of the transmitting port of the first chip to a fixed level and set the receiving port of the first chip to a low-power wake-up port, so as to control the first chip to exit the low-power state by detecting the level signal received by the low-power wake-up port.

[0112] Specifically, the fixed level can be either a stable high-level signal or a stable low-level signal. Whether the fixed level is high or low can be determined according to actual needs. For example, if power consumption is a concern, a low-level signal with lower power consumption can be selected. This is not a mandatory requirement.

[0113] For example, for a timed wake-up MCU in low-power mode, this I / O port can be set as an input port. During the wake-up phase, the I / O port level is detected to determine whether to re-enter low-power mode. For an MCU that is always in low-power mode, this I / O port can be set as an external interrupt port. If the I / O port level changes, it will exit low-power mode. Which method to use depends on factors such as system stability. For example, if there are too many interference signals, the second method cannot be used, and a timed wake-up method is needed to filter out interference signals. This is just an example, and the present invention is not limited thereto.

[0114] After entering low power mode, the first chip sets its own transmitting port to a fixed level to distinguish it from the normal high and low level communication signals, thereby improving the accuracy of the second chip's judgment of the first chip's current state. It also sets the receiving port to a low power wake-up port to realize the external wake-up function of the first chip.

[0115] Step S405: Based on the receiving time, if it is detected that communication data with a low power status flag sent by the first chip is continuously received within a preset time interval during the second preset receiving duration, the sending of communication data to the first chip is stopped, and the output of the transmitting port of the second chip is set to a fixed level.

[0116] The second preset reception duration is not less than a preset time interval and not greater than a low-power countdown. For example, the second preset reception duration T3 is 2 seconds.

[0117] Specifically, setting the output of the second chip's transmitting port to a fixed level is similar to setting the first chip's transmitting port to a fixed level in step S304 above. For details, please refer to the relevant description of step S304 above, which will not be repeated here.

[0118] Therefore, when the second chip determines that the first chip is about to enter a low-power state, it avoids erroneously waking up the first chip by stopping sending communication data to the first chip and setting the sending port to a fixed level.

[0119] In step S305, when the first wake-up signal is detected, the first chip is controlled to exit the low-power state and send third communication data to each of the second chips.

[0120] The first wake-up signal is a signal used to control all chips in the low-power state synchronization system to exit the low-power state. This first wake-up signal is a user instruction to the first chip to exit the low-power state.

[0121] Thus, by waking up the first chip when it detects a wake-up signal and sending communication data with a non-low power flag to the second chip, the synchronous wake-up function of the second chip and the first chip can be achieved.

[0122] Step S406: Upon receiving the third communication data sent by the first chip, control the second chip to exit the low-power state.

[0123] Thus, the second chip synchronously controls the second chip to exit the low-power state when it receives the communication data sent by the first chip after it is woken up, thereby achieving synchronous control of the first chip and the second chip exiting the low-power state. This further improves the accuracy of the second chip in judging whether the first chip enters the low-power state and further improves the precision of synchronous low-power control.

[0124] Step S407: Upon receiving the third communication data sent by the first chip, send the fourth communication data to the first chip.

[0125] The fourth communication data is the response data corresponding to the third communication data. Under normal circumstances, during communication between the first chip and the second chip, when the first chip sends communication data to the second chip, the second chip will automatically send response data to the first chip upon receiving the communication data to inform the first chip that it has received the communication data. This is existing technology and will not be described in detail here.

[0126] When the second chip receives the communication data that wakes up the first chip, it sends a corresponding communication signal back to the first chip, so that the first chip knows whether the second chip has been woken up. This further ensures that the first chip and the second chip exit the low-power state synchronously, thus achieving wake-up synchronization control.

[0127] Step S306: Receive the fourth communication data sent by the second chip.

[0128] When the first chip receives the fourth communication data, it indicates that the second chip has received the communication data to exit the low-power state and is about to exit the low-power state.

[0129] Thus, by receiving communication data with a non-low power flag sent by the first chip, the second chip can determine that it is about to be woken up. After knowing the status of the second chip, the first chip can communicate with it normally.

[0130] This embodiment provides a low-power state synchronization control method, which can be used for, for example... Figure 1 The first chip 101 and the second chip 102 shown are, for example, MCUs, microcontrollers, etc. Figure 5This is a schematic diagram of the interaction process of a low-power state synchronization control system according to an embodiment of the present invention. The first chip 101 is used to execute steps S501 to S505, and the second chip 102 is used to execute steps S601 to S607. The specific interaction process between the first chip 101 and the second chip 102 is as follows:

[0131] Step S501: When the low-power state synchronization control system detects that the low-power state entry condition is met, the low-power entry countdown is started. For details, please refer to... Figure 4 The specific description of step S301 shown will not be repeated here.

[0132] Step S502: Send first communication data with a low-power status flag to each second chip at preset time intervals until the low-power countdown ends. For details, please refer to... Figure 4 The specific description of step S302 shown will not be repeated here.

[0133] Step S601: Receive the first communication data sent by the first chip. For details, please refer to... Figure 4 The specific description of step S401 shown will not be repeated here.

[0134] Step S602: Determine whether the first communication data contains a low-power status flag. For details, please refer to... Figure 4 The specific description of step S402 shown will not be repeated here.

[0135] Step S603: If the first communication data contains a low-power state flag, record the reception time of the first communication data. For details, please refer to... Figure 4 The specific description of step S403 shown will not be repeated here.

[0136] Step S604: Based on the reception time, if it is detected that first communication data with a low-power state flag sent by the first chip is continuously received at preset time intervals within a first preset reception duration, the second chip is controlled to enter a low-power state. The first preset reception duration is not less than a low-power countdown. For details, please refer to... Figure 4 The specific description of step S404 shown will not be repeated here.

[0137] Step S503: After the low-power countdown ends, control the first chip to enter a low-power state. For details, please refer to... Figure 4 The specific description of step S303 shown will not be repeated here.

[0138] In step S605, when the second wake-up signal is detected, the second chip is controlled to exit the low-power state and send the fifth communication data to the first chip.

[0139] The second wake-up signal is a signal used to control all chips in the low-power state synchronization system to exit the low-power state. This second wake-up signal is also a wake-up command corresponding to user operation of the second chip. In practical applications, the user can wake up the system through either the first chip or the second chip.

[0140] Thus, when the second chip detects the wake-up signal, the first chip is simultaneously woken up by sending communication data to the first chip.

[0141] Step S504: Receive the fifth communication data sent by the second chip.

[0142] Step S505: Based on the fifth communication data, control the first chip to exit the low-power state and send the sixth communication data to each of the second chips.

[0143] The sixth communication data is the communication data fed back from the first chip to each of the second chips when the first chip receives the fifth communication data. This is to enable the second chip to enter the normal communication state upon receiving the sixth communication data, and to enable the remaining second chips to exit the low-power state upon receiving the sixth communication data.

[0144] Thus, when the first chip receives communication data from the second chip, it determines that the second chip has received a wake-up signal, automatically controls the first chip to exit the low-power state, realizes the external wake-up function of the first chip, and synchronously controls the other second chips to exit the low-power state by sending communication data to the second chip. This realizes the synchronous wake-up control of all first chips and second chips, so as to ensure the state synchronization of each chip in the low-power state synchronous control system and meet the synchronization requirements of the product.

[0145] Step S606: Receive the sixth communication data sent by the first chip.

[0146] Step S607: Control the second chip to enter normal communication state.

[0147] Specifically, when the second chip receives the first communication data, it indicates that the first chip has exited the low-power state.

[0148] By utilizing the communication data fed back by the first chip when it receives the communication data sent by the second chip to wake up the first chip, the second chip is controlled to enter the normal communication state, thereby realizing normal communication between the second chip and the first chip and further ensuring the synchronization and reliability of their states.

[0149] The low-power state synchronization control method provided in this embodiment of the invention will be described in detail below with specific application examples.

[0150] Taking the low-power state synchronization control system with a first chip hereinafter referred to as the main MCU and a second chip hereinafter referred to as the sub-MCU as an example, where the main MCU is the MCU that "decides whether to enter the low-power state"; the sub-MCU is the MCU that "keeps the same state as the main MCU"; since some low-power wake-up signals can only be detected by the sub-MCU, there will be a situation where "the sub-MCU wakes up the main MCU in reverse", but in fact, whether to enter the low-power state is still determined by the main MCU.

[0151] As Figure 6 shown, between the main MCU and the sub-MCU, low-power state synchronization is carried out through serial communication, and the send / receive ports are used as the medium for waking each other up from low power. The main MCU continuously sends status flags to the sub-MCU (the sending interval time t < T1). If the countdown to enter low power is greater than T1, a non-low-power flag bit is sent, otherwise a low-power flag bit is sent (after meeting the low-power conditions, the low-power countdown starts).

[0152] Specifically, the main MCU judges whether it needs to enter the low-power state through external signals. When the main MCU judges that it needs to enter low power, it will start the low-power countdown. If no low-power wake-up signal is detected during the countdown, it will officially enter the low-power state at the end of the countdown. That is, a non-low-power flag bit is sent in the first half of this countdown, and a low-power flag bit is sent in the second half. After the main MCU enters low power, it stops data transmission and sets its own send port to a stable level. This stable level is the above-mentioned fixed level, which is used to distinguish from the waveforms during the communication between the main MCU and the sub-MCU (the high and low levels keep flipping). Its own receive port is set as a low-power wake-up port (such as an external interrupt port).

[0153] After the sub-MCU continuously detects the low-power flag bit sent by the main MCU for t1 (t1 < T1), it stops data feedback to the main MCU and sets its own transmit port to a stable level, so as to avoid incorrect wake-up of the main MCU by communication data. If the sub-MCU continuously detects the low-power flag bit sent by the main MCU for T2, it is considered that the main MCU has been in the low-power state. After a delay, the sub-MCU also enters the low-power mode and sets its own receive port as a low-power wake-up port. Through communication data, the main MCU can transmit its own state to the sub-MCU in advance, so that the sub-MCU knows as soon as the main MCU enters low power (T2 is slightly greater than T1). Exemplarily, t1 < T1 < T2.

[0154] When the main MCU has entered a low-power state, the secondary MCU detects a wake-up signal and, while waking itself up, continuously sends data to the main MCU through its own transmit port to wake it up. This can be achieved through high-low level transitions during serial data transmission, waking up another MCU in a low-power state. After receiving the communication data from the main MCU, it switches to normal operating mode (the low-power countdown is reset after the main MCU is woken up). In normal mode, the secondary MCU only replies to the corresponding command after receiving it from the main MCU, and only sends one frame of data. During the wake-up process, the secondary MCU continuously and cyclically sends data to wake up the main MCU. Low-power state refers to the chip's own mode. Compared to normal state, the chip shuts down most functions and peripherals in low-power state, thereby reducing power consumption.

[0155] When both the master and slave MCUs are in a low-power state, upon detecting a wake-up signal, either MCU will simultaneously wake itself up and begin sending communication data to the other to wake it up. After receiving the other's communication data, it will enter normal operating mode, i.e., normal communication state. MCUs waking each other up via serial communication saves I / O resources required for state synchronization.

[0156] In practical applications, IIC, SPI, or other methods can be used instead of serial ports, as long as the MCUs have two communication lines and can exchange information. Two MCUs with only two communication lines can achieve early synchronization in low-power states and mutual wake-up. Furthermore, for wireless communication, as long as the voltage levels at the MCU's I / O ports differ between communication and non-communication processes, this solution is also applicable.

[0157] To detect the voltage level at the low-power wake-up port, besides setting it as an external interrupt port, it can also be tested by periodically waking the device up to low power. If the wake-up signal is met, it will operate normally; otherwise, it will re-enter low power mode. Specifically, during the wake-up phase, the presence of a wake-up signal is determined by detecting the I / O port voltage level. Since wake-up and non-wake-up signals have characteristic differences, this can be determined by detecting the I / O port voltage level. By measuring the characteristics of the existing signal, it can be determined whether it is more similar to a wake-up signal or an interference signal, thus determining its nature. It should be noted that the characteristics of the wake-up signal are not fixed and need to be adjusted according to the actual project scheme, which will not be elaborated here.

[0158] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A low-power state synchronization control method, applied to a first chip in a low-power state synchronization control system composed of at least two chips with low-power and communication functions, wherein the first chip is the chip that controls all chips in the low-power state synchronization control system to enter a low-power state, characterized in that, The method includes: When the low-power state synchronization control system detects that it meets the low-power entry condition, it starts the low-power entry countdown. According to a preset time interval, first communication data with a low power status flag is sent to each second chip until the low power countdown ends, so that each second chip controls each second chip to enter a low power state based on the received first communication data with a low power status flag and the corresponding receiving time. The second chip is a chip other than the first chip in the low power state synchronization control system. The preset time interval is less than or equal to the low power countdown. After the low-power countdown ends, the first chip is controlled to enter a low-power state.

2. The method of claim 1, wherein, The method further includes: When the low-power state synchronization control system detects that it does not meet the conditions for entering low power, it sends second communication data with a non-low-power state flag to each of the second chips at the preset time interval.

3. The method of claim 1, wherein, After controlling the first chip to enter a low-power state, the method further includes: The transmitting port of the first chip is set to output a fixed level, and the receiving port of the first chip is set to a low-power wake-up port, so as to control the first chip to exit the low-power state by detecting the level signal received by the low-power wake-up port.

4. The method of claim 1, wherein, After controlling the first chip to enter a low-power state, the method further includes: Upon detecting the first wake-up signal, the first chip is controlled to exit the low-power state and sends third communication data to each of the second chips, so that each of the second chips, upon receiving the third communication data, controls itself to exit the low-power state. The first wake-up signal is a signal that controls all chips in the low-power state synchronization control system to exit the low-power state.

5. The method of claim 4, wherein, Also includes: The system receives fourth communication data sent by the second chip, which is communication data fed back by the second chip after receiving the third communication data.

6. The method according to any one of claims 1 to 5, characterized in that, Also includes: The system receives fifth communication data sent by the second chip. The fifth communication data is the communication data sent by the second chip when it detects a second wake-up signal. The second wake-up signal is a signal that controls all chips in the low-power state synchronization control system to exit the low-power state. Based on the fifth communication data, the first chip is controlled to exit the low-power state, and the sixth communication data is sent to each of the second chips, so that the second chip enters the normal communication state when it receives the sixth communication data, and the remaining second chips are controlled to exit the low-power state when they receive the sixth communication data.

7. A low-power state synchronization control method, applied to a second chip in a low-power state synchronization control system composed of at least two chips with low-power and communication functions, wherein the second chip is a chip that is synchronously controlled by the first chip in the low-power state synchronization control system to enter a low-power state, characterized in that, The method includes: Receive the first communication data sent by the first chip; Determine whether the first communication data contains a low power state flag. The low power state flag is a flag that the first chip sends to each second chip at a preset time interval during the low power countdown period when it detects that the low power state synchronization control system meets the low power entry conditions. The preset time interval is less than or equal to the low power countdown. When the first communication data contains a low-power status flag, record the time when the first communication data is received. Based on the receiving time, if it is detected that the first communication data with a low power status flag sent by the first chip is continuously received within the first preset receiving time period according to the preset time interval, the second chip is controlled to enter the low power status, and the first preset receiving time period is not less than the low power countdown.

8. The method of claim 7, wherein, Also includes: Upon receiving the third communication data sent by the first chip, the second chip is controlled to exit the low-power state. The third communication data is the communication data sent by the first chip to the second chip when it detects the first wake-up signal.

9. The method of claim 8, wherein, Upon receiving the third communication data sent by the first chip, the method further includes: Send the fourth communication data to the first chip.

10. The method of claim 7, wherein, The method further includes: Based on the receiving time, if it is detected that communication data with a low-power status flag is continuously received from the first chip within the second preset receiving time period according to the preset time interval, the sending of communication data to the first chip is stopped, and the output of the sending port of the second chip is set to a fixed level. The second preset receiving time period is not less than the preset time interval and not greater than the low-power countdown.

11. The method of claim 7, wherein, The process of controlling the second chip to enter a low-power state includes: The second chip is controlled to enter a low-power state after a fixed delay.

12. The method according to any one of claims 7-11, characterized in that, The method further includes: When the second wake-up signal is detected, the second chip is controlled to exit the low-power state and sends the fifth communication data to the first chip, so that the first chip controls the first chip to exit the low-power state after receiving the fifth communication data. The second wake-up signal is a signal that controls all chips in the low-power state synchronization control system to exit the low-power state.

13. The method of claim 12, wherein, The method further includes: The sixth communication data sent by the first chip is communication data fed back by the first chip after receiving the fifth communication data. Control the second chip to enter normal communication state.

14. A low power state synchronization control system, characterized by, include: A first chip and at least one second chip, wherein both the first chip and the second chip are chips with low power consumption and communication functions, the first chip is the chip that controls all chips in the low power state synchronization control system to enter the low power state, and the second chip is the chip in the low power state synchronization control system other than the first chip. When the first chip detects that the low-power state synchronization control system meets the low-power entry conditions, it starts the low-power entry countdown; it sends first communication data with a low-power state flag to each second chip at a preset time interval until the low-power countdown ends, and the preset time interval is less than or equal to the low-power countdown. The second chip receives the first communication data sent by the first chip; determines whether the first communication data contains a low-power status flag; and records the reception time of the first communication data when the first communication data contains a low-power status flag. Based on the receiving time, if it is detected that the first communication data with a low power state flag sent by the first chip is continuously received within the first preset receiving time period according to the preset time interval, the second chip is controlled to enter the low power state, and the first preset receiving time period is not less than the low power countdown. After the low-power countdown ends, the first chip controls itself to enter a low-power state.

15. The low-power state synchronization control system of claim 14, wherein, The first chip and the second chip communicate via a serial port.

16. The low-power state synchronization control system of claim 14 or 15, wherein, Both the first chip and the second chip are MCUs.

17. An electrical appliance, characterized in that, include: The low-power state synchronization control system as described in any one of claims 14-16.

18. The electrical equipment according to claim 17, characterized in that, The electrical device is an electric fan.

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