Shift register unit and driving method thereof, gate driving circuit, display device

Abstract

Provided are a shift register unit and a driving method thereof, a gate driving circuit and a display device, and belong to the technical field of display. The input circuit can control the potentials of the first node and the second node in response to the first clock signal; the output control circuit can control the on-off of the first clock end and the second node and the on-off of the third power supply end and the first node under the control of the potential of the first node; the output circuit can control the on-off of the second power supply end and the cascaded first output end and the on-off of the first power supply end and the second output end for driving the pixels under the control of the potential of the second node; and the output circuit can control the on-off of the second clock end and the first output end and the on-off of the third clock end and the second output end under the control of the potential of the first node. In this way, the signals provided by each end can be flexibly set, the output circuit reliably outputs the required potential signals to two output ends, and the potential of the first node ensures the reliable output of the output circuit.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register unit and its driving method, gate driving circuit, and display device. Background Technology

[0002] Gate drive circuits, also known as gate drive on array (GOA) circuits, typically include multiple cascaded GOA units (also called shift register units). These GOA units are coupled to multiple rows of pixels in a display device to scan and drive the pixels, enabling the display device to display an image.

[0003] In related technologies, a GOA (Getting Over-Ahead) unit generally includes an input circuit and an output circuit, with the input circuit further comprising multiple sub-circuits. These sub-circuits are coupled to multiple input signal terminals and an output node, respectively, and are used to control the potential of the output node based on signals provided by the multiple input signal terminals. The output circuit is coupled to the output node and an output terminal, and is used to transmit an output signal to the output terminal based on the potential of the output node. The output signal includes a clock signal and a constant-potential power supply signal.

[0004] However, due to the charging and discharging delays of transistors in various circuits, the stability of the output node potential controlled by the input circuit is poor, causing the output circuit to be unable to reliably transmit the output signal to the output terminal based on the output node potential. The output stability of the GOA unit in related technologies is also poor. Summary of the Invention

[0005] A shift register unit and its driving method, gate driving circuit, and display device are provided, which can solve the problem of poor output stability of GOA units in related technologies. The technical solution is as follows:

[0006] On the one hand, a shift register unit is provided, the shift register unit comprising:

[0007] The input circuit is coupled to a first clock terminal, a first power supply terminal, a start signal terminal, a first node, and a second node, respectively, and is used to control the on / off state of the start signal terminal and the first node in response to the first clock signal provided by the first clock terminal, and to control the on / off state of the first power supply terminal and the second node.

[0008] An output control circuit is coupled to the first node, the second node, the first clock terminal, the second clock terminal, the second power supply terminal, and the third power supply terminal, respectively. It is used to control the on / off state of the first clock terminal and the second node in response to the potential of the first node, and to control the on / off state of the third power supply terminal and the first node. It is also used to control the on / off state of the second power supply terminal and the first node in response to the potential of the second node and the second clock signal provided by the second clock terminal.

[0009] The output circuit is coupled to the first node, the second node, the second clock terminal, the first power supply terminal, the second power supply terminal, the third clock terminal, the first output terminal, and the second output terminal, respectively. It is used to control the switching between the second clock terminal and the first output terminal, and the switching between the third clock terminal and the second output terminal, in response to the potential of the first node. It is also used to control the switching between the second power supply terminal and the first output terminal, and the switching between the first power supply terminal and the second output terminal, in response to the potential of the second node. The first output terminal is coupled to the next-level shift register unit cascaded with the shift register unit, and the second output terminal is coupled to a pixel.

[0010] Optionally, the output circuit includes:

[0011] The first output sub-circuit is coupled to the first node, the second node, the second clock terminal, the second power supply terminal and the first output terminal respectively, and is used to control the on / off state of the second clock terminal and the first output terminal in response to the potential of the first node, and to control the on / off state of the second power supply terminal and the first output terminal in response to the potential of the second node.

[0012] The second output sub-circuit is coupled to the first node, the second node, the third clock terminal, the first power supply terminal, and the second output terminal, respectively. It is used to control the on / off state of the third clock terminal and the second output terminal in response to the potential of the first node, and to control the on / off state of the first power supply terminal and the second output terminal in response to the potential of the second node.

[0013] Optionally, the output control circuit includes:

[0014] A first control sub-circuit is coupled to the first node and the third power supply terminal respectively, and is used to control the connection and disconnection between the third power supply terminal and the first node in response to the potential of the first node.

[0015] The second control sub-circuit is coupled to the first node, the first clock terminal and the second node respectively, and is used to control the on / off state of the first clock terminal and the second node in response to the potential of the first node.

[0016] The third control sub-circuit is coupled to the second node, the second clock terminal, the second power supply terminal and the first node respectively, and is used to control the on / off state of the second power supply terminal and the first node in response to the potential of the second node and the second clock signal.

[0017] Optionally, the input circuit includes:

[0018] The first input sub-circuit is coupled to the first clock terminal, the start signal terminal and the first node respectively, and is used to control the on / off state of the start signal terminal and the first node in response to the first clock signal.

[0019] The second input sub-circuit is coupled to the first clock terminal, the first power supply terminal, and the second node, respectively, and is used to control the on / off state of the first power supply terminal and the second node in response to the first clock signal.

[0020] Optionally, the output circuit includes: a first output sub-circuit and a second output sub-circuit; the output control circuit includes: a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit; the first node includes: a first sub-node and a second sub-node; the shift register unit further includes:

[0021] A voltage regulator circuit is coupled to the first power supply terminal, the first sub-node and the second sub-node respectively, and is used to control the first sub-node and the second sub-node to be turned on in response to the first power signal provided by the first power supply terminal.

[0022] Furthermore, the first output sub-circuit is coupled to the second sub-node in the first node, and is used to control the on / off state of the second clock terminal and the first output terminal in response to the potential of the second sub-node; the second output sub-circuit is coupled to the first sub-node in the first node, and is used to control the on / off state of the third clock terminal and the second output terminal in response to the potential of the first sub-node.

[0023] The first control sub-circuit is coupled to the first sub-node and the second sub-node in the first node, and is used to control the connection and disconnection of the third power supply terminal with the first sub-node in response to the potential of the second sub-node; the second control sub-circuit and the third control sub-circuit are both coupled to the first sub-node in the first node, the second control sub-circuit is used to control the connection and disconnection of the first clock terminal with the second node in response to the potential of the first sub-node, and the third control sub-circuit is used to control the connection and disconnection of the second power supply terminal with the first sub-node in response to the potential of the second node and the second clock signal;

[0024] The first input sub-circuit is coupled to the first sub-node in the first node and is used to control the on / off state of the start signal terminal and the first sub-node in response to the first clock signal.

[0025] Optionally, the first node further includes a third sub-node; the voltage regulator circuit is also coupled to the third sub-node and is also used to control the first sub-node and the third sub-node to conduct in response to the first power signal.

[0026] The second output sub-circuit is coupled to the third sub-node in the first node and is used to control the on / off state of the third clock terminal and the second output terminal in response to the potential of the third sub-node.

[0027] Optionally, the voltage regulator circuit includes:

[0028] The first voltage regulator circuit is coupled to the first power supply terminal, the first sub-node and the second sub-node respectively, and is used to control the first sub-node and the second sub-node to be turned on in response to the first power supply signal.

[0029] The second voltage regulator circuit is coupled to the first power supply terminal, the first sub-node, and the third sub-node respectively, and is used to control the first sub-node and the third sub-node to conduct in response to the first power supply signal.

[0030] Optionally, the first voltage regulator sub-circuit includes a first transistor; the second voltage regulator sub-circuit includes a second transistor.

[0031] In this configuration, the gates of the first transistor and the second transistor are both coupled to the first power supply terminal, the first terminals of the first transistor and the second transistor are both coupled to the first sub-node, the second terminal of the first transistor is coupled to the second sub-node, and the second terminal of the second transistor is coupled to the third sub-node.

[0032] Optionally, the first output sub-circuit includes: a third transistor, a fourth transistor, and a first capacitor; the second output sub-circuit includes: a fifth transistor, a sixth transistor, and a second capacitor;

[0033] The gate of the third transistor is coupled to the second child node, the first terminal of the third transistor is coupled to the second clock terminal, and the second terminal of the third transistor is coupled to the first output terminal.

[0034] The gate of the fourth transistor is coupled to the second node, the first terminal of the fourth transistor is coupled to the second power supply terminal, and the second terminal of the fourth transistor is coupled to the first output terminal.

[0035] One end of the first capacitor is coupled to the second child node, and the other end of the first capacitor is coupled to the first output terminal;

[0036] The gate of the fifth transistor is coupled to the third child node, the first terminal of the fifth transistor is coupled to the third clock terminal, and the second terminal of the fifth transistor is coupled to the second output terminal.

[0037] The gate of the sixth transistor is coupled to the second node, the first terminal of the sixth transistor is coupled to the first power supply terminal, and the second terminal of the sixth transistor is coupled to the second output terminal.

[0038] One end of the second capacitor is coupled to the second node, and the other end of the second capacitor is coupled to the first power supply terminal.

[0039] Optionally, the first control sub-circuit includes a seventh transistor; the second control sub-circuit includes an eighth transistor; and the third control sub-circuit includes a ninth transistor and a tenth transistor.

[0040] The gate of the seventh transistor is coupled to the second sub-node, the first terminal of the seventh transistor is coupled to the third power supply terminal, and the second terminal of the seventh transistor is coupled to the first sub-node;

[0041] The gate of the eighth transistor is coupled to the first child node, the first terminal of the eighth transistor is coupled to the first clock terminal, and the second terminal of the eighth transistor is coupled to the second node;

[0042] The gate of the ninth transistor is coupled to the second node, the first terminal of the ninth transistor is coupled to the second power supply terminal, and the second terminal of the ninth transistor is coupled to the first terminal of the tenth transistor; the gate of the tenth transistor is coupled to the second clock terminal, and the second terminal of the tenth transistor is coupled to the first sub-node.

[0043] Optionally, the first input sub-circuit includes an eleventh transistor; the second input sub-circuit includes a twelfth transistor.

[0044] The gate of the eleventh transistor is coupled to the first clock terminal, the first terminal of the eleventh transistor is coupled to the start signal terminal, and the second terminal of the eleventh transistor is coupled to the first child node.

[0045] The gate of the twelfth transistor is coupled to the first clock terminal, the first terminal of the twelfth transistor is coupled to the first power supply terminal, and the second terminal of the twelfth transistor is coupled to the second node.

[0046] Optionally, the transistor in the shift register unit is made of low-temperature polycrystalline silicon; the transistor in the pixel to which the shift register unit is coupled is made of oxide.

[0047] On the other hand, a method for driving a shift register unit is provided, for driving the shift register unit as described in the above aspect; the method includes:

[0048] In the first stage, the potential of the start signal provided by the start signal terminal is the first potential, the potential of the first clock signal provided by the first clock terminal is the first potential and the second potential in sequence, and the potential of the second clock signal provided by the second clock terminal is the second potential and the first potential in sequence. The input circuit responds to the first clock signal, controls the start signal terminal to be first connected and then disconnected from the first node, and controls the first power supply terminal to be first connected and then disconnected from the second node. The output control circuit responds to the potential of the first node, controls the first clock terminal to be connected to the second node, and responds to the potential of the second node and the second clock signal, controls the second power supply terminal to be disconnected from the first node. The output circuit responds to the potential of the first node, controls the second clock terminal to be connected to the first output terminal, and controls the third clock terminal to be connected to the second output terminal, and responds to the potential of the second node, controls the second power supply terminal to be disconnected from the first output terminal, and controls the first power supply terminal to be disconnected from the second output terminal.

[0049] In the second stage, the potential of the starting signal is the second potential, the potential of the first clock signal is sequentially the first potential and the second potential, and the potential of the second clock signal is sequentially the second potential and the first potential. The input circuit, responding to the first clock signal, controls the starting signal terminal to be first connected and then disconnected from the first node, and controls the first power supply terminal to be first connected and then disconnected from the second node. The output control circuit, responding to the potential of the first node, controls the first clock terminal to be disconnected from the second node, and responding to the potential of the second node and the second clock signal, controls the second power supply terminal to be connected to the first node. The output circuit, responding to the potential of the first node, controls the second clock terminal to be disconnected from the first output terminal, and controls the third clock terminal to be disconnected from the second output terminal, and responding to the potential of the second node, controls the second power supply terminal to be connected to the first output terminal, and controls the first power supply terminal to be connected to the second output terminal.

[0050] During the same time period, the potential of the third clock signal provided by the third clock terminal is opposite to the potential of the second clock signal.

[0051] In another aspect, a gate driving circuit is provided, the gate driving circuit comprising: at least two cascaded shift register units as described in the preceding aspect.

[0052] In another aspect, a display device is provided, the display device comprising: a display panel, and a gate driving circuit as described in yet another aspect above;

[0053] The display panel includes multiple pixels, and the gate driving circuit is coupled to the multiple pixels and is used to transmit gate driving signals to the multiple pixels to drive the multiple pixels to emit light.

[0054] In summary, the beneficial effects of the technical solutions provided by the embodiments of this disclosure can at least include:

[0055] A shift register unit and its driving method, gate driving circuit, and display device are provided. The shift register unit includes an input circuit, an output control circuit, and an output circuit. The input circuit, responding to a first clock signal, controls the potentials of a first node and a second node. The output control circuit, under the potential control of the first node, controls the connection and disconnection between the first clock terminal and the second node, and also controls the connection and disconnection between the third power supply terminal and the first node. The output circuit, under the potential control of the second node, controls the connection and disconnection between the second power supply terminal and the cascaded first output terminal, and also controls the connection and disconnection between the first power supply terminal and the second output terminal driving the pixel. Furthermore, under the potential control of the first node, it controls the connection and disconnection between the second clock terminal and the first output terminal, and also controls the connection and disconnection between the third clock terminal and the second output terminal. Thus, by flexibly setting the signals provided by each terminal, the output circuit can reliably output the required potential signals to the first and second output terminals respectively, ensuring normal circuit operation, while also ensuring that the potential of the first node can guarantee reliable output from the output circuit, i.e., ensuring good output stability. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a schematic diagram of the structure of a shift register unit provided in an embodiment of this disclosure;

[0058] Figure 2 This is a schematic diagram of another shift register unit provided in an embodiment of this disclosure;

[0059] Figure 3This is a schematic diagram of the structure of another shift register unit provided in this embodiment;

[0060] Figure 4 This is a schematic diagram of another shift register unit provided in an embodiment of the present disclosure;

[0061] Figure 5 This is a schematic diagram of another shift register unit provided in an embodiment of the present disclosure;

[0062] Figure 6 This is a circuit structure diagram of a shift register unit provided in an embodiment of this disclosure;

[0063] Figure 7 This is a circuit structure diagram of another shift register unit provided in an embodiment of this disclosure;

[0064] Figure 8 This is a flowchart of a driving method for a shift register unit provided in an embodiment of this disclosure;

[0065] Figure 9 Is Figure 6 The following is a timing diagram of a shift register unit based on the above.

[0066] Figure 10 Is Figure 7 The following is a timing diagram of a shift register unit based on the above.

[0067] Figure 11 Is Figure 9 and Figure 10 A timing comparison diagram is shown based on the above.

[0068] Figure 12 Is Figure 11 The diagram illustrates a comparison of the first child node in a time series.

[0069] Figure 13 Is Figure 11 A comparative schematic diagram of the second output terminal in a timing sequence is shown below;

[0070] Figure 14 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present disclosure;

[0071] Figure 15 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0073] It should be noted that the transistors used in all embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of this disclosure are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this disclosure, the source is referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is designated as the control electrode, also known as the gate; the signal input terminal is the source; and the signal output terminal is the drain. Furthermore, the switching transistors used in the embodiments of this disclosure can include either P-type or N-type switching transistors. A P-type switching transistor conducts when the gate is low and is cut off when the gate is high, while an N-type switching transistor conducts when the gate is high and is cut off when the gate is low. Additionally, multiple signals in various embodiments of this disclosure correspond to a first potential and a second potential. The first potential and the second potential only represent that the signal has two potential states and do not represent that the first potential or the second potential has a specific value throughout the text.

[0074] In related technologies, to address the issue of insufficient charging in large-size, foldable (portrait) display products, it is necessary to develop and design discrete circuits with characteristics such as short scanning time and long compensation time. This allows for better compensation for high-resolution portraits, resulting in better display quality. Furthermore, to accommodate narrow bezel requirements, many display products use oxide materials to fabricate pixel circuits in the display area (N-type transistors), while simultaneously using low-temperature polysilicon (LTPS) materials to fabricate GOA circuits in the non-display area (P-type transistors). Display products based on this material combination can also be called low-temperature polysilicon oxide (LTPO) products. Therefore, the LTPS GOA circuit needs to transmit a high-potential gate drive signal to the oxide pixel circuit to control the writing of data signals, which is difficult to achieve with conventional GOA circuits.

[0075] This disclosure provides a GOA circuit for LTPO framework driving with good output stability. Figure 1 This is a schematic diagram of the structure of a shift register unit provided in an embodiment of this disclosure. For example... Figure 1 As shown, the shift register unit includes: input circuit 01, output control circuit 02, and output circuit 03.

[0076] The input circuit 01 is coupled to the first clock terminal CK1, the first power supply terminal VGL1, the start signal terminal STV, the first node N1, and the second node N2. The input circuit 01 is used to control the switching of the start signal terminal STV and the first node N1 in response to the first clock signal provided by the first clock terminal CK1, and to control the switching of the first power supply terminal VGL1 and the second node N2.

[0077] For example, when the potential of the first clock signal provided by the first clock terminal CK1 is a first potential, the input circuit 01 can control the start signal terminal STV to conduct with the first node N1 and control the first power supply terminal VGL1 to conduct with the second node N2, so that the start signal provided by the start signal terminal STV can be transmitted to the first node N1 and the first power supply signal provided by the first power supply terminal VGL1 can be transmitted to the second node N2. Furthermore, when the potential of the first clock signal provided by the first clock terminal CK1 is a second potential, the input circuit 01 can control the start signal terminal STV to decouple from the first node N1 and control the first power supply terminal VGL1 to decouple from the second node N2.

[0078] The output control circuit 02 is coupled to the first node N1, the second node N2, the first clock terminal CK1, the second clock terminal CK2, the second power supply terminal VGH, and the third power supply terminal VGL2, respectively. The output control circuit 02 is used to control the switching between the first clock terminal CK1 and the second node N2 in response to the potential of the first node N1, and to control the switching between the third power supply terminal VGL2 and the first node N1. It is also used to control the switching between the second power supply terminal VGH and the first node N1 in response to the potential of the second node N2 and the second clock signal provided by the second clock terminal CK2.

[0079] For example, when the potential of the first node N1 is at the first potential, the output control circuit 02 can control the first clock terminal CK1 to conduct with the second node N2, and control the third power supply terminal VGL2 to conduct with the first node N1, so that the first clock signal provided by the first clock terminal CK1 can be transmitted to the second node N2, and the third power supply signal provided by the third power supply terminal VGL2 can be transmitted to the first node N1. Furthermore, when the potential of the first node N1 is at the second potential, the output control circuit 02 can control the first clock terminal CK1 to decouple from the second node N2, and control the third power supply terminal VGL2 to decouple from the first node N1.

[0080] Similarly, when the potential of the second node N2 is the first potential and the potential of the second clock signal provided by the second clock terminal CB is the first potential, the output control circuit 02 can control the second power supply terminal VGH to conduct with the first node N1, so that the second power supply signal provided by the second power supply terminal VGH can be transmitted to the first node N1. Furthermore, when the potential of the second node N2 is the second potential and / or the potential of the second clock signal provided by the second clock terminal CB is the second potential, the output control circuit 02 can control the second power supply terminal VGH to decouple from the first node N1.

[0081] Output circuit 03 is coupled to the first node N1, the second node N2, the second clock terminal CK2, the first power supply terminal VGL1, the second power supply terminal VGH, the third clock terminal CK3, the first output terminal Pout, and the second output terminal Nout, respectively. Output circuit 03 is used to control the switching between the second clock terminal CK2 and the first output terminal Pout in response to the potential of the first node N1, and to control the switching between the third clock terminal CK3 and the second output terminal Nout; and to control the switching between the second power supply terminal VGH and the first output terminal Pout, and to control the switching between the first power supply terminal VGL1 and the second output terminal Nout, in response to the potential of the second node N2.

[0082] For example, when the potential of the first node N1 is the first potential, the output circuit 03 can control the second clock terminal CK2 to conduct with the first output terminal Pout, and control the third clock terminal CK3 to conduct with the second output terminal Nout, so that the second clock signal provided by the second clock terminal CK2 can be transmitted to the first output terminal Pout, and the third clock signal provided by the third clock terminal CK3 can be transmitted to the second output terminal Nout. Furthermore, when the potential of the first node N1 is the second potential, the output circuit 03 can control the second clock terminal CK2 to decouple from the first output terminal Pout, and control the third clock terminal CK3 to decouple from the second output terminal Nout.

[0083] Similarly, when the potential of the second node N2 is the first potential, the output circuit 03 can control the second power supply terminal VGH to conduct with the first output terminal Pout, and control the first power supply terminal VGL1 to conduct with the second output terminal Nout, so that the second power signal provided by the second power supply terminal VGH can be transmitted to the first output terminal Pout, and the first power signal provided by the first power supply terminal VGL1 can be transmitted to the second output terminal Nout. Furthermore, when the potential of the second node N2 is the second potential, the output circuit 03 can control the second power supply terminal VGH to decouple from the first output terminal Pout, and control the first power supply terminal VGL1 to decouple from the second output terminal Nout.

[0084] The first output terminal Pout is used to couple with the next-stage shift register unit cascaded with the shift register unit. Specifically, Pout can be coupled to the start signal terminal STV of the cascaded next-stage shift register unit to transmit the start signal. Correspondingly, Pout can also be called the cascaded output terminal. The second output terminal Nout is used to couple with the pixel. Specifically, Nout can be coupled to the gate of the transistor that provides the data signal among the multiple transistors included in the pixel circuit, to transmit the gate drive signal to that transistor, enabling the transistor to reliably control the writing of the data signal based on the received gate drive signal.

[0085] Optionally, in this embodiment, the first potential can be an active potential, the second potential can be an inactive potential, and the first potential can be a low potential relative to the second potential. The corresponding shift register unit can be made of LTPS material. Of course, in some other embodiments, the first potential can also be a high potential relative to the second potential. The potential of the first power signal provided by the first power supply terminal VGL1 and the potential of the third power signal provided by the third power supply terminal VGL2 can both be constant low potentials, and the potential of the third power signal can be less than or equal to the potential of the first power signal. The potential of the second power signal provided by the second power supply terminal VGH can be a constant high potential. Furthermore, in this embodiment, during the same time period, the potential of the first clock signal provided by the first clock terminal CK1 can be opposite to the potential of the second clock signal provided by the second clock terminal CK2, and the potential of the third clock signal provided by the third clock terminal CK3 can be opposite to the potential of the second clock signal provided by the second clock terminal CK2. Potential opposition can mean that one signal has a low potential and the other signal has a high potential.

[0086] As described in the above embodiments, for the shift register unit provided in this disclosure, the coupled signal potentials can be flexibly set so that, during the same period, the output circuit 03 can output output signals with opposite potentials to the first output terminal Pout and the second output terminal Nout respectively. For example, during the output period, a low-potential second clock signal is output to the first output terminal Pout, and a high-potential third clock signal is simultaneously output to the second output terminal Nout. The low-potential second clock signal can be transmitted to the start signal terminal STV of the next-stage shift register unit, ensuring reliable operation of the next-stage shift register unit; the high-potential third clock signal can be transmitted to the pixel circuit, such as that made of oxide material, ensuring reliable writing of data signals. During other periods, the output circuit 03 can output a high-potential second power supply signal to the first output terminal Pout, and simultaneously output a low-potential first power supply signal to the second output terminal Nout. Thus, in the scenario where the shift register unit is made of LTPS material, the purpose of reliably transmitting a high-potential gate drive signal to the oxide pixel circuit is achieved, ensuring the normal operation of the LTPO product.

[0087] Furthermore, in the shift register unit protected by this embodiment, not only is the input circuit 01 configured to control the potential of the first node N1 in response to the first clock signal provided by the first clock terminal CK1, but also an output control circuit 02 is configured to control the on / off state of the third power supply terminal VGL2 and the first node N1. Thus, when the potential of the first node N1 is low, the low-potential third power supply signal provided by the third power supply terminal VGL2 can further pull down the potential of the first node N1, thereby ensuring that the transistor in the output circuit 03 is fully turned on. This, in response to the even lower potential of the first node N1, reliably connects the second clock terminal CK2 and the first output terminal Pout, and reliably connects the third clock terminal CK3 and the second output terminal Nout, so as to reliably output the second clock signal to the first output terminal Pout and the third clock signal to the second output terminal Nout, thus ensuring good output stability.

[0088] In summary, this disclosure provides a shift register unit. The shift register unit includes an input circuit, an output control circuit, and an output circuit. The input circuit, responding to a first clock signal, controls the potentials of a first node and a second node. The output control circuit, under the potential control of the first node, controls the connection and disconnection between the first clock terminal and the second node, and also controls the connection and disconnection between the third power supply terminal and the first node. The output circuit, under the potential control of the second node, controls the connection and disconnection between the second power supply terminal and the cascaded first output terminal, and also controls the connection and disconnection between the first power supply terminal and the second output terminal driving the pixel. Furthermore, under the potential control of the first node, it controls the connection and disconnection between the second clock terminal and the first output terminal, and also controls the connection and disconnection between the third clock terminal and the second output terminal. Thus, by flexibly setting the signals provided by each terminal, the output circuit can reliably output the required potential signals to the first and second output terminals respectively, ensuring normal circuit operation, while also ensuring that the potential of the first node can guarantee reliable output from the output circuit, i.e., ensuring good output stability.

[0089] Optional, Figure 2 This is a schematic diagram of another shift register unit provided in an embodiment of this disclosure. For example... Figure 2 As shown, the input circuit 01 may include: a first input sub-circuit 011 and a second input sub-circuit 012.

[0090] The first input sub-circuit 011 can be coupled to the first clock terminal CK1, the start signal terminal STV, and the first node N1, respectively. The first input sub-circuit 011 can be used to control the on / off state of the start signal terminal STV and the first node N1 in response to the first clock signal.

[0091] For example, the first input sub-circuit 011 can control the start signal terminal STV to be turned on and the first node N1 to be turned on when the potential of the first clock signal is the first potential, and can control the start signal terminal STV to be disconnected from the first node N1 when the potential of the first clock signal is the second potential.

[0092] The second input sub-circuit 012 can be coupled to the first clock terminal CK1, the first power supply terminal VGL1, and the second node N2, respectively. The second input sub-circuit 012 can be used to control the on / off state of the first power supply terminal VGL1 and the second node N2 in response to the first clock signal.

[0093] For example, the second input sub-circuit 012 can control the first power supply terminal VGL1 to conduct with the second node N2 when the potential of the first clock signal is the first potential, and can control the first power supply terminal VGL1 to disconnect from the second node N2 when the potential of the first clock signal is the second potential.

[0094] Optional, continue to refer to Figure 2It can be seen that the output control circuit 02 may include: a first control sub-circuit 021, a second control sub-circuit 022, and a third control sub-circuit 023.

[0095] The first control sub-circuit 021 can be coupled to the first node N1 and the third power supply terminal VGL2 respectively. The first control sub-circuit 021 can be used to control the on / off state of the third power supply terminal VGL2 and the first node N1 in response to the potential of the first node N1.

[0096] For example, the first control sub-circuit 021 can control the third power supply terminal VGL2 to conduct with the first node N1 when the potential of the first node N1 is the first potential, and can control the third power supply terminal VGL2 to disconnect from the first node N1 when the potential of the first node N1 is the second potential.

[0097] The second control sub-circuit 022 can be coupled to the first node N1, the first clock terminal CK1, and the second node N2, respectively. The second control sub-circuit 022 can be used to control the on / off state of the first clock terminal CK1 and the second node N2 in response to the potential of the first node N1.

[0098] For example, the second control sub-circuit 022 can control the first clock terminal CK1 to conduct with the second node N2 when the potential of the first node N1 is the first potential, and can control the first clock terminal CK1 to disconnect from the second node N2 when the potential of the first node N1 is the second potential.

[0099] The third control sub-circuit 023 can be coupled to the second node N2, the second clock terminal CK2, the second power supply terminal VGH, and the first node N1, respectively. The third control sub-circuit 023 can be used to control the switching of the second power supply terminal VGH and the first node N1 in response to the potential of the second node N2 and the second clock signal.

[0100] For example, the third control sub-circuit 023 can control the second power supply terminal VGH to conduct with the first node N1 when the potential of the second node N2 is the first potential and the potential of the second clock signal is the first potential, and can control the second power supply terminal VGH to disconnect from the first node N1 when the potential of the second node N2 is the second potential and / or the potential of the second clock signal is the second potential.

[0101] Optional, continue to refer to Figure 2 It can be seen that the output circuit 03 may include: the first output sub-circuit 031 and the second output sub-circuit 032.

[0102] The first output sub-circuit 031 can be coupled to the first node N1, the second node N2, the second clock terminal CK2, the second power supply terminal VGH, and the first output terminal Pout, respectively. The first output sub-circuit 031 can be used to control the switching between the second clock terminal CK2 and the first output terminal Pout in response to the potential of the first node N1, and to control the switching between the second power supply terminal VGH and the first output terminal Pout in response to the potential of the second node N2.

[0103] For example, the first output sub-circuit 031 can control the second clock terminal CK2 to conduct with the first output terminal Pout when the potential of the first node N1 is at the first potential, and can control the second clock terminal CK2 to decouple from the first output terminal Pout when the potential of the first node N1 is at the second potential. Similarly, the first output sub-circuit 031 can control the second power supply terminal VGH to conduct with the first output terminal Pout when the potential of the second node N2 is at the first potential, and can control the second power supply terminal VGH to decouple from the first output terminal Pout when the potential of the second node N2 is at the second potential.

[0104] The second output sub-circuit 032 can be coupled to the first node N1, the second node N2, the third clock terminal CK3, the first power supply terminal VGL1, and the second output terminal Nout, respectively. The second output sub-circuit 032 can be used to control the switching of the third clock terminal CK3 and the second output terminal Nout in response to the potential of the first node N1, and to control the switching of the first power supply terminal VGL1 and the second output terminal Nout in response to the potential of the second node N2.

[0105] For example, the second output sub-circuit 032 can control the third clock terminal CK3 to conduct with the second output terminal Nout when the potential of the first node N1 is the first potential, and can control the third clock terminal CK3 to decouple from the second output terminal Nout when the potential of the first node N1 is the second potential. Similarly, the second output sub-circuit 032 can control the first power supply terminal VGL1 to conduct with the second output terminal Nout when the potential of the second node N2 is the first potential, and can control the first power supply terminal VGL1 to decouple from the second output terminal Nout when the potential of the second node N2 is the second potential.

[0106] Optional, Figure 3 This is a schematic diagram of the structure of another shift register unit provided in an embodiment of this disclosure. For example... Figure 3 As shown, the first node N1 may include: a first child node N11 and a second child node N12. Furthermore, the shift register unit may also include: a voltage regulator circuit 04.

[0107] The voltage regulator circuit 04 can be coupled to the first power supply terminal VGL1, the first sub-node N11, and the second sub-node N12, respectively. The voltage regulator circuit 04 can be used to control the first sub-node N11 and the second sub-node N12 to conduct in response to the first power supply signal provided by the first power supply terminal VGL1. That is, the voltage regulator circuit 04 can control the first sub-node N11 and the second sub-node N12 to be constantly conducting under the control of the first power supply signal at a constant low potential.

[0108] Based on the above node division, continue to refer to Figure 3 It can be seen that:

[0109] The first output sub-circuit 031 can be coupled to the second sub-node N12 in the first node N1. The first output sub-circuit 031 can be used to control the switching of the second clock terminal CK2 and the first output terminal Pout in response to the potential of the second sub-node N12. The second output sub-circuit 032 can be coupled to the first sub-node N11 in the first node N1. The second output sub-circuit 032 can be used to control the switching of the third clock terminal CK3 and the second output terminal Nout in response to the potential of the first sub-node N11.

[0110] That is, for example, the first output sub-circuit 031 can control the second clock terminal CK2 to conduct with the first output terminal Pout when the potential of the second sub-node N12 is the first potential, and can control the second clock terminal CK2 to decouple from the first output terminal Pout when the potential of the second sub-node N12 is the second potential. The second output sub-circuit 032 can control the third clock terminal CK3 to conduct with the second output terminal Nout when the potential of the first sub-node N11 is the first potential, and can control the third clock terminal CK3 to decouple from the second output terminal Nout when the potential of the first sub-node N11 is the second potential.

[0111] The first control sub-circuit 021 can be coupled to the first sub-node N11 and the second sub-node N12 in the first node N1, respectively. The first control sub-circuit 021 can be used to control the switching of the third power supply terminal VGL2 with the first sub-node N11 in response to the potential of the second sub-node N12. The second control sub-circuit 022 and the third control sub-circuit 023 can both be coupled to the first sub-node N11 in the first node N1. The second control sub-circuit 022 can be used to control the switching of the first clock terminal CK1 with the second node N2 in response to the potential of the first sub-node N11. The third control sub-circuit 023 can be used to control the switching of the second power supply terminal VGH with the first sub-node N11 in response to the potential of the second node N2 and the second clock signal.

[0112] That is, for example, the first control sub-circuit 021 can control the third power supply terminal VGL2 to conduct with the first sub-node N11 when the potential of the second sub-node N12 is the first potential, and can control the third power supply terminal VGL2 to decouple from the first sub-node N11 when the potential of the second sub-node N12 is the second potential. The second control sub-circuit 022 can control the first clock terminal CK1 to conduct with the second node N2 when the potential of the first sub-node N11 is the first potential, and can control the first clock terminal CK1 to decouple from the second node N2 when the potential of the first sub-node N11 is the second potential. The third control sub-circuit 023 can control the second power supply terminal VGH to conduct with the first sub-node N11 when the potential of the second node N2 and / or the potential of the second clock signal are both the first potential, and can control the second power supply terminal VGH to decouple from the first sub-node N11 when the potential of the second node N2 and / or the potential of the second clock signal are the second potential.

[0113] The first input sub-circuit 011 can be coupled to the first child node N11 in the first node N1. The first input sub-circuit 011 can be used to control the on / off state of the start signal terminal STV and the first child node N11 in response to the first clock signal.

[0114] That is, for example, the first input sub-circuit 011 can control the start signal terminal STV to conduct with the first sub-node N11 when the potential of the first clock signal is the first potential, and can control the start signal terminal STV to disconnect from the first sub-node N11 when the potential of the first clock signal is the second potential.

[0115] Optional, in Figure 3 Based on this, further reference Figure 4 As can be seen from the other shift register unit shown, the first node N1 may also include a third child node N13. The voltage regulator circuit 04 may also be coupled to the third child node N13, and the voltage regulator circuit 04 may also be used to control the first child node N11 and the third child node N13 to conduct in response to the first power supply signal. That is, the voltage regulator circuit 04 may also control the first child node N11 and the third child node N13 to be constantly conducting under the control of the first power supply signal with a constant low potential.

[0116] Based on this, continue to refer to Figure 4 It can be seen that the second output sub-circuit 032 can be coupled to the third sub-node N13 in the first node N1. The second output sub-circuit 032 can be used to control the on / off state of the third clock terminal CK3 and the second output terminal Nout in response to the potential of the third sub-node N13.

[0117] That is, for example, the second output sub-circuit 032 can control the third clock terminal CK3 and the second output terminal Nout to be turned on when the potential of the third sub-node N13 is the first potential, and can control the third clock terminal CK3 and the second output terminal Nout to be disconnected when the potential of the third sub-node N13 is the second potential.

[0118] Optional, in Figure 4 On this basis, Figure 5 A schematic diagram of another shift register unit provided in an embodiment of this disclosure is shown. Figure 5 As shown, the voltage regulator circuit 04 may include: a first voltage regulator sub-circuit 041 and a second voltage regulator sub-circuit 042.

[0119] The first voltage regulator circuit 041 can be coupled to the first power supply terminal VGL1, the first sub-node N11, and the second sub-node N12, respectively. The first voltage regulator circuit 041 can be used to control the first sub-node N11 and the second sub-node N12 to be turned on in response to the first power supply signal.

[0120] The second voltage regulator circuit 042 can be coupled to the first power supply terminal VGL1, the first sub-node N11, and the third sub-node N13, respectively. The second voltage regulator circuit 042 can be used to control the first sub-node N11 and the third sub-node N13 to conduct in response to the first power supply signal.

[0121] Optional, in Figure 3 On this basis, Figure 6 A circuit diagram of a shift register unit is shown. Figure 5 On this basis, Figure 7 A circuit diagram of a shift register unit is shown. (Reference) Figure 6 and Figure 7 It can be seen that the first voltage regulator circuit 041 may include: a first transistor T1. (Reference) Figure 7 It can be seen that the second voltage regulator circuit 042 may include: the second transistor T2.

[0122] The gate of the first transistor T1 and the gate of the second transistor T2 can both be coupled to the first power supply terminal VGL1. The first electrode of the first transistor T1 and the first electrode of the second transistor T2 can both be coupled to the first sub-node N11. The second electrode of the first transistor T1 can be coupled to the second sub-node N12. The second electrode of the second transistor T2 can be coupled to the third sub-node N13.

[0123] Optional, continue to refer to Figure 6 and Figure 7It can be seen that the first output sub-circuit 031 may include: a third transistor T3, a fourth transistor T4, and a first capacitor C1. The second output sub-circuit 032 may include: a fifth transistor T5, a sixth transistor T6, and a second capacitor C2.

[0124] The gate of the third transistor T3 can be coupled to the second child node N12, the first terminal of the third transistor T3 can be coupled to the second clock terminal CK2, and the second terminal of the third transistor T3 can be coupled to the first output terminal Pout.

[0125] The gate of the fourth transistor T4 can be coupled to the second node N2, the first terminal of the fourth transistor T4 can be coupled to the second power supply terminal VGH, and the second terminal of the fourth transistor T4 can be coupled to the first output terminal Pout.

[0126] One end of the first capacitor C1 can be coupled to the second child node N12, and the other end of the first capacitor C1 can be coupled to the first output terminal Pout.

[0127] The gate of the fifth transistor T5 can be coupled to the third child node N13, the first terminal of the fifth transistor T5 can be coupled to the third clock terminal CK3, and the second terminal of the fifth transistor T5 can be coupled to the second output terminal Nout.

[0128] The gate of the sixth transistor T6 can be coupled to the second node N2, the first terminal of the sixth transistor T6 can be coupled to the first power supply terminal VGL1, and the second terminal of the sixth transistor T6 can be coupled to the second output terminal Nout.

[0129] One end of the second capacitor C2 can be coupled to the second node N2, and the other end of the second capacitor C2 can be coupled to the first power supply terminal VGL1.

[0130] It should be noted that, for Figure 2 In the structure shown, the gates of the third transistor T3 and the fifth transistor T5 can both be directly coupled to the first node N1.

[0131] Optionally, in some other embodiments, in addition to the first capacitor C1, a capacitor can also be provided between the third child node N13 and the second output terminal Nout. Similarly, in addition to the second capacitor C2, a capacitor can also be provided between the second node N2 and the second power supply terminal VGH2. The capacitors can be used to store the node's potential, ensuring good potential stability of the node.

[0132] Optional, continue to refer to Figure 7 It can be seen that the first control sub-circuit 021 may include: the seventh transistor T7. (Continue to refer to...) Figure 6 and Figure 7It can be seen that the second control sub-circuit 022 may include: the eighth transistor T8. The third control sub-circuit 023 may include: the ninth transistor T9 and the tenth transistor T10.

[0133] The gate of the seventh transistor T7 can be coupled to the second sub-node N12, the first terminal of the seventh transistor T7 can be coupled to the third power supply terminal VGL2, and the second terminal of the seventh transistor T7 can be coupled to the first sub-node N11.

[0134] The gate of the eighth transistor T8 can be coupled to the first child node N11, the first terminal of the eighth transistor T8 can be coupled to the first clock terminal CK1, and the second terminal of the eighth transistor T8 can be coupled to the second node N2.

[0135] The gate of the ninth transistor T9 can be coupled to the second node N2, the first terminal of the ninth transistor T9 can be coupled to the second power supply terminal VGH, and the second terminal of the ninth transistor T9 can be coupled to the first terminal of the tenth transistor T10. The gate of the tenth transistor T10 can be coupled to the second clock terminal CK2, and the second terminal of the tenth transistor T10 can be coupled to the first child node N11. Figure 6 and Figure 7 The node where the second terminal of the ninth transistor T9 is coupled to the first terminal of the tenth transistor T10 is designated as the third node N3.

[0136] It should be noted that, for Figure 2 In the structure shown, the gate and first terminal of the seventh transistor T7, the gate of the eighth transistor T8, and the second terminal of the tenth transistor T10 can all be directly coupled to the first node N1.

[0137] Optional, continue to refer to Figure 6 and Figure 7 It can be seen that the first input sub-circuit 011 may include: the eleventh transistor T11. The second input sub-circuit 012 may include: the twelfth transistor T12.

[0138] Among them, the gate of the eleventh transistor T11 can be coupled to the first clock terminal CK1, the first terminal of the eleventh transistor T11 can be coupled to the start signal terminal STV, and the second terminal of the eleventh transistor T11 can be coupled to the first child node N11.

[0139] The gate of the twelfth transistor T12 can be coupled to the first clock terminal CK1, the first terminal of the twelfth transistor T12 can be coupled to the first power supply terminal VGL1, and the second terminal of the twelfth transistor T12 can be coupled to the second node N2.

[0140] It should be noted that, for Figure 2In the structure shown, the second terminal of the eleventh transistor T11 can be directly coupled to the first node N1.

[0141] It should be noted that, Figure 6 The shift register unit shown can be a 10T2C structure (i.e., it includes 10 transistors and 2 capacitors). Figure 7 The shift register unit shown can be a 12T2C structure (i.e., including 12 transistors and 2 capacitors). Of course, in some other embodiments, the shift register unit can also have other structures. This disclosure does not limit this aspect.

[0142] contrast Figure 6 and Figure 7 The structure shown, with the first control sub-circuit 021 (i.e., the seventh transistor T7) provided, compared to the structure without the first control sub-circuit 021, allows the potential of the first node N1 to be further pulled down to a low potential third power supply signal, thereby enabling the fifth transistor T5 in the output circuit 03 to be fully turned on, so as to stably and reliably output a signal to the second output terminal Nout of the driving pixel.

[0143] In addition, on the one hand, for Figure 6 Regarding the shift register unit structure of the first voltage regulator sub-circuit 041 (i.e., the first transistor T1): because the first voltage regulator sub-circuit 041 can separate the first sub-node N11 and the second sub-node N12, and control the first sub-node N11 and the second sub-node N12 to be constantly conducting, and the third transistor T3 in the first output sub-circuit 031 is coupled to the second sub-node N12, and responds to the potential of the second sub-node N12 to control the on / off of the second clock terminal CK2 and the first output terminal Pout, it can avoid the second clock signal jump provided by the second clock terminal CK2 from directly affecting the potential of the first sub-node N11, thus ensuring better potential stability of the first sub-node N11, thereby protecting other transistors directly coupled to the first sub-node N11 (such as the eighth transistor T8, the tenth transistor T10 and the eleventh transistor T11) from being broken down.

[0144] On the other hand, for Figure 7Regarding the shift register unit structure that also includes a second voltage regulator sub-circuit 042 (i.e., the second transistor T2): Similarly, since the second voltage regulator sub-circuit 042 can separate the first sub-node N11 and the third sub-node N13, and control the first sub-node N11 and the third sub-node N13 to be constantly conducting, and the fifth transistor T5 in the second output sub-circuit 032 is coupled to the third sub-node N13, and responds to the potential of the third sub-node N13 to control the on / off state of the third clock terminal CK3 and the second output terminal Nout, it can avoid the third clock signal jump provided by the third clock terminal CK3 from directly affecting the potential of the first sub-node N11, that is, it can also ensure that the potential stability of the first sub-node N11 is better, thereby further protecting other transistors directly coupled to the first sub-node N11 and preventing them from being broken down.

[0145] Optionally, as described in the above embodiments, the material of the transistor in the shift register unit protected by this disclosure may include: low-temperature polycrystalline silicon (LTPS) material. The material of the transistor in the pixel to which the shift register unit is coupled may include: oxide material. That is, it can be applied to LTPO products. Here, the transistor material refers to the material of the active layer included in the transistor. For LTPS material transistors, it can be a P-type transistor. Correspondingly, as described in the above embodiments, the first potential (i.e., the effective potential) can be a low potential, and the second potential (i.e., the ineffective potential) can be a high potential.

[0146] As described in the above embodiments, this disclosure, for products with an LTPO architecture, adds a seventh transistor T7 to transmit a low-potential third power signal to the first child node N11, thereby pulling down the potential of the first child node N11 and ensuring that the fifth transistor T5 can be fully turned on, thus allowing the second output terminal Nout to output normally and stably. On the other hand, a normally open second transistor T2 is also added to separate the first child node N11 from the third child node N13, protecting the eighth transistor T8, tenth transistor T10, and eleventh transistor T11, reducing the voltage difference between them, and preventing them from being damaged. The overall structure has lower power consumption and manufacturing cost, but better drive stability.

[0147] In summary, this disclosure provides a shift register unit. The shift register unit includes an input circuit, an output control circuit, and an output circuit. The input circuit, responding to a first clock signal, controls the potentials of a first node and a second node. The output control circuit, under the potential control of the first node, controls the connection and disconnection between the first clock terminal and the second node, and also controls the connection and disconnection between the third power supply terminal and the first node. The output circuit, under the potential control of the second node, controls the connection and disconnection between the second power supply terminal and the cascaded first output terminal, and also controls the connection and disconnection between the first power supply terminal and the second output terminal driving the pixel. Furthermore, under the potential control of the first node, it controls the connection and disconnection between the second clock terminal and the first output terminal, and also controls the connection and disconnection between the third clock terminal and the second output terminal. Thus, by flexibly setting the signals provided by each terminal, the output circuit can reliably output the required potential signals to the first and second output terminals respectively, ensuring normal circuit operation, while also ensuring that the potential of the first node can guarantee reliable output from the output circuit, i.e., ensuring good output stability.

[0148] Figure 8 This is a flowchart of a driving method for a shift register unit provided in an embodiment of this disclosure, used to drive such... Figures 1 to 7 Any of the shift register units shown. For example... Figure 8 As shown, the method includes:

[0149] Step 801, First Stage: The potential of the start signal provided by the start signal terminal is the first potential; the potential of the first clock signal provided by the first clock terminal is the first potential and the second potential in sequence; the potential of the second clock signal provided by the second clock terminal is the second potential and the first potential in sequence. The input circuit responds to the first clock signal, controlling the start signal terminal to be first connected and then disconnected from the first node, and controlling the first power supply terminal to be first connected and then disconnected from the second node. The output control circuit responds to the potential of the first node, controlling the first clock terminal to be connected to the second node, and responding to the potential of the second node and the second clock signal, controlling the second power supply terminal to be disconnected from the first node. The output circuit responds to the potential of the first node, controlling the second clock terminal to be connected to the first output terminal, and controlling the third clock terminal to be connected to the second output terminal, and responding to the potential of the second node, controlling the second power supply terminal to be disconnected from the first output terminal, and controlling the first power supply terminal to be disconnected from the second output terminal.

[0150] Step 802, Second Stage: The potential of the start signal is the second potential; the potential of the first clock signal is sequentially the first potential and the second potential; the potential of the second clock signal is sequentially the second potential and the first potential; the input circuit responds to the first clock signal, controlling the start signal terminal to be first connected and then disconnected from the first node, and controlling the first power supply terminal to be first connected and then disconnected from the second node; the output control circuit responds to the potential of the first node, controlling the first clock terminal to be disconnected from the second node, and responds to the potential of the second node and the second clock signal, controlling the second power supply terminal to be connected to the first node; the output circuit responds to the potential of the first node, controlling the second clock terminal to be disconnected from the first output terminal, and controlling the third clock terminal to be disconnected from the second output terminal, and responds to the potential of the second node, controlling the second power supply terminal to be connected to the first output terminal, and controlling the first power supply terminal to be connected to the second output terminal.

[0151] During the same time period, the potential of the third clock signal provided by the third clock terminal is opposite to the potential of the second clock signal.

[0152] Optional, with Figure 6 and Figure 7 The structure shown uses P-type transistors, with the effective potential being low and the inactive potential being high. Figure 9 and Figure 10 The timing diagrams for each shift register unit are shown in a one-to-one correspondence. Combined with... Figure 9 and Figure 10 The working principle of the shift register unit described in the embodiments of this disclosure is explained as follows:

[0153] First, in stages t01 and t02, the potential of the start signal provided by the start signal terminal STV is low. The potential of the first clock signal provided by the first clock terminal CK1 is initially low and then jumps to a high potential. The potential of the second clock signal provided by the second clock terminal CK2 is initially high and then jumps to a low potential. The potential of the third clock signal provided by the third clock terminal CK3 is initially low and then jumps to a high potential. Correspondingly, the eleventh transistor T11 and the twelfth transistor T12 are both turned on and then turned off, while the tenth transistor T10 is turned off and then turned on.

[0154] When the first clock signal is at a low potential, causing the eleventh transistor T11 and the twelfth transistor T12 to be turned on, the low-potential start signal provided by the start signal terminal STV can be transmitted to the first child node N11 via the turned-on eleventh transistor T11, and the low-potential first power signal provided by the first power supply terminal VGL1 can be transmitted to the second node N2 via the turned-on twelfth transistor T12, thus writing both the first child node N11 and the second node N2 to a low potential. At this time, because the potential of the second node N2 is low, the ninth transistor T9 is turned on, and the high-potential second power signal can be transmitted to the third node N3 via the turned-on ninth transistor T9. However, since the potential of the second clock signal is high at this time, the tenth transistor T10 is turned off, thereby preventing the high potential of the third node N3 from being further transmitted to the first child node N11. Furthermore, since the first transistor T1 is normally turned on under the control of the low-potential first power supply signal, it controls the first sub-node N11 and the second sub-node N12 to be normally conducted. Therefore, the low-potential start signal transmitted to the first sub-node N11 can be further transmitted to the second sub-node N12 via the first transistor T1. Under the storage function of the first capacitor C1, the potentials of the first sub-node N11 and the second sub-node N12 can be maintained at a low potential.

[0155] When the first clock signal is at a high potential, turning off the eleventh transistor T11 and the twelfth transistor T12, the eighth transistor T8 remains on because the potentials of both the first and second child nodes N11 and N12 are low. This allows the high-potential first clock signal to be transmitted to the second node N2 via the on-screen eighth transistor T8, effectively writing a high potential to the second node N2. At this point, although the second clock signal is at a low potential, turning on the tenth transistor T10, the ninth transistor T9 is off because the second node N2 is at a high potential. Therefore, the high-potential second power supply signal will not be transmitted to the third node N3, and thus will not affect the potential of the first child node N11.

[0156] That is, in stage t01, the potentials of the first child node N11 and the second child node N12 can both be low, the potential of the second node N2 can jump from low to high, and the potential of the third node N3 can be high. Furthermore, for Figure 7In the structure shown, since the potential of the second child node N12 is low, the seventh transistor T7 can be turned on. Therefore, the low-potential third power signal provided by the third power supply terminal VGL2 can be transmitted to the first child node N11 via the turned-on seventh transistor T7, further pulling down the potential of the first child node N11. Furthermore, the second transistor T2 is normally turned on under the control of the low-potential first power signal, controlling the first child node N11 and the third child node N13 to be normally conducting. Therefore, the low-potential start signal transmitted to the first child node N11 can be further transmitted to the third child node N13 via the second transistor T2. That is, refer to... Figure 11 As shown Figure 9 and Figure 10 Overall waveform comparison chart, and Figure 12 As shown Figure 9 and Figure 10 As can be seen from the comparison diagram of the first child node N11, Figure 7 Different from Figure 6 In this configuration, the first child node N11 has better potential stability, and the first node N1 also includes a third child node N13, whose potential is also low. Therefore, the third transistor T3 and the fifth transistor T5 can both be turned on, while the fourth transistor T4 and the sixth transistor T6 can both be turned off. Correspondingly, the second clock terminal CK2 can be connected to the first output terminal Pout, and the third clock terminal CK3 can be connected to the second output terminal Nout, while the second power supply terminal VGH is decoupled from the first output terminal Pout, and the first power supply terminal VGL1 is also decoupled from the second output terminal Nout. Therefore, the second clock signal provided by the second clock terminal CK2 can be transmitted to the first output terminal Pout, and the third clock signal provided by the third clock terminal CK3 can be transmitted to the second output terminal Nout. Since the potentials of the second clock signal and the third clock signal are high and low respectively in stage t01, a high-potential clock signal can be transmitted to the first output terminal Pout, and a low-potential clock signal can be transmitted to the second output terminal Nout in stage t01. Since the potentials of the second clock signal and the third clock signal are low and high respectively during the t02 stage, a low-potential clock signal can be transmitted to the first output terminal Pout and a high-potential clock signal can be transmitted to the second output terminal Nout during the t02 stage.

[0157] In addition, because Figure 7 Compared to Figure 6 In the structure shown, the first child node N11 has better stability, therefore, refer to... Figure 11 Overall waveform comparison chart, and Figure 13 As shown Figure 9 and Figure 10 As can be seen from the comparison chart of the second output terminal Nout, Figure 7 Different from Figure 6In this regard, the fifth transistor T5 is more fully turned on, and can more reliably output the third clock signal provided by the third clock terminal CK3 to the second output terminal Nout.

[0158] Secondly, in stages t03 and t04, the potential of the start signal provided by the start signal terminal STV is high, the potential of the first clock signal provided by the first clock terminal CK1 is initially low and then jumps to high, the potential of the second clock signal provided by the second clock terminal CK2 is initially high and then jumps to low, and the potential of the third clock signal provided by the third clock terminal CK3 is initially low and then jumps to high. Correspondingly, the eleventh transistor T11 and the twelfth transistor T12 are both turned on and then turned off, while the tenth transistor T10 is turned off and then turned on.

[0159] When the first clock signal is at a low potential, causing the eleventh transistor T11 and the twelfth transistor T12 to be turned on, the high-potential start signal provided by the start signal terminal STV can be transmitted to the first child node N11 via the turned-on eleventh transistor T11, and the low-potential first power signal provided by the first power supply terminal VGL1 can be transmitted to the second node N2 via the turned-on twelfth transistor T12. This results in the first child node N11 being written with a high potential, and the second node N2 being written with a low potential. At this time, because the potential of the second node N2 is low, the ninth transistor T9 is turned on, and the high-potential second power signal can be transmitted to the third node N3 via the turned-on ninth transistor T9. However, because the potential of the second clock signal is high at this time, the tenth transistor T10 is turned off, thereby preventing the high potential of the third node N3 from being further transmitted to the first child node N11. Furthermore, since the first transistor T1 is normally turned on under the control of the low-potential first power supply signal, it controls the first sub-node N11 and the second sub-node N12 to be normally conducted. Therefore, the high-potential start signal transmitted to the first sub-node N11 can be further transmitted to the second sub-node N12 via the first transistor T1. Under the storage function of the first capacitor C1, the potentials of the first sub-node N11 and the second sub-node N12 can be maintained at a high potential.

[0160] When the first clock signal is at a high potential, turning off the eleventh transistor T11 and the twelfth transistor T12, the eighth transistor T8 remains off because the potentials of both the first and second sub-nodes N11 and N12 are high. Furthermore, the second node N2 remains low due to the storage effect of the second capacitor C2. At this time, the tenth transistor T10 turns on because the second clock signal is low, and the ninth transistor T9 turns on because the potential of the second node N2 remains low. The high-potential second power supply signal is then transmitted to the third node N3 via the turned-on ninth transistor T9, and then to the first sub-node N11 via the turned-on tenth transistor T10, ensuring that the potential of the first sub-node N11 remains high. Based on the first transistor T1 controlling the constant conduction of the first sub-node N11 and the second sub-node N12, the potential of the second sub-node N12 is also ensured to remain high.

[0161] That is, in stage t01, the potentials of the first child node N11 and the second child node N12 can both be high, the potential of the second node N2 can remain low, and the potential of the third node N3 can be high. Furthermore, for Figure 7 In the illustrated structure, since the potential of the second sub-node N12 is high, the seventh transistor T7 can be turned off. Furthermore, the second transistor T2 is normally on under the control of a low-potential first power supply signal, controlling the first sub-node N11 and the third sub-node N13 to be normally on. Therefore, the high-potential start signal transmitted to the first sub-node N11 can be further transmitted to the third sub-node N13 via the second transistor T2. Consequently, the third transistor T3 and the fifth transistor T5 can both be turned off, while the fourth transistor T4 and the sixth transistor T6 can both be turned on. Correspondingly, the second power supply terminal VGH and the first output terminal Pout can be connected, and the first power supply terminal VGL1 and the second output terminal Nout can be connected. The second clock terminal CK2 is decoupled from the first output terminal Pout, and the third clock terminal CK3 is decoupled from the second output terminal Nout. Furthermore, the high-potential second power supply signal provided by the second power supply terminal VGH can be transmitted to the first output terminal Pout, and the low-potential first power supply signal provided by the first power supply terminal VGL1 can be transmitted to the second output terminal Nout. That is, in stages t03 and t04, a high-potential second power supply signal can be continuously transmitted to the first output terminal Pout, and a low-potential first power supply signal can be continuously transmitted to the second output terminal Nout.

[0162] It should be noted that the first stage corresponding to step 801 above can refer to... Figure 9 and Figure 10 The stages t01 and t02 shown, the second stage can refer to Figure 9 and Figure 10The stages t03 and t04 are shown.

[0163] In summary, this disclosure provides a driving method for a shift register unit. In this method, the input circuit can respond to a first clock signal to control the potentials of the first node and the second node; the output control circuit can control the connection and disconnection between the first clock terminal and the second node, and the connection and disconnection between the third power supply terminal and the first node, under the potential control of the first node; the output circuit can control the connection and disconnection between the second power supply terminal and the cascaded first output terminal, and the connection and disconnection between the first power supply terminal and the second output terminal of the driving pixel, under the potential control of the second node; and can control the connection and disconnection between the second clock terminal and the first output terminal, and the connection and disconnection between the third clock terminal and the second output terminal, under the potential control of the first node. Thus, by flexibly setting the signals provided by each terminal, the output circuit can reliably output the required potential signals to the first and second output terminals respectively, ensuring normal circuit operation, while also ensuring that the potential of the first node can ensure reliable output from the output circuit, i.e., ensuring good output stability.

[0164] Figure 14 This is a schematic diagram of a gate driving circuit provided in an embodiment of this disclosure. Figure 14 As shown, the gate drive circuit includes: at least two cascaded gates such as... Figures 1 to 7 Any of the shift register cells shown, 00. For example, Figure 14 The four cascaded shift register units 00_1, 00_2, 00_3, and 00_4 are shown.

[0165] Furthermore, based on the above embodiments, refer to Figure 14 It can be seen that each shift register unit 00 is coupled to the first output terminal Pout and the second output terminal Nout. In the two cascaded shift register units 00, the previous shift register unit 00 is coupled to the next shift register unit 00 through the first output terminal Pout, and each shift register unit 00 is coupled to the pixel through the second output terminal Nout.

[0166] Since the gate drive circuit can have essentially the same technical effect as the shift register unit described in the previous embodiment, for the sake of brevity, the technical effect of the gate drive circuit will not be described again here.

[0167] Figure 15 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Figure 15 As shown, the display device includes: a display panel 100, and as shown in the figure. Figure 14 The gate drive circuit shown is 000.

[0168] The display panel 100 includes multiple pixels ( Figure 15(Not shown), the gate drive circuit 000 is coupled to multiple pixels and is used to transmit gate drive signals to the multiple pixels to drive the multiple pixels to emit light.

[0169] Optionally, the display device described in the embodiments of this disclosure can be any product or component with display function, such as an active-matrix organic light-emitting diode (AMOLED) display device, an organic light-emitting diode (OLED) display device, or a liquid crystal display device.

[0170] Among them, AMOLED displays, with their low power consumption, wide operating temperature range, low cost, high contrast, wide viewing angle, wide color gamut, and thinner display panels, are capable of flexible displays and are gradually becoming the next generation of display crown jewels. OLED displays can meet most of the high-performance and high-capacity requirements of today's information age, and can be used for indoor and outdoor lighting, as wallpaper decorations, to make foldable electronic newspapers, and can also be applied to portable electronic products such as mobile phones, tablets, and wearable electronic devices.

[0171] Since the display device can have essentially the same technical effect as the gate driving circuit described in the previous embodiments, the technical effect of the gate driving circuit will not be described again here for the sake of brevity.

[0172] It should be noted that the terminology used in the embodiments of this disclosure is for illustrative purposes only and is not intended to limit the scope of this disclosure. Unless otherwise defined, the technical or scientific terms used in the implementation of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains.

[0173] For example, the terms “first,” “second,” or “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0174] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0175] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0176] Terms like "up," "down," "left," or "right" are used only to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connection" or "coupled" refers to an electrical connection.

[0177] The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0178] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A shift register unit, comprising: The input circuit is coupled to a first clock terminal, a first power supply terminal, a start signal terminal, a first node, and a second node, and is used to control the on / off state of the start signal terminal and the first node, and to control the on / off state of the first power supply terminal and the second node in response to the first clock signal provided by the first clock terminal. The first control sub-circuit is coupled to the first node and the third power supply terminal, and is used to control the connection and disconnection between the third power supply terminal and the first node in response to the potential of the first node. The second control sub-circuit, coupled to the first node, the first clock terminal, and the second node, is used to control the on / off state of the first clock terminal and the second node in response to the potential of the first node. The third control sub-circuit is coupled to the second node, the second clock terminal, the second power supply terminal and the first node, and is used to control the on / off state of the second power supply terminal and the first node in response to the potential of the second node and the second clock signal provided by the second clock terminal. The output circuit is coupled to a first node, a second node, a second clock terminal, a first power supply terminal, a second power supply terminal, a third clock terminal, a first output terminal, and a second output terminal. It is used to control the switching between the second clock terminal and the first output terminal in response to the potential of the first node, and to control the switching between the third clock terminal and the second output terminal. It also controls the switching between the second power supply terminal and the first output terminal in response to the potential of the second node, and to control the switching between the first power supply terminal and the second output terminal. The second power supply signal provided by the second power supply terminal has a potential opposite to the first power supply signal provided by the first power supply terminal, and the third clock signal provided by the third clock terminal is an inverted signal of the second clock terminal.

2. The shift register unit according to claim 1, characterized in that, The output circuit includes: The first output sub-circuit is coupled to the first node, the second node, the second clock terminal, the second power supply terminal and the first output terminal respectively, and is used to control the on / off state of the second clock terminal and the first output terminal in response to the potential of the first node, and to control the on / off state of the second power supply terminal and the first output terminal in response to the potential of the second node. The second output sub-circuit is coupled to the first node, the second node, the third clock terminal, the first power supply terminal, and the second output terminal, respectively. It is used to control the on / off state of the third clock terminal and the second output terminal in response to the potential of the first node, and to control the on / off state of the first power supply terminal and the second output terminal in response to the potential of the second node.

3. The shift register unit according to claim 1, characterized in that, The input circuit includes: The first input sub-circuit is coupled to the first clock terminal, the start signal terminal and the first node respectively, and is used to control the on / off state of the start signal terminal and the first node in response to the first clock signal. The second input sub-circuit is coupled to the first clock terminal, the first power supply terminal, and the second node, respectively, and is used to control the on / off state of the first power supply terminal and the second node in response to the first clock signal.

4. The shift register unit according to claim 3, characterized in that, The output circuit includes: a first output sub-circuit and a second output sub-circuit; the output control circuit includes: a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit; the first node includes: a first sub-node and a second sub-node; the shift register unit further includes: A voltage regulator circuit is coupled to the first power supply terminal, the first sub-node and the second sub-node respectively, and is used to control the first sub-node and the second sub-node to be turned on in response to the first power signal provided by the first power supply terminal. Furthermore, the first output sub-circuit is coupled to the second sub-node in the first node, and is used to control the on / off state of the second clock terminal and the first output terminal in response to the potential of the second sub-node; the second output sub-circuit is coupled to the first sub-node in the first node, and is used to control the on / off state of the third clock terminal and the second output terminal in response to the potential of the first sub-node. The first control sub-circuit is coupled to the first sub-node and the second sub-node in the first node, and is used to control the connection and disconnection of the third power supply terminal with the first sub-node in response to the potential of the second sub-node; the second control sub-circuit and the third control sub-circuit are both coupled to the first sub-node in the first node, the second control sub-circuit is used to control the connection and disconnection of the first clock terminal with the second node in response to the potential of the first sub-node, and the third control sub-circuit is used to control the connection and disconnection of the second power supply terminal with the first sub-node in response to the potential of the second node and the second clock signal; The first input sub-circuit is coupled to the first sub-node in the first node and is used to control the on / off state of the start signal terminal and the first sub-node in response to the first clock signal.

5. The shift register unit according to claim 4, characterized in that, The first node further includes a third sub-node; the voltage regulator circuit is also coupled to the third sub-node and is also used to control the first sub-node and the third sub-node to conduct in response to the first power signal. The second output sub-circuit is coupled to the third sub-node in the first node and is used to control the on / off state of the third clock terminal and the second output terminal in response to the potential of the third sub-node.

6. The shift register unit according to claim 5, characterized in that, The voltage regulator circuit includes: The first voltage regulator circuit is coupled to the first power supply terminal, the first sub-node and the second sub-node respectively, and is used to control the first sub-node and the second sub-node to be turned on in response to the first power supply signal. The second voltage regulator circuit is coupled to the first power supply terminal, the first sub-node, and the third sub-node respectively, and is used to control the first sub-node and the third sub-node to conduct in response to the first power supply signal.

7. The shift register unit according to claim 6, characterized in that, The first voltage regulator circuit includes a first transistor; the second voltage regulator circuit includes a second transistor. In this configuration, the gates of the first transistor and the second transistor are both coupled to the first power supply terminal, the first terminals of the first transistor and the second transistor are both coupled to the first sub-node, the second terminal of the first transistor is coupled to the second sub-node, and the second terminal of the second transistor is coupled to the third sub-node.

8. The shift register unit according to any one of claims 5 to 7, characterized in that, The first output sub-circuit includes: a third transistor, a fourth transistor, and a first capacitor; the second output sub-circuit includes: a fifth transistor, a sixth transistor, and a second capacitor; The gate of the third transistor is coupled to the second child node, the first terminal of the third transistor is coupled to the second clock terminal, and the second terminal of the third transistor is coupled to the first output terminal. The gate of the fourth transistor is coupled to the second node, the first terminal of the fourth transistor is coupled to the second power supply terminal, and the second terminal of the fourth transistor is coupled to the first output terminal. One end of the first capacitor is coupled to the second child node, and the other end of the first capacitor is coupled to the first output terminal; The gate of the fifth transistor is coupled to the third child node, the first terminal of the fifth transistor is coupled to the third clock terminal, and the second terminal of the fifth transistor is coupled to the second output terminal. The gate of the sixth transistor is coupled to the second node, the first terminal of the sixth transistor is coupled to the first power supply terminal, and the second terminal of the sixth transistor is coupled to the second output terminal. One end of the second capacitor is coupled to the second node, and the other end of the second capacitor is coupled to the first power supply terminal.

9. The shift register unit according to any one of claims 4 to 7, characterized in that, The first control sub-circuit includes a seventh transistor; the second control sub-circuit includes an eighth transistor; the third control sub-circuit includes a ninth transistor and a tenth transistor. The gate of the seventh transistor is coupled to the second sub-node, the first terminal of the seventh transistor is coupled to the third power supply terminal, and the second terminal of the seventh transistor is coupled to the first sub-node; The gate of the eighth transistor is coupled to the first child node, the first terminal of the eighth transistor is coupled to the first clock terminal, and the second terminal of the eighth transistor is coupled to the second node; The gate of the ninth transistor is coupled to the second node, the first terminal of the ninth transistor is coupled to the second power supply terminal, and the second terminal of the ninth transistor is coupled to the first terminal of the tenth transistor; the gate of the tenth transistor is coupled to the second clock terminal, and the second terminal of the tenth transistor is coupled to the first sub-node.

10. The shift register unit according to any one of claims 4 to 7, characterized in that, The first input sub-circuit includes an eleventh transistor; the second input sub-circuit includes a twelfth transistor. The gate of the eleventh transistor is coupled to the first clock terminal, the first terminal of the eleventh transistor is coupled to the start signal terminal, and the second terminal of the eleventh transistor is coupled to the first child node. The gate of the twelfth transistor is coupled to the first clock terminal, the first terminal of the twelfth transistor is coupled to the first power supply terminal, and the second terminal of the twelfth transistor is coupled to the second node.

11. The shift register unit according to any one of claims 1 to 7, characterized in that, The transistors in the shift register unit are made of low-temperature polycrystalline silicon; the transistors in the pixels coupled by the shift register unit are made of oxide.

12. A method for driving a shift register unit, characterized in that, For driving a shift register unit as described in any one of claims 1 to 11; the method includes: In the first stage, the potential of the start signal provided by the start signal terminal is the first potential, the potential of the first clock signal provided by the first clock terminal is the first potential and the second potential in sequence, and the potential of the second clock signal provided by the second clock terminal is the second potential and the first potential in sequence. The input circuit responds to the first clock signal, controls the start signal terminal to be first connected and then disconnected from the first node, and controls the first power supply terminal to be first connected and then disconnected from the second node. The output control circuit responds to the potential of the first node, controls the first clock terminal to be connected to the second node, and responds to the potential of the second node and the second clock signal, controls the second power supply terminal to be disconnected from the first node. The output circuit responds to the potential of the first node, controls the second clock terminal to be connected to the first output terminal, and controls the third clock terminal to be connected to the second output terminal, and responds to the potential of the second node, controls the second power supply terminal to be disconnected from the first output terminal, and controls the first power supply terminal to be disconnected from the second output terminal. In the second stage, the potential of the starting signal is the second potential, the potential of the first clock signal is sequentially the first potential and the second potential, and the potential of the second clock signal is sequentially the second potential and the first potential. The input circuit, responding to the first clock signal, controls the starting signal terminal to be first connected and then disconnected from the first node, and controls the first power supply terminal to be first connected and then disconnected from the second node. The output control circuit, responding to the potential of the first node, controls the first clock terminal to be disconnected from the second node, and responding to the potential of the second node and the second clock signal, controls the second power supply terminal to be connected to the first node. The output circuit, responding to the potential of the first node, controls the second clock terminal to be disconnected from the first output terminal, and controls the third clock terminal to be disconnected from the second output terminal, and responding to the potential of the second node, controls the second power supply terminal to be connected to the first output terminal, and controls the first power supply terminal to be connected to the second output terminal. During the same time period, the potential of the third clock signal provided by the third clock terminal is opposite to the potential of the second clock signal.

13. A gate driving circuit, characterized in that, The gate drive circuit includes at least two cascaded shift register units as described in any one of claims 1 to 11.

14. A display device, characterized in that, The display device includes: a display panel, and a gate driving circuit as described in claim 13; The display panel includes multiple pixels, and the gate driving circuit is coupled to the multiple pixels and is used to transmit gate driving signals to the multiple pixels to drive the multiple pixels to emit light.

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