LCD panels and LCD monitors

Abstract

This application discloses a liquid crystal display panel and a liquid crystal display, belonging to the technical field of liquid crystal display devices. The liquid crystal display panel includes a display area and a non-display area surrounding the display area. A clock signal line, a scan driving circuit, and at least one inductor are disposed in the non-display area. The display area is provided with multiple scan lines spaced apart and arranged along a first direction, and multiple data lines spaced apart and insulated from the scan lines. Each scan driving unit is connected to a scan line in a one-to-one correspondence; each scan driving unit is connected to a corresponding clock signal line, and at least one scan driving unit is connected to the corresponding clock signal line with an inductor. For signal lines with large RC delays, this application reduces the RC delay effect by connecting an inductor between the corresponding scan driving unit and the corresponding clock signal line, effectively solving the problem of insufficient or incorrect charging of the pixel area and improving display quality.

Description

Technical Field

[0001] This application relates to the field of liquid crystal display technology, and more particularly to a liquid crystal display panel and a liquid crystal display. Background Technology

[0002] Liquid crystal display devices experience RC delay due to the parasitic resistance and capacitance of signal lines on the substrate. This delay effect causes changes in the signal waveform. During display, some signal lines may exhibit significant RC delay, leading to insufficient or incorrect charging of pixel areas, severely impacting display quality. Summary of the Invention

[0003] The main objective of this application is to provide a liquid crystal display panel and a liquid crystal display. The aim is to reduce the RC delay effect by connecting an inductor between the corresponding scan driving unit and the corresponding clock signal line for signal lines with large RC delays, effectively solving the problem of insufficient or incorrect charging of pixel areas and improving display quality.

[0004] To achieve the above objectives, a first aspect of this application provides a liquid crystal display panel, including a display area and a non-display area surrounding the display area;

[0005] The non-display area is provided with clock signal lines, a scan drive circuit and at least one inductor. Multiple clock signal lines are arranged along a first direction. The scan drive circuit includes multiple cascaded scan drive units, which are arranged along a second direction, which intersects the first direction.

[0006] The display area is provided with multiple scan lines spaced apart and arranged along the first direction, and multiple data lines spaced apart and insulated from the scan lines;

[0007] Each of the scan driving units is connected to a scan line in a one-to-one correspondence;

[0008] Each of the scan drive units is connected to a corresponding clock signal line, and at least one of the scan drive units is connected to an inductor between itself and the corresponding clock signal line.

[0009] In one embodiment of this application, the liquid crystal display panel is further provided with a source driving circuit board; the distance between the scan driving unit and the source driving circuit board is positively correlated with the inductance of the inductor connected between the scan driving unit and the corresponding clock signal line.

[0010] In one embodiment of this application, the liquid crystal display panel is further provided with a source driving circuit board; with the source driving circuit board as the starting position, multiple regions are arranged sequentially in the second direction along the direction close to the scan driving unit, and adjacent regions are adjacent to each other. The inductance of the inductor connected between each scan driving unit falling into the region and the corresponding clock signal line is the same, and the inductance of the inductor connected between the scan driving unit and the corresponding clock signal line in the multiple regions increases sequentially.

[0011] In one embodiment of this application, with the source drive circuit board as the starting position, a first region, a second region, and a third region are arranged sequentially in the second direction along the direction close to the scan drive unit; each scan drive unit falling into the third region is connected to the corresponding clock signal line with a first inductor, and each scan drive unit falling into the second region is connected to the corresponding clock signal line with a second inductor; the inductance of the first inductor is greater than the inductance of the second inductor.

[0012] In one embodiment of this application, the first inductor is a double-layer coil inductor and the second inductor is a single-layer coil inductor.

[0013] In one embodiment of this application, the number of coils in the first inductor is greater than the number of coils in the second inductor.

[0014] In one embodiment of this application, each of the scan driving units is connected to the corresponding clock signal line via a via.

[0015] In one embodiment of this application, the inductor is disposed at the via between the scan driving unit and the corresponding clock signal line.

[0016] A second aspect of this application provides a liquid crystal display, including a timing control module and a liquid crystal display panel as described in any embodiment of this application. The timing control module is used to provide a clock signal and transmit it to the scan driving unit through the clock signal line.

[0017] In one embodiment of this application, multiple data lines are connected to a source driver circuit board, which is connected to the timing control module to input data voltage to the data lines.

[0018] In the technical solution provided in this application embodiment, the liquid crystal display panel includes a display area and a non-display area surrounding the display area. The non-display area is provided with clock signal lines, a scan driving circuit, and at least one inductor. Multiple clock signal lines are arranged along a first direction. The scan driving circuit includes multiple cascaded scan driving units arranged along a second direction, which intersects the first direction. The display area is provided with multiple spaced scan lines arranged along the first direction and multiple spaced data lines that are insulated from and intersect the scan lines. Each scan driving unit is connected to a scan line in a one-to-one correspondence; each scan driving unit is connected to a corresponding clock signal line, and at least one scan driving unit is connected to its corresponding clock signal line via an inductor. For signal lines with large RC delays, this application reduces the RC delay effect by connecting an inductor between the corresponding scan driving unit and the corresponding clock signal line, effectively solving the problem of insufficient or incorrect charging of the pixel area and improving display quality. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a liquid crystal display panel provided by related technologies;

[0020] Figure 2 This is a schematic diagram of the structure of the liquid crystal display panel provided in the embodiments of this application;

[0021] Figure 3 This is another structural schematic diagram of the liquid crystal display panel provided in the embodiments of this application;

[0022] Figure 4 This is another structural schematic diagram of the liquid crystal display panel provided in the embodiments of this application;

[0023] Figure 5 This is another structural schematic diagram of the liquid crystal display panel provided in the embodiments of this application;

[0024] Figure 6 This is a schematic diagram of the structure of the liquid crystal display provided in the embodiments of this application.

[0025] Explanation of key component symbols:

[0026] 10-Liquid crystal display panel; 101-Display sub-area; 11-Scan driving circuit; 12-Data driving circuit; 13-Scan line; 14-Data line; 15-Thin film transistor; 151-Pixel electrode; 152-Common electrode; 16-Sub-pixel; 20-Display area; 30-Non-display area; 310-Clock signal line; 320-Scan driving circuit; 330-Inductor; 340-Source driving circuit board; 110-First area; 120-Second area; 130-Third area; 40-Via; 610-Timing control module; 620-Liquid crystal display panel. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0028] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps described or executed may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0030] LCD monitors have become increasingly popular in recent years. They not only save space but also reduce power consumption. Large-size, high-resolution LCD monitors are gradually replacing traditional monitors, such as cathode ray tube (CRT) displays.

[0031] A liquid crystal display panel typically includes an array substrate, a color filter substrate, liquid crystal, and polarizers. The array substrate comprises multiple pixel units arranged in an array, defined by data lines extending along a first direction and scan lines extending along a second direction. Each pixel unit includes a TFT (Thin Film Transistor). (See reference...) Figure 1 , Figure 1 This is a schematic diagram of a liquid crystal display panel provided by related technologies. The liquid crystal display panel 10 includes a display area 101, a scan driving circuit 11, a data driving circuit 12, and a backlight module (not shown).

[0032] The display area 101 includes multiple spaced scan lines 13, multiple spaced data lines 14 that intersect the scan lines 13 insulated from them, multiple thin-film transistors 15 located at the intersections of the scan lines 13 and the data lines 14, multiple pixel electrodes 151, and multiple common electrodes 152 opposite to the pixel electrodes. The smallest area defined by the scan lines 13 and the data lines 14 is a sub-pixel 16, and the sub-pixels in each row are arranged periodically in red, green, and blue (RGB) order. A consecutive red sub-pixel, a green sub-pixel, and a blue sub-pixel constitute a pixel (not shown).

[0033] The gate (not shown) of the thin-film transistor 15 is connected to the scan line 13, the source (not shown) is connected to the data line 14, and the drain (not shown) is connected to the pixel electrode 151.

[0034] The scan drive circuit 11 generates a scan signal to drive the scan line 13. The data drive circuit 12 receives the image signal, converts it into grayscale voltage via digital-to-analog conversion, and applies it to the data line 14. The backlight module provides a light source for the liquid crystal display panel 10. Figure 1 As shown, the liquid crystal display device uses a scan drive circuit 11 to drive thin-film transistors 15 to control the data line 14 to charge and discharge pixel units, thereby achieving normal image display. However, due to the delay caused by parasitic resistance and capacitance, the signal waveform transmitted on a signal line will be distorted, resulting in a delay in the voltage of the pixel electrodes transmitted along the signal line. Since the voltage applied to the common electrode is basically consistent, the voltage difference between each pixel electrode and the common electrode in the entire liquid crystal display panel is inconsistent. This leads to phenomena such as insufficient charging and incorrect charging of pixel areas in the liquid crystal panel, thereby reducing the image display quality of the liquid crystal display device.

[0035] Based on this, this application proposes a liquid crystal display panel, which aims to reduce the RC delay effect by connecting an inductor between the corresponding scan driving unit and the corresponding clock signal line for signal lines with large RC delay, effectively solving the problem of insufficient or incorrect charging of pixel areas and improving display quality.

[0036] Reference Figure 2 , Figure 2 This is a schematic diagram of the structure of a liquid crystal display panel provided in an embodiment of this application. Figure 2 As shown, the liquid crystal display panel includes a display area 20 and a non-display area 30 surrounding the display area.

[0037] The non-display area 30 is provided with a clock signal line 310, a scan drive circuit 320 and at least one inductor 330. Multiple clock signal lines 310 are arranged along a first direction. The scan drive circuit 320 includes multiple cascaded scan drive units 321. The multiple scan drive units 321 are arranged along a second direction, which intersects with the first direction.

[0038] The display area 20 is provided with multiple scan lines 13 spaced apart and arranged along a first direction, and multiple data lines 14 spaced apart and insulated from the scan lines 13. Each scan driving unit 321 is connected to a scan line 13 in a one-to-one correspondence; each scan driving unit 321 is connected to a corresponding clock signal line 310, and at least one scan driving unit 321 is connected to the corresponding clock signal line 310 by an inductor 330.

[0039] In this embodiment, the scan driving circuit 320 is a GDL circuit, which means that the driving circuit for the horizontal scan lines is fabricated on the substrate surrounding the display area using the existing array process of the liquid crystal display panel, so that it can replace the external integrated circuit board to complete the driving of the horizontal scan lines. By using GDL (Data Driver Less) technology to fabricate the gate driver on the thin film transistor array substrate, space can be saved, thereby making the liquid crystal display panel more suitable for manufacturing narrow-bezel or bezel-less display products.

[0040] In this embodiment, considering that in the liquid crystal display panel, due to issues such as excessively long signal lines or wiring problems, some signal lines may have excessively large resistive-capacitive delays, which can lead to insufficient or incorrect charging of pixel areas in the liquid crystal panel, thus reducing the image display quality of the liquid crystal display device. However, based on the RLC circuit, since the impedance of the RLC circuit is: Where the real part R is the resistance, and the imaginary part... Let w be the reactance, w = 2πf be the angular frequency, f be the signal frequency, and j be the imaginary unit. The impedance amplitude is the modulus of Z. When the capacitance C in the circuit is constant, increasing the inductance L will decrease the circuit impedance Z. And when... At the specified moment, the circuit impedance is at its minimum, equal to the resistance value R. Afterward, increasing the inductance causes the impedance to increase again. Therefore, with a fixed capacitance C, adjusting the inductance L allows for... This minimizes the circuit impedance to a resistance value R. Therefore, by adding an inductor to the signal line, the RC delay caused by the capacitance and resistance on the signal line can be mitigated. Thus, in this embodiment, for signal lines with significant RC delay, connecting an inductor between the corresponding scan drive unit and the corresponding clock signal line can reduce the RC delay effect, effectively solving the problem of insufficient or incorrect charging of pixel areas and improving display quality.

[0041] In one embodiment of this application, the liquid crystal display panel is further provided with a source drive circuit board 340; the distance between the scan drive unit 321 and the source drive circuit board 340 is positively correlated with the inductance of the inductor connected between the scan drive unit 321 and the corresponding clock signal line 310.

[0042] In this embodiment, it is considered that the longer the signal line, the greater the corresponding RC delay. The length of the signal line depends on the distance from the signal source to each scan driving unit 321, or each scan line. In this embodiment, the liquid crystal display panel is also provided with a source driving circuit board 340. The distance between each level of scan driving unit 321 arranged along the second direction and the source driving circuit board 340 is different, so the length of the signal line corresponding to each level of scan driving unit 321 is different, that is, the RC delay generated on the signal line corresponding to each level of scan driving unit 321 is also different. In this embodiment, the distance between the scan driving unit 321 and the source driving circuit board 340 is positively correlated with the inductance of the inductor connected between the scan driving unit 321 and the corresponding clock signal line 310. That is, the farther the distance between the scan driving unit 321 and the source driving circuit board 340, the greater the RC delay generated by the corresponding signal line. At this time, it is necessary to set the inductance of the inductor connected between the scan driving unit 321 and the corresponding clock signal line 310 to reduce the RC delay accordingly.

[0043] For example, refer to Figure 3 , Figure 3 This is another structural schematic diagram of the liquid crystal display panel provided in an embodiment of this application. Figure 3 As shown, each scan line 13 is arranged horizontally, and each data line 14 intersects with the scan line 13 and is arranged vertically. Correspondingly, each scan driving unit 321 is also arranged horizontally and connected to its corresponding scan line 13. Each clock signal line 310 is arranged vertically and connected to its corresponding scan driving unit 321. The liquid crystal display panel also includes a source drive circuit board 340. The source drive circuit board 340 is horizontally positioned below the scan driving circuit 320. The first scan driving unit 321 corresponding to the first scan line 13 is furthest from the source drive circuit board 340, while the last scan driving unit 321 corresponding to the last scan line 13 is closest to the source drive circuit board 340. In the case where an inductor is connected between the scan drive unit 321 and the corresponding clock signal line 310, the greater the distance between the scan drive unit 321 and the source drive circuit board 340, the greater the RC delay generated on the corresponding signal line. Therefore, the larger the inductance of the inductor connected between the scan drive unit 321 and the corresponding clock signal line 310, the greater the RC delay can be reduced, the problem of insufficient or incorrect charging of the pixel area can be solved, and the display quality can be improved.

[0044] For example, assuming the display area contains N scan lines 13, there are corresponding N scan driving units 321, and each scan driving unit 321 is connected to a scan line 13 in a one-to-one correspondence, and each scan driving unit 321 is connected to a corresponding clock signal line 310. Assume that an inductor 330 is connected between each scan driving unit 321 and its corresponding clock signal line 310. That is, N inductors 330 are provided in the non-display area. In this case, the inductance of the inductor 330 connected between each scan driving unit 321 and its corresponding clock signal line 310 decreases sequentially downwards row by row.

[0045] It should be noted that the scanning drive units 321 at each level are also arranged in the horizontal direction. They can be arranged at the left and right ends of the display area 20, or only at one end of the left and right ends of 20. This application embodiment does not make specific limitations on this.

[0046] It should be noted that the signal line mentioned in this application embodiment does not refer to the clock signal line 310, but rather to all the traces laid out from the signal source end (source drive circuit board 340) to each pixel electrode in the display area 20, including the clock signal line 310, the connection between the clock signal line 310 and the scan drive unit 321, the connection between the scan drive unit 321 and the scan line 13, and the scan line 13, etc.

[0047] In this embodiment, since the resistance-capacitance delays corresponding to driving different rows of scan lines 13 are different, by placing the inductor 330 inside the panel and between the scan driving unit 321 and the corresponding clock signal line 310, the resistance-capacitance delays generated by driving different rows can be processed by changing the inductance of the inductor 330, which can play the role of providing different charging supplements to the scan lines 13 of different rows.

[0048] In one embodiment of this application, the liquid crystal display panel is further provided with a source driving circuit board 340. Starting from the source driving circuit board 340, multiple regions are arranged sequentially in a second direction along the direction close to the scan driving unit 321. Adjacent regions are adjacent. The inductance of the inductor 330 connected between each scan driving unit 321 and the corresponding clock signal line in each region is the same. The inductance of the inductor 330 connected between the scan driving unit 321 and the corresponding clock signal line 310 in the multiple regions increases sequentially.

[0049] In this embodiment, it is considered that although the longer the signal line, the greater the corresponding RC delay, the RC delay for signal lines within a certain length range is basically the same. For example, when the length of the signal line exceeds A, the RC delay begins to affect the display. For signal lines with lengths greater than A and less than B, the display impact caused by the RC delay is basically the same. For signal lines with lengths greater than B and less than C, the display impact caused by the RC delay is basically the same. Based on this, the inductance of the inductor 330 connected between the scan drive unit 321 and the corresponding clock signal line 310 can be controlled by region.

[0050] For example, refer to Figure 4 , Figure 4 This is another structural schematic diagram of the liquid crystal display panel provided in an embodiment of this application. Figure 4 As shown, each scan line 13 is arranged horizontally, and each data line 14 intersects with the scan line 13 and is arranged vertically. Correspondingly, each scan driving unit 321 is also arranged horizontally and connected to its corresponding scan line 13. Each clock signal line 310 is arranged vertically and connected to its corresponding scan driving unit 321. The liquid crystal display panel is also provided with a source driving circuit board 340. The source driving circuit board 340 is horizontally positioned below the scan driving circuit 320. Starting from the source driving circuit board 340, multiple regions 10 are arranged sequentially in the vertical direction close to the scan driving unit 321, with adjacent regions 10 being adjacent. In each region 10, multiple scan driving units 321 fall into it, and the inductance of the inductor 330 connected between each scan driving unit 321 and its corresponding clock signal line is the same. However, the inductance of the inductor 330 connected between the corresponding scan drive unit 321 and the corresponding clock signal line 310 in each region 10 increases sequentially from bottom to top in the vertical direction.

[0051] For example, starting with the source drive circuit board 340, five regions, A, B, C, D, and E, are arranged vertically along the direction closest to the scan drive unit 321. There are N1 scan drive units 321 falling into region A, N2 into region B, N3 into region C, N4 into region D, and N5 into region D. That is, there are a total of N (N = N1 + N2 + N3 + N4 + N5) scan drive units 321 and N scan lines 13. At this time, although the signal lines in region A will experience RC delay, the resulting display effect is imperceptible to the human eye and can be ignored. Therefore, for the N1 scan drive units 321 in region A, the inductance of the inductor 330 connected between each scan drive unit 321 and the corresponding clock signal line 310 is set to 0, or in other words, no inductor is connected between each scan drive unit 321 and the corresponding clock signal line 310. Since the display impact caused by the RC delay generated by each signal line in region B is basically the same, for the N2 scan drive units 321 in region B, the inductance of the inductor 330 connected between each scan drive unit 321 and the corresponding clock signal line 310 is set to the same value, for example, L2. Similarly, since the display impact caused by the RC delay generated by each signal line in region C is basically the same, for the N3 scan drive units 321 in region C, the inductance of the inductor 330 connected between each scan drive unit 321 and the corresponding clock signal line 310 is set to the same value, for example, L3. Since the display impact caused by the RC delay of each signal line in region D is basically the same, the inductance of the inductor 330 connected between each of the N4 scan drive units 321 in region D and the corresponding clock signal line 310 is set to the same value, for example, L4. Similarly, since the display impact caused by the RC delay of each signal line in region E is basically the same, the inductance of the inductor 330 connected between each of the N5 scan drive units 321 in region E and the corresponding clock signal line 310 is set to the same value, for example, L5. L2, L3, L4, and L5 increase sequentially.

[0052] In this embodiment, since the RC delay corresponding to each scan line in the same area is roughly the same, while the RC delay corresponding to different areas as a whole is different, by dividing the display panel into multiple areas along the second direction, and then setting the inductor 330 inside the panel and between the scan drive unit 321 and the corresponding clock signal line 310 in each area, the RC delay generated by driving the scan lines in different areas can be processed by changing the inductance of the inductor 330 in different areas, which can play the role of charging and supplementing the scan lines 13 in different areas differently.

[0053] In this embodiment, by controlling the inductance of the inductor 330 connected between the scanning drive unit 321 and the corresponding clock signal line 310 by region, the RC delay effect can be reduced, effectively solving the problem of insufficient or incorrect charging in the pixel area, improving display quality. At the same time, the layout of the inductor can be simplified, the layout cost can be reduced, and the layout speed of the inductor can be improved.

[0054] In one embodiment of this application, with the source drive circuit board as the starting position, a first region, a second region, and a third region are arranged sequentially in the second direction along the direction close to the scan drive unit; each scan drive unit falling into the third region is connected to a first inductor between itself and the corresponding clock signal line, and each scan drive unit falling into the second region is connected to a second inductor between itself and the corresponding clock signal line; the inductance of the first inductor is greater than the inductance of the second inductor.

[0055] In the embodiments of this application, reference is made to Figure 5 , Figure 5 This is another structural schematic diagram of the liquid crystal display panel provided in an embodiment of this application. Figure 5 As shown, the scan lines 13 are arranged horizontally, and the data lines 14 intersect with the scan lines 13 and are arranged vertically. Correspondingly, each scan driving unit 321 is also arranged horizontally and connected to its corresponding scan line 13. Each clock signal line 310 is arranged vertically and connected to its corresponding scan driving unit 321. The liquid crystal display panel also includes a source drive circuit board 340, which is horizontally positioned below the scan driving circuit 320. Starting with the source drive circuit board 340, a first region 110, a second region 120, and a third region 130 are arranged sequentially in the vertical direction along the direction close to the scan drive unit 321. Each scan drive unit 321 falling into the third region 130 is connected to the corresponding clock signal line 310 with a first inductor 331, and each scan drive unit 321 falling into the second region 120 is connected to the corresponding clock signal line 310 with a second inductor 332. The inductance of the first inductor 331 is greater than the inductance of the second inductor 332.

[0056] In this embodiment, starting with the source driver circuit board 340, a first region 110, a second region 120, and a third region 130 are arranged sequentially in the vertical direction near the scan driver unit 321. The first region 110 is the near-end region, i.e., the region relatively close to the source driver circuit board 340. The second region 120 is the middle region, i.e., the region relatively far from the source driver circuit board 340. The third region 130 is the far-end region, i.e., the region furthest from the source driver circuit board 340. Although the signal lines in the first region 110 generate RC delay, the resulting display impact is imperceptible to the human eye and can be ignored. Therefore, no inductor is connected between each scan driver unit 321 and its corresponding clock signal line 310 in the first region 110. Since the RC delay generated by each signal line in the second region 120 has a substantially similar display impact, a first inductor 331 is connected between each scan driver unit 321 and its corresponding clock signal line 310 in the second region 120. Similarly, since the display effects caused by the RC delay generated by each signal line in the third region 130 are basically the same, a second inductor 332 is connected between each scan drive unit 321 in the third region 130 and the corresponding clock signal line 310. The inductance of the first inductor 331 is greater than that of the second inductor 332.

[0057] In one embodiment of this application, the first inductor 331 is a double-layer coil inductor and the second inductor 332 is a single-layer coil inductor.

[0058] In this embodiment of the application, by setting the first inductor 331 as a double-layer coil inductor and the second inductor 332 as a single-layer coil inductor, the inductance of the first inductor 331 can be quickly made greater than the inductance of the second inductor 332.

[0059] In one embodiment of this application, the number of coils in the first inductor 331 is greater than the number of coils in the second inductor 331.

[0060] In this embodiment, by setting the number of coils in the first inductor 331 to be greater than the number of coils in the second inductor 331, the inductance of the first inductor 331 can also be quickly made greater than the inductance of the second inductor 332. Alternatively, by setting the first inductor 331 as a double-layer coil inductor and the second inductor 332 as a single-layer coil inductor, and setting the number of coils in the first inductor 331 to be greater than the number of coils in the second inductor 331, the inductance of the first inductor 331 can be quickly made greater than the inductance of the second inductor 332.

[0061] In this embodiment, by controlling the inductance of the inductor 330 connected between the scanning drive unit 321 and the corresponding clock signal line 310 in three regions, the RC delay effect can be reduced, effectively solving the problem of insufficient or incorrect charging in the pixel area, improving display quality. At the same time, the layout of the inductor can be simplified, the layout cost can be reduced, and the layout speed of the inductor can be improved.

[0062] In one embodiment of this application, each scan driving unit 321 is connected to the corresponding clock signal line 310 through a via 40.

[0063] In this embodiment, by connecting each scan drive unit 321 to the corresponding clock signal line 310 through a via 40, signal interference and distortion can be reduced, and signal transmission can be improved. Simultaneously, no additional conductors or contact points are required, reducing circuit complexity, simplifying the circuit, and lowering manufacturing costs.

[0064] In one embodiment of this application, the inductor 330 is disposed at the via 40 between the scan drive unit 321 and the corresponding clock signal line 310.

[0065] In this embodiment of the application, for cases where an inductor 330 needs to be installed to reduce RC delay, the inductor 330 is placed at the via 40 between the scan drive unit 321 and the corresponding clock signal line 310. This eliminates the need for additional contact points, reduces circuit complexity, simplifies the circuit, and lowers manufacturing costs.

[0066] Reference Figure 6 This application also provides a liquid crystal display, including a timing control module 610 and a liquid crystal display panel 620 provided in any embodiment of this application. The timing control module 610 is used to provide a clock signal and transmit it to the scan driving unit 321 through the clock signal line 310.

[0067] In one embodiment of this application, multiple data lines are connected to a source driver circuit board 340, which is connected to a timing control module 610 to input data voltage to the data lines.

[0068] Since the liquid crystal display panel 620 in the liquid crystal display provided in this application embodiment has at least one scanning driving unit 321 connected to an inductor 330 between it and the corresponding clock signal line 310, for signal lines with large resistance-capacitance delay, by connecting an inductor between the corresponding scanning driving unit and the corresponding clock signal line, the resistance-capacitance delay effect can be reduced, effectively solving the problem of insufficient or incorrect charging of the pixel area and improving the display quality.

[0069] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0070] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0071] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0072] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0073] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0074] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0075] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0076] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0077] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0078] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0079] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A liquid crystal display panel, characterized in that, Includes a display area and a non-display area surrounding the display area; The non-display area is provided with clock signal lines, a scan drive circuit and at least one inductor. Multiple clock signal lines are arranged along a first direction. The scan drive circuit includes multiple cascaded scan drive units, which are arranged along a second direction, which intersects the first direction. The display area is provided with multiple scan lines spaced apart and arranged along the first direction, and multiple data lines spaced apart and insulated from the scan lines; Each of the scan driving units is connected to a scan line in a one-to-one correspondence; Each of the scan driving units is connected to the corresponding clock signal line, and at least one of the scan driving units is connected to the corresponding clock signal line via the inductor; The liquid crystal display panel is also provided with a source driving circuit board; the distance between the scan driving unit and the source driving circuit board is different, and the length of the signal line corresponding to each scan driving unit is different. The distance between the scan driving unit and the source driving circuit board is positively correlated with the inductance of the inductor connected between the scan driving unit and the corresponding clock signal line. The signal line includes the clock signal line, the connection between the clock signal line and the scan driving unit, the connection between the scan driving unit and the corresponding scan line, and the corresponding scan line.

2. The liquid crystal display panel according to claim 1, characterized in that, The liquid crystal display panel is further provided with a source driving circuit board; with the source driving circuit board as the starting position, multiple regions are arranged sequentially in the second direction along the direction close to the scan driving unit, and adjacent regions are adjacent to each other. The inductance of the inductor connected between each scan driving unit falling into the region and the corresponding clock signal line is the same, and the inductance of the inductor connected between the scan driving unit and the corresponding clock signal line in the multiple regions increases sequentially.

3. The liquid crystal display panel according to claim 2, characterized in that, Starting with the source drive circuit board, a first region, a second region, and a third region are arranged sequentially in the second direction along the direction close to the scan drive unit; each scan drive unit falling into the third region is connected to the corresponding clock signal line with a first inductor, and each scan drive unit falling into the second region is connected to the corresponding clock signal line with a second inductor; the inductance of the first inductor is greater than the inductance of the second inductor.

4. The liquid crystal display panel according to claim 3, characterized in that, The first inductor is a double-layer coil inductor, and the second inductor is a single-layer coil inductor.

5. The liquid crystal display panel according to claim 3 or 4, characterized in that, The number of coils in the first inductor is greater than the number of coils in the second inductor.

6. The liquid crystal display panel according to claim 1, characterized in that, Each of the scan drive units is connected to the corresponding clock signal line via a via.

7. The liquid crystal display panel according to claim 6, characterized in that, The inductor is disposed at the via between the scan drive unit and the corresponding clock signal line.

8. A liquid crystal display, characterized in that, The device includes a timing control module and a liquid crystal display panel as described in any one of claims 1-7, wherein the timing control module is used to provide a clock signal and transmit it to the scan driving unit through the clock signal line.

9. The liquid crystal display according to claim 8, characterized in that, Multiple data lines are connected to the source driver circuit board, which is connected to the timing control module to input data voltage to the data lines.

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