Radiographic apparatus

Abstract

A radiation imaging apparatus (1) includes a charge generating chip that generates charges, a readout chip (30) that outputs a digital value based on the charges, and a circuit board (4) on which the readout chip (30) is disposed. The charge generating chip (20) has a charge output surface (21b) including a first output region (20F1) facing the readout chip (30) and a second output region (20F2) facing another readout chip (30). The readout chip (30) has a signal input / output electrode (30e), respectively. The charge generating chip (20) has a signal connection wiring (20e) that extends from the first output region (20F1) to the second output region (20F2) and electrically connects the signal input / output electrode (30e) of the readout chip (30) to the signal input / output electrode (30e) of the other readout chip (30).

Description

Technical Field

[0001] This invention relates to a radiographic imaging device. Background Technology

[0002] Technology for detecting radiation is under continuous development. It is anticipated that radiation detection technology will be applied in medical, industrial, and security fields. Radiation imaging devices, which acquire radiation images, are among the devices used for radiation detection. For example, Patent Document 1 discloses a radiation imaging device that includes a radiation detection element and an integrated circuit element. The radiation detection element is a separate component from the integrated circuit element. The radiation detection element is disposed on the integrated circuit element. Furthermore, the back side of the radiation detection element and the front side of the integrated circuit element are electrically connected via multiple electrodes. For example, Patent Document 2 discloses a sensor employing a structure of stacked detection elements and circuit elements.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2007-155562

[0006] Patent Document 2: Japanese Patent Application Publication No. 2012-9607 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] In the field of radiography equipment technology, there has been a persistent pursuit of maximizing the effective pixel area. However, it is difficult to achieve a large area for a single radiation detector that constitutes a radiography device. Therefore, a structure that expands the effective pixel area by arranging multiple radiation detectors on a circuit board has been considered.

[0009] When employing a structure that mounts multiple radiation detectors onto a circuit board, the manufacturing process of the radiation imaging device requires repeatedly mounting the detectors onto the circuit board. As the repetition of this mounting process increases, the likelihood of a malfunctioning detector among the multiple detectors increases. In other words, while increasing the number of radiation detectors is necessary to increase the area of ​​the effective pixel region, the probability of mounting defects also increases with the number of detectors. Consequently, a larger effective pixel area results in a lower yield.

[0010] The purpose of this invention is to provide a radiation imaging device that can suppress the decline in yield.

[0011] Technical solutions for solving the problem

[0012] An embodiment of the present invention provides a radiation imaging apparatus comprising: a charge generating chip that generates a charge corresponding to the energy or number of particles of an incident radiation; a first readout chip electrically connected to the charge generating chip and outputting a digital value based on the charge received from the charge generating chip; a second readout chip electrically connected to the charge generating chip, outputting a digital value based on the charge received from the charge generating chip, and adjacent to the first readout chip; and a circuit board on which the first readout chip and the second readout chip are disposed. The charge generating chip has a charge output surface, the charge output surface including a first output region facing the first readout chip and a second output region facing the second readout chip. The first readout chip has a first readout surface facing the charge output surface and a first signal input / output electrode disposed on the first readout surface. The second readout chip has a second readout surface facing the charge output surface and a second signal input / output electrode disposed on the second readout surface. The charge generating chip includes: a signal connection wiring extending from the first output region to the second output region on the charge output surface, and electrically connecting the first signal input / output electrode to the second signal input / output electrode.

[0013] The first and second readout chips of the radiography apparatus have first and second signal input / output electrodes disposed on a first and second readout surface facing the charge generation chip. The first signal input / output electrode is connected to the second signal input / output electrode via a signal connection wiring disposed on the charge generation chip. Therefore, by configuring the charge generation chip to span only the first and second readout chips, the first readout chip can be connected to the second readout chip. As a result, connecting the first readout chip to the second readout chip is easy, and operational defects during the assembly of the radiography apparatus are suppressed. Therefore, a decrease in yield can be suppressed.

[0014] In one embodiment of the radiographic imaging apparatus, the charge generation chip may have multiple charge output electrodes disposed on a charge output surface. The first readout chip may have multiple charge readout electrodes disposed on the first readout surface, facing the charge output electrodes and electrically connected to them. According to this configuration, by simply configuring the charge generation chip to span across the first and second readout chips, connections between the first and second readout chips, between the charge generation chip and the first readout chip, and between the charge generation chip and the second readout chip can be made.

[0015] In one embodiment of a radiography apparatus, the charge generation chip may include a charge output surface provided with signal connection wiring and charge output electrodes, and a semiconductor detection section that outputs charge from the charge output electrodes. The first readout chip may include a first readout surface provided with first signal input / output electrodes and charge readout electrodes, and a derivation section that generates a digital value based on the charge received from the semiconductor detection section. In this configuration, the charge output electrodes provided in the semiconductor detection section define an effective pixel area. Furthermore, the configuration of the charge output electrodes of the charge generation chip is consistent with the configuration of the charge readout electrodes of the readout chip. As a result, a configuration that matches the configuration of the charge output electrodes with the configuration of the charge readout electrodes is not required. Therefore, the structure of the radiography apparatus can be simplified.

[0016] One embodiment of a radiographic imaging apparatus includes a charge generation chip comprising: a charge redistribution section including a charge output surface provided with signal connection wiring and charge output electrodes; and a semiconductor detection section that outputs charge to the charge redistribution section via a plurality of pixel electrodes separated from each other. A first readout chip may include a first readout surface provided with first signal input / output electrodes and charge readout electrodes, and has a derivation section that generates a digital value based on the charge received from the charge redistribution section. The arrangement spacing of the pixel electrodes may differ from the arrangement spacing of the charge output electrodes. In this configuration, the pixel electrodes provided in the semiconductor detection section define an effective pixel area. Furthermore, the charge redistribution section matches the arrangement of the pixel electrodes with the arrangement of the charge readout electrodes. As a result, the arrangement of the pixel electrodes defining the effective pixel area is not limited by the arrangement of the charge readout electrodes. Therefore, the degree of freedom in the arrangement of the pixel electrodes defining the effective pixel area can be increased.

[0017] A charge generation chip in one embodiment of a radiography apparatus may include a charge output surface provided with signal connection wiring and charge output electrodes, and a semiconductor detection unit that outputs charge from the charge output electrodes. A first readout chip may include: a readout rewiring unit including a first readout surface provided with first signal input / output electrodes and charge readout electrodes; and a lead-out unit that generates digital values ​​based on charges received from the readout rewiring unit via a plurality of separate rewiring electrodes. The arrangement spacing of the rewiring electrodes may differ from the arrangement spacing of the charge readout electrodes. In this configuration, the arrangement of the charge output electrodes provided in the semiconductor detection unit defines an effective pixel area. The readout rewiring unit matches the arrangement of the charge readout electrodes facing the charge output electrodes with the arrangement of the rewiring electrodes. As a result, the arrangement of the charge output electrodes defining the effective pixel area is not limited by the arrangement of the rewiring electrodes. Therefore, the degree of freedom in the arrangement of the charge output electrodes defining the effective pixel area can be increased.

[0018] A charge generation chip in one embodiment of a radiographic imaging apparatus may include: a charge rewiring section, comprising a charge output surface provided with signal connection wiring and charge output electrodes; and a semiconductor detection section that outputs charge to the charge rewiring section via a plurality of pixel electrodes separated from each other. A first readout chip may include: a readout rewiring section, comprising a first readout surface provided with a first signal input / output electrode and a charge readout electrode; and a delivery section that generates a digital value based on the charge received from the readout rewiring section via a plurality of rewiring electrodes separated from each other. The arrangement spacing of the pixel electrodes may differ from the arrangement spacing of the charge output electrodes. The arrangement spacing of the rewiring electrodes may differ from the arrangement spacing of the charge readout electrodes. In this configuration, the pixel electrodes provided in the semiconductor detection section define an effective pixel area. Furthermore, the charge rewiring section matches the arrangement of the pixel electrodes and the arrangement of the charge readout electrodes. Further, the readout rewiring section matches the arrangement of the charge readout electrodes facing the charge output electrodes and the arrangement of the reconfigured electrodes. As a result, the arrangement of the pixel electrodes defining the effective pixel area is not limited by the arrangement of the reconfigured electrodes. Therefore, it can increase the degree of freedom in the configuration of pixel electrodes in the specified effective pixel area.

[0019] One embodiment of the radiographic imaging apparatus may further include a third readout chip electrically connected to a charge generation chip, outputting a digital value based on the charge received from the charge generation chip, and adjacent to the second readout chip. The third readout chip may have a third readout surface facing a charge output surface and a third signal input / output electrode disposed on the third readout surface. The charge output surface of the charge generation chip may further include a third output region facing the third readout portion. The second readout chip may further have a second additional signal input / output electrode disposed on the second readout surface. The charge generation chip may further have additional signal connection wiring extending from the second output region to the third output region, connecting the second additional signal input / output electrode to the third signal input / output electrode. According to this configuration, three readout chips can be electrically connected through a single charge generation chip.

[0020] One embodiment of the radiographic imaging apparatus may further include a third readout chip electrically connected to a charge generation chip, outputting a digital value based on the charge received from the charge generation chip, and adjacent to the second readout chip. The third readout chip may have a third readout surface facing the charge output surface and third signal input / output electrodes disposed on the third readout surface. The charge output surface of the charge generation chip may further include a third output region facing the third readout section. Signal connection wiring may be provided across the first output region, the second output region, and the third output region, and electrically connects the first signal input / output electrodes, the second signal input / output electrodes, and the third signal input / output electrodes to each other. With this configuration, three readout chips can be electrically connected using a single charge generation chip.

[0021] Technical effect

[0022] According to the present invention, a radiation imaging device capable of suppressing the decline in yield is provided. Attached Figure Description

[0023] Figure 1 This is a perspective view of the radiation imaging device according to the first embodiment.

[0024] Figure 2 It is shown Figure 1 An exploded 3D view of the charge generation chip and the readout chip.

[0025] Figure 3 It is shown Figure 1 A three-dimensional view of the charge output surface of the charge generation chip.

[0026] Figure 4 It is shown Figure 1 A 3D view of the readout chip.

[0027] Figure 5 It is shown Figure 1 A diagram of the connection structure of a radiographic imaging device.

[0028] Figure 6 yes Figure 1 Functional block diagram of a radiographic imaging device.

[0029] Figure 7 This is an exploded perspective view showing the charge generation chip and readout chip of the radiation imaging apparatus according to the second embodiment.

[0030] Figure 8 shows Figure 7 A diagram of the connection structure of a radiographic imaging device.

[0031] Figure 9 This is an exploded perspective view showing the charge generation chip and readout chip of the radiation imaging apparatus according to the third embodiment.

[0032] Figure 10 It is shown Figure 9 A diagram of the connection structure of a radiographic imaging device.

[0033] Figure 11 This is an exploded perspective view showing the charge generation chip and readout chip of the radiation imaging apparatus according to the fourth embodiment.

[0034] Figure 12 It is shown Figure 11 A diagram of the connection structure of a radiographic imaging device.

[0035] Figure 13 This is an exploded perspective view showing the charge generation chip and readout chip of the radiation imaging device of the first modified example.

[0036] Figure 14 This is an exploded perspective view showing the charge generation chip and readout chip of the radiation imaging device of the second modified example. Detailed Implementation

[0037] Figure 1 The radiation imaging apparatus 1 shown acquires a two-dimensional image based on radiation arriving from the object being examined. Radiation includes, for example, gamma rays, X-rays, alpha rays, and beta rays. The radiation imaging apparatus 1 includes a charge generator 2, a reader 3, and a circuit board 4. The charge generator 2 is disposed on the reader 3. The charge generator 2 includes a plurality of charge generating chips 20. The charge generating chips 20 are arranged in a two-dimensional configuration on the reader 3. The charge generator 2 outputs a charge corresponding to the incident radiation to the reader 3.

[0038] A reader 3 is disposed on a circuit board 4. The reader 3 includes a plurality of readout chips 30. The readout chips 30 are arranged in a two-dimensional configuration on the circuit board 4. The reader 3 receives control signals from a controller 5 via the circuit board 4. The reader 3 generates pixel signals corresponding to charges. Additionally, the reader 3 outputs image signals to an image generator 6 via the circuit board 4. Specifically, the reader 3 outputs image signals to the circuit board 4 via signal input / output electrodes 30e. The signal input / output electrodes 30e are disposed on the outer periphery of the reader 3. A first end of a bonding wire 7 is connected to the signal input / output electrode 30e. The second end of the bonding wire 7 is connected to a substrate electrode 40e of the circuit board 4.

[0039] Signal input and output between the reader 3 and the circuit board 4 are performed only through the signal input / output electrodes 30e connected to the bonding line 7. That is, the reader chip 30 does not have bump electrodes disposed on the back surface 30b of the reader chip. The back surface 30b of the reader chip is a flat surface without electrodes. In this embodiment, "flat surface" refers to a surface without electrodes or other electrical structures. Therefore, signal input and output between the reader chip 30 and the outside world is limited to the reader chip surface 30a. In other words, signal input and output between the reader chip 30 and the outside world cannot occur from the back surface 30b of the reader chip.

[0040] However, the read chip 30 connected to the bonding line 7 is only disposed on the outermost periphery of the reader 3. In the following description, the read chip 30 disposed on the outermost periphery of the reader 3 is referred to as the outer read chip 30S. That is, the outer read chip 30S is connected to the bonding line 7. On the other hand, the read chip 30 disposed in the area surrounded by the outer read chip 30S is referred to as the inner read chip 30K. That is, the inner read chip 30K is not connected to the bonding line 7. It should be noted that in the following description, the outer read chip 30S and the inner read chip 30K are used as needed. Where no special distinction is required, they are simply referred to as read chip 30.

[0041] In the claims, the first readout chip and the second readout chip refer to readout chips that are adjacent to each other. Therefore, the outer readout chip 30S can be the first readout chip, and the inner readout chip 30K can be the second readout chip. Alternatively, the outer readout chip 30S can be the first readout chip, and another adjacent outer readout chip 30S can be the second readout chip. Furthermore, the inner readout chip 30K can be the first readout chip, and another adjacent inner readout chip 30K can be the second readout chip.

[0042] The inner readout chip 30K uses the outer readout chip 30S for signal input and output. For example, Figure 1 The inner readout chip 30K shown outputs image signals through an adjacent outer readout chip 30S. It should be noted that the inner readout chip 30K can also be connected to the adjacent outer readout chip 30S via another adjacent inner readout chip 30K.

[0043] This connection structure can be achieved by... Figure 2The configuration is achieved by electrically connecting the signal input / output electrode 30e (first signal input / output electrode) of the readout chip 30 shown, and the signal input / output electrode 30e (second signal input / output electrode) of another readout chip 30 adjacent to it. That is, the signal input / output electrode 30e of one readout chip 30 is connected to the signal input / output electrode 30e of the other readout chip 30 via the signal connection wiring 20e. The signal connection wiring 20e is provided in the charge generation chip 20. That is, the charge generation chip 20 is configured to span across adjacent readout chips 30. As a result, the signal connection wiring 20e provided in the charge generation chip 20 electrically connects one readout chip 30 to the other. The charge generation chip 20 of the radiation imaging apparatus 1 of this embodiment not only has the first function of outputting charge by receiving radiation, but also has the second function of electrically connecting adjacent readout chips 30.

[0044] <Charge Generation Chip>

[0045] The charge generating chip 20 generates a charge corresponding to the incident radiation. The charge generating chip 20 outputs a charge to the readout chip 30. Both the charge generating chip 20 and the readout chip 30 are plate-shaped. When viewed from above, the shape of the charge generating chip 20 can be the same as the shape of the readout chip 30. Alternatively, the shape of the charge generating chip 20 can be different from the shape of the readout chip 30. In the following description, it is assumed that the planar shape of the charge generating chip 20 is the same as the planar shape of the readout chip 30.

[0046] The charge generation chip 20 is disposed on top of the readout chip 30. The charge generation chip 20 may be disposed on two or more readout chips 30. Figure 2 In the example shown, a charge generating chip 20 spans four readout chips 30. For example, the end face of the charge generating chip 20 is offset relative to the end face of the readout chips 30. Specifically, the offset between the end face of the charge generating chip 20 and the end face of the readout chips 30 is half of one side of the charge generating chip 20. With this configuration, the charge generated by the charge generating chip 20 moves to the four readout chips 30 respectively.

[0047] When the charge generation chip 20 is configured to span four readout chips 30, the charge output surface 21b of the charge generation chip 20 includes four output regions. For example... Figure 3 As shown, the charge output surface 21b includes output region 21F1 (first output region), output region 21F2 (second output region), output region 21F3 (third output region) and output region 21F4 (fourth output region).

[0048] Refer again Figure 2The charge generation chip 20 includes a semiconductor detection section 21, a control electrode section 22, a charge output electrode 20g, and signal connection wiring 20e.

[0049] The semiconductor detection unit 21 generates electron-hole pairs (charge pairs) by receiving X-rays. That is, the semiconductor detection unit 21 converts the received radiation into a current signal (charge signal) corresponding to its energy. The planar shape of the semiconductor detection unit 21 is rectangular. The size of the semiconductor detection unit 21 is, for example, 9.6 mm × 9.6 mm. The semiconductor detection unit 21 has a semiconductor injection surface 21a for receiving radiation such as X-rays and a charge output surface 21b for outputting charges. The charge-based signal is provided to the readout chip 30 from the charge output surface 21b. For example, a Cd(Zn)Te charge generator, a Si charge generator, a Ge charge generator, a GaAs charge generator, a GaN charge generator, and a TlBr charge generator can be used as the semiconductor detection unit 21. Alternatively, a device with a scintillator and a photodetector can also be used as the semiconductor detection unit 21. The scintillator converts X-rays into light. The photodetector converts the light generated by the scintillator into charges.

[0050] A control electrode section 22 is disposed on the semiconductor injection surface 21a. The control electrode section 22 covers the entire surface of the semiconductor injection surface 21a. When viewed from above, the planar shape of the control electrode section 22 is consistent with the planar shape of the semiconductor injection surface 21a. An electric field is formed in the area of ​​the control electrode section 22 where the semiconductor detection section 21 is disposed. The electric field determines the direction of charge movement generated in the semiconductor detection section 21. The electric field generated by the control electrode section 22 causes the charge to move inside the semiconductor detection section 21 toward the charge output surface 21b.

[0051] Figure 3 This is a three-dimensional view of the charge generation chip 20 viewed from the charge output surface 21b. (See image below.) Figure 3 As shown, multiple charge output electrodes 20g are disposed on the charge output surface 21b. The charge output electrodes 20g can be bumps. The multiple charge output electrodes 20g are configured in a grid shape. Figure 3 The charge generation chip 20 shown has six charge output electrodes 20g arranged vertically and six charge output electrodes 20g arranged horizontally. That is, Figure 3 The charge generation chip 20 shown has 36 charge output electrodes 20g. Each charge output electrode 20g is associated with a pixel G ( Figure 5 (Refer to the corresponding area). Therefore, the area where the charge output electrode 20g is disposed is an effective pixel area. A gap is formed between adjacent charge output electrodes 20g. This gap exposes the charge output surface 21b.

[0052] Multiple signal connection wires 20e are disposed on the charge output surface 21b. The signal connection wires 20e are disposed between the charge output electrodes 20g. Figure 3 The charge generation chip 20 shown has eight signal connection lines 20e. The signal connection lines 20e cross the center line 20L1 when viewed from above the charge generation chip 20. That is, the output region where the first end of the signal connection line 20e is located is different from the output region where the second end of the signal connection line 20e is located. For example, Figure 3 The signal connection wiring 20ea shown extends from output region 21F1 to output region 21F2. Additionally, signal connection wiring 20e crosses another centerline 20L2 when viewed from above the charge generation chip 20. When the charge generation chip 20 is positioned on the readout chip 30, these centerlines 20L1, 20L2 overlap with the gaps formed between adjacent readout chips 30. The lateral length of signal connection wiring 20e is less than the spacing between the charge output electrodes 20g. The longitudinal length of signal connection wiring 20e is greater than one side of the charge output electrodes 20g. For example, the longitudinal length of signal connection wiring 20e can be the sum of the lengths of the two charge output electrodes 20g and the length of a gap. The thickness of signal connection wiring 20e can be approximately the same as the thickness of the charge output electrodes 20g.

[0053] <Reading the chip>

[0054] Figure 4 This is a 3D view of the readout chip 30. It should be noted that, when viewed as individual chips, there is a fundamental difference between the outer readout chip 30S and the inner readout chip 30K.

[0055] The readout chip 30 generates pixel signals based on the charge generated by the semiconductor detection unit 21. The pixel signals are digital values. The readout chip 30 outputs the pixel signals to the circuit board 4 via adjacent readout chips 30. Figure 5 (Refer to). The readout chip 30 has a readout rewiring layer 31 (readout rewiring section) and a lead-out substrate 32 (lead-out section).

[0056] The readout rewiring layer 31 receives charge from the semiconductor detection unit 21. The readout rewiring layer 31 transfers the received charge to the output substrate 32. The readout rewiring layer 31 has a readout rewiring input surface 31a (first readout surface, second readout surface) and a readout rewiring output surface 31b. The readout rewiring input surface 31a faces the charge generator 10. The readout rewiring output surface 31b faces the output substrate 32.

[0057] The readout rewiring input surface 31a faces the charge output surface 21b of the semiconductor detection unit 21. Multiple charge readout electrodes 30g are arranged in a two-dimensional shape and at equal intervals on the readout rewiring input surface 31a. Figure 4In the readout chip 30 shown, a plurality of charge readout electrodes 30g are arranged on the entire surface of the readout redistribution input surface 31a. The charge readout electrodes 30g face the charge output electrode 20g. Therefore, the arrangement spacing of the charge readout electrodes 30g is approximately the same as the arrangement spacing of the charge output electrodes 20g. It should be noted that it is preferable for the charge readout electrodes 30g to face the charge output electrode 20g. This orientation also allows for a portion of the charge readout electrodes 30g to face the charge output electrode 20g. That is, it is not necessary for the entire surface of the charge readout electrodes 30g to face the charge output electrode 20g. Furthermore, the charge readout electrodes 30g are electrically connected to the charge output electrode 20g via solder or the like. It should be noted that although it is preferable for the charge readout electrodes 30g and the charge output electrodes 20g to be electrically connected and fixed to each other, they do not necessarily have to be fixed.

[0058] A plurality of signal input / output electrodes 30e are disposed on the readout rewiring input surface 31a. The signal input / output electrodes 30e are positioned between charge readout electrodes 30g. Specifically, the signal input / output electrodes 30e are positioned between the charge readout electrodes 30g disposed at the outermost periphery of the readout rewiring input surface 31a. For example, the charge readout electrodes 30g and signal input / output electrodes 30e are alternately positioned at the edges of the readout rewiring input surface 31a. The signal input / output electrodes 30e extend from the readout rewiring input surface 31a toward the lead-out substrate 32. The first end of the signal input / output electrode 30e is exposed on the readout rewiring input surface 31a. The second end of the signal input / output electrode 30e is disposed inside the lead-out substrate 32. Figure 5 (Refer to). That is, the second end of the signal input / output electrode 30e is not exposed on the back side of the lead-out substrate 32. In other words, the signal input / output electrode 30e does not penetrate the readout chip 30. That is, the signal input / output electrode 30e is not a so-called through electrode.

[0059] like Figure 5 As shown, the signal input / output electrode 30e is connected to the signal processor 33 disposed on the output substrate 32. The signal input / output electrode 30e is electrically connected to the signal connection wiring 20e disposed on the charge generation chip 20. Therefore, the signal input / output electrode 30e faces the signal connection wiring 20e. The signal input / output electrode 30e is connected to the signal input / output electrode 30e of the adjacent readout chip 30 via the signal connection wiring 20e. In addition, a portion of the signal input / output electrode 30e of the outer readout chip 30S functions as the input / output terminal of the reader 3. That is, a bonding line 7 is connected to a portion of the signal input / output electrode 30e of the outer readout chip 30S.

[0060] Signal input / output electrodes 30e output signals from signal processor 33 to the outside of readout chip 30. Alternatively, signal input / output electrodes 30e can transmit signals received from the outside of readout chip 30 to signal processor 33. In this case, signal processor 33 can directly transmit signals received from one signal input / output electrode 30e to other signal input / output electrodes 30e. In this case, signals received from the inner readout chip 30K adjacent to one side can be output to the outer readout chip 30S adjacent to the other side.

[0061] The readout rewiring output surface 31b contacts the output input surface 32a of the output substrate 32. Multiple rewiring electrodes 31p are arranged in a two-dimensional configuration on the readout rewiring output surface 31b. The readout rewiring layer 31 transfers charge to the output substrate 32 through the rewiring electrodes 31p. The rewiring electrodes 31p are electrical connection points between the readout rewiring layer 31 and the output substrate 32. The specific configuration of the rewiring electrodes 31p is not particularly limited. The number of rewiring electrodes 31p is the same as the number of charge readout electrodes 30g. That is, one rewiring electrode 31p is connected to one charge readout electrode 30g. The rewiring electrodes 31p are arranged in a two-dimensional configuration on the readout rewiring output surface 31b. The spacing between the rewiring electrodes 31p is different from the spacing between the charge readout electrodes 30g. Specifically, the spacing between the rewiring electrodes 31p is narrower than the spacing between the charge readout electrodes 30g.

[0062] The export substrate 32 has an export input surface 32a, an export back surface 32b, and a signal processor 33.

[0063] A redistribution electrode 31p is disposed on the input / output surface 32a. The redistribution electrode 31p is connected to the signal processor 33. The signal processor 33 converts charge into pixel signals as digital values. The signal processor 33 converts the charge output from the charge generator 10 into an energy integral signal as a pixel signal. The energy integral signal contains at least information about the energy of the incident radiation. The signal processor 33 outputs an image signal through the signal input / output electrodes 30e. The signal processor 33 receives control signals from the signal input / output electrodes 30e. In addition, the signal processor 33 can directly transmit the image signal or control signal received from one signal input / output electrode 30e to other signal input / output electrodes 30e.

[0064] The back surface 32b of the readout chip 30 faces the main surface 4a of the circuit board. No electrical or physical components are formed on the back surface 32b. For example, the second end of the signal input / output electrode 30e is not exposed on the back surface 32b. The back surface 32b is only physically fixed relative to the main surface 4a of the circuit board. Therefore, no electrical or physical components are formed in the area of ​​the main surface 4a of the circuit board facing the back surface 32b. That is, the flat back surface 32b of the readout chip 30 is mounted on the flat main surface 4a of the circuit board 4.

[0065] The signal processor 33 has multiple signal processing units 33a. Each signal processing unit 33a corresponds to one pixel G. Therefore, a redistribution electrode 31p is connected to each signal processing unit 33a.

[0066] It is important to note that the arrangement spacing of the signal processing units 33a is different from the arrangement spacing of the pixels G. Specifically, the arrangement spacing of the signal processing units 33a is narrower than the arrangement spacing of the pixels G. This is because the pixels G are disposed over the entire surface of the charge generation chip 20, while the signal processing units 33a are disposed in the area surrounded by the signal input / output electrodes 30e. The area surrounded by the signal input / output electrodes 30e is narrower than the entire area of ​​the charge generation chip 20. Furthermore, one pixel G corresponds to one signal processing unit 33a. That is, the number of pixels G and the number of signal processing units 33a are equal. Therefore, it is necessary to make the arrangement spacing of the signal processing units 33a narrower than the arrangement spacing of the pixels G. Therefore, the readout chip 30 has a readout rewiring layer 31 for converting the arrangement spacing of the signal processing units 33a into the arrangement spacing of the pixels G. That is, the readout rewiring layer 31 is a pitch conversion substrate.

[0067] It should be noted that the relationship between the arrangement interval of the signal processing unit 33a and the arrangement interval of the pixel G is not limited to the relationship described above. It is also possible to implement a structure in which the arrangement interval of the signal processing unit 33a is the same as the arrangement interval of the pixel G. In this case, the readout rewiring layer 31 can be omitted. Furthermore, the configuration that performs the function of changing the arrangement interval can exist between the pixel G and the signal processing unit 33a. That is, the configuration that performs the function of changing the arrangement interval can also be provided in the charge generation chip 20. Furthermore, the configuration that performs the function of changing the arrangement interval can also be provided in both the charge generation chip 20 and the readout chip 30. These examples will be described later as the second, third, and fourth embodiments.

[0068] like Figure 6As shown, the readout chip 30 includes a signal converter 33a1 and a memory 33a2. The signal converter 33a1 and the memory 33a2 constitute the signal processing unit 33a. That is, for one pixel of the charge generation chip 20, a signal converter 33a1 and a memory 33a2 are connected.

[0069] A signal converter 33a1 is connected to a charge output electrode 20g of a charge generation chip 20 via wiring 31c of the readout rewiring layer 31. Figure 5 (Refer to). Signal converter 33a1 receives charge from charge generation chip 20. Φ 1. The signal converter 33a1 enables charge-based... Φ The analog signal is discrete. The analog signal is represented as voltage. The voltage corresponds to the energy or number of particles of the radiation emitted into the corresponding pixel G of the charge generation chip 20. Therefore, the signal converter 33a1 is an A / D converter that outputs a digital signal. For example, the resolution of the signal converter 33a1 can be 10 bits.

[0070] Memory 33a2 is connected to signal converter 33a1. Memory 33a2 receives digital signals from signal converter 33a1. Φ 2. Furthermore, the memory 33a2 receives each input digital signal. Φ 2-hour storage of digital signals Φ 2. The memory 33a2 stores digital signals. Φ 2. These are sequentially stored in the designated memory space. Then, memory 33a2 operates according to the control signals provided by controller 5. θ Output digital signal to image generator 6 Φ 2.

[0071] <Effects>

[0072] The following describes the development process of the radiation imaging device 1 and explains its function and effects.

[0073] The inventors of this application have developed a process for manufacturing a radiation imaging device 1. Examples of processes for manufacturing the radiation imaging device 1 include, for example, a process for forming electrodes in a semiconductor detector, a process for cutting chips from a wafer, and a process for bonding chips together.

[0074] As detectors for radiation, scintillation detectors and semiconductor detectors can be cited as examples. Comparing scintillation detectors and semiconductor detectors, semiconductor detectors can easily achieve high sensitivity and high resolution in X-ray imaging techniques. The X-ray imaging apparatus 1 with a semiconductor detector can capture finer X-ray images in a shorter time. As a result, the X-ray imaging apparatus 1 with a semiconductor detector can be used in medical, industrial, non-destructive inspection, security, and industrial / social infrastructure inspection applications.

[0075] However, it is difficult to achieve a large detection area with a single semiconductor detector. For example, the detection area of ​​a single semiconductor detector is approximately 20 mm × 20 mm. In the field of using the aforementioned X-ray imaging apparatus 1, a detection area of, for example, 400 mm × 400 mm is required. Therefore, a method for achieving a larger detection area that cannot be achieved with a single semiconductor detector by using multiple semiconductor detection units has been investigated.

[0076] Regarding the signal output by the semiconductor detector due to the injection of radiation, the semiconductor detector alone cannot read it. That is, the radiation imaging apparatus 1, in addition to the semiconductor detector, also has a readout circuit that processes the signal output by the semiconductor detector. The semiconductor detector and the readout circuit are stacked. Thus, the part containing the semiconductor detector and the readout circuit is called the detector module. Furthermore, the signal output to each pixel of the semiconductor detector is converted into a digital value through signal processing in the readout circuit. The digital value is converted into a radiation image through further signal processing. Therefore, it is necessary to transmit the digital value from the readout circuit to the processing device that performs the radiation image generation process. That is, it is necessary to electrically connect the processing device and the readout circuit.

[0077] One example of such a connection structure is a configuration where each of a plurality of readout circuits disposed on a circuit board is connected to the circuit board and the readout circuit via bonding wires. However, this structure requires pads to be arranged around the readout circuits. That is, a gap of a certain size, sized to accommodate the pads, is created between adjacent readout circuits. A semiconductor detector is disposed on top of the readout circuit. Therefore, it can be said that the gap between the readout circuits is the gap of the semiconductor detector. The gap of the semiconductor detector does not function as a radiation detection area. As a result, this is detrimental to the imaging device.

[0078] Another technique for connecting readout chips to circuit boards is through-hole electrodes exposed on the back side of the readout chip. This technique is also known as through-silicon vias (TSVs). Because the TSVs are exposed on the back side of the readout chip, the connection points between the readout chip and the circuit board are the facing portions of the readout chip and the circuit board. This eliminates the need for pads around the readout chip, thus allowing for smaller gaps in the readout circuitry.

[0079] However, to create through-silicon vias (TSVs), the readout chip needs to be thin to a specified thickness. As a result, the mechanical strength of the readout chip decreases. When the mechanical strength of the readout chip decreases, the bonding process between the charge generation chip and the readout chip becomes more difficult. Specifically, maintaining the charge generation chip and the readout chip becomes more challenging. Furthermore, it increases the difficulty of placing the readout chip onto the circuit board.

[0080] Based on the aforementioned technical background, the inventors of this application have invented a radiation imaging device 1. Specifically, the charge generation chip 20 and the readout chip 30 are stacked in a manner where their positions are offset horizontally, rather than stacked one-to-one. Then, for each readout chip 30, electrodes disposed on the surface of the readout chip 30 are connected to each other via signal connection wiring 20e disposed on the charge generation chip 20.

[0081] In simple terms, the readout chip 30 of the X-ray imaging apparatus 1 has signal input / output electrodes 30e disposed on the readout rewiring input surface 31a facing the charge generation chip 20. For example, the signal input / output electrodes 30e of the outer readout chip 30S are connected to the signal input / output electrodes 30e of the inner readout chip 30K via signal connection wiring 20e disposed on the charge generation chip 20. Therefore, by configuring the charge generation chip 20 to span adjacent readout chips 30, the outer readout chip 30S can be connected to the inner readout chip 30K. As a result, the outer readout chip 30S can be easily connected to the inner readout chip 30K, thus suppressing operational defects during the assembly of the X-ray imaging apparatus 1. Consequently, a decrease in yield can be suppressed.

[0082] Based on this connection structure, it is unnecessary to set pads around each readout chip 30. Furthermore, it is unnecessary to set charge generation chips and readout chips within the readout chip 30.

[0083] As a result, the X-ray imaging apparatus 1 achieves the following effects: Since there is no need to provide pads around the readout chip 30, the spacing between the readout chips 30 can be reduced. Because the readout chip 30 and the charge generation chip 20 are offset, the charge generation chip 20 exists above the gap between the readout chips 30. Therefore, the charge generation chip 20 is less affected by the gap between the readout chips 30. Since there is no need to provide through-silicon vias (TSVs) in the readout chip 30, there is no need to thin-film the readout chip 30. As a result, the decrease in mechanical strength caused by thin-film forming is suppressed, making it easier to process the readout chip 30. Furthermore, since the readout chip 30 has sufficient thickness, it can withstand the thermal stress generated in the readout chip 30 due to heat generated during operation.

[0084] Furthermore, the through-silicon vias (TSVs) are not exposed on the back side of the readout chip 30. Therefore, a process for connecting the TSVs to the electrodes of the circuit board 4 is unnecessary. In addition, since the TSVs are not exposed on the back side of the readout chip 30, the back side of the readout chip 30 is flat. This reduces the mounting dimension error of the readout chip 30 relative to the circuit board 4. Specifically, the readout chip 30 can be easily mounted parallel to the surface of the circuit board 4. Furthermore, the height direction position of each readout chip 30 can be easily aligned using the surface of the circuit board 4 as a reference.

[0085] Processing of thin-film chips, electrical bonding of through-silicon vias, and assembly to meet required mounting precision can all lead to defects. The X-ray imaging apparatus 1 can eliminate these defects in its manufacturing process. As a result, the generation of defective products during the manufacturing of the X-ray imaging apparatus 1 can be suppressed. Therefore, the manufacturing yield of the X-ray imaging apparatus 1 can be improved.

[0086] <Second Implementation>

[0087] Figure 7 Figure 8 is an exploded perspective view showing the charge generation chip 20A and readout chip 30A of the radiation imaging apparatus 1A according to the second embodiment. Figure 7 A diagram showing the connection structure of the radiography apparatus 1A. As described above, when the arrangement interval of the pixels G and the arrangement interval of the signal processing unit 33a are different, the readout rewiring layer 31 is required as a configuration to match the arrangement intervals. In the second embodiment, a radiography apparatus 1A with the same arrangement interval of the pixels G and the arrangement interval of the signal processing unit 33a will be described. That is, the radiography apparatus 1A of the second embodiment does not have a configuration that changes the arrangement interval.

[0088] The radiographic imaging apparatus 1A includes a charge generator 2A and a reader 3A. The charge generator 2A has multiple charge generation chips 20A. In the radiographic imaging apparatus 1 of the first embodiment, the arrangement of the charge output electrode 20g is not limited by the arrangement of the signal processing unit 33a. Conversely, the arrangement of the signal processing unit 33a is not limited by the arrangement of the charge output electrode 20g. On the other hand, in the radiographic imaging apparatus 1A of the second embodiment, the configuration of the charge output electrode 20g is limited by the configuration of the signal processing unit 33a. That is, the charge output electrode 20g is configured to correspond to the configuration of the multiple signal processing units 33a constituting the signal processor 33. In the charge generation chip 20A, the configuration of the charge output electrode 20g is different from that of the charge output electrode 20g of the charge generation chip 20 of the first embodiment. Specifically, in the charge output surface 21b, the charge output electrode 20g is provided only in the area overlapping with the signal processing unit 33a. That is, the charge output electrode 20g is not provided in the area that does not overlap with the signal processing unit 33a. The area that does not overlap with the signal processing unit 33a refers to the area where the signal connection wiring 20e is disposed. Therefore, the charge generation chip 20A of the second embodiment does not have charge output electrodes 20g disposed between the signal connection wiring 20e like the charge generation chip 20 of the first embodiment.

[0089] When this condition is met, the charge output electrodes 20g and the signal processing unit 33a, which are electrically bonded to each other, can overlap in the thickness direction of the charge generation chip 20A and the thickness direction of the readout chip 30A. That is, the arrangement spacing of the charge output electrodes 20g corresponds to the arrangement spacing of the signal processing unit 33a, thus eliminating the need for a configuration that matches the individual arrangement spacings. As a result, as... Figure 7 As shown, the readout chip 30A of the second embodiment does not have a readout redistribution layer 31. The readout chip 30A of the second embodiment only has an output substrate 32. In addition, a charge readout electrode 30g and a signal input / output electrode 30e are provided on the output input surface 32a of the output substrate 32.

[0090] According to the second embodiment of the radiation imaging device 1A, the configuration of the readout chip 30A can be simplified.

[0091] <Third Implementation Method>

[0092] Figure 9 This is an exploded perspective view showing the charge generation chip 20B and readout chip 30B of the radiation imaging apparatus 1B according to the third embodiment. Figure 10 It is shown Figure 9A diagram showing the connection structure of the radiation imaging apparatus 1B. Similar to the radiation imaging apparatus 1 of the first embodiment, the radiation imaging apparatus 1B of the third embodiment employs a configuration where the arrangement of the charge output electrodes 20g is not limited by the arrangement of the signal processing unit 33a. In the first embodiment, a configuration for matching the arrangement intervals is provided in the readout chip 30. This configuration for matching the arrangement intervals can be provided between the semiconductor detection unit 21 and the signal processing unit 33a. Therefore, in the radiation imaging apparatus 1B of the third embodiment, the configuration for matching the arrangement intervals is provided in the charge generation chip 20B.

[0093] like Figure 9 As shown, the radiation imaging device 1B includes a charge generator 2B and a reader 3B. The charge generator 2B has multiple charge generating chips 20B. The reader 3B has multiple readout chips 30B.

[0094] The charge generation chip 20B includes a semiconductor detection unit 21, a control electrode unit 22, and a charge rewiring layer 23 (charge rewiring section). The charge rewiring layer 23 matches the arrangement spacing of the pixels G with the arrangement spacing of the signal processing unit 33a. The charge rewiring layer 23 is disposed on the charge output surface 21b of the semiconductor detection unit 21. The charge rewiring layer 23 has a charge rewiring input surface 23a facing the charge output surface 21b; and a charge rewiring output surface 23b facing the readout chip 30B. In the third embodiment, the charge rewiring output surface 23b corresponds to the charge output surface in the claim.

[0095] A plurality of pixel electrodes 23p are provided on the charge rewiring input surface 23a. The pixel electrodes 23p are arranged separately from each other and in a two-dimensional shape. In the third embodiment, the arrangement of the pixel electrodes 23p corresponds to the arrangement of the pixel G. That is, the arrangement of the pixel electrodes 23p determines the effective pixel area. A charge output electrode 20g, signal connection wirings 20e and 20f are provided on the charge rewiring output surface 23b. Here, the charge rewiring layer 23 includes wiring 23c that electrically connects a pixel electrode 23p and a charge output electrode 20g to each other (see reference). Figure 10 Through this wiring 23c, the arrangement spacing of the charge output electrode 20g can be different from that of the pixel electrode 23p.

[0096] Therefore, the charge output electrode 20g is disposed in the area where the signal connection wirings 20e and 20f are not disposed. In this case, the arrangement of the charge output electrode 20g can correspond to the arrangement of the signal processing unit 33a of the readout chip 30B. That is, it is not necessary to arrange a configuration between the charge output electrode 20g and the signal processing unit 33a to match the arrangement interval. Furthermore, in the charge rewiring output surface 23b, the area where the charge output electrode 20g is disposed and the area where the signal connection wirings 20e and 20f are disposed do not overlap with each other. As a result, the structure of the signal connection wirings 20e and 20f is not limited by the structure of the charge output electrode 20g when determining the structure. For example, in the first embodiment, the signal connection wirings 20e are disposed between the charge output electrodes 20g. Therefore, the width of the signal connection wirings 20e is limited by the interval of the charge output electrodes 20g. That is, the width of the signal connection wirings 20e cannot be greater than the interval of the charge output electrodes 20g. In addition, the signal connection wirings 20e cannot be disposed in the area where the charge output electrodes 20g are disposed.

[0097] In response to this, in the radiation imaging apparatus 1B of the third embodiment, the charge output electrode 20g is not provided in the area where the signal connection lines 20e and 20f are provided. Therefore, the arrangement of the signal connection lines 20e and 20f is not limited by the arrangement of the charge output electrode 20g. For example, a signal connection line 20e with a first width and a signal connection line 20f with a second width greater than the first width can be provided. In addition, the signal connection lines 20e and 20f can be provided at any location in the area where the signal connection lines 20e and 20f can be provided.

[0098] The readout chip 30B has a lead-out substrate 32. That is, the readout chip 30B does not have a readout rewiring layer 31. The lead-out input surface 32a (first readout surface, second readout surface) of the lead-out substrate 32 faces the charge generation chip 20B. Charge readout electrodes 30g, signal input / output electrodes 30e and 30f are provided on the lead-out input surface 32a. The charge readout electrode 30g faces the charge output electrode 20g. The charge readout electrode 30g is electrically connected to the charge output electrode 20g. The arrangement of the charge readout electrode 30g can correspond to the arrangement of the signal processing unit 33a. The signal input / output electrode 30e faces the signal connection wiring 20e. The signal input / output electrode 30e is electrically connected to the signal connection wiring 20e. The signal input / output electrode 30f faces the signal connection wiring 20f. The signal input / output electrode 30f is electrically connected to the signal connection wiring 20f.

[0099] According to the third embodiment of the radiation imaging apparatus 1B, the effective pixel area can be fully ensured while increasing the freedom of shape and configuration of signal connection wirings 20e and 20f.

[0100] <Fourth Implementation>

[0101] Figure 11 This is an exploded perspective view showing the charge generation chip 20C and readout chip 30C of the radiation imaging apparatus 1C according to the fourth embodiment. Figure 12 It is shown Figure 11 The diagram shows the connection structure of the radiation imaging device 1C. Like the first and third embodiments, the radiation imaging device 1C of the fourth embodiment employs a configuration where the arrangement of the pixels G is not limited by the arrangement of the signal processing unit 33a. Therefore, in the radiation imaging device 1C of the fourth embodiment, not only is a configuration for matching the arrangement interval provided in the charge generation chip 20C, but a configuration for matching the arrangement interval is also provided in the readout chip 30C.

[0102] like Figure 11 As shown, the radiation imaging apparatus 1C of the fourth embodiment includes a charge generator 2C and a reader 3C. Furthermore, the charge generator 2C has multiple charge generating chips 20C. The reader 3C has multiple readout chips 30C.

[0103] The charge generation chip 20C includes a semiconductor detection unit 21, a control electrode unit 22, and a charge redistribution layer 23. A pixel electrode 23p is provided on the charge redistribution input surface 23a of the charge redistribution layer 23. The configuration of the pixel electrode 23p can be determined based on the effective pixel area. A charge output electrode 20g and a signal connection wiring 20e are provided on the charge redistribution output surface 23b. The configuration of the charge output electrode 20g and the signal connection wiring 20e is not particularly limited. For example, as... Figure 11 As shown, the region where the charge output electrode 20g is provided and the region where the signal connection wiring 20e is provided may not overlap with each other. Alternatively, for example, as in the first embodiment, the region where the charge output electrode 20g is provided and the region where the signal connection wiring 20e is provided may partially overlap with each other. It should be noted that the arrangement of the charge output electrode 20g does not correspond to the arrangement of the signal processing unit 33a.

[0104] The readout chip 30C includes a readout rewiring layer 31 and an output substrate 32. A charge readout electrode 30g is provided on the readout rewiring input surface 31a (first readout surface) of the readout rewiring layer 31. The arrangement of the charge readout electrode 30g corresponds to the arrangement of the charge output electrode 20g. That is, the charge readout electrode 30g and the charge output electrode 20g are electrically connected. A rewiring electrode 31p is provided on the readout rewiring output surface 31b of the readout rewiring layer 31. The arrangement of the rewiring electrode 31p corresponds to the arrangement of the signal processing unit 33a.

[0105] The first embodiment of the radiation imaging apparatus 1 and the third embodiment of the radiation imaging apparatus 1B each use a rewiring layer to match the arrangement of the pixel G with the arrangement of the signal processing unit 33a. The fourth embodiment of the radiation imaging apparatus 1C uses two rewiring layers to match the arrangement of the pixel G with the arrangement of the signal processing unit 33a. With this configuration, the matching length of each rewiring layer can be shortened.

[0106] The radiation imaging device 1 of the present invention is not limited to the above-described embodiments.

[0107] <First Variation>

[0108] Figure 13 This is an exploded perspective view showing the charge generation chip 20D and readout chips 30D1 to 30D6 of the radiation imaging apparatus 1D in the first modified example. In the radiation imaging apparatus 1 of the first embodiment, one charge generation chip 20 spans four readout chips 30. Therefore, one charge generation chip 20 is electrically connected to adjacent readout chips 30. For example, as... Figure 13 The first modified example of the radiographic imaging device 1D shown has a charge generation chip 20D that can span more than four readout chips 30D1 to 30D6. Figure 13 The charge generation chip 20D shown spans the first readout chip 30D1, the second readout chip 30D2, the third readout chip 30D3, the fourth readout chip 30D4, the fifth readout chip 30D5, and the sixth readout chip 30D6. Therefore, the charge generation chip 20D has a first output region 21F1, a second output region 21F2, a third output region 21F3, a fourth output region 21F4, a fifth output region 21F5, and a sixth output region 21F6. The first output region 21F1, the second output region 21F2, the third output region 21F3, the fourth output region 21F4, the fifth output region 21F5, and the sixth output region 21F6 each face the first readout chip 30D1, the second readout chip 30D2, the third readout chip 30D3, the fourth readout chip 30D4, the fifth readout chip 30D5, and the sixth readout chip 30D6.

[0109] The charge generation chip 20D is connected to three first readout chips 30D1, second readout chips 30D2, and third readout chips 30D3 (third readout chips) arranged side-by-side along the left-right direction of the paper. The third readout chip 30D3 has a readout rewiring input surface 31a serving as the third readout surface and signal input / output electrodes 30e serving as the third signal input / output electrodes. Furthermore, the charge generation chip 20D is also connected to three fourth readout chips 30D4, fifth readout chips 30D5, and sixth readout chips 30D6 arranged side-by-side along the left-right direction of the paper. The charge generation chip 20D has a first signal connection wiring 20e1, a second signal connection wiring 20e2, a third signal connection wiring 20e3, and a fourth signal connection wiring 20e4. The first signal connection wiring 20e1 connects the signal input / output electrodes 30e of the first readout chip 30D1 to the signal input / output electrodes 30e1 of the second readout chip 30D2. The second signal connection wiring 20e2 (additional signal connection wiring) connects another signal input / output electrode 30e2 (second additional signal input / output electrode) of the second read chip 30D2 to the signal input / output electrode 30e of the third read chip 30D3. The third signal connection wiring 20e3 connects the signal input / output electrode 30e of the fourth read chip 30D4 to the signal input / output electrode 30e of the fifth read chip 30D5. The fourth signal connection wiring 20e4 connects the signal input / output electrode 30e of the fifth read chip 30D5 to the signal input / output electrode 30e of the sixth read chip 30D6. With this configuration, the first read chip 30D1 can be connected to the third read chip 30D3 via the second read chip 30D2 through a charge generation chip 20D. Similarly, the fourth read chip 30D4 can be connected to the sixth read chip 30D6 via the fifth read chip 30D5.

[0110] <Second Variation>

[0111] Figure 14 This is an exploded perspective view showing the charge generation chip 20E and readout chips 30E1 to 30E6 of the radiation imaging apparatus 1E in the second modified example. In the radiation imaging apparatus 1D of the first modified example, a first signal connection wiring 20e1 electrically connects the first readout chip 30D1 to the second readout chip 30D2. For example, Figure 14The second variation of the radiographic imaging apparatus 1E includes a signal connection line 20e5 that extends from the first readout chip 30E1 via the second readout chip 30E2 to the third readout chip 30E3. Similarly, the signal connection line 20e6 extends from the fourth readout chip 30E4 via the fifth readout chip 30E5 to the sixth readout chip 30E6. According to this configuration, the first readout chip 30E1 can be directly connected to the third readout chip 30E3 via the signal connection line 20e5 through a charge generation chip 20e. Similarly, the fourth readout chip 30E4 can be directly connected to the sixth readout chip 30E6 via the signal connection line 20e6.

[0112] Explanation of reference numerals in the attached figures

[0113] 1, 1A, 1B, 1C, 1D, 1E: Radiation imaging device; 4: Circuit board; 20, 20A, 20B, 20C, 20D, 20E: Charge generation chip; 20e, 20f: Signal connection wiring; 20e2: Second signal connection wiring (additional signal connection wiring); 21F1: First output area; 21F2: Second output area; 21F3: Third output area; 21F4: Fourth output area; 20g: Charge output electrode; 21: Semiconductor detection unit; 23: Charge rewiring layer (charge rewiring section); 23p: Pixel electrode; 30e: Signal input / output electrode (first signal input / output electrode, second signal input / output electrode); 30e2: Signal input / output electrode (second additional signal input / output electrode); 30g: Charge readout electrode; 31: Readout rewiring layer (readout rewiring section); 31p: Rewiring electrode; 32: Outgoing substrate (outgoing section).

Claims

1. A radiation imaging device, wherein, include: A charge-generating chip that generates a charge corresponding to the energy or number of particles of the incident radiation; The first readout chip is electrically connected to the charge generation chip and outputs a digital value based on the charge received from the charge generation chip; The second readout chip is electrically connected to the charge generation chip and outputs a digital value based on the charge received from the charge generation chip, and is adjacent to the first readout chip; as well as The circuit board is equipped with the first readout chip and the second readout chip; The charge generation chip has a charge output surface, which includes a first output area facing the first readout chip and a second output area facing the second readout chip. The first readout chip has a first readout surface facing the charge output surface and a first signal input / output electrode disposed on the first readout surface. The second readout chip has a second readout surface facing the charge output surface and a second signal input / output electrode disposed on the second readout surface. The charge generation chip has a signal connection wiring that, on the charge output surface, spans between the first readout chip and the second readout chip, extends from the first output region to the second output region, and electrically connects the first signal input / output electrode to the second signal input / output electrode.

2. The radiation imaging device according to claim 1, wherein, The charge generation chip has multiple charge output electrodes disposed on the charge output surface. The first readout chip has: a plurality of charge readout electrodes disposed on the first readout surface, facing the charge output electrode and electrically connected to the charge output electrode.

3. The radiation imaging apparatus according to claim 2, wherein, The charge generation chip includes a charge output surface with the signal connection wiring and the charge output electrode, and a semiconductor detection unit that outputs the charge from the charge output electrode. The first readout chip includes a first readout surface provided with the first signal input / output electrode and the charge readout electrode, and has a derivation section for generating a digital value based on the charge received from the semiconductor detection section.

4. The radiation imaging apparatus according to claim 2, wherein, The charge generation chip has: The charge redistribution section includes a charge output surface on which the signal connection wiring and the charge output electrode are disposed; as well as The semiconductor detection unit outputs the charge to the charge redistribution unit via multiple pixel electrodes that are separated from each other; The first readout chip includes a first readout surface provided with the first signal input / output electrode and the charge readout electrode, and has a derivation section for generating a digital value based on the charge received from the charge rewiring section. The arrangement spacing of the pixel electrodes is different from that of the charge output electrodes.

5. The radiographic imaging apparatus according to claim 2, wherein, The charge generation chip includes a charge output surface with the signal connection wiring and the charge output electrode, and a semiconductor detection unit that outputs the charge from the charge output electrode. The first readout chip has: The readout rewiring section includes a first readout surface provided with the first signal input / output electrode and the charge readout electrode; and The output section generates the digital value based on the charge received from the readout rewiring section via a plurality of rewiring electrodes that are separated from each other; The spacing between the rewiring electrodes is different from the spacing between the charge readout electrodes.

6. The radiographic imaging apparatus according to claim 2, wherein, The charge generation chip has: The charge redistribution section includes a charge output surface on which the signal connection wiring and the charge output electrode are disposed; as well as The semiconductor detection unit outputs the charge to the charge redistribution unit via multiple pixel electrodes that are separated from each other; The first readout chip has: The readout rewiring section includes a first readout surface provided with the first signal input / output electrode and the charge readout electrode; as well as The output section generates the digital value based on the charge received from the readout rewiring section via a plurality of rewiring electrodes that are separated from each other; The pixel electrode spacing is different from the charge output electrode spacing. The spacing between the rewiring electrodes is different from the spacing between the charge readout electrodes.

7. The radiographic imaging apparatus according to any one of claims 1 to 6, wherein, It also includes: a third readout chip, electrically connected to the charge generation chip, outputting a digital value based on the charge received from the charge generation chip, and adjacent to the second readout chip. The third readout chip has: a third readout surface facing the charge output surface; and a third signal input / output electrode disposed on the third readout surface; The charge output surface of the charge generation chip further includes a third output region facing the third readout chip. The second readout chip also has a second additional signal input / output electrode disposed on the second readout surface. The charge generation chip further includes: an additional signal connection wiring extending from the second output region to the third output region, and electrically connecting the second additional signal input / output electrode to the third signal input / output electrode.

8. The radiographic imaging apparatus according to any one of claims 1 to 6, wherein, It also includes: a third readout chip, electrically connected to the charge generation chip, outputting a digital value based on the charge received from the charge generation chip, and adjacent to the second readout chip. The third readout chip has: a third readout surface facing the charge output surface; and a third signal input / output electrode disposed on the third readout surface; The charge output surface of the charge generation chip further includes a third output region facing the third readout chip. The signal connection wiring is provided across the first output area, the second output area and the third output area, and electrically connects the first signal input / output electrode, the second signal input / output electrode and the third signal input / output electrode to each other.

Images