Polarity self-controlled wideband large-scale dither structure applied to differential input

Abstract

The application discloses a polar self-control wideband large-amplitude dither structure applied to differential input, which comprises a counter, two zero-crossing comparators, an improved PN code generator, a DAC, a register, two adders, a differential ADC, a look-up table module, a delay module and a subtractor; the zero-crossing comparator added at the input end can control the positive and negative polarity of random noise with low complexity, and ensures that the final signal amplitude does not exceed the quantization range; in addition to the method of combining the multiplication congruence method with the Fibonacci sequence, the initial sequence generated by the Fibonacci sequence is changed by using an improved random number generation formula, so that the randomness is enhanced; a group of different uniformly distributed random sequences is generated by using a simple logic structure for the generated PN code for differential input; the PN code corresponding to the differential input structure ADC is added, so that the application range of the structure is widened; and the operation demand is not obviously increased, the structure is simple, and the overall complexity is low.

Description

Technical Field

[0001] This invention belongs to the field of analog-to-digital conversion, specifically relating to a polarity-controlled wideband large-amplitude dither structure applied to differential inputs. Background Technology

[0002] Dithering technology in analog-to-digital converters (ADCs) involves adding jitter noise to the ADC's input signal. This jitter noise varies randomly relative to the input signal. Adding dithering during the ADC conversion process improves the ADC's dynamic performance and reduces out-of-band noise. Dithering technology can be categorized into several types based on its characteristics: small-amplitude dithering and large-amplitude dithering; and wideband dithering and narrowband dithering based on the bandwidth of the added noise.

[0003] Regarding the existing dither scheme, Figure 1 This is the basic structure of wideband large-amplitude dithering technology. First, a pseudo-random number generator (PN) generates pseudo-random numbers. Then, a digital-to-analog converter (DAC) converts these pseudo-random numbers into an analog signal, which is then added to the analog input signal. An ADC quantizes the added signal, and the quantized result is subtracted from the previously generated pseudo-random number to remove noise, yielding the final quantized result. This process achieves the functions of wideband large-amplitude dithering technology, namely, reducing harmonics generated during coherent sampling, reducing quantization errors, randomizing quantization noise, averaging differential nonlinearity macroscopically, and improving the spurious-free dynamic range of the ADC. However, because the amplitude of the analog input signal is uncertain, the amplitude of the dither signal added to this structure cannot be too large; otherwise, signal overflow can easily occur, meaning the total amplitude of the input signal after adding the dither signal exceeds the quantization range, causing the final input signal amplitude to exceed the quantization range, thus affecting the dynamic range of the input signal and leading to quantization errors. A common amplitude adaptive method now requires a high-speed comparator to detect the maximum and minimum amplitudes of the input signal, which increases design complexity. At the same time, this structure requires the DAC to have the same number of quantization bits as the ADC, which is equivalent to integrating a DAC with the same resolution inside the ADC. When the ADC has a very high number of quantization bits, it will greatly increase the complexity of system design and implementation.

[0004] Figure 2This is a common, improved wideband large-amplitude dithering technique with a basic structure representing a stored dither. Firstly, it adds a voltage conversion module, eliminating the need for the DAC (Digital Converter) to maintain the same bit depth as the ADC (Digital Converter), significantly reducing design and implementation complexity. Secondly, it adds a code table and counter module. During the first few clock cycles after ADC reset, the counter controls a switch to cut off the analog signal, preventing the input signal from entering the ADC. At this time, all random numbers generated by the PN code generator are quantized by the DAC and ADC. The quantized codewords are mapped one-to-one with the PN sequence codes to establish a code table for storage. After the code table is established, the counter controls the ADC to quantize the input signal after dithering. By looking up the code table, the ADC quantization result is subtracted from the codeword corresponding to the dither noise to obtain the codeword of the input signal. This structure, while ensuring accuracy, can quickly complete subtraction, improving the speed of the entire process. Thirdly, for the generation of PN sequences, it uses a combination of multiplicative congruence and Fibonacci sequence methods. Compared to traditional multiplicative congruence methods and methods using shift registers, this overcomes the non-uniformity and short periodicity of high dimensions, improving the quality of the random number sequence. However, to reduce computational complexity, this structure selects several smaller values ​​from the typical parameters of the Fibonacci sequence. The amplitude of dither (usually in the tens) may be smaller than this typical value. This results in strong repetition in the first few terms of the generated random number sequence when the sequence length is short. Therefore, when the required sequence length is short, the overall good randomness is compromised, reducing the quality of the random number sequence and weakening the overall good randomness. Furthermore, this structure only has one set of sequence outputs and cannot be directly applied to differential input ADCs. To apply it to differential input ADCs, directly adding a PN code generator would increase the overall circuit area and computational complexity. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a polarity-controlled wideband large-amplitude dither structure applied to differential inputs. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] A polarity-controlled wideband large-amplitude dither structure applied to differential inputs includes:

[0007] A counter is used to control the switch to receive differential input analog signals after the lookup table is built.

[0008] Two zero-crossing comparators are used to receive one differential input analog signal respectively, perform zero-crossing comparison, and generate the corresponding control signal input to the improved PN code generator;

[0009] An improved PN code generator is used to generate a random number using an improved random number generation formula, logically process the generated random number into two random numbers, and process the highest bit of the two random numbers according to two input control signals to obtain two target random numbers with polarity self-control corresponding to the input of the differential ADC; wherein, the improved random number generation formula uses the multiplication congruence method to generate the initial random number, and uses the delayed Fibonacci sequence algorithm to generate the random number after the initial random number;

[0010] A DAC is used to receive the target random number and generate a corresponding analog signal;

[0011] A register is used to buffer the analog signal output by the DAC;

[0012] Two adders are used to receive one analog signal output from the register and add it to the corresponding differential input analog signal to obtain the corresponding summed analog signal input differential ADC;

[0013] A differential ADC is used to quantize two summed analog input signals to obtain differential ADC quantization codewords.

[0014] The lookup table module is used to receive the target random number and determine the corresponding quantized codeword in a pre-constructed lookup table;

[0015] The delay module is used to delay the quantized codewords determined in the lookup table;

[0016] The subtractor is used to subtract the quantized codeword of the differential ADC from the quantized codeword output by the delay module to obtain the final output codeword.

[0017] In one embodiment of the present invention, the process of constructing the lookup table includes:

[0018] Before the differential ADC is reset, the differential input analog signal is cut off by the counter control switch;

[0019] The improved PN code generator is controlled to produce a ladder signal containing all the possibilities of random numbers;

[0020] The stepped signal is processed based on the DAC and the differential ADC to output the quantized codeword;

[0021] A lookup table is constructed and stored based on the mapping relationship between the quantized codewords and their corresponding digital codes.

[0022] In one embodiment of the present invention, the improved random number generation formula includes:

[0023]

[0024] Among them, X i+1 Let be the (i+1)th random number in the random number sequence; mod is the modulo function; M is the amplitude of dither, which is a prime number; a1~a k Let be the different values ​​of parameter a, where a is a prime number coprime to M; (q, p) are the parameter values ​​in the Fibonacci sequence; when M ≤ p, k > 1.

[0025] In one embodiment of the present invention, the step of logically processing the generated random number into two random numbers includes:

[0026] Based on the mathematical logic calculation of M and the random number, another random number corresponding to the random number is obtained.

[0027] In one embodiment of the present invention, the mathematical logic calculation based on M and the random number to obtain another random number corresponding to the random number includes:

[0028] Let the generated random number be denoted as number, where number is the random number X corresponding to the input P terminal of the differential ADC. P ;

[0029] Another random number is calculated using M-number-1, which serves as the random number X corresponding to the input N terminal of the differential ADC. N .

[0030] In one embodiment of the present invention, the control signals generated by the two zero-crossing comparators are both 1-bit, including 1 or 0.

[0031] In one embodiment of the present invention, the step of processing the most significant bit of the two random numbers according to the two input control signals to obtain two target random numbers with polarity self-control corresponding to the input of the differential ADC includes:

[0032] Divide the random number range into intervals using (M-1) / 2 as the intermediate value. Based on the control signal and the range in which the random number X falls, process the highest bit of the random number X to obtain the corresponding target random number; where X is X P or X N .

[0033] In one embodiment of the present invention, the step of dividing the random number range using (M-1) / 2 as an intermediate value, and processing the highest bit of the random number X according to the control signal and the range in which the random number X is located to obtain the corresponding target random number includes:

[0034] When the control signal is 1, if X is greater than (M-1) / 2, the target random number output by the improved PN code generator is X-(M+1) / 2; if X is less than or equal to (M-1) / 2, the target random number output by the improved PN code generator is X.

[0035] When the control signal is 0, if X is greater than (M-1) / 2, the target random number output by the improved PN code generator is X; if X is less than or equal to (M-1) / 2, the target random number output by the improved PN code generator is X+(M+1) / 2.

[0036] In one embodiment of the present invention, the clock frequency of the DAC is twice or more than that of the differential ADC.

[0037] In one embodiment of the present invention, (q, p) takes the value (24, 55).

[0038] The beneficial effects of this invention are:

[0039] This invention addresses the problems encountered in the application of commonly used dithering techniques in ADCs, such as the sum of random noise amplitude and input signal amplitude exceeding the quantization range, and insufficient randomness of random noise. Based on the stored-type dithering, it improves the original structure and proposes a polarity-controlled wideband large-amplitude dithering structure for differential inputs. Regarding randomness, a zero-crossing comparator is added at the input to judge the input signal and accordingly change the highest bit of the pseudo-random number, controlling the positive and negative polarities of random noise with low complexity, achieving polarity self-control. This polarity self-control adjusts the dynamic range of the final input signal, ensuring that the final signal amplitude does not exceed the quantization range. In terms of random noise generation, in addition to using a combination of multiplicative congruence and the Fibonacci sequence, this invention addresses the phenomenon of small-part random sequence repetition caused by the amplitude value of the wideband large-amplitude dithering being less than the typical value of the parameters in the Fibonacci sequence. It utilizes an improved random number generation formula to modify the Fibonacci sequence. The initial sequence generated by the sequence enhances its randomness, thereby improving the overall randomness of the sequence while still achieving the dither's inherent functions, such as reducing harmonics generated during coherent sampling, reducing quantization errors, randomizing quantization noise, averaging differential nonlinearity on a macroscopic level, and improving the spurious-free dynamic range of the ADC. This is especially true for shorter sequences, where the randomness is significantly enhanced, leading to better performance in ADCs. For differential input structures, this embodiment of the invention performs logical operations on the generated PN code to generate a set of different uniformly distributed random sequences for differential input with a simple logical structure. Furthermore, the addition of the PN code corresponding to the differential input structure ADC broadens the application range of this structure. While traditional storage-type dithers are mostly used in pipelined ADCs, the structure of this invention can also be applied to other ADCs such as SAR ADCs (successive approximation analog-to-digital converters) and Sigma-Delta ADCs. Additionally, this embodiment of the invention does not significantly increase computational requirements, has a simple structure, and low overall complexity. Attached Figure Description

[0040] Figure 1 A schematic diagram of the additive / subtractive structure of a traditional broadband dithering system;

[0041] Figure 2 This is a schematic diagram of an existing improved broadband large-amplitude dither structure;

[0042] Figure 3 This is a schematic diagram of a polarity-controlled wideband large-amplitude dither structure applied to differential input, provided by an embodiment of the present invention.

[0043] Figure 4 This is a schematic diagram illustrating the principle of generating PN sequences for differential input in an embodiment of the present invention. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] like Figure 3 As shown in the embodiment of the present invention, a polarity-controlled wideband large-amplitude dither structure applied to differential inputs may include:

[0046] A counter is used to control the switch to receive differential input analog signals after the lookup table is built.

[0047] Two zero-crossing comparators are used to receive one differential input analog signal respectively, perform zero-crossing comparison, and generate the corresponding control signal input to the improved PN code generator;

[0048] An improved PN code generator is used to generate a random number using an improved random number generation formula, logically process the generated random number into two random numbers, and process the highest bit of the two random numbers according to two input control signals to obtain two target random numbers with polarity self-control corresponding to the input of the differential ADC; wherein, the improved random number generation formula uses the multiplication congruence method to generate the initial random number, and uses the delayed Fibonacci sequence algorithm to generate the random number after the initial random number;

[0049] A DAC is used to receive the target random number and generate a corresponding analog signal; wherein the DAC is m-bit; m is a natural number greater than 0;

[0050] A register is used to buffer the analog signal output by the DAC;

[0051] Two adders are used to receive one analog signal output from the register and add it to the corresponding differential input analog signal to obtain the corresponding summed analog signal input differential ADC;

[0052] A differential ADC is used to quantize two input summed analog signals to obtain differential ADC quantization codewords; wherein the differential ADC is n-bit, where n is a natural number greater than 0, and m < n;

[0053] The lookup table module is used to receive the target random number and determine the corresponding quantized codeword in a pre-constructed lookup table;

[0054] The delay module is used to delay the quantized codewords determined in the lookup table;

[0055] The subtractor is used to subtract the quantized codeword of the differential ADC from the quantized codeword output by the delay module to obtain the final output codeword.

[0056] The following combination Figure 3 This paper provides a detailed explanation of the polarity-controlled wideband large amplitude dither structure applied to differential inputs and its working principle.

[0057] Please Figure 2 Based on the improved wideband large-amplitude dither structure shown, before this polarity-controlled wideband large-amplitude dither structure applied to differential inputs can operate, a lookup table needs to be constructed first. This process can be considered a preparation stage. Specifically, the construction process of the lookup table includes:

[0058] 1) Before the differential ADC is reset, the differential input analog signal is cut off by the counter control switch;

[0059] It is understandable that after the counter control switch cuts off the differential input analog signal, the differential input analog signal will not enter the differential ADC, nor will it enter the zero-crossing comparator. Figure 3 In the diagram, IN+ and IN- represent two paths of the differential input analog signal, corresponding to the positive and negative signals, respectively.

[0060] 2) Control the improved PN code generator to generate a ladder signal containing all possible random numbers;

[0061] This step involves the improved PN code generator generating and sending a ladder signal containing all possible random numbers multiple times to cover the lookup range of codewords in the lookup table. The improved PN code generator generates all possible random numbers using an improved random number generation formula. It can be understood that, due to the remainder when M is taken, the possible value range is from 0 to M-1. The specific generation process will not be described in detail here.

[0062] 3) The stepped signal is processed based on the DAC and the differential ADC to output the quantized codeword;

[0063] Among them, DAC converts digital signals, i.e., stepped signals, into analog signals; differential ADC quantizes the input analog signal and outputs the quantized codeword.

[0064] 4) Construct a lookup table and store it based on the mapping relationship between the codewords obtained by quantization and the corresponding digital codes.

[0065] The digital code corresponding to the codeword obtained by quantization is the random number generated by the improved PN code generator.

[0066] The constructed lookup table is also known as a code table, where each random number generated by the improved PN code generator corresponds to a quantized codeword. In this embodiment of the invention, the lookup table is stored in the lookup table module after construction.

[0067] The following describes the working process of the polarity-controlled wideband large-amplitude dither structure applied to differential inputs.

[0068] First, after the lookup table is built, the counter control switch receives the differential input analog signal. At this time, the differential input analog signal simultaneously enters the corresponding zero-crossing comparator and the corresponding adder. Please refer to [link to relevant documentation]. Figure 3 Understand, IN+ enters the zero-crossing comparator below and the adder above, while IN- enters the zero-crossing comparator above and the adder below.

[0069] A zero-crossing comparator performs zero-crossing processing on the input analog signal. Essentially, a zero-crossing comparator is a two-input comparator where one input is grounded (i.e., the other input is compared to 0), and the output is a control signal. This control signal indicates the positive or negative status of the corresponding analog signal and can be implemented using different voltage levels or digital codes. For example, in one possible implementation, the control signals generated by both zero-crossing comparators are each 1-bit, containing either 1 or 0. A control signal of 1 indicates that the corresponding analog signal is positive, and a control signal of 0 indicates that the corresponding analog signal is negative.

[0070] The improved PN code generator receives control signals from two zero-crossing comparators, and then enters the PN code generation stage.

[0071] In the PN code generation stage, the improved PN code generator first generates a random number using an improved random number generation formula. To facilitate understanding of the random numbers generated by the improved PN code generator, the method of generating the PN sequence, i.e., the method of generating the random number sequence, is introduced here.

[0072] Unlike multiplicative congruent sequences, which have high-dimensional non-uniformity and short periodicity, and unlike m-sequences, which only have long periodicity when there are enough shift registers, the Fibonacci sequence can generate a uniformly distributed sequence with long periodicity as long as the initialization sequence (which is determined by the typical Fibonacci value and is therefore relatively short) has good randomness.

[0073] Therefore, this embodiment of the invention improves the random number generation formula. In the improved random number generation formula, an initial random number is first generated using the multiplicative congruence method, i.e., an initial Fibonacci sequence is generated to ensure sufficient randomness when the sequence is short. Then, a delayed Fibonacci sequence algorithm is used to generate random numbers after the initial random number. The improved random number generation formula includes:

[0074]

[0075] Among them, X i+1 Let be the (i+1)th random number in the random number sequence; mod is the modulo function; M is the amplitude of dither, which is a prime number; a1~a k Let be the different values ​​of parameter a, where a is a prime number coprime to M; (q, p) are the parameter values ​​in the Fibonacci sequence; when M ≤ p, k > 1.

[0076] Typical values ​​of (q, p) may include: (24, 55), (30, 127), (85, 285), (107, 378), (576, 3217), (1029, 2287), etc. In one optional implementation, in order to reduce computational complexity, (q, p) is taken as (24, 55).

[0077] Secondly, existing methods generally generate a sufficient number of initial sequences directly using a single parameter 'a' in the congruential sequence. However, when M ≤ p, random numbers exceeding M will fall into a loop due to the short periodicity of the congruential method. That is, the first M terms are random, and the values ​​between the Mth and pth terms (i.e., p-M+1 values) will fall into a loop. Therefore, to solve this problem, as shown in the above formula, when M ≤ p, the value of 'a' is changed once each time M is exceeded. For large dithers, M is generally in the tens, so only one or two changes to the value of 'a' are needed. This does not increase computational complexity. In the circuit implementation, different inputs are given at different periods, followed by multiplication with the same number of bits. At the same time, it can ensure that the first few terms of the PN sequence have good randomness. As long as the value of parameter 'a' is different, the possible repetition of the sequence can be completely eliminated. It can be seen that the embodiment of the present invention can ensure the randomness of the entire sequence, especially the initial part of the sequence, by adding different coprime numbers, thereby ensuring good performance. Furthermore, since the initial sequence is generated using the congruential method, the speed is very fast.

[0078] After generating the initial Fibonacci sequence, a delayed Fibonacci sequence algorithm is used to generate high-dimensional random numbers. The newly generated random number X is then set to... i+1 With the previous random number X i-q X i-p Related.

[0079] In summary, the present invention uses the multiplicative congruence method to generate the first p initial random numbers (the calculation formula can be found in the first row to the second to last row of formula (1)). The generation of the p+1th random number uses the delayed Fibonacci sequence algorithm (the calculation formula can be found in the last row of formula (1)). The generated PN sequence can solve the problem of short periodicity of the multiplicative congruence sequence, and at the same time can achieve a uniform distribution with long periodicity.

[0080] Based on the above process, it can be understood that the improved PN code generator can generate a random number in each iteration using an improved random number generation formula. For each iteration, in order to simultaneously input the two inputs of the differential ADC, the generated random number needs to be logically processed into two random numbers.

[0081] In one optional implementation, the step of logically processing the generated random number into two random numbers may include:

[0082] Based on the mathematical logic calculation of M and the random number, another random number corresponding to the random number is obtained.

[0083] Specifically, this may include:

[0084] Let the generated random number be denoted as number, where number is the random number X corresponding to the input P terminal of the differential ADC. P ;

[0085] Another random number is calculated using M-number-1, which serves as the random number X corresponding to the input N terminal of the differential ADC. N .

[0086] Since the result is modulo M, the random number must be less than M. Obtaining two random numbers only requires simple logical operations on the existing random numbers, so the complexity is extremely low.

[0087] Please refer to the following process. Figure 4 The above diagram illustrates this. Where X... P Let X be a number. N It is M-number-1.

[0088] In obtaining X N and X N Subsequently, in order to ensure that the total input signal does not overflow, this embodiment of the invention processes the highest bit of the two random numbers according to the two input control signals to obtain two target random numbers with polarity self-control corresponding to the input of the differential ADC, so that the polarity meets the requirements.

[0089] In one optional implementation, the step of processing the most significant bit of the two random numbers according to the two input control signals to obtain two target random numbers with polarity self-control corresponding to the input of the differential ADC includes:

[0090] Divide the random number range into intervals using (M-1) / 2 as the intermediate value. Based on the control signal and the range in which the random number X falls, process the highest bit of the random number X to obtain the corresponding target random number; where X is X P or X N .

[0091] Specifically, since M is a prime number, M must be an odd number. The random number can be divided into two parts with (M-1) / 2 (i.e. 0) as the intermediate value. Values ​​less than (M-1) / 2 are called negative polarity (corresponding to random numbers less than 0) after DAC conversion, and vice versa (corresponding to random numbers greater than 0).

[0092] For example, if the control signal is 1 or 0, please refer to [link / reference]. Figure 4 Understandably, the above process may include:

[0093] (1) When the control signal is 1, if X is greater than (M-1) / 2, the target random number output by the improved PN code generator is X-(M+1) / 2; if X is less than or equal to (M-1) / 2, the target random number output by the improved PN code generator is X.

[0094] Specifically, when the control signal is 1, it indicates that the corresponding differential input analog signal is positive, and the random number should take negative polarity, that is, the highest bit of the random number should be 0. If X is greater than (M-1) / 2, it means that the highest bit of the original random number is 1 and needs to be changed to 0. Therefore, the target random number output by the improved PN code generator is X-(M+1) / 2. If X is less than or equal to (M-1) / 2, it means that the highest bit of the original random number is 0. Therefore, the target random number output by the improved PN code generator is X.

[0095] (2) When the control signal is 0, if X is greater than (M-1) / 2, the target random number output by the improved PN code generator is X; if X is less than or equal to (M-1) / 2, the target random number output by the improved PN code generator is X+(M+1) / 2.

[0096] Specifically, when the control signal is 0, it means that the corresponding differential input analog signal is negative, and the random number should be positive, that is, the highest bit of the random number should be 1. If X is greater than (M-1) / 2, it means that the highest bit of the original random number is 1, so the target random number output by the improved PN code generator is X; if X is less than or equal to (M-1) / 2, it means that the highest bit of the original random number is 0 and needs to be changed to 1, so the target random number output by the improved PN code generator is X+(M+1) / 2.

[0097] The two target random numbers obtained are the two values ​​of the PN sequence corresponding to the differential input after polarity self-control.

[0098] The above approach has two advantages. First, it achieves polarity self-control with a simple structure, ensuring that the total input amplitude does not exceed the quantization range, significantly reducing complexity compared to some common adaptive methods. Second, it only requires simple computational steps to obtain two sets of uniformly distributed random sequences, eliminating the need for an additional PN code generator. This satisfies the requirement of two sets of random numbers for differential input, while essentially not increasing design complexity or area, which is crucial for low-power design requirements.

[0099] The following explains the quantification stage:

[0100] After the PN code, i.e., the target random number, is generated, it is sent to the DAC and lookup table module. The DAC generates a corresponding analog signal, i.e., the converted dither signal, for the input target random number, and then buffers it in a register. It should be noted that in this embodiment of the invention, two target random numbers are generated simultaneously. If two DACs were used to process them separately, it would significantly increase the area. Since the DAC connected to the improved PN code generator has a relatively low bit depth, the fastest clock frequency that can be achieved is much faster than that of the ADC. Before the differential ADC starts working, the improved PN code generator sends two random numbers to its P and N terminals respectively; therefore, to further improve multiplexing, as long as the DAC clock frequency is at least twice the clock frequency of the differential ADC, the conversion result of the two random numbers can be given within one cycle of the ADC, without the need to use two DACs. Therefore, in the preferred embodiment, the DAC clock frequency is at least twice that of the differential ADC.

[0101] After the analog signals corresponding to the two target random numbers are buffered in the register, the two analog signals are input into the corresponding adders.

[0102] Each adder adds one differential input analog signal to the other analog signal to obtain the corresponding summed analog signal, which is then input to the differential ADC. See also... Figure 3 understand.

[0103] The differential ADC quantizes the two summed analog input signals to obtain the differential ADC quantized codewords; for details on the quantization process, please refer to the relevant technical explanations, which will not be described in detail here.

[0104] In the lookup table module, after finding the quantized codeword corresponding to the PN code (i.e., the target random number) in the lookup table, a delay is applied via the delay module. Specifically, for... Figure 3 In terms of the structure, a delay of one ADC cycle is sufficient to accurately correspond to the result after the ADC quantization is completed.

[0105] The differential ADC quantized codeword and the corresponding quantized codeword in the lookup table are delayed and then subtracted using a subtractor to obtain the final output codeword.

[0106] Understandably, besides being accurate and fast, the biggest advantage of this method is that it simplifies the DAC structure, so that it does not need to maintain the same number of bits as the ADC, which greatly reduces the complexity.

[0107] To facilitate understanding of the embodiments of the present invention, a specific example is given below for illustration.

[0108] With M=31, firstly, in the preparation stage, the counter control switch cuts off the differential input analog signal, and the improved PN code generator generates all kinds of random numbers, which are processed by DAC and differential ADC to establish a lookup table and store them.

[0109] After the lookup table is built, the counter controls the differential input analog signal input. The differential input analog signal enters the corresponding zero-crossing comparator and generates a 1-bit control signal, which is then fed into the improved PN code generator. Let the random number generated by the improved PN code generator be denoted as `number`. To generate two inputs simultaneously, X is used. P (number) and X N (30-number) Two random numbers are processed based on a control signal generated by a zero-crossing comparator. The random number 'number' is divided into two parts with 15 as the median. The smaller value is converted by a DAC and becomes negative, while the larger value becomes positive. X will be used to represent X below. P X N .

[0110] When the control signal is 1, meaning the input analog signal is positive, the random number should have a negative polarity, i.e., the highest bit of the random number should be 0. If X is greater than 15, it means the highest bit of the original random number is 1 and needs to be changed to 0. Therefore, the final output of the improved PN code generator is X-16. If X is less than or equal to 15, it means the highest bit of the original random number is 0. Therefore, the final output of the improved PN code generator is X.

[0111] When the control signal is 0, meaning the input analog signal is negative, the random number should have a positive polarity, i.e., the highest bit of the random number should be 1. If X is greater than 15, it means the highest bit of the original random number was 1, so the improved PN code generator directly outputs X; if X is less than or equal to 15, it means the highest bit of the original random number was 0 and needs to be changed to 1, so the improved PN code generator outputs X+16. This yields two values ​​of the PN sequence corresponding to the differential input after polarity self-control.

[0112] In the lookup table, once the quantization result corresponding to the PN code, i.e. the aforementioned target random number, is found, it will be delayed by the delay module to accurately correspond to the result after the ADC quantization is completed.

[0113] This invention addresses the problems encountered in the application of dithering technology commonly used in ADCs, such as the sum of random noise amplitude and input signal amplitude exceeding the quantization range, and insufficient randomness of random noise. Based on the stored-type dithering technology, an improved structure is proposed: a polarity-controlled wideband large-amplitude dithering structure for differential inputs. To address randomness, a zero-crossing comparator is added at the input to judge the input signal and accordingly change the highest bit of the pseudo-random number, controlling the polarity of the random noise with low complexity, achieving polarity self-control. This polarity self-control adjusts the dynamic range of the final input signal, ensuring that the final signal amplitude does not exceed the quantization range. Regarding the random noise generation method, in addition to using a combination of multiplicative congruence and the Fibonacci sequence, this invention addresses the phenomenon of small-part random sequence repetition caused by the amplitude value of the wideband large-amplitude dithering being less than the typical value of the parameters in the Fibonacci sequence. This invention utilizes an improved random number generation formula to modify the Fibonacci sequence... The initial sequence generated by the trichius sequence enhances its randomness. This improves the overall randomness of the sequence while still achieving the dither's inherent functions, such as reducing harmonics during coherent sampling, minimizing quantization errors, randomizing quantization noise, averaging differential nonlinearity on a macroscopic scale, and improving the spurious-free dynamic range of the ADC. This is especially true for shorter sequences, where the randomness is significantly enhanced, leading to better performance in ADCs. For differential input structures, this embodiment uses logical operations on the generated PN code to generate a set of different uniformly distributed random sequences for differential input with a simple logical structure. Furthermore, the addition of the PN code corresponding to the differential input ADC structure broadens its application range. While traditional storage-type dithers are primarily used in pipelined ADCs, this invention's structure can also be applied to other ADCs such as SAR ADCs (successive approximation analog-to-digital converters) and Sigma-Delta ADCs. Additionally, this embodiment does not significantly increase computational requirements, has a simple structure, and low overall complexity.

[0114] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A polarity self-controlled wideband large-swing dither structure applied to differential input, characterized in that, include: A counter is used to control the switch to receive differential input analog signals after the lookup table is built. Two zero-crossing comparators are used to receive one differential input analog signal respectively, perform zero-crossing comparison, and generate the corresponding control signal input to the improved PN code generator; An improved PN code generator is used to generate a random number using an improved random number generation formula, logically process the generated random number into two random numbers, and process the highest bit of the two random numbers according to two input control signals to obtain two target random numbers with polarity self-control corresponding to the input of the differential ADC; wherein, the improved random number generation formula uses the multiplication congruence method to generate the initial random number, and uses the delayed Fibonacci sequence algorithm to generate the random number after the initial random number; A DAC is used to receive the target random number and generate a corresponding analog signal; A register is used to buffer the analog signal output by the DAC; Two adders are used to receive one analog signal output from the register and add it to the corresponding differential input analog signal to obtain the corresponding summed analog signal input differential ADC; A differential ADC is used to quantize two summed analog input signals to obtain differential ADC quantization codewords. The lookup table module is used to receive the target random number and determine the corresponding quantized codeword in a pre-constructed lookup table; The delay module is used to delay the quantized codewords determined in the lookup table; The subtractor is used to subtract the quantized codeword of the differential ADC from the quantized codeword output by the delay module to obtain the final output codeword.

2. The polar self-controlled wideband large-swing dither architecture for differential input of claim 1, wherein, The process of constructing the lookup table includes: Before the differential ADC is reset, the differential input analog signal is cut off by the counter control switch; The improved PN code generator is controlled to produce a ladder signal containing all the possibilities of random numbers; The stepped signal is processed based on the DAC and the differential ADC to output the quantized codeword; A lookup table is constructed and stored based on the mapping relationship between the quantized codewords and their corresponding digital codes.

3. The polar self-controlled wideband large-swing dither architecture for differential input of claim 1, wherein, The improved random number generation formula includes: in, The first random number in the sequence A random number; For the remainder function; Let the value be a prime number representing the amplitude of dither. ~ For parameters Different values ​​of , To and Coprime prime numbers; The parameter value in the Fibonacci sequence; when hour, .

4. The polarity-controlled wideband large-amplitude dither structure applied to differential input according to claim 3, characterized in that, The step of logically processing the generated random number into two random numbers includes: based on The mathematical logic calculation of the random number yields another random number corresponding to it.

5. The polarity-controlled wideband large-amplitude dither structure applied to differential input according to claim 4, characterized in that, The basis The mathematical logic calculation of the random number yields another random number corresponding to it, including: Let the generated random number be denoted as number, where number corresponds to the random number at the input P terminal of the differential ADC. ; use Another random number is calculated and used as the random number corresponding to the input N terminal of the differential ADC. .

6. The polarity-controlled wideband large-amplitude dither structure applied to differential input according to claim 1, characterized in that, The control signals generated by the two zero-crossing comparators are both 1-bit, including 1 or 0.

7. The polarity-controlled wideband large-amplitude dither structure applied to differential input according to claim 5, characterized in that, The process of processing the most significant bit of the two random numbers based on the two input control signals to obtain two target random numbers with polarity self-control, corresponding to the input of the differential ADC, includes: by Divide the random number range into intermediate values, based on the control signal and the random number. The range of the random number The highest bit is processed to obtain the corresponding target random number; where, for or .

8. The polarity-controlled wideband large-amplitude dither structure applied to differential input according to claim 7, characterized in that, The Divide the random number range into intermediate values, based on the control signal and the random number. The range of the random number The highest bit is processed to obtain the corresponding target random number, including: When the control signal is 1, if Greater than The target random number output by the improved PN code generator is: If X is less than or equal to The target random number output by the improved PN code generator is: ; When the control signal is 0, if Greater than The target random number output by the improved PN code generator is: ;like Less than or equal to The target random number output by the improved PN code generator is: .

9. The polarity-controlled wideband large-amplitude dither structure applied to differential input according to claim 1, characterized in that, The clock frequency of the DAC is more than twice that of the differential ADC.

10. The polarity-controlled wideband large-amplitude dither structure applied to differential input according to claim 3, characterized in that, The value is (24, 55).

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