Compiler backend automatic generation method and system
By automatically generating compiler backend code using neural network models, the problem of low compiler backend development efficiency is solved, enabling fast and efficient compiler support.
Patent Information
- Application Number
- CN202311050170.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-21
- Publication Date
- 2025-11-25
- Estimated Expiration
- 2043-08-21
AI Technical Summary
Compiler backend development is inefficient, especially due to differences in instruction set architectures and inconsistent developer styles, making it complex and time-consuming.
A neural network model training method is adopted, and a target-related index table is generated through abstract syntax tree matching and feature extraction. The compiler backend code is automatically generated using a pre-trained Transformer model.
It improves the efficiency of compiler backend development, lowers the threshold and labor costs of chip development, and shortens development time.
Smart Images
Figure CN117075868B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of computers, and particularly relates to automatic generation of compiler code, and especially to automatic generation of compiler backend code. BACKGROUND
[0002] As important basic software for chips, compilers encapsulate high-level languages upwards to improve the development efficiency and compatibility of application software, and adapt to architectures downwards to generate efficient executable code, and are the bridge between software and hardware. The pros and cons of compilation technology determine whether the individualized design of a processor and the advantages of an architecture can be fully utilized to a great extent; and the speed of compiler development directly affects the speed of chip development.
[0003] After decades of efforts, the compiler community has successfully established a powerful modern compiler infrastructure, such as GCC (GNU Compiler Collection), MLIR (Multi-Level Intermediate Representation), and LLVM. Among them, LLVM is a framework system for building compilers, written in C++, which provides support related to compilers and can be used as the background of a variety of language compilers. It is a modular and reusable collection of compiler and tool technologies. Modern compilers usually adopt a three-stage architecture, which divides the compiler into a front end, a middle end, and a back end, providing great flexibility for compiler porting. When a new target architecture needs to be supported, only a back end needs to be developed, and the front end and middle end are reused, greatly improving the efficiency of compiler porting. Existing compiler framework systems, such as LLVM, usually use a target-independent code generation mechanism to support different microprocessors. The target-independent code generation mechanism provides a series of reusable components in the form of interfaces such as classes and virtual methods, which are used to convert the intermediate representation of the compiler into a specified type of machine code. It is not limited to a certain architecture, so it is called target-independent. When developers develop a compiler backend for a new target architecture, they need to manually write code, create specific target-architecture-specific implementations for the provided interfaces, and embed a set of target-specific property values.
[0004] The compiler backend is responsible for code generation and optimization functions and is the core of the entire compiler. Its complexity is the main reason for the low development efficiency. Moreover, different instruction set architectures (ISAs) differ greatly and have their own characteristics. During development, target-architecture-specific information is involved, and different developers are involved in developing backends for different target architectures. The file organization method and code style are inconsistent, which ultimately leads to low efficiency in developing compiler backends.
[0005] With the continuous acceleration of chip development cycles, a large number of new chips are flooding the market. How to efficiently develop compilers for new chips in a short time has become one of the bottlenecks in tool chain development. SUMMARY
[0006] Therefore, the purpose of the present application is to overcome the defects of the prior art described above, to provide a training method for a neural network model generated by a compiler backend, and a compiler backend generation method of a neural network model generated according to the training method.
[0007] According to a first aspect of the present application, a training method for a neural network model generated by a compiler backend is provided, comprising:
[0008] S1: For functions of different target architectures, matching the abstract syntax trees corresponding to the functions in the same group to obtain the statement templates corresponding to the statements in each function, and the positions of the information specific to the target architecture;
[0009] S2: Analyzing the statement templates and the information specific to the target architecture to form a target-related index table to save the mapping relationship from the features to the definition positions of the feature values;
[0010] S3: According to each statement template, searching the target-related index table, and extracting the feature values of the statement template from the target description files of different target architectures to generate the feature sequence corresponding to the statement template under the different target architectures;
[0011] S4: Training the neural network model using the feature sequence.
[0012] According to an embodiment of the present application, the S1 comprises:
[0013] S1-1: Grouping the functions of different target architectures by name and converting them into abstract syntax trees;
[0014] S1-2: Matching the abstract syntax trees corresponding to the functions in the same group to obtain the statement templates corresponding to the statements in each function, and the positions of the information specific to the target architecture.
[0015] 3. The training method of the neural network model according to claim 1 or 2, characterized in that the abstract syntax trees corresponding to the functions in the same group are matched using a tree difference algorithm.
[0016] According to an embodiment of the present application, the S2 comprises:
[0017] S2-1: Constructing features from the commonalities of the statement templates and the information specific to the target architecture respectively from the architecture, function, and statement levels;
[0018] S2-2: Recording the feature names, the levels to which they belong, the associated information of the statement templates, the file names in which the corresponding feature values are located, and the positions of the corresponding feature values in the files to form a target-related index table.
[0019] According to an embodiment of the present application, the S3 comprises:
[0020] S3-1: For each statement template, according to the target architecture name, function name, statement name, find the statement template associated information in the target related index table, determine the features contained in the statement template;
[0021] S3-2: According to the features contained in the statement template, according to the file name and file location in the corresponding target related index table, extract the feature value;
[0022] S3-3: Combine the statement template and the feature value of the statement template into the feature sequence of the statement template under the target architecture.
[0023] According to an embodiment of the present application, when a statement template does not have a corresponding statement in the back end of a target architecture, the feature value of the statement template under the target architecture is empty.
[0024] According to an embodiment of the present application, the S4 comprises:
[0025] S4-1: Input the feature sequence and the corresponding statement into the neural network model in turn;
[0026] S4-2: Repeat S4-1 for a predetermined number of times.
[0027] According to an embodiment of the present application, the feature sequence preserves the correspondence between the statement template and its feature value under different target architectures.
[0028] According to an embodiment of the present application, the neural network model is a pre-trained Transformer model.
[0029] According to a second aspect of the present application, a compiler backend generation method based on the neural network model generated by any of the above methods is provided, for generating a compiler backend according to the target description file of the architecture of the compiler backend to be generated, comprising:
[0030] S1: Replace the corresponding names in the target related index table with the name of the architecture of the compiler backend to be generated;
[0031] S2: Use the target related index table to extract the feature values of each statement template in the code template, and generate the feature sequence of the architecture of the compiler backend to be generated;
[0032] S3: Input the feature sequence into the trained neural network model to generate the compiler backend.
[0033] Through the above embodiment of the present application, the problem of slow and difficult development of the compiler backend can be solved, the chip development threshold is reduced, the time and labor cost are saved, the traditional compiler backend manual transplantation mode is changed, and the compiler development efficiency is greatly improved. BRIEF DESCRIPTION OF DRAWINGS
[0034] The embodiments of the present application are further described below with reference to the drawings, in which:
[0035] Figure 1 is a work framework according to the embodiment of the present application;
[0036] Figure 2 is handwritten code of a getRelocType function according to two architectures of the embodiment of the present application.
[0037] Figure 3 is an example diagram of a feature extraction stage of semantic guidance according to the embodiment of the present application.
[0038] Figure 4 is an example diagram of a target-related index according to the embodiment of the present application.
[0039] Figure 5 is an example diagram of a model training stage according to the embodiment of the present application.
[0040] Figure 6 is an example diagram of a code generation stage according to the embodiment of the present application. DETAILED DESCRIPTION
[0041] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings through specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.
[0042] Through research and analysis on the C++ code of different architecture backends in LLVM, the inventors found that: (1) the various target architecture-specific implementations of the same abstract interface usually have similar code structures and similar expressions; (2) the compiler backend must involve some information specific to target architecture characteristics in the process of supporting different target architectures; (3) different developers, when developing the backends corresponding to different target architectures, have inconsistent code styles, which brings difficulties and obstacles to the development and transplantation of the compiler backend.
[0043] In the past few years, the machine learning community has made great progress in AI generation, and AlphaCode, one of the representatives of AI programming, has proven that AI has the ability to write high-level computer programs. This has inspired the inventors to research "AI-generated compiler". The inventors seek an efficient compiler backend code generation method, i.e., learning the valuable experience of existing compiler backend design through an AI model, automatically generating compiler backend code for a new target architecture, and ultimately achieving automatic development of the compiler backend.
[0044] As shown in Figure 1 , the workflow of the present application is divided into three stages: the semantic-guided feature extraction stage, the model training stage, and the target-architecture-specific code generation stage. The semantic-guided feature extraction stage preprocesses the collected data, extracts features and feature values after generating a code template, and generates a feature sequence (FS). The model training stage inputs the statements corresponding to the statement template T in the code template and the feature sequence FS in each target architecture into the pre-trained Transformer model for training. The target-architecture-specific code generation stage generates target-architecture-specific compiler backend code using the trained model. The three stages are described in detail below.
[0045] I. Semantic-guided feature extraction stage
[0046] The purpose of this stage is to prepare a data set for model training. As shown in Figure 1 , it mainly includes data collection and data preprocessing.
[0047] 1. Data collection
[0048] The keywords "LLVM" and "backends" are used to collect existing target architecture compiler backend code from the Github code repository, and each backend design has a corresponding target description file (*.td, *.h, and *.def files).
[0049] After collecting the data, the data needs to be preprocessed. The existing target architecture compiler backend code is too much and too complex, for example, the ARM backend has 83,704 lines of code, and the existing AI model cannot accurately capture its meaning and cannot be directly used to train the model. Therefore, the present application uses the backend semantics of the compiler to first map the large and complex backend code to a small and precise feature sequence FS, and then use the feature sequence FS to train the AI model. That is, before training the AI model, prepare data that the AI model can "understand".
[0050] 2. Data preprocessing
[0051] The collected data is first cleaned, and the compiler backend of the existing target architecture that cannot be compiled is removed, and then the code is rewritten to unify the code style between different target architectures. For example, the code rewriting can be a function inline operation, as shown in Figure 2 The ARM architecture getRelocTypeInner function is inlined into the getRelocType function, so that it is the same as the getRelocType function style of the MIPS architecture, thereby improving the consistency of the same function across the backend. Next, the collected code is segmented by function, and then each function is converted into an abstract syntax tree (AST). The construction of the abstract syntax tree is a general method, which is a tree representation of the abstract syntax structure of the source code, and each node on the tree represents a structure in the source code.
[0052] The code is segmented by function, that is, functions of different target architectures are grouped by name, functions with the same name are grouped, and tree difference algorithm is used for node matching of the abstract syntax tree. Common tree difference algorithms include GumTree, Myers, etc. According to an embodiment of the present application, GumTree algorithm is used. GumTree is an algorithm based on abstract syntax tree, which finds the longest common subexpression by matching nodes in two syntax trees.
[0053] Taking the getRelocType functions of the ARM architecture and the MIPS architecture as an example, the process of constructing the function template is described. As shown in Figure 3 (a), the left subgraph is the getRelocType function of the ARM architecture after function inline processing, and the right subgraph is the getRelocType function of the MIPS architecture. The similarity of the two functions is calculated by the tree difference algorithm, and a set of statement pairs is obtained. represents the ARM architecture statement, represents the MIPS architecture statement, for example, S4 statement of the ARM architecture, S4 statement of the MIPS architecture.
[0054] Next, each statement pair is matched. The matched node becomes Figure 3 (b) shows five statement templates T0-T4, and the five statement templates further constitute the function template of the getRelocType function; the unmatched node is the information specific to the target architecture, which corresponds to Figure 3 the underlined part in (b) is represented by SV4 and SV5. In the ARM architecture, SV4 and SV5 represent Figure 3(a) is shown in the underlined part of the left figure; in the MIPS architecture, the contents represented by SV4 and SV5 are as follows Figure 3 (a) is shown in the underlined part of the right figure.
[0055] The tree difference algorithm is used to match the nodes of the abstract syntax trees in all function groups, to obtain the statement templates T contained in each function group, and the statement templates T have positions embedded with information specific to the target architecture. The statement templates T are obtained, and then the function templates corresponding to the respective functions are also obtained. All the function templates constitute the code templates of the existing compiler backends, and the code templates are the features at the compiler level independent of the target architecture. Because the code templates are the union of the function templates of the compiler backends of all existing architectures and the union of the statement templates of the compiler backends of all existing architectures, the statement templates of the compiler backend of a specific architecture are a subset of the code templates.
[0056] Based on the code templates and the information specific to the target architecture, artificial experience is used to construct features. In one embodiment of the present application, a total of 345 features are constructed, in which the getRelocType function template and the information specific to the target architecture (the contents corresponding to SV4 and SV5) related to the getRelocType function template involve 5 features, as shown in Figure 3 (c) is shown in the feature list in the upper half, which are Name ①, RegAltNameIndices ②, MCValue ③, Fixups ④ and ELF RELOC ⑤ respectively. Among them, the Name ① feature is related to the ISA type, and the RegAltNameIndices ② feature is related to the PC register. For the ARM architecture, the feature values corresponding to these two features are explicitly defined in the files ARM.td and ARMInstrInfo.td, as shown in Figure 3 (d) shows that these two features belong to the target architecture level features, and the statements of the ARM architecture all have this feature. The MCValue ③ feature is related to the variable type of the getRelocType function, and the feature value corresponding to this feature is defined in the file MCValue.h and referenced by ARMELFObjectWriter.cpp. Due to the limitation of the picture space, it is not shown in Figure 3(d) shows the MCValue.h file, which specifies the information associated with the function, and is a function-level feature. The statements in the getRelocType function have this feature. The Name 1, RegAltNameIndices 2, and MCValue 3 features are built based on the code templates. The Fixups 4 and ELF RELOC 5 features are built based on the information specific to the target architecture. The SV4 part after the two architecture cases describes the same feature on the fixup type, so the Fixups 4 feature is built. The SV5 part after the return describes the same feature on the relocation type, so the ELF RELOC 5 feature is built. For the ARM architecture, the feature values corresponding to these two features are explicitly defined in the ARMFixupKinds.h and ARM.def files, as shown in Figure 3 (d) shows the MCValue.h file, which specifies the information associated with the function, and is a function-level feature. The statements in the getRelocType function have this feature. The Name 1, RegAltNameIndices 2, and MCValue 3 features are built based on the code templates. The Fixups 4 and ELF RELOC 5 features are built based on the information specific to the target architecture. The SV4 part after the two architecture cases describes the same feature on the fixup type, so the Fixups 4 feature is built. The SV5 part after the return describes the same feature on the relocation type, so the ELF RELOC 5 feature is built. For the ARM architecture, the feature values corresponding to these two features are explicitly defined in the ARMFixupKinds.h and ARM.def files, as shown in Figure 3 (c) shows the lower part.
[0057] When the features are built, information associated with the features is recorded, and a target-dependent index table is created. The target-dependent index table bridges the code templates and the location of the feature values of the target architecture, and helps to automatically retrieve the feature value V corresponding to a statement T in the code template. According to an embodiment of the present application, the target-dependent index table can be divided into three parts, as shown in Figure 4 The first part is associated with the features, and includes the first column and the second column, which indicate the feature name and the category (level) of the feature, respectively. The second part is associated with the templates, and includes the third column. If the feature is a function-level feature, the third column indicates the functions to which the feature is associated, and only the statements in these functions will retrieve the feature value of the feature. If the feature is a statement-level feature, the third column indicates the statements to which the feature is associated, and only the statements will retrieve the feature value of the feature. The ellipsis in the template association index of the function-level feature represents the function names associated with the feature. The ellipsis in the template association index of the statement-level feature represents the statement names associated with the feature, and is expressed as "function name.statement", such as "getRelocType.S4". The third part is associated with the feature values, and includes the fourth column and the fifth column, which indicate the file index and the location index of the feature value, respectively. The fourth column of the target-dependent index table is the file index of the feature value, and the fifth column is the location index of the feature value in the file. The file index is the index of the file in which the feature value is located, and the location index is the location of the feature value in the file. <target>The target architecture name.
[0058] This invention uses a feature sequence FS to store the correspondence between a statement template T and its feature value V, which is used to represent a statement, i.e., FS = <statement template, feature value of statement> =<T,V> .For example, Figure 3 (a) Statement The characteristic sequence can be represented as FS4 =<T4,V4> =<"case#:\n return#;”,"ARM”,T,T,"movt_hi16”,"MOVT_PREL”>. For a specific target architecture, you only need to... <target>According to the target-related index table, the sentence feature value V of the sentence template T under the architecture can be automatically extracted, and a feature sequence FS under the architecture is generated. The feature sequence FS is a highly refined and complete description of the manually written code in the existing back-end design, which describes the compiler back-end code from the compiler level, the target architecture level, the function level, and the statement level. Finally, each statement in the program can be represented by the feature sequence, which is the design basis of the application. By abstracting the huge and complex compiler back-end code into a feature sequence FS, the standardized representation of the code and the uniformity of the code style are realized, and accordingly the pre-trained model can be trained.
[0059] According to an embodiment of the application, a pre-trained Transformer model is used to generate compiler back-end code. The pre-trained Transformer model (hereinafter referred to as the model) is an artificial intelligence model widely used in the field of natural language processing. It is based on the Transformer architecture, a revolutionary deep learning architecture proposed by Vaswani et al. in 2017. The Transformer architecture has achieved great success in processing sequential data, especially text data.
[0060] II. Model training phase
[0061] All extracted feature sequences FS are input into the model to complete the model training. The training output guides the specialization decision with predicates, which decides whether to keep a function or a statement. The value of the predicate is predicted to be 0 or 1. If the predicate value of the definition statement of a function (such as ) is 0, it is recommended not to keep the function; if the predicate value is 1, it is recommended to keep the function. If the predicate value of other statements is 0, it is recommended not to keep the statement; if the predicted predicate value is 1, it is recommended to keep the statement.
[0062] According to an embodiment of the application, the loss function TLoss of the model training consists of two parts, and the calculation formula is as follows:
[0063] TLoss = 0.5PLoss + 0.5SLoss
[0064] Where PLoss is the predicate loss, and SLoss is the statement loss.
[0065] The predicate loss PLoss is the mean square error loss of the predicted value of the predicate output by the model, and the calculation formula is:
[0066]
[0067] Where y is the true value of the predicate, which is 0 or 1. is the predicted value, a decimal number between 0 and 1, N = 1 (predicate is one-dimensional value).
[0068] The sentence loss is the cross-entropy loss of the tokens of the predicted sentence output by the model, and the sentence is processed as a group of tokens inside the model, so the calculation formula of the sentence loss is:
[0069]
[0070] wherein s is the token of the input sentence, is the token of the predicted sentence, both are n-dimensional vectors, and represents the dot product operation of the vectors.
[0071] According to one embodiment of the present application, the training of the model is ended after a specified number of rounds, preferably 50 rounds.
[0072] For the back end of each target architecture, according to the code template, the sentence corresponding to the sentence template in the code template and the feature sequence FS of the target architecture are taken as input. Since the sentence template of a certain architecture back end is a subset of the code template, if there is a corresponding sentence in the architecture back end, <template, feature value> is taken as input, and the expected output is <1, target sentence>; if there is no corresponding sentence in the architecture back end, <template, empty> is taken as input, and the expected output is the predicate value 0.
[0073] The training example is shown in the following table. Figure 5 Figure 5 The input and output examples when training the ARM architecture and the MIPS architecture are given. In the ARM architecture, there is a sentence S4 corresponding to T4 S , so the input of this sentence is <T4, V4> = <"case#:\n return#;”,"ARM”, T, T, "movt_hi16”,"MOVT_PREL”>, and the expected output of the model is <1, S4 S = <"1”,"caseARM::fixup_arm_movt_hi16:\n return ELF::R_ARM_MOVT_PREL;”>. If there is no template T4 sentence in a certain architecture back end, the input of this sentence is <T4, empty> = <"case#:\n return#;”,"”>, and the expected output is <"0”,"case#:\n return#;”>.
[0074] The feature sequence FS collected from the existing architecture back end is input into the model for training. Other specific details about the training are known in the art, and will not be described here. After the model is trained, it can be used to generate a compiler back end for a new architecture.
[0075] III. Target architecture specific code generation phase
[0076] When the training is completed, the pre-trained model has learned the mapping from the feature sequence FS representation of a sentence to the predicate and the target sentence. When a new architecture requests the compiler support, the compiler developer provides the target description file of the new architecture, and uses the target dependent index table to get the index of the target predicate and the target sentence from the table <target>Replace the name of the new architecture, extract the feature values V (statement feature values) corresponding to the features contained in each statement template T in the code template, and generate the feature sequence FS of the new architecture. Input the feature sequence FS of the new architecture into the trained pre-trained Transformer model, and the compiler backend of the new architecture can be obtained.
[0077] Figure 6 Take the getRelocType function of the RISC-V architecture as an example to illustrate the code generation process. Based on the target description file provided by the developer, the statement feature values V0-V4 corresponding to each statement T0-T4 in the getRelocType function template of the RISC-V architecture are retrieved using the target-related index table, and the feature sequence FS0-FS4 is generated. Input the generated feature sequence FS0-FS4 into the trained pre-trained Transformer model, and generate a getRelocType function for the RISC-V architecture. As shown in Figure 6 The predicate predicted by the function definition statement S0 is 1, which reserves the function for the RISC-V architecture compiler backend, and the predicate values of statements S1-S4 are 1, which reserves the four statements. Figure 6 (g) shows that the statement S4 of the RISC-V architecture compiler backend embeds the target architecture RISC-V specific values of SV4 and SV5. As can be seen, the new function code generated by the trained pre-trained Transformer model has a similar code structure to the existing manually designed backend code in LLVM-12.0 and implements the same function.
[0078] After generating a new compiler backend code for a new architecture, it needs to be compiled to test its correctness and reliability.
[0079] The present application is an efficient auxiliary tool for chip developers, which enables chip developers to quickly implement compiler support for new chips without deep understanding of the compiler, greatly reducing the labor and time cost of compiler backend development, and improving the research and development efficiency.
[0080] Although the present application has been described by preferred embodiments, the present application is not limited to the embodiments described herein, and includes various changes and variations made without departing from the scope of the present application.< / target> < / target> < / target>
Claims
1. A training method for a neural network model generated by a compiler backend, characterized in that, include: S1: For functions with different target architectures, match the abstract syntax trees corresponding to the same group of functions to obtain the statement templates corresponding to the statements in each function, as well as the location of information specific to the target architecture; S2: Analyze statement templates and target-specific information to form a target-related index table to store the mapping relationship between features and feature value definition locations; S3: Based on each statement template, search the target-related index table, extract the feature values of the statement template from the target description file of different target architectures to generate the feature sequence corresponding to the statement template under the different target architectures; S4: Train the neural network model using the feature sequence; Wherein, S1 includes: S1-1: Group functions from different target architectures by name and convert them into abstract syntax trees; S1-2: Match the abstract syntax trees corresponding to the functions in the same group to obtain the statement templates corresponding to the statements in each function, as well as the location of information specific to the target architecture; S2 includes: S2-1: Find common construction features of statement templates and target architecture-specific information from the architecture, function, and statement levels respectively; S2-2: Record the feature name, its level, statement template association information, the file name where the corresponding feature value is located, and the position of the corresponding feature value in the file to form a target-related index table; S3 includes: S3-1: For each statement template, based on the target architecture name, function name, and statement name, search the target-related index table for information associated with the statement template to determine the features contained in the statement template; S3-2: Based on the features contained in the statement template, extract feature values according to the file name and file location in the corresponding target-related index table; S3-3: Combine the statement template and the feature values of the statement template to form a feature sequence of the statement template under the target architecture; S4 includes: S4-1: Input the feature sequence and the corresponding statement into the neural network model in sequence; S4-2: Repeat S4-1 a predetermined number of times.
2. The training method for the neural network model according to claim 1, characterized in that, The tree difference algorithm is used to match the abstract syntax trees corresponding to the same group of functions.
3. The training method for the neural network model according to claim 1, characterized in that, When a statement template does not have a corresponding statement in the backend of a target architecture, the feature value of the statement template under the target architecture is empty.
4. The training method for the neural network model according to claim 1, characterized in that, The feature sequence stores the correspondence between statement templates and their feature values under different target architectures.
5. The training method for the neural network model according to claim 1, characterized in that, The neural network model is a pre-trained Transformer model.
6. A compiler backend generation method based on a neural network model generated by any one of the methods described in claims 1-5, used to generate a compiler backend according to a target description file of the architecture to be generated, comprising: S1: Replace the corresponding name in the target-related index table with the name of the architecture to be generated compiler backend; S2: Using the target-related index table, extract the feature values of each statement template in the code template to generate the feature sequence of the architecture of the compiler backend to be generated; S3: Input the feature sequence into the trained neural network model to generate the compiler backend.