Word line control circuit, memory and memory control method

Abstract

The present disclosure provides a word line control circuit, a memory and a memory control method. The word line control circuit comprises: a word line driving circuit coupled with a word line, configured to receive an operation instruction of the memory to turn on and off the corresponding word line; a voltage generating circuit for generating at least one reference voltage; a voltage regulating circuit coupled with the word line driving circuit and the voltage generating circuit, configured to generate a target voltage output to the word line driving circuit after adjusting the at least one reference voltage. In the present disclosure, since the voltage regulating circuit can compensate the coupling effect of the word line, prevent the closed word line from being mistakenly turned on due to the coupling effect, thereby improving the reliability of the memory operation. At the same time, since the voltage regulating circuit can adjust the voltage output to the word line driving circuit, the leakage current of the transistor in the word line driving circuit is reduced, thereby improving the performance of the memory operation.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a word line control circuit, a memory, and a memory control method. Background Technology

[0002] Currently, with the development of memory manufacturing processes, the distance between word lines in memory is getting closer and closer to improve memory performance. However, when the distance between word lines decreases to a certain extent, the enabled word lines will have a coupling effect on adjacent disabled word lines, leading to a decrease in the reliability of memory operation. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a word line control circuit, a memory, and a memory control method.

[0005] According to a first aspect of the present disclosure, a word line control circuit is provided, the word line control circuit comprising:

[0006] A word line driving circuit, coupled to a word line, is configured to receive operation instructions from the memory to turn the corresponding word line on and off.

[0007] A voltage generation circuit, the voltage generation circuit being used to generate at least one reference voltage;

[0008] A voltage regulating circuit, which is coupled to both the word line driving circuit and the voltage generation circuit, is configured to regulate at least one of the reference voltages and generate a target voltage to be output to the word line driving circuit.

[0009] According to some embodiments of this disclosure, the reference voltage includes a first reference voltage, a second reference voltage, and / or a third reference voltage; the first reference voltage is a power supply voltage, the second reference voltage is a ground voltage, and the third reference voltage is located between the first reference voltage and the second reference voltage.

[0010] According to some embodiments of this disclosure, the voltage regulating circuit includes:

[0011] An adjustment code generation module receives an address signal and an enable signal, and is configured to generate an adjustment code corresponding to the address signal.

[0012] An adjustable voltage generation module is coupled to the adjustment code generation module, the word line driving circuit, and the voltage generation module, and is configured to adjust the reference voltage according to the adjustment code to generate the target voltage;

[0013] The enable signal is the enable signal for the repository.

[0014] According to some embodiments of this disclosure, the word line control circuit further includes:

[0015] A decoding circuit, coupled to the word line driving circuit, is configured to receive command signals from the memory, decode the command signals to generate address signals and operation instructions, and output them to the word line driving circuit.

[0016] A second aspect of this disclosure provides a memory that includes word line control circuitry as described above.

[0017] A third aspect of this disclosure provides a memory control method, the memory control method comprising:

[0018] In response to an operation command on the memory, the voltage of a portion of the word lines in the memory is adjusted to a target voltage;

[0019] Turn the corresponding word lines in the memory on and off;

[0020] The target voltage is less than the reference voltage.

[0021] According to some embodiments of this disclosure, the word line that is turned on is a first word line, and the word line that is turned off is a second word line; adjusting the voltage of the corresponding word line in the memory to the target voltage includes:

[0022] Determine the target voltage;

[0023] Adjust the voltage of the second word line to the target voltage;

[0024] Wherein, the second word line is at least one word line adjacent to the first word line; or, the second word line is at least one word line in the repository where the first word line is located.

[0025] According to some embodiments of this disclosure, determining the target voltage includes:

[0026] Determine the address information of the first word line and the second word line;

[0027] Based on the address information, determine the voltage adjustment amount;

[0028] The target voltage is determined based on the reference voltage and the voltage adjustment amount.

[0029] According to some embodiments of this disclosure, determining the voltage regulation amount based on the address information includes:

[0030] Determine the address comparison result between the address information of the first word line and the address information of the second word line;

[0031] The voltage adjustment amount is determined based on the address comparison result;

[0032] The greater the difference between the address information of the first word line and the address information of the second word line, the smaller the voltage adjustment amount.

[0033] According to some embodiments of this disclosure, determining the voltage adjustment amount based on the address comparison result includes:

[0034] The product of the address comparison result and the word line spacing information is determined as the spacing comparison result;

[0035] The voltage adjustment amount is determined based on the spacing comparison results;

[0036] The larger the distance comparison result, the smaller the voltage adjustment amount.

[0037] In the word line control circuit, memory, and memory control method provided in this disclosure, the word line control circuit includes a word line driving circuit, a voltage generation circuit, and a voltage regulation circuit. The voltage regulation circuit is coupled to both the word line driving circuit and the voltage generation circuit. The voltage regulation circuit can adjust the reference voltage generated by the voltage generation circuit to generate a target voltage and output it to the word line driving circuit, thereby compensating for the coupling effect generated by the word lines coupled to the word line driving circuit. Because the voltage regulation circuit can compensate for the coupling effect of the word lines, it prevents closed word lines from being accidentally turned on due to the coupling effect, thus improving the reliability of memory operation. At the same time, because the voltage regulation circuit can adjust the voltage output to the word line driving circuit, it reduces the leakage current of the transistors in the word line driving circuit, thereby improving the performance of memory operation.

[0038] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0039] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0040] Figure 1 This is a schematic diagram of a word line control circuit according to an exemplary embodiment;

[0041] Figure 2This is a schematic diagram of a sub-word line driving circuit according to an exemplary embodiment;

[0042] Figure 3 This is a schematic diagram of a word line driving circuit according to an exemplary embodiment;

[0043] Figure 4 This is a schematic diagram of a voltage regulation circuit according to an exemplary embodiment;

[0044] Figure 5a This is a schematic diagram of the structure of a voltage generation module according to an exemplary embodiment;

[0045] Figure 5b This is a schematic diagram of the structure of a voltage generation module according to another exemplary embodiment;

[0046] Figure 6 This is a schematic diagram of the structure of a word line control circuit according to another exemplary embodiment;

[0047] Figure 7 This is a flowchart illustrating a memory control method according to an exemplary embodiment;

[0048] Figure 8 This is a flowchart illustrating a memory control method according to another exemplary embodiment;

[0049] Figure 9 This is a flowchart illustrating a memory control method according to another exemplary embodiment;

[0050] Figure 10 This is a flowchart illustrating a memory control method according to another exemplary embodiment;

[0051] Figure 11 This is a flowchart illustrating a memory control method according to another exemplary embodiment;

[0052] Figure 12 This is a flowchart illustrating a memory control method according to another exemplary embodiment;

[0053] Figure 13 This is a flowchart illustrating a memory control method according to another exemplary embodiment;

[0054] Figure 14 This is a flowchart illustrating a memory control method according to another exemplary embodiment;

[0055] Figure 15 This is a block diagram illustrating a memory control device according to an exemplary embodiment;

[0056] Figure 16 This is a block diagram illustrating a memory control device according to an exemplary embodiment.

[0057] In the diagram: 10, word line driving circuit; 11, sub-word line driving circuit; 12, memory array; 20, voltage generation circuit; 30, voltage regulation circuit; 40, decoding circuit; 100, adjustment module; 200, switch module; 300, computer equipment; 301, processor; 302, memory; 310, adjustment code generation module; 320, adjustment voltage generation module; Q1, first transistor; Q2, second transistor; Q3, third transistor; Q4, fourth transistor; R, adjustment resistor; WL, word line; FXT, first driving voltage signal; VWLN, second driving voltage signal; FXB, third driving voltage signal; MWL, control signal; En, enable signal; Add, address signal; CMD, operation instruction. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0059] Currently, with the advancement of memory manufacturing processes, the distance between word lines in memory is becoming increasingly shorter to improve memory performance. A memory array within a storage repository contains word line driver circuitry and multiple word lines, with the word line driver circuitry coupled to each word line. In response to memory operation commands, the word line driver circuitry controls one word line to turn on and the remaining word lines to turn off. Because the distance between the turned-on and turned-off word lines is close, the turned-on word line can couple to the turned-off word line, causing a drop in the threshold voltage of the transistor in the memory cell coupled to the turned-off word line, resulting in the word line being falsely turned on. Falsely turned-on word lines may overwrite the data in the coupled memory cells, leading to a decrease in the reliability of memory operation.

[0060] Based on this, this disclosure provides a word line control circuit. After adjusting the reference voltage generated by the voltage generation circuit through a voltage regulating circuit, a target voltage is generated and output to the word line drive circuit to change the word line voltage. By adjusting the word line voltage, the voltage of the word line changes in accordance with the threshold voltage of the transistor in the memory cell, thereby compensating for the coupling effect generated by the word line. Because the voltage regulating circuit can compensate for the coupling effect of the word line, it prevents a closed word line from being mistakenly turned on due to the coupling effect, thus improving the reliability of the memory operation.

[0061] This disclosure provides a word line control circuit in exemplary embodiments, such as... Figure 1 As shown, Figure 1 A schematic diagram of a word line control circuit according to an exemplary embodiment of the present disclosure is shown. The word line control circuit includes a word line driving circuit 10, a voltage generation circuit 20, and a voltage regulating circuit 30. The word line driving circuit 10 is coupled to a word line WL and is configured to receive operation instructions from the memory to turn the corresponding word line WL on and off. The voltage generation circuit 20 is used to generate at least one reference voltage. The voltage regulating circuit 30 is coupled to both the word line driving circuit 10 and the voltage generation circuit 20 and is configured to regulate the at least one reference voltage and generate a target voltage output to the word line driving circuit 10.

[0062] In this embodiment, the word line control circuit includes a word line driving circuit, a voltage generation circuit, and a voltage regulation circuit. The voltage regulation circuit is coupled to both the word line driving circuit and the voltage generation circuit. The voltage regulation circuit adjusts the reference voltage generated by the voltage generation circuit to generate a target voltage, which is then output to the word line driving circuit, compensating for the coupling effect of the word lines coupled to the word line driving circuit. Because the voltage regulation circuit can compensate for the coupling effect of the word lines, it prevents closed word lines from being accidentally turned on due to coupling, thereby improving the reliability of the memory operation. Simultaneously, because the voltage regulation circuit can adjust the voltage output to the word line driving circuit, it reduces the leakage current of the transistors in the word line driving circuit, thereby improving the performance of the memory operation.

[0063] In some exemplary embodiments provided in this disclosure, the reference voltage may include a first reference voltage. The first reference voltage is the power supply voltage VPP. The reference voltage may also include a second reference voltage. The second reference voltage is the ground voltage VSS. The reference voltage may also include a third reference voltage. The third reference voltage, VKK, is located between the first and second reference voltages.

[0064] In this embodiment, under different coupling methods of the word line driving circuit, the first reference voltage, the second reference voltage, and the third reference voltage will affect the coupling effect of the word line and the leakage current of the transistors in the word line driving circuit. By adjusting the first reference voltage, the second reference voltage, and / or the third reference voltage as reference voltages, the coupling effect of the word line can be compensated and the leakage current of the transistors in the word line driving circuit can be reduced, thereby improving the reliability of the memory operation.

[0065] For example, such as Figure 2 and Figure 3 As shown, Figure 2 A schematic diagram of a sub-word line driving circuit according to an exemplary embodiment of the present disclosure is shown. The word line driving circuit 10 includes a plurality of sub-word line driving circuits 11, each sub-word line driving circuit 11 being coupled to a word line WL. Each sub-word line driving circuit 11 includes a first transistor Q1, a second transistor Q2, and a third transistor Q3. A first terminal of the first transistor Q1 is coupled to a first driving voltage signal FXT, and a second terminal is coupled to a first terminal of the second transistor Q2. A second terminal of the second transistor Q2 is coupled to a second driving voltage signal VWLN. The gates of both the first transistor Q1 and the second transistor Q2 are coupled to a control signal MWL. The word line WL is coupled between the second terminal of the first transistor Q1 and the first terminal of the second transistor Q2. A first terminal of the third transistor Q3 is coupled to the word line WL, a second terminal is coupled to the second driving voltage signal VWLN, and its gate is coupled to a third driving voltage signal FXB. The first driving voltage signal FXT and the third driving voltage signal FXB are complementary signals. The first driving voltage signal FXT and the third driving voltage signal FXB, at different levels, represent the power supply voltage VPP and the ground voltage VSS, respectively, or the first target voltage VPP_t adjusted by the first reference voltage and the second target voltage VSS_t adjusted by the second reference voltage. The second driving voltage signal VWLN represents the third target voltage VKK_t adjusted by the third reference voltage.

[0066] For example, the first transistor Q1 is a P-type transistor, and the second transistor Q2 and the third transistor Q3 are N-type transistors. When the sub-word line driving circuit 11 needs to shut down the corresponding word line WL, the first driving voltage signal FXT is ground voltage VSS or the second target voltage VSS_t, the third driving voltage signal FXB is power supply voltage VPP or the first target voltage VPP_t, and the control signal MWL is ground voltage VSS or the second target voltage VSS_t; or, the first driving voltage signal FXT is ground voltage VSS or the second target voltage VSS_t, the third driving voltage signal FXB is power supply voltage VPP or the first target voltage VPP_t, and the control signal MWL is power supply voltage VPP or the first target voltage VPP_t. The first transistor Q1 and the second transistor Q2 can shut down the corresponding word line WL under different control signals MWL. However, under different control signals MWL, the gate voltage of the first transistor Q1 is different, and the leakage current in the first transistor Q1 is different.

[0067] For example, since an active word line WL will couple to a closed word line WL, the threshold voltage of the transistor in the memory cell coupled to the closed word line WL will decrease, leading to the false activation of the closed word line WL. When the word line WL is closed, the word line driving circuit 10 outputs a second driving voltage signal VWLN to the coupled word line WL by turning on the second transistor Q2 and / or the third transistor Q3 in the sub-word line driving circuit 11. To compensate for the coupling effect of the word line WL, the voltage regulating circuit 30 adjusts at least one reference voltage as a third reference voltage, and lowers the third reference voltage. That is, the third target voltage VKK_t after the third reference voltage is lowered is used as the second driving voltage signal VWLN and output to the second terminal of the second transistor Q2 and the second terminal of the third transistor Q3 in the word line driving circuit 10. Since the word line WL is closed with the lowered third reference voltage, the threshold voltage of the transistor in the memory cell can be compensated, thereby avoiding the false activation of the word line WL.

[0068] For example, such as Figure 3 As shown, Figure 3 A schematic diagram of a word line driving circuit according to an exemplary embodiment of the present disclosure is shown. The sub-word line driving circuits 11 in the word line driving circuit 10 can be arranged in an interpolated structure to improve the driving capability of the word lines WL in an odd-even differential driving manner. Each word line WL is coupled to the memory array 12.

[0069] For example, the number of voltage regulating circuits 30 is the same as the number of reference voltages. Since each sub-word line drive circuit 11 in a memory repository uses the same reference voltage, the target voltage of each sub-word line drive circuit 11 is the same during the adjustment of the reference voltage by the voltage regulating circuits 30. By setting the number of voltage regulating circuits 30 to be the same as the number of reference voltages, the cost and structural complexity of the word line control circuitry are reduced while still being able to adjust the reference voltage to improve the reliability of memory operation.

[0070] For example, the number of voltage regulating circuits 30 is the same as or an integer multiple of the number of word lines WL. Since each word line WL corresponds to at least one voltage regulating circuit 30, the target voltage of each sub-word line drive circuit 11 can be different during the adjustment of the reference voltage by the regulating circuit 30. By setting the number of voltage regulating circuits 30 to be the same as or an integer multiple of the number of word lines WL, the target voltage of different sub-word line drive circuits 11 can be adjusted as needed, thereby improving the coupling effect compensation and effectively reducing the leakage current of transistors in the word line drive circuit.

[0071] It is understandable that the number of voltage regulating circuits 30 can be set as needed, in addition to being the same as the number of reference voltages, the same as the number of word lines WL, or an integer multiple of the number of word lines WL.

[0072] In some exemplary embodiments provided in this disclosure, such as Figure 4 As shown, Figure 4 A schematic diagram of a voltage regulation circuit according to an exemplary embodiment of the present disclosure is shown. The voltage regulation circuit 30 includes an adjustment code generation module 310 and an adjustment voltage generation module 320. The adjustment code generation module 310 receives an address signal Add and an enable signal En, and is configured to generate an adjustment code corresponding to the address signal Add. The adjustment voltage generation module 320 is coupled to the adjustment code generation module 310, the word line driving circuit 10, and the voltage generation circuit 20, and is configured to adjust the reference voltage according to the adjustment code to generate a target voltage. The enable signal En is the enable signal En of the storage repository.

[0073] In this embodiment, the adjustment code generation module receives the address signal and generates an adjustment code corresponding to the address signal, ensuring that the target voltage generated by the adjustment voltage generation module corresponds to the address signal. Since the target voltage corresponds to the address signal, different target voltages can be generated for different sub-word line driving circuits, thereby improving the coupling effect compensation and effectively reducing the leakage current of transistors in the word line driving circuit. Simultaneously, because the enable signal can enable and disable the adjustment code generation module and its corresponding repository, signal multiplexing is achieved, thus reducing the complexity of the word line control circuit structure.

[0074] For example, the adjustment code generation module 310 can be a decoder, such as a 2-to-4 decoder or a 3-to-8 decoder. The enable terminal of the adjustment code generation module 310 is coupled to the enable signal En, the input terminal is coupled to the address signal Add, and the output terminal is coupled to the adjustment voltage generation module 320. When the enable signal En is 0, all output terminals of the adjustment code generation module 310 are 0, and the adjustment voltage generation module 320 does not adjust the reference voltage. At this time, since the repository is disabled, the word line will not generate a coupling effect, and the reference voltage is directly output to the word line drive circuit 10. When the enable signal En is 1, only one output terminal of the adjustment code generation module 310 is 1, and the adjustment voltage generation module 320 adjusts the reference voltage.

[0075] For example, such as Figure 5a and Figure 5b As shown, Figure 5a and Figure 5b A schematic diagram of a regulating voltage generation module according to an exemplary embodiment of this disclosure is shown. The regulating voltage generation module 320 includes multiple fourth transistors Q4 and multiple regulating resistors R. The multiple fourth transistors Q4 and multiple regulating resistors R constitute multiple parallel branches, including fixed branches and regulating branches. The fixed branches contain only regulating resistors R. The regulating branches can be multiple fourth transistors Q4 connected in parallel and then in series with the regulating resistors R, or fourth transistors Q4 connected in series with the regulating resistors R and then in parallel. The input terminal of each parallel branch is coupled to a reference voltage (i.e., voltage generation circuit 20), and the output terminal is coupled to a word line driving circuit 10. The gate of each fourth transistor Q4 is coupled to one output terminal of the regulating code generation module 310. That is, the number of fourth transistors Q4 is the same as the number of output terminals of the regulating code generation module 310. When the address signal Add is different, different fourth transistors Q4 are turned on. The resistance values ​​of the regulating resistors R can be the same or different.

[0076] It is understandable that, in addition to the structure described above, the voltage generation module 320 can also connect multiple regulating resistors R in series between the first reference voltage and the second reference voltage, and use the fourth transistor Q4 to select different voltage division points for output as the target voltage.

[0077] In some exemplary embodiments provided in this disclosure, such as Figure 6 As shown, the word line control circuit also includes a decoding circuit 40. The decoding circuit 40 is coupled to the word line drive circuit 10 and is configured to receive command signals from the memory, decode the command signals to generate an address signal Add and an operation instruction CMD, and output them to the word line drive circuit 10.

[0078] In this embodiment, the memory's command signals are decoded by a decoding circuit to generate address signals and operation instructions. These address signals and operation instructions enable or disable the corresponding word lines, allowing the memory to write or read data. Since the address signals can also be used by a voltage regulation circuit to adjust the reference voltage, the coupling effect of the word lines is compensated through signal multiplexing, thereby reducing the complexity of the word line control circuit structure.

[0079] For example, such as Figure 2 and Figure 6 As shown, the first driving voltage signal FXT, the third driving voltage signal FXB, and the control signal MWL in each sub-word line driving circuit 11 are generated by the word line control circuit based on the address signal Add.

[0080] For example, when the address signal Add generated by the decoding circuit 40 after decoding the command signal generates a first driving voltage signal FXT, a third driving voltage signal FXB, and a control signal MWL to control each sub-word line driving circuit 11, if the sub-word line driving circuit 11 needs to shut down the corresponding word line WL, the first driving voltage signal FXT is ground voltage VSS or the second target voltage VSS_t, the third driving voltage signal FXB is power supply voltage VPP or the first target voltage VPP_t, and the control signal MWL is ground voltage VSS or the second target voltage VSS_t. At this time, since the gate of the first transistor Q1 is ground voltage VSS or the second target voltage VSS_t, and the source of the first transistor Q1 is ground voltage VSS or the second target voltage VSS_t, the first transistor Q1 is not turned on and the leakage current is low. That is, using the address signal Add generated by the decoding circuit 40 to control the word line driving circuit 10 can reduce the leakage current of the transistors in the word line driving circuit 10, and the leakage current is not affected by the adjustment of the third reference voltage.

[0081] For example, for a word line control circuit without decoding, if the sub-word line driving circuit 11 needs to shut down the corresponding word line WL, the first driving voltage signal FXT is ground voltage VSS or the second target voltage VSS_t, the third driving voltage signal FXB is power supply voltage VPP or the first target voltage VPP_t, and the control signal MWL is power supply voltage VPP or the first target voltage VPP_t. At this time, since the gate of the first transistor Q1 is power supply voltage VPP or the first target voltage VPP_t, in order to compensate for the coupling effect of word line WL, the third reference voltage is reduced to the third target voltage VKK_t and output to the corresponding word line WL in the word line driving circuit 10. In the sub-word line driving circuit 11 coupled to the closed word line WL, the voltage at the first terminal of the first transistor Q1 is ground voltage VSS or the second target voltage VSS_t, the voltage at the second terminal is the third target voltage VKK_t, and the voltage at the control terminal is the power supply voltage VPP or the first target voltage VPP_t. This results in a larger voltage difference between the gate and the second terminal (drain) of the first transistor Q1, leading to a higher leakage current in the first transistor Q1. In other words, not decoding to generate the address signal Add to control the word line driving circuit 10 will result in a higher leakage current in the transistors within the word line driving circuit 10. Therefore, for a word line control circuit that does not perform decoding, the first target voltage VPP_t, adjusted by lowering the power supply voltage VPP, can be used as the control signal MWL. As the voltage of the control signal MWL decreases, the voltage difference between the gate and the second terminal (drain) of the first transistor Q1 decreases, reducing the leakage current of the first transistor Q1, and / or, the third reference voltage can be increased as much as possible while compensating for the coupling effect of the word line. Alternatively, to avoid increasing the leakage current of the transistors in the word line drive circuit 10, the third reference voltage may not be adjusted.

[0082] For example, for word line control circuits with / without decoding circuit 40, if the sub-word line driving circuit 11 needs to turn on the corresponding word line WL, the first driving voltage signal FXT is the power supply voltage VPP or the first target voltage VPP_t, the third driving voltage signal FXB is the ground voltage VSS or the second target voltage VSS_t, and the control signal MWL is the ground voltage VSS or the second target voltage VSS_t. In this case, since only one word line WL is turned on in the word line control circuit, and the closed word line WL will not have a coupling effect on the turned-on word line WL, there is no problem of word line WL being mistakenly turned on or off. Therefore, the third reference voltage of the sub-word line driving circuit 11 corresponding to the turned-on word line WL does not need to be adjusted. Simultaneously, the gate-drain voltage difference of the first transistor Q1 in the sub-word line driving circuit 11 corresponding to the turned-on word line WL is negative, and the first transistor Q1 does not have leakage current. Therefore, the first reference voltage of the sub-word line driving circuit 11 corresponding to the turned-on word line WL does not need to be adjusted.

[0083] This disclosure also provides a memory that includes word line control circuitry as described in any of the above embodiments.

[0084] This disclosure provides an exemplary embodiment of a memory control method, which can be executed by the word line control circuit described above. For example... Figure 7 As shown, Figure 7 A flowchart of a memory control method provided according to an exemplary embodiment of the present disclosure is shown, including:

[0085] S200: In response to an operation instruction on the memory, adjust the voltage of some word lines in the memory to the target voltage.

[0086] S300, turn on and off the corresponding word lines in the memory.

[0087] The target voltage is less than the reference voltage.

[0088] In this embodiment, in response to an operation command on the memory, the voltage of the corresponding word line in the memory is reduced to a target voltage to compensate for the coupling effect between the enabled and disabled word lines. After the voltage of the corresponding word line is reduced, the corresponding word line in the memory is enabled and disabled, causing the memory to operate in response to the operation command. Since reducing the voltage of the corresponding word line can compensate for the coupling effect of the word line, it prevents the disabled word line from being accidentally enabled due to the coupling effect, thereby improving the reliability of the memory operation. At the same time, reducing the voltage of the corresponding word line can reduce the leakage current of the transistors in the word line drive circuit, thereby improving the performance of the memory operation.

[0089] For example, adjusting the voltage of the corresponding word line in the memory to the target voltage in step S200 can be done by reducing the first reference voltage to the first target voltage VPP_t, reducing the second reference voltage to the second target voltage VSS_t, or reducing the third reference voltage to the third target voltage VKK_t.

[0090] In some exemplary embodiments provided in this disclosure, the open word line is the first word line, and the closed word line is the second word line. For example... Figure 8 As shown, Figure 8 An example flowchart illustrates a method for adjusting the voltage of the corresponding word line in the memory to a target voltage in step S200, including:

[0091] S210. Determine the target voltage.

[0092] S220, Adjust the voltage of the second word line to the target voltage.

[0093] The second word line can be at least one word line adjacent to the first word line, or it can be at least one word line in the repository where the first word line is located.

[0094] In this embodiment, the coupling effect between the first word line and the second word line may cause the second word line to be erroneously turned on, affecting the reliability of memory operation. For the second word line, the closer it is to the first word line, the greater the impact of the coupling effect. The second word line whose voltage needs adjustment is identified as at least one word line adjacent to the first word line. The voltage of the second word line with the greatest coupling effect is adjusted to reduce the complexity of voltage adjustment. Besides adjacent second word lines, non-adjacent second word lines may also be affected by the coupling effect of the first word line. Therefore, the voltage of second word lines located in the same storage area as the first word line can also be adjusted to increase the range of coupling effect compensation. Before adjusting the voltage of the second word line, the target voltage of the second word line is determined, and then the voltage of the second word line is adjusted to the target voltage. By identifying the second word line whose voltage needs adjustment and adjusting its voltage to the target voltage to compensate for the coupling effect, the reliability of memory operation is improved.

[0095] For example, the target voltage determined in step S210 can be determined based on the number of voltage regulating circuits. When there is only one voltage regulating circuit in a storage unit corresponding to a reference voltage, the target voltage can be determined as the voltage that can compensate for the maximum coupling effect, that is, the voltage that can compensate for the coupling effect of the second word line adjacent to the first word line. When there are multiple voltage regulating circuits in a storage unit corresponding to a reference voltage, the corresponding target voltage can be determined for different second word lines.

[0096] For example, adjusting the voltage of the second word line to the target voltage in step S220 means adjusting the voltage at which the second word line is turned off to the target voltage. That is, adjusting the voltage at the second terminal of the second transistor and the second terminal of the third transistor in the sub-word line driving circuit corresponding to the second word line to the target voltage.

[0097] In some exemplary embodiments provided in this disclosure, such as Figure 9 As shown, Figure 9 An example flowchart of the method for determining the target voltage in step S210 is shown, including:

[0098] S211. Determine the address information of the first word line and the second word line.

[0099] S212. Determine the voltage regulation amount based on the address information.

[0100] S213. Determine the target voltage based on the reference voltage and voltage adjustment amount.

[0101] In this embodiment, since the distance between the first word line and the second word line affects the strength of the coupling effect, the address information of the first and second word lines is determined to determine the distance between the second word line and the first word line. Based on the address information of the first and second word lines, a voltage adjustment amount is determined to determine the magnitude of voltage compensation. Based on the voltage adjustment amount, the reference voltage is adjusted to determine the target voltage. By adjusting the reference voltage according to the voltage adjustment amount determined by the address information, the influence of the coupling effect on the second word line can be compensated, thereby improving the reliability of memory operation. Simultaneously, since the voltage adjustment amount is determined based on the address information, the leakage current of the transistors in the word line driving circuit is reduced due to the influence of the target voltage, thereby improving the performance of memory operation.

[0102] For example, determining the address information of the first word line and the second word line in step S211 can be determined according to the memory operation instructions.

[0103] For example, in step S213, the target voltage is determined based on the reference voltage and the voltage adjustment amount. When the voltage adjustment amount is negative, the sum of the reference voltage and the voltage adjustment amount is determined as the target voltage. When the voltage adjustment amount is positive, the difference between the reference voltage and the voltage adjustment amount is determined as the target voltage.

[0104] In some exemplary embodiments provided in this disclosure, such as Figure 10 As shown, Figure 10 An example flowchart illustrates the method for determining the voltage regulation amount based on address information in step S212, including:

[0105] S2121. Determine the address information of the first word line and the address comparison result of the address information of the second word line.

[0106] S2122. Determine the voltage adjustment amount based on the address comparison results.

[0107] The greater the difference between the address information of the first word line and the address information of the second word line, the smaller the voltage regulation amount.

[0108] In this embodiment, during the determination of the voltage adjustment amount, the address information of the first word line and the second word line is compared to obtain the address comparison result. Based on the address comparison result, the voltage adjustment amount is determined to adjust the voltage of the second word line, which is separated from the first word line by different distances. Since the greater the distance between the first and second word lines, the weaker the coupling effect, and the greater the difference between the address information of the first and second word lines, the smaller the determined voltage adjustment amount is to adapt to the strength of the coupling effect. Because the address comparison result can reflect the distance between the first and second word lines, the voltage adjustment amount determined based on the address comparison result can effectively compensate for coupling effects of different strengths, thereby improving the reliability of memory operation.

[0109] For example, the address comparison result of determining the address information of the first word line and the address information of the second word line in step S2121 can be an address comparison result of obtaining the difference by subtracting the address information of the first word line from the address information of the second word line, an address comparison result of obtaining the ratio by comparing the address information of the first word line from the address information of the second word line, or an address comparison result of obtaining the difference ratio by subtracting the address information of the first word line from the address information of the second word line.

[0110] For example, the magnitude of the voltage regulation refers to the magnitude of the absolute value of the voltage regulation.

[0111] In some exemplary embodiments provided in this disclosure, such as Figure 11 As shown, Figure 11 An example flowchart illustrates the method for determining the voltage regulation amount based on the address comparison result in step S2122, including:

[0112] S21221. The product of the address comparison result and the word line spacing information is the spacing comparison result.

[0113] S21222. Determine the voltage adjustment amount based on the spacing comparison results.

[0114] The larger the distance comparison result, the smaller the voltage adjustment amount.

[0115] In this embodiment, since the address comparison result can only indirectly reflect the distance between the first word line and the second word line, the product of the address comparison result and the word line spacing information is determined as the spacing comparison result, so as to directly reflect the distance between the first word line and the second word line. Based on the spacing comparison result, a voltage adjustment amount is determined to adjust the voltage of the second word line at different distances from the first word line. Since the greater the distance between the first and second word lines, the weaker the coupling effect, the larger the absolute distance between the first and second word lines, the smaller the determined voltage adjustment amount is to adapt to the strength of the coupling effect. Because the spacing comparison result can directly reflect the distance between the first and second word lines, the voltage adjustment amount determined based on the spacing comparison result can effectively compensate for coupling effects of different strengths, thereby improving the reliability of memory operation.

[0116] For example, in step S21222, determining the voltage adjustment amount based on the spacing comparison result can be achieved by multiplying the reciprocal of the spacing comparison result by a preset voltage. The preset voltage can be selected based on the method used to determine the address comparison result. For example, if the address comparison result is determined by subtraction without considering the unit of word line spacing information, the preset voltage could be, for example, 0.5V, 1V, 2V, 3V, etc.

[0117] For example, the word line spacing information includes the size of the spacing between adjacent word lines.

[0118] In some exemplary embodiments provided in this disclosure, such as Figure 12 As shown, the memory control method further includes the following steps:

[0119] S100. Perform a coupling test on each word line in the memory and obtain the test results.

[0120] S110. Determine the target voltage based on the test results.

[0121] In this embodiment, since the adjusted target voltage is used to compensate for the coupling effect between word lines, a coupling test is performed on each word line in the memory to obtain the test results and determine whether a coupling effect exists between word lines and the strength of the coupling effect. Based on the test results, the target voltage is determined to compensate for the coupling effect. Since the target voltage is determined based on the test results of the word line coupling test, the target voltage can compensate for the coupling effect of word lines and reduce the leakage current of transistors in the word line drive circuit, thereby improving the reliability of memory operation.

[0122] For example, the coupling test performed on each word line in the memory in step S100 to obtain the test result can be performed by sequentially enabling the first word line according to the address information of the word line in the word line driving circuit, and then performing a coupling test on each second word line while the first word line is enabled. The coupling test process can involve writing test data into the memory area corresponding to the first word line, reading target data from the memory area corresponding to each second word line, and comparing the target data with the test data to determine whether the second word line has been mistakenly enabled and to what extent. For example, when the target data and the test data are the same, it is determined that the second word line corresponding to the memory area containing the target data is affected by the coupling effect of the first word line. If the target data and the test data are the same multiple times in multiple tests, the second word line is more affected by the coupling effect. If the target data and the test data are the same fewer times in multiple tests, the second word line is less affected by the coupling effect.

[0123] In some exemplary embodiments provided in this disclosure, step S110, determining the target voltage based on the test results, includes:

[0124] When the test results indicate that there is coupling between word lines, the target voltage is reduced by the first adjustment amount.

[0125] When the test result shows that there is no coupling between word lines, obtain the previous voltage regulation method for the target voltage.

[0126] Adjust the target voltage according to the previous voltage adjustment method.

[0127] In this embodiment, when the coupling test result indicates that coupling exists between word lines, the target voltage needs to be reduced to minimize the impact of the coupling effect, and the target voltage is reduced by a first adjustment amount. When the coupling test result indicates that there is no coupling between word lines, the leakage current of the transistors in the word line drive circuit needs to be reduced, and the previous voltage adjustment method of the target voltage is obtained. Based on the previous voltage adjustment method, the direction of change of the target voltage during the adjustment process is determined, and the target voltage is adjusted accordingly. By reducing the target voltage by a first adjustment amount when coupling exists between word lines to compensate for the coupling effect of the word lines, the reliability of memory operation is improved. Simultaneously, by adjusting the target voltage according to the previous voltage adjustment method when there is no coupling between word lines to reduce the leakage current of the transistors in the word line drive circuit, the performance of memory operation is improved.

[0128] For example, the range of the first adjustment amount is (0, 0.5]V. The first adjustment amount can be 0.05V, 0.1V, 0.15V, etc.

[0129] In some exemplary embodiments provided in this disclosure, the step of determining the target voltage based on the test results in the above steps includes:

[0130] The current voltage regulation method is to reduce the first regulation amount while keeping the target voltage unchanged.

[0131] When the current voltage regulation method is to increase the second regulation amount, the target voltage will be increased by the second regulation amount.

[0132] In this embodiment, when the current voltage adjustment method is to decrease the first adjustment amount, the word line coupling effect is precisely eliminated, keeping the target voltage unchanged to avoid the recurrence of the coupling effect. When the current voltage adjustment method is to increase the second adjustment amount, the leakage current of the transistor in the word line driving circuit can be further reduced on the basis of compensating for the coupling effect, and the target voltage can be increased by the second adjustment amount. By adopting different target voltage adjustment methods under different previous voltage adjustment methods, the leakage current of the transistor in the word line driving circuit can be reduced to the greatest extent, thereby improving the performance of the memory operation.

[0133] For example, the value range of the second adjustment amount is (0, 0.5]V. The second adjustment amount can be 0.05V, 0.1V, 0.15V, etc. The first adjustment amount and the second adjustment amount can be the same or different.

[0134] In some exemplary embodiments provided in this disclosure, such as Figure 13 As shown, the memory control method includes:

[0135] S400: In response to a memory operation instruction, determine the address information of the first word line and the second word line.

[0136] S410. Determine the address information of the first word line and the address comparison result of the address information of the second word line.

[0137] S420. The product of the address comparison result and the word line spacing information is determined as the spacing comparison result.

[0138] S430: The product of the reciprocal of the spacing comparison result and the preset voltage is used as the voltage adjustment amount.

[0139] S440. Determine the target voltage based on the reference voltage and voltage adjustment amount.

[0140] S450, Adjust the voltage of the second word line to the target voltage.

[0141] S460, Enable and disable the corresponding word lines in the memory.

[0142] In this embodiment, in response to memory operation instructions, the word line driving circuit needs to turn on and off corresponding word lines, determining the address information of the first word line to be turned on and the second word line to be turned off. The address comparison result of the address information of the first word line and the address information of the second word line is determined to determine the relative spacing between the first and second word lines. The product of the address comparison result and the word line spacing information is determined as the spacing comparison result to determine the absolute spacing between the first and second word lines. The reciprocal of the spacing comparison result is multiplied by a preset voltage to obtain a voltage adjustment amount, which is used to adjust the reference voltage. Based on the reference voltage and the voltage adjustment amount, a target voltage is determined, and the voltage of the second word line is adjusted to the target voltage. After the voltage adjustment of the second word line is completed, the corresponding word lines in the memory are turned on and off. Since reducing the voltage of the second word line can compensate for the coupling effect of the word line, preventing the second word line from being mistakenly turned on due to the coupling effect, the reliability of the memory operation is improved. At the same time, reducing the voltage of the second word line can reduce the leakage current of the transistors in the word line driving circuit, thereby improving the performance of the memory operation.

[0143] In some exemplary embodiments provided in this disclosure, such as Figure 14 As shown, the memory control method includes:

[0144] S500: Perform coupling tests on each word line in the memory to obtain the test results.

[0145] S510. When the test result shows that there is coupling between word lines, reduce the target voltage by the first adjustment amount and return to step S500.

[0146] S520. When the test result shows that there is no coupling between word lines, obtain the previous voltage adjustment method of the target voltage.

[0147] S530. When the current voltage regulation method is to reduce the first regulation amount, keep the target voltage unchanged and execute step 550.

[0148] S540. When the current voltage regulation method is to increase the second regulation amount, increase the target voltage by the second regulation amount and return to step S500.

[0149] S550, in response to an operation instruction on the memory, adjusts the voltage of the corresponding word line in the memory to the target voltage.

[0150] S560, Enable and disable the corresponding word lines in the memory.

[0151] In this embodiment, coupling tests are performed on word lines to determine whether and how strong the coupling effect exists, thus obtaining test results. When coupling exists between word lines, the target voltage needs to be reduced to mitigate the impact of the coupling effect, and the coupling test is performed again after reducing the target voltage to determine if the coupling effect has been compensated. When there is no coupling between word lines, the target voltage may cause leakage current in the transistors of the word line driving circuit. The previous voltage adjustment method of the target voltage is obtained. When the previous voltage adjustment method is to reduce the first adjustment amount, the leakage current of the transistors in the word line driving circuit is minimized. The target voltage is kept constant, and the corresponding word line is turned off at this target voltage. When the previous voltage adjustment method is to increase the second adjustment amount, the leakage current of the transistors in the word line driving circuit may decrease. The target voltage is increased by the second adjustment amount, and the coupling test is performed again to determine whether a coupling effect exists. By adjusting the voltage of the word lines in advance by determining the target voltage through coupling tests, the complexity of memory control is reduced. At the same time, since reducing the voltage of the second word line can compensate for the coupling effect of the word line, it prevents the second word line from being mistakenly turned on due to the coupling effect, thereby improving the reliability of memory operation. Furthermore, the target voltage minimizes the leakage current of transistors in the word line drive circuit, thereby improving the performance of the memory.

[0152] Figure 15 A block diagram of a memory control device is shown according to an exemplary embodiment. (See diagram below.) Figure 15 As shown, the device includes at least an adjustment module 100 and a switch module 200.

[0153] The adjustment module 100 is configured to adjust the voltage of the corresponding word line in the memory to the target voltage in response to an operation command on the memory.

[0154] The switch module 200 is configured to turn on and off the corresponding word lines in the memory.

[0155] The target voltage is less than the reference voltage.

[0156] In one exemplary embodiment, a memory control device is provided, wherein an adjustment module 100 is configured to:

[0157] Determine the target voltage.

[0158] Adjust the voltage of the second line to the target voltage.

[0159] The second word line is at least one word line adjacent to the first word line. Alternatively, the second word line is at least one word line in the repository containing the first word line.

[0160] In one exemplary embodiment, a memory control device is provided, wherein an adjustment module 100 is configured to:

[0161] Determine the address information of the first word line and the second word line.

[0162] Determine the voltage regulation amount based on the address information.

[0163] Determine the target voltage based on the reference voltage and the voltage adjustment amount.

[0164] In one exemplary embodiment, a memory control device is provided, wherein an adjustment module 100 is configured to:

[0165] Determine the address information of the first word line and the address comparison result of the address information of the second word line.

[0166] The voltage adjustment amount is determined based on the address comparison results.

[0167] The greater the difference between the address information of the first word line and the address information of the second word line, the smaller the voltage regulation amount.

[0168] In one exemplary embodiment, a memory control device is provided, wherein an adjustment module 100 is configured to:

[0169] The product of the address comparison result and the word line spacing information is determined as the spacing comparison result.

[0170] The voltage adjustment amount is determined based on the distance comparison results.

[0171] The larger the distance comparison result, the smaller the voltage adjustment amount.

[0172] Figure 16 This is a block diagram illustrating a memory control device, namely a computer device 300, according to an exemplary embodiment. For example, the computer device 300 may be provided as a terminal device. (Refer to...) Figure 16The computer device 300 includes a processor 301, the number of which can be set to one or more as needed. The computer device 300 also includes a memory 302 for storing instructions executable by the processor 301, such as application programs. The number of memories can be set to one or more as needed. The stored application programs can be one or more. The processor 301 is configured to execute instructions to perform the methods described above.

[0173] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, apparatus (devices), or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. Computer storage media include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data), including but not limited to RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible by a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and can include any information delivery medium.

[0174] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is provided, such as a memory 302 including instructions, which can be executed by a processor 301 of the device 300 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0175] A non-transitory computer-readable storage medium, which, when instructions in the storage medium are executed by a processor of a memory control device, enables the memory control device to perform:

[0176] In response to an operation instruction on the memory, the voltage of the corresponding word line in the memory is adjusted to the target voltage.

[0177] Enables and disables the corresponding word lines in the memory.

[0178] The target voltage is less than the reference voltage.

[0179] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0180] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0181] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0182] In this disclosure, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase “comprising…” does not exclude the presence of additional identical elements in the article or device that includes said element.

[0183] Although preferred embodiments of the present disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0184] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, the intent of this disclosure also includes these modifications and variations.

Claims

1. A word line control circuit, characterized in that, The word line control circuit includes: A word line driving circuit, coupled to a word line, is configured to receive an operation instruction from the memory to turn on and off the corresponding word line; the turned-on word line is a first word line, and the turned-off word line is a second word line. A voltage generation circuit, the voltage generation circuit being used to generate at least one reference voltage; A voltage regulating circuit, which is coupled to both the word line driving circuit and the voltage generation circuit, is configured to regulate at least one of the reference voltages to generate a target voltage and output it to the word line driving circuit; the voltage of the second word line is the target voltage. Generating the target voltage includes: Determine the address comparison result between the address information of the first word line and the address information of the second word line; The voltage adjustment amount is determined based on the address comparison result; The target voltage is determined based on the reference voltage and the voltage adjustment amount; The greater the difference between the address information of the first word line and the address information of the second word line, the smaller the voltage adjustment amount; The target voltage is less than the reference voltage.

2. The word line control circuit according to claim 1, characterized in that, The reference voltage includes a first reference voltage, a second reference voltage, and / or a third reference voltage; the first reference voltage is a power supply voltage, the second reference voltage is a ground voltage, and the third reference voltage is located between the first reference voltage and the second reference voltage.

3. The word line control circuit according to claim 1, characterized in that, The voltage regulation circuit includes: An adjustment code generation module receives an address signal and an enable signal, and is configured to generate an adjustment code corresponding to the address signal. An adjustable voltage generation module is coupled to the adjustment code generation module, the word line driving circuit, and the voltage generation module, and is configured to adjust the reference voltage according to the adjustment code to generate the target voltage; The enable signal is the enable signal for the repository.

4. The word line control circuit according to any one of claims 1 to 3, characterized in that, The word line control circuit also includes: A decoding circuit, coupled to the word line driving circuit, is configured to receive command signals from the memory, decode the command signals to generate address signals and operation instructions, and output them to the word line driving circuit.

5. A memory, characterized in that, The memory includes the word line control circuitry as described in any one of claims 1 to 4.

6. A memory control method, characterized in that, The memory control method includes: In response to an operation command on the memory, the voltage of a portion of the word lines in the memory is adjusted to a target voltage; Turn on and off the corresponding word lines in the memory; the word line that is turned on is the first word line, and the word line that is turned off is the second word line; Adjusting the voltage of the second word line to the target voltage includes: Determine the address comparison result between the address information of the first word line and the address information of the second word line; The voltage adjustment amount is determined based on the address comparison result; The target voltage is determined based on the reference voltage and the voltage adjustment amount; The greater the difference between the address information of the first word line and the address information of the second word line, the smaller the voltage adjustment amount; The target voltage is less than the reference voltage.

7. The memory control method according to claim 6, characterized in that, The second word line is at least one word line adjacent to the first word line; or, the second word line is at least one word line in the repository where the first word line is located.

8. The memory control method according to claim 7, characterized in that, Determining the voltage adjustment amount based on the address comparison result includes: The product of the address comparison result and the word line spacing information is determined as the spacing comparison result; The voltage adjustment amount is determined based on the spacing comparison results; The larger the distance comparison result, the smaller the voltage adjustment amount.

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