Spaceborne anti-jamming PMOS threshold voltage signal readout circuit and method

Abstract

The present invention discloses a spaceborne anti-interference PMOS threshold voltage signal readout circuit and method. The readout circuit includes a first voltage follower, a second voltage follower, a third voltage follower, a multiplexer, signal processing electronics, an analog-to-digital converter, and a controller. In the present invention, by proposing a new spaceborne PMOS threshold voltage signal readout circuit with strong anti-interference ability and small temperature drift error, and a method for measuring the PMOS threshold voltage using this circuit, it can provide a basis for the accurate detection of the total ionizing dose effect of satellites and other spacecraft. The readout circuit and method measure the PMOS threshold voltage in a "pseudo-differential" manner, which can effectively suppress the interference in the voltage signals at both ends of the PMOS; all the measured signals are processed by the same circuit in a time-sharing manner, reducing the error introduced by the temperature drift of the signal processing circuit; and, the reduction of the signal processing circuit channels is beneficial to reducing the volume and weight of the electronics.

Description

Technical Field

[0001] The present invention relates to the technical field of on - orbit ionization radiation total dose effect measurement, and particularly to an on - orbit anti - interference PMOS threshold voltage signal readout circuit and method. Background Art

[0002] With the increase in cost - sensitive space missions such as commercial spaceflight, commercial off - the - shelf (COTS) devices are increasingly used in space activities. In spacecraft such as satellites, the most important problems to be solved when using COTS devices are the design and verification of space environment adaptation. Specifically, it mainly involves the evaluation of the tolerance of COTS devices to the space thermal environment, space radiation environment and effects, as well as the protection design and verification. The satellite orbit is in the space radiation environment and inevitably encounters the radiation of high - energy particles (mainly high - energy protons and heavy ions), which will cause the ionization radiation total dose effect (TID) on COTS devices. This effect is determined by the ionization radiation dose generated by space high - energy particles and may cause the failure of COTS devices. Conducting ionization radiation total dose effect detection and obtaining the total dose effect data of typical orbits can provide support for the index formulation of COTS devices selected for commercial spaceflight and the radiation protection design of devices.

[0003] The most direct and effective means of measuring the ionization radiation total dose effect is to carry a total dose sensor device on the satellite. Currently, the total dose sensor is realized by measuring the threshold voltage of a PMOS - type field - effect transistor sensitive to radiation. The readout circuit generally obtains the threshold voltage of the PMOS by directly measuring the voltage difference between the source and drain of the PMOS transistor. However, the sensitivity of the threshold voltage of the PMOS - type transistor to the change in the total dose is not high. When using this readout circuit for radiation total dose measurement, the external electromagnetic interference and the temperature drift error of the readout circuit are close to the change amount of the PMOS threshold voltage, thus significantly affecting the accuracy of the threshold voltage measurement and becoming the main limiting factor for improving the total dose measurement accuracy. Therefore, in order to improve the accuracy of on - orbit ionization radiation total dose effect measurement, there are still many limitations in the existing PMOS threshold voltage signal readout circuit, and it is necessary to design a new PMOS threshold voltage signal readout circuit and method with strong anti - interference ability and small temperature drift error. Summary of the Invention

[0004] The purpose of the present invention is to provide an on - orbit anti - interference PMOS threshold voltage signal readout circuit and method to solve the above problems.

[0005] In order to achieve the above purpose, the present invention adopts the following technical solutions:

[0006] Spaceborne anti-jamming PMOS threshold voltage signal readout circuit. The readout circuit includes voltage follower 1, voltage follower 2, voltage follower 3, multiplexer, signal processing electronics, analog-to-digital converter, and controller;

[0007] The input ports of voltage follower 1, voltage follower 2, and voltage follower 3 are respectively the input ports V1, V2, and SGND of the readout circuit;

[0008] The multiplexer has at least three input ports X1, X2, and X3 and one output port Y1;

[0009] The output port Y1 of the multiplexer is connected to the input port of the signal processing electronics;

[0010] The output port of the signal processing electronics is connected to the input port of the analog-to-digital converter.

[0011] Preferably, the output ports of voltage follower 1, voltage follower 2, and voltage follower 3 are respectively connected to the input ports X1, X2, and X3 of the multiplexer. Voltage follower 1, voltage follower 2, and voltage follower 3 are made of operational amplifier A 1 manufactured.

[0012] Preferably, the multiplexer can electrically connect any one of the input ports X1, X2, and X3 to the output port Y1 under the control of the controller.

[0013] Preferably, under the control of the controller, the analog-to-digital converter converts the analog voltage signal output by the signal processing electronics into a digital signal, and the digital signal is sent to the controller.

[0014] Preferably, the input terminal V1 of the readout circuit is connected to the positive electrode of the temperature-measuring diode D, the input terminal V2 is connected to the negative electrode of the temperature-measuring diode D, the input terminal SGND is connected to the drain of the PMOS transistor Q. The temperature-measuring diode D and the PMOS transistor Q are connected in series. The negative electrode of the temperature-measuring diode D is connected to the source of the PMOS transistor Q, and the drain of the PMOS transistor Q is connected to the reference ground.

[0015] Preferably, the signal processing electronics includes resistor R 1 resistor R 2 resistor R 3 resistor R 4 operational amplifier A 2 operational amplifier A 3 capacitor C 1 capacitor C 2 operational amplifier A 2 resistor R 1 resistor R 2Compose a non-inverting proportional amplifier circuit, with the operational amplifier A 3 , resistor R 3 , resistor R 4 , capacitor C 1 and capacitor C 2 to form a low-pass filter circuit.

[0016] Preferably, the method for the spaceborne anti-interference PMOS threshold voltage signal readout circuit includes the following steps:

[0017] S1. Measure the positive voltage V 1a of the temperature-measuring diode D; the controller controls the multiplexer to connect the input port X1 and the output port Y1. After waiting for a time ΔT, the controller controls the analog-to-digital converter to sample and quantize to obtain the positive voltage V 1a of the temperature-measuring diode D;

[0018] S2. Measure the source voltage V 2a of the PMOS transistor Q; the controller controls the multiplexer to connect the input port X2 and the output port Y1. After waiting for a time ΔT, the controller controls the analog-to-digital converter to sample and quantize to obtain the source voltage V 2a of the PMOS transistor Q;

[0019] S3. Measure the reference ground voltage V SGND ; the controller controls the multiplexer to connect the input port X3 and the output port Y1. After waiting for a time ΔT, the controller controls the analog-to-digital converter to sample and quantize to obtain the reference ground voltage V SGND ;

[0020] S4. Measure the source voltage V 2b of the PMOS transistor Q again; the controller controls the multiplexer to connect the input port X2 and the output port Y1. After waiting for a time ΔT, the controller controls the analog-to-digital converter to sample and quantize to obtain the source voltage V 2b of the PMOS transistor Q;

[0021] S5. Measure the positive voltage V 1b of the temperature-measuring diode D again; the controller controls the multiplexer to connect the input port X1 and the output port Y1. After waiting for a time ΔT, the controller controls the analog-to-digital converter to sample and quantize to obtain the positive voltage V 1b of the temperature-measuring diode D;

[0022] S6. Calculate the forward voltage drop V D and the threshold voltage V R ;

[0023]

[0024]

[0025] In the controller, the forward voltage drop V of the temperature-measuring diode D is calculated according to the above formula D and the threshold voltage V of the PMOS transistor Q R .

[0026] In summary, due to the adoption of the above technical solutions, the beneficial effects of the present invention are as follows:

[0027] 1. The present application proposes a new spaceborne PMOS threshold voltage signal readout circuit with strong anti-interference ability and small temperature drift error, as well as a method for measuring the PMOS threshold voltage using this circuit, which can provide a basis for the accurate detection of the total ionizing dose effect of satellites and other spacecraft. The readout circuit and method measure the PMOS threshold voltage in a "pseudo-differential" manner, which can effectively suppress the interference in the voltage signals at both ends of the PMOS; all the measured signals are processed by the same circuit in a time-sharing manner, reducing the error introduced by the temperature drift of the signal processing circuit; moreover, the number of channels of the signal processing circuit is reduced, which is beneficial to reducing the volume and weight of the electronics.

[0028] 2. The readout circuit and method proposed in the present application have stronger anti-interference ability. The existing PMOS threshold voltage signal readout circuits and methods generally measure the voltage difference between the source and drain of the PMOS transistor directly. Among them, the threshold voltage is processed as a single-ended signal at the PMOS transistor position and is easily affected by external environmental interference. In the present application, the source voltage, drain voltage, and reference ground voltage of the PMOS transistor are all sampled and quantified. Then, by calculating the voltage difference between the source and drain in the digital circuit, the PMOS threshold voltage is obtained, forming a "pseudo-differential" measurement method. In this case, since the external interference acts on the voltage signals at both the source and drain simultaneously, after sampling and quantization, the common-mode interference existing in the signals can be eliminated when the two are subtracted in the digital circuit, thereby improving the anti-interference ability of the threshold measurement.

[0029] 3. The readout circuit and method proposed in the present application have smaller temperature drift error. In the existing readout circuits and methods, the threshold voltage is transmitted as a single-ended signal in the signal processing electronics. Errors such as the temperature drift of the electronics are mixed into the measured threshold voltage signal, reducing the signal measurement accuracy. The present application uses a time-sharing method to process the source voltage, drain voltage, and reference ground voltage of the PMOS transistor using the same electronics channel. The temperature drift error of this electronics channel will be superimposed on the above signals with a similar amplitude. Due to the "pseudo-differential" measurement method, the PMOS threshold voltage is obtained by calculating the voltage difference between the source and drain in the digital circuit, and the temperature drift error of the electronics superimposed on the source and drain voltage signals can be approximately eliminated, thereby reducing the temperature drift error of the electronics.

[0030] 4. The hardware implementation of this application is simple, reducing the volume and weight of the electronics. The source voltage, drain voltage, reference ground voltage and other signals of the PMOS tube are processed using the same electronic channel in a time-sharing manner, reducing the number of signal processing electronic channels and saving volume and weight. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It shows a block diagram of a satellite-borne anti-interference PMOS threshold voltage signal readout circuit according to an embodiment of the present invention;

[0032] Figure 2 A schematic diagram showing a circuit for measuring a PMOS threshold voltage signal according to an embodiment of the present invention is shown;

[0033] Figure 3 A flowchart of the implementation steps of a method for measuring a PMOS threshold voltage signal provided in accordance with an embodiment of the present invention is shown;

[0034] Figure 4 A schematic diagram of a voltage follower provided according to an embodiment of the present invention is shown;

[0035] Figure 5 A schematic diagram of signal processing electronics provided according to an embodiment of the present invention is shown.

[0036] Legend:

[0037] 1. Readout circuit; 2. Voltage follower 1; 3. Voltage follower 2; 4. Voltage follower 3; 5. Multi-way switch; 6. Signal processing electronics; 7. Analog-to-digital converter; 8. Controller; 9. Operational amplifier A 1 ; 10. Resistor R 1 ; 11. Resistor R 2 ; 12. Resistor R 3 13. Resistor R 4 ; 14. Operational amplifier A 2 ; 15. Operational amplifier A 3 ; 16. Capacitor C 1 ; 17. Capacitor C 2 . DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] See also Figures 1-5, the present invention provides a technical solution:

[0040] A spaceborne anti-jamming PMOS threshold voltage signal readout circuit, the readout circuit 1 includes a voltage follower 2, a voltage follower 3, a voltage follower 4, a multiplexer 5, signal processing electronics 6, an analog-to-digital converter 7 and a controller 8;

[0041] The input ports of the voltage follower 2, the voltage follower 3 and the voltage follower 4 are respectively the input ports V1, V2 and SGND of the readout circuit 1;

[0042] The multiplexer 5 has at least three input ports X1, X2 and X3 and an output port Y1;

[0043] The output port Y1 of the multiplexer 5 is connected to the input port of the signal processing electronics 6;

[0044] The multiplexer 5 is implemented using a multiplexer integrated circuit chip, and the model is selected as ADG408. This multiplexer integrated circuit has eight signal input terminals and one signal output terminal, meeting the requirement of having at least three input ports. Among them, its input ports S1 to S3 respectively correspond to Figure 1 the input ports X1 to X3 therein, and the output port D corresponds to the output port Y1.

[0045] The output port of the signal processing electronics 6 is connected to the input port of the analog-to-digital converter 7; its function is to amplify and low-pass filter the voltage signal. Amplification is to make the amplitude of the voltage signal match the input range of the analog-to-digital converter 7, and low-pass filtering is to avoid frequency aliasing during the acquisition of the analog-to-digital converter 7 and can reduce the noise in the signal. The signal processing electronics 6 has a low-pass characteristic with a time constant of T 0 . This characteristic will cause a transient process when the multiplexer 5 switches the voltage signal. In engineering, the duration of the transient process can be considered as 10T 0 . To ensure the stability and accuracy of the acquired voltage signal, sampling and quantization need to avoid this transient time.

[0046] Specifically, as Figure 1 and Figure 4 shown, the output ports of the voltage follower 2, the voltage follower 3 and the voltage follower 4 are respectively connected to the input ports X1, X2 and X3 of the multiplexer 5. The voltage follower 2, the voltage follower 3 and the voltage follower 4 are made of an operational amplifier A 1 9, and the operational amplifier A 1Select the quad operational amplifier with the model number JL147. It has a wide output voltage range and can meet the voltage range of the signals involved in PMOS threshold voltage measurement; the functions of voltage follower 2, voltage follower 3, and voltage follower 4 are to increase the input impedance of the readout circuit 1 and reduce the current flowing into ports V1, V2, and SGND, thereby reducing the disturbance to the measured voltage.

[0047] U in is the input port of voltage follower 2, voltage follower 3, and voltage follower 4, and U out is the output port.

[0048] The multiplexer 5 can electrically connect any one of the input ports X1, X2, and X3 to the output port Y1 under the control of the controller 8, thereby transmitting the corresponding voltage signal to the subsequent processing circuit;

[0049] The analog-to-digital converter 7 converts the analog voltage signal output by the signal processing electronics 6 into a digital signal under the control of the controller 8, and the digital signal is sent to the controller 8.

[0050] Specifically, as Figure 1 and Figure 2 shown, the input terminal V1 of the readout circuit 1 is connected to the positive electrode of the temperature-measuring diode D, the input terminal V2 is connected to the negative electrode of the temperature-measuring diode D, the input terminal SGND is connected to the drain of the PMOS transistor Q, the temperature-measuring diode D and the PMOS transistor Q are connected in series, the negative electrode of the temperature-measuring diode D is connected to the source of the PMOS transistor Q, and the drain of the PMOS transistor Q is connected to the reference ground;

[0051] The drive current I 0 flows into the positive electrode of the temperature-measuring diode D. Under its excitation, the temperature-measuring diode D generates a forward voltage drop V D , and a threshold voltage V R is generated between the source and drain of the PMOS transistor Q. According to the connection method shown in Figure 2 , it can be known that the forward voltage drop is V D =V 1 -V 2 , and the threshold voltage is V R =V 2 -V SGND . Among them, V 1 , V 2 and V SGND respectively represent the voltages of ports V1, V2, and SGND, and the voltage ranges of the signals V 1 , V 2 and V SGND involved in PMOS threshold voltage measurement are -4V to +4V.

[0052] Specifically, as Figure 5As shown, the signal processing electronics 6 includes resistor R 1 10, resistor R 2 11, resistor R 3 12, resistor R 4 13, operational amplifier A 2 14, operational amplifier A 3 15, capacitor C 1 16 and capacitor C 2 17, operational amplifier A 2 14, resistor R 1 10 and resistor R 2 11 form a non-inverting proportional amplifier circuit, and the amplification factor is determined by the values of resistor R 1 (10), R 2 (11), which is (R 1 + R 2 ) / R 1 . Operational amplifier A 3 15, resistor R 3 12, resistor R 4 13, capacitor C 1 16 and capacitor C 2 17 form a low-pass filter circuit. Generally, the resistance value R 3 = R 4 , and the capacitance value C 1 = C 2 . At this time, the time constant of the low-pass filter circuit is T 0 = C 1 R 3 .

[0053] Operational amplifier A 2 14 and operational amplifier A 3 15 also select the model JL147. The values of resistor R 1 (10) and R 2 (11) are both selected as 10 kΩ. Therefore, the amplification factor is (R 1 + R 2 ) / R 1 = 2. After amplification, the signal voltage range is -8V to +8V; the values of resistor R 3 12 and resistor R 4 13 are both selected as 20 kΩ; the values of capacitor C 1 16 and capacitor C 2 17 are both selected as 10 nF. At this time, the time constant of the low-pass filter circuit is T 0 = C 1 R 3 = 0.2 ms.

[0054] The analog-to-digital converter 7 is implemented using an analog-to-digital converter integrated circuit chip, with the model selected as AD976. The analog voltage input range of this chip is -10V to +10V, which matches the amplified signal voltage range of -8V to +8V.

[0055] The controller 8 is implemented using a programmed FPGA integrated circuit chip, with the model selected as A3P1000.

[0056] The reading of the PMOS threshold voltage signal is carried out according to the method shown in the Figure 3 flow chart. Among them, the waiting time △T is taken as △T = 10T 0 = 2ms.

[0057] Specifically, as shown in Figure 3 , the method for the on-board anti-interference PMOS threshold voltage signal reading circuit is characterized by including the following steps:

[0058] S1. Measure the positive voltage V 1a of the temperature-measuring diode D; the controller 8 controls the multiplexer 5 to connect the input port X1 and the output port Y1. After waiting for △T (△T ≥ 10T 0 ) time, the controller 8 controls the analog-to-digital converter 7 to sample and quantize to obtain the positive voltage V 1a of the temperature-measuring diode D;

[0059] S2. Measure the source voltage V 2a of the PMOS transistor Q; the controller 8 controls the multiplexer 5 to connect the input port X2 and the output port Y1. After waiting for △T time, the controller 8 controls the analog-to-digital converter 7 to sample and quantize to obtain the source voltage V 2a of the PMOS transistor Q;

[0060] S3. Measure the reference ground voltage V SGND ; the controller 8 controls the multiplexer 5 to connect the input port X3 and the output port Y1. After waiting for △T time, the controller 8 controls the analog-to-digital converter 7 to sample and quantize to obtain the reference ground voltage V SGND ;

[0061] S4. Measure the source voltage V 2b of the PMOS transistor Q again; the controller 8 controls the multiplexer 5 to connect the input port X2 and the output port Y1. After waiting for △T time, the controller 8 controls the analog-to-digital converter 7 to sample and quantize to obtain the source voltage V 2b of the PMOS transistor Q;

[0062] S5. Measure the positive voltage V 1b of the temperature-measuring diode D again.; The controller 8 controls the multiplexer 5 to connect the input port X1 and the output port Y1. After waiting for a time period of △T, the controller 8 controls the analog-to-digital converter 7 to sample and quantize to obtain the positive voltage V of the temperature-measuring diode D 1b ;

[0063] S6. Calculate the forward voltage drop V D and the threshold voltage V R ;

[0064]

[0065]

[0066] In the controller 8, the forward voltage drop V of the temperature-measuring diode D is calculated according to the above formula D and the threshold voltage V of the PMOS transistor Q R .

[0067] The PMOS threshold voltage signal reading circuit and method of the present application implement a "pseudo-differential" measurement method, which has the function of suppressing external interference and electronic temperature drift error, and has higher measurement accuracy compared with the existing threshold voltage signal reading circuit. The principle of the "pseudo-differential" measurement method is described below

[0068] When measuring the PMOS threshold voltage, the measured signal will be mixed with interference generated by the external environment in the measurement circuit. The present application uses the same electronic channel to process all signals. When the measurement times of each signal are close, it can be considered that the interference voltages mixed into each signal by the outside are approximately equal, and the interference voltage is denoted as V i .

[0069] On the other hand, affected by temperature changes, etc., the output voltage of the signal processing electronic channel will drift, which is equivalent to superimposing a slowly changing voltage on each measured signal. If the measurement times of each signal are close, it can be considered that this voltage approximately changes linearly in a short time, denoted as:

[0070] V e =V e0 +L·t

[0071] In the formula, Ve is the drift error voltage; Ve0 is the drift error voltage at t = 0; L is the change rate of the drift error voltage with time under the linear approximation condition; t is the measurement time

[0072] Due to the existence of the interference voltage V i introduced from the outside and the drift error voltage V e of the electronic channel, there will inevitably be an error (V i +Ve ), thus reducing the measurement accuracy.

[0073] Measure according to the PMOS threshold voltage signal reading circuit and method in this application. The theoretical value of the forward voltage drop is V D = V 1 - V 2 . The theoretical value of the threshold voltage is V R = V 2 - V SGND . Among them, V 1 , V 2 and V SGND respectively represent the ideal values of the voltages at ports V1, V2 and SGND when there are no interference and drift errors. If the influence of interference and drift errors is considered, the respective signal voltages measured according to the flowchart shown in Figure 3 are:

[0074] V 1a ' = V 1 + V i + V e0

[0075] V 2a ' = V 2 + V i + V e0 + L·ΔT

[0076] V SGND ' = V SGND + V i + V e0 + 2L·ΔT

[0077] V 2b ' = V 2 + V i + V e0 + 3L·ΔT

[0078] V 1b ' = V 1 + V i + V e0 + 4L·ΔT

[0079] Substitute these voltages into the formula in step S6 above to calculate the measured value of the forward voltage drop V D as:

[0080]

[0081] The measured value of the threshold voltage V R is:

[0082]

[0083] It can be seen from this that by measuring according to the readout circuit and method of the present application, the interference and drift errors in the PMOS threshold voltage can be suppressed, and the measurement accuracy can be improved. Especially under the linear approximation condition, the interference and drift errors can be completely eliminated, and the measured result is close to the situation without interference and drift errors.

[0084] The PMOS threshold voltage signal readout circuit and method implemented by the present application: The "pseudo-differential" method is used to measure the PMOS threshold voltage, which can effectively suppress the interference in the voltage signals at both ends of the PMOS and has strong anti-interference ability; all the measured signals are processed by the same signal processing circuit in a time-sharing manner, reducing the errors introduced by circuit temperature drift, etc.; and because the number of electronic channels is reduced, the circuit has a small volume and light weight. The present application has clear application prospects and development potential in space science and engineering fields such as spaceborne total ionizing dose effect detection technology.

[0085] The characteristics of the PMOS threshold voltage signal readout circuit and method of the present application are as follows: The source voltage, drain voltage, and reference ground voltage of the PMOS transistor are all sampled and quantized, and the PMOS threshold voltage is obtained by calculating the voltage difference between the source and the drain in the digital circuit, which has stronger anti-interference ability; the same electronic channel is used in a time-division multiplexing manner to process signals such as the source voltage, drain voltage, and reference ground voltage of the PMOS transistor, which can reduce the influence of the temperature drift error of the signal processing electronics and reduce the number of signal processing electronics channels, saving volume and weight. Therefore, the readout circuit and method have strong anti-interference ability, small temperature drift error, small volume, and light weight, and are suitable for use in precise detection devices for the total ionizing dose effect of satellites and other spacecraft to measure the threshold voltage of radiation-sensitive field effect transistors.

[0086] The above description of the embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. Spaceborne anti-jamming PMOS threshold voltage signal readout circuit, Characterized in that, The readout circuit (1) includes a first voltage follower (2), a second voltage follower (3), a third voltage follower (4), a multiplexer (5), signal processing electronics (6), an analog-to-digital converter (7) and a controller (8); The input ports of the first voltage follower (2), the second voltage follower (3) and the third voltage follower (4) are the input ports V1, V2 and SGND of the readout circuit (1) respectively; The input port V1 of the readout circuit (1) is connected to the positive electrode of the temperature-measuring diode D, the input port V2 is connected to the negative electrode of the temperature-measuring diode D, the input port SGND is connected to the drain of the PMOS transistor Q of the measured threshold voltage, the temperature-measuring diode D and the PMOS transistor Q are connected in series, the negative electrode of the temperature-measuring diode D is connected to the source of the PMOS transistor Q, and the drain of the PMOS transistor Q is connected to the reference ground; The multiplexer (5) has at least three input ports X1, X2 and X3 and an output port Y1; The output port Y1 of the multiplexer (5) is connected to the input port of the signal processing electronics (6); The output port of the signal processing electronics (6) is connected to the input port of the analog-to-digital converter (7).

2. The spaceborne anti-jamming PMOS threshold voltage signal readout circuit according to claim 1, Characterized in that, The output ports of the first voltage follower (2), the second voltage follower (3) and the third voltage follower (4) are respectively connected to the input ports X1, X2 and X3 of the multiplexer (5), and the first voltage follower (2), the second voltage follower (3) and the third voltage follower (4) are made by an operational amplifier A 1 (9).

3. The spaceborne anti-jamming PMOS threshold voltage signal readout circuit according to claim 1, Characterized in that, The multiplexer (5) can electrically connect any one of the input ports X1, X2 and X3 to the output port Y1 under the control of the controller (8).

4. The spaceborne anti-jamming PMOS threshold voltage signal readout circuit according to claim 1, Characterized in that, The analog-to-digital converter (7) converts the analog voltage signal output by the signal processing electronics (6) into a digital signal under the control of the controller (8), and the digital signal is sent to the controller (8).

5. The spaceborne anti-jamming PMOS threshold voltage signal readout circuit according to claim 1, Characterized in that, The signal processing electronics (6) includes resistor R 1 (10), resistor R 2 (11), resistor R 3 (12), resistor R 4 (13), operational amplifier A 2 (14), operational amplifier A 3 (15), capacitor C 1 (16) and capacitor C 2 (17), the operational amplifier A 2 (14), resistor R 1 (10) and resistor R 2 (11) form a non-inverting proportional amplification circuit, and the operational amplifier A 3 (15), resistor R 3 (12), resistor R 4 (13), capacitor C 1 (16) and capacitor C 2 (17) form a low-pass filter circuit.

6. The method for the spaceborne anti-jamming PMOS threshold voltage signal readout circuit according to claim 1, Characterized in that, Comprises the following steps: S1. Measure the positive voltage V of the temperature-measuring diode D 1a ; The controller (8) controls the multiplexer (5) to connect the input port X1 and the output port Y1. After waiting for a time ΔT, the controller (8) controls the analog-to-digital converter (7) to sample and quantify to obtain the positive voltage V of the temperature-measuring diode D 1a ; S2. Measure the source voltage V of PMOS transistor Q 2a ; The controller (8) controls the multiplexer (5) to connect the input port X2 and the output port Y1. After waiting for a time △T, the controller (8) controls the analog-to-digital converter (7) to sample and quantize to obtain the source voltage V of PMOS transistor Q 2a ; S3. Measure the reference ground voltage V SGND ; The controller (8) controls the multiplexer (5) to connect the input port X3 and the output port Y1. After waiting for a time △T, the controller (8) controls the analog-to-digital converter (7) to sample and quantize to obtain the reference ground voltage V SGND ; S4. Measure the source voltage V of the PMOS transistor Q again 2b ; The controller (8) controls the multiplexer (5) to connect the input port X2 and the output port Y1. After waiting for a time △T, the controller (8) controls the analog-to-digital converter (7) to sample and quantize to obtain the source voltage V of the PMOS transistor Q 2b ; S5. Measure the positive voltage V of the temperature-measuring diode D again 1b ; The controller (8) controls the multiplexer (5) to connect the input port X1 and the output port Y1. After waiting for a time △T, the controller (8) controls the analog-to-digital converter (7) to sample and quantize to obtain the positive voltage V of the temperature-measuring diode D 1b ; S6. Calculate the forward voltage drop V D and the threshold voltage V R ; In the controller (8), the forward voltage drop V of the temperature measuring diode D is calculated according to the above formula D and the threshold voltage V of the PMOS transistor Q R .

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