A voltage stabilizing control circuit

Abstract

The embodiment of the present application discloses a kind of voltage stabilizing control circuit, the circuit includes first control module, second control module, logic drive module, first control module and logic drive module are used to when the voltage value of the output voltage signal of boost conversion circuit is not less than first preset voltage threshold, the conduction time of the first switch tube in boost conversion circuit is unchanged;Second control module is used to output first control signal, the voltage value of the output voltage signal of boost conversion circuit is not less than first preset voltage threshold and the voltage value of the first voltage signal output by first capacitor drops to third preset voltage threshold, the voltage value of first control signal is suddenly changed from low level to high level;Logic drive module is used to control the first switch tube conduction when the voltage value of first control signal is suddenly changed from low level to high level.The embodiment of the present application can reduce the output voltage ripple when boost conversion circuit works.

Description

Technical Field

[0001] This application relates to driving technology, applied in the field of electrical engineering, and in particular to a voltage regulation control circuit. Background Technology

[0002] When the load changes from heavy to light, the output current of the boost converter circuit based on constant off-time (CFT) control decreases, and the output voltage increases due to disturbances. To maintain output voltage stability, the on-time of the power switch in the boost converter circuit is reduced to the minimum on-time (i.e., the duty cycle of the power switch is reduced to the minimum duty cycle). The output voltage rises slowly. When it reaches a set threshold, the input of the boost converter circuit stops working, and the load is powered entirely by the output capacitor. The output voltage then slowly decreases. When it drops back to the set threshold, the input of the boost converter circuit starts working again, and the output voltage rises slowly once more. Due to the setting of two thresholds, and considering the effects of hysteresis and delay, the output voltage ripple of the boost converter circuit is relatively large. Therefore, the CFT-based boost converter circuit is not suitable for scenarios with high requirements for output voltage ripple. Summary of the Invention

[0003] This application discloses a voltage regulation control circuit for reducing the output voltage ripple when a Boost converter circuit is operating.

[0004] In a first aspect, embodiments of this application provide a voltage regulation control circuit, which includes a first control module 101, a second control module 102, and a logic drive module 103. The second control module 102 includes a first capacitor C1. The first control module 101 and the logic drive module 103 are used to control the conduction time of the first switch M1 in the Boost converter circuit to remain unchanged when the voltage value of the output voltage signal VOUT of the Boost converter circuit is not less than a first preset voltage threshold. The second control module 102 is used to output a first control signal TOFF_ED. When the voltage value of the output voltage signal VOUT of the Boost converter circuit is not less than the first preset voltage threshold and the voltage value of the first voltage signal V_C1 output by the first capacitor C1 drops to a third preset voltage threshold, the voltage value of the first control signal TOFF_ED changes abruptly from a low level to a high level. As the voltage value of the output voltage signal VOUT of the Boost converter circuit increases, the discharge speed of the first capacitor C1 decreases. The logic drive module 103 is used to control the first switch M1 to conduct when the voltage value of the first control signal TOFF_ED changes abruptly from a low level to a high level.

[0005] When the load changes from heavy to light, the output current of the Boost converter gradually decreases, and the output voltage signal VOUT (i.e., the output voltage) is disturbed and gradually increases. In the above voltage regulation control circuit, after the output voltage of the Boost converter reaches the first preset voltage threshold, the time required for the voltage value of the first voltage signal V_C1 to drop to the third preset voltage threshold is the turn-off time of the first switch M1. Since the discharge rate of the first capacitor C1 slows down as the output voltage increases, the conduction time of the first switch M1 remains unchanged, while the turn-off time increases with the increase of the output voltage.

[0006] Therefore, when the load connected to the Boost converter circuit changes from heavy load to light load, the above-mentioned voltage regulation control circuit can extend the turn-off time of the first switch M1 (which can be regarded as a power switch) after the on-time of the first switch M1 is constant, so that the Boost converter circuit can operate based on the constant open-time (COT) control mode, reduce the duty cycle of the first switch M1 until the output voltage stabilizes, thereby reducing the output voltage ripple when the Boost converter circuit is working.

[0007] In conjunction with the first aspect, in one possible implementation, the first control module 101 includes a second capacitor C2. The first control module 101 outputs a second control signal TON_ED. When the voltage value of the output voltage signal VOUT of the Boost converter circuit is not less than a first preset voltage threshold and the voltage value of the second voltage signal V_C2 output by the second capacitor C2 rises to the second preset voltage threshold, the voltage value of the second control signal TON_ED abruptly changes from low to high. The voltage value of the output voltage signal VOUT of the Boost converter circuit increases, while the charging speed of the second capacitor C2 remains unchanged. The logic drive module 103 controls the first switch M1 in the Boost converter circuit to disconnect when the voltage value of the second control signal TON_ED abruptly changes from low to high.

[0008] In the above voltage regulation control circuit, after the output voltage of the Boost converter circuit reaches the first preset voltage threshold, the time taken for the voltage value of the second voltage signal V_C2 to rise to the second preset voltage threshold is the conduction time of the first switch M1. Since the charging speed of the second capacitor C2 remains unchanged, the conduction time of the first switch M1 remains unchanged.

[0009] Optionally, the time required for the voltage value of the second voltage signal V_C2 to rise to the second preset voltage threshold can be the minimum conduction time of the first switch M1.

[0010] In conjunction with the first aspect, or any of the above possible implementations of the first aspect, in another possible implementation, the second control module 102 further includes a third capacitor C3, wherein when the voltage value of the output voltage signal VOUT of the Boost converter circuit is less than the first preset voltage threshold and the voltage value of the third voltage signal VSENSE obtained by converting the first current signal I_M1 flowing through the first switch M1 in the Boost converter circuit rises to the first voltage value, the voltage value of the second control signal TON_ED changes abruptly from low level to high level; the voltage value of the output voltage signal VOUT of the Boost converter circuit increases, and the first voltage value decreases; when the voltage value of the output voltage signal VOUT of the Boost converter circuit is less than the first preset voltage threshold and the voltage value of the fourth voltage signal V_C3 output by the third capacitor C3 rises to the fourth preset voltage threshold, the voltage value of the first control signal TOFF_ED changes abruptly from low level to high level; the voltage value of the output voltage signal VOUT of the Boost converter circuit increases, and the charging speed of the third capacitor C3 remains unchanged.

[0011] In the aforementioned voltage regulation control circuit, before the output voltage of the Boost converter circuit reaches the first preset voltage threshold, the time required for the voltage value of the third voltage signal VSENSE to rise to the first voltage value is the turn-on time of the first switch M1, and the time required for the voltage value of the fourth voltage signal V_C3 to rise to the fourth preset voltage threshold is the turn-off time of the first switch M1. Since the charging speed of the third capacitor C3 remains constant and the first voltage value decreases as the output voltage increases, the turn-off time of the first switch M1 remains constant while its turn-on time decreases as the output voltage increases.

[0012] Therefore, when the load changes from heavy to light, and the output voltage of the Boost converter circuit begins to increase due to disturbance, the Boost converter circuit operates in a constant off-time (CFT) control mode under the control of the aforementioned voltage regulation control circuit. When the output voltage of the Boost converter circuit further increases and reaches the first preset voltage threshold, the Boost converter circuit operates in a constant on-time (COT) control mode under the control of the aforementioned voltage regulation control circuit. In other words, the Boost converter circuit always operates in a single-cycle control mode, reducing the duty cycle of the first switching transistor M1 until the output voltage stabilizes, thereby reducing the output voltage ripple during the operation of the Boost converter circuit.

[0013] In conjunction with the first aspect, or any of the possible implementations of the first aspect described above, in yet another possible implementation, the voltage regulation control circuit further includes a current sampling module 104 and an error amplification module 105. The first input terminal a1 of the first control module 101 is connected to the drain of the first switching transistor M1 in the Boost converter circuit through the current sampling module 104. The second input terminal a2 of the first control module 101 and the first input terminal b1 of the second control module 102 are connected to the output terminal c of the error amplification module 105. The input terminal d of the error amplification module 105 is connected to the positive output terminal o1 of the Boost converter circuit. The output terminal e of the control module 101 is connected to the first input terminal f1 of the logic drive module 103, and the output terminal g of the second control module 102 is connected to the second input terminal f2 of the logic drive module 103. The current sampling module 104 is used to convert the first current signal I_M1 into the third voltage signal VSENSE. When the current value of the first current signal I_M1 increases, the voltage value of the third voltage signal VSENSE increases. The error amplification module 105 is used to output the error signal VEA. When the voltage value of the output voltage signal VOUT of the Boost converter circuit increases, the voltage value of the output error signal VEA decreases.

[0014] Considering that the output voltage of the Boost converter circuit increases only slightly due to disturbances, the error amplification module in the above-mentioned voltage regulation control circuit can amplify the extent to which the output voltage increases due to disturbances. This allows the voltage regulation control circuit to adjust the duty cycle of the first switching transistor M1 according to changes in the load, thereby reducing the output voltage ripple when the Boost converter circuit is operating.

[0015] In conjunction with the first aspect, or any of the possible implementations of the first aspect described above, in yet another possible implementation, the voltage regulation control circuit further includes a current zero-crossing detection module 106. The third input terminal f3 of the logic drive module 103 is connected to the source of the second switch M2 in the Boost converter circuit through the current zero-crossing detection module 106. The first output terminal h1 of the logic drive module 103 is connected to the gate of the first switch M1, and the second output terminal h2 of the logic drive module 103 is connected to the gate of the second switch M2. The current zero-crossing detection module 106 is used to output a zero-crossing signal ZERO. When the second current signal I_M2 flowing through the second switch M2 becomes zero, the zero-crossing signal ZERO changes abruptly from low level to high level. The logic drive module 103 is used to control the second switch M2 to turn off when the first switch M1 is in the on state. The logic drive module 103 is used to control the second switch M2 to turn on when the first switch M1 is in the off state and the voltage value of the zero-crossing signal ZERO is low level, and to control the second switch M2 to turn off when the first switch M1 is in the off state and the voltage value of the zero-crossing signal ZERO changes abruptly from low level to high level.

[0016] Considering that when the load connected to the Boost converter circuit changes from heavy load to light load, the output current of the Boost converter circuit gradually decreases, and the current flowing through the inductor L in the Boost converter circuit is no longer continuous, that is, it changes from continuous working mode to intermittent working mode. When the first switch M1 is turned off, the current flowing through the second switch M2 (which can be regarded as a synchronous rectifier) ​​is equal to zero for a period of time. The logic drive module in the above-mentioned voltage regulation control circuit can control the second switch M2 to turn off when the first switch M1 is turned off and the current flowing through the second switch M2 is zero, based on the current zero-crossing detection module, to prevent current backflow.

[0017] In conjunction with the first aspect, or any of the above possible implementations of the first aspect, in yet another possible implementation, the error amplification module 105 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a third amplifier EA, a fourth capacitor C4, a fifth capacitor C5, and a fourth voltage source S4; one end of the third resistor R3 is connected to the input terminal d of the error amplification module 105, one end of the fourth capacitor C4 is connected to the output terminal c of the error amplification module 105, the other end of the third resistor R3 is connected to the negative input terminal of the third amplifier EA and one end of the fourth resistor R4, the positive input terminal of the third amplifier EA is connected to the fourth voltage source S4, the other end of the fourth resistor R4 is connected to reference ground, the output terminal of the third amplifier EA is connected to one end of the fifth resistor R5 and one end of the fourth capacitor C4, the other end of the fifth resistor R5 is connected to one end of the fifth capacitor C5, the other end of the fifth capacitor C5 is connected to the other end of the fourth capacitor C4, and the other end of the fourth capacitor C4 is connected to reference ground.

[0018] In conjunction with the first aspect, or any of the possible implementations of the first aspect described above, in yet another possible implementation, the first control module 101 includes a first conduction time generation module 107, a second conduction time generation module 108, and a conduction time control module 109. The second conduction time generation module 108 includes a second capacitor C2. The first conduction time generation module 107 is used to output a fifth control signal TON_PRE, where the voltage value of the third voltage signal VSENSE rises to the first voltage value, and the voltage value of the fifth control signal TON_PRE changes abruptly from low to high. The second conduction time generation module 108 is used to output a sixth control signal TON_MIN, where the voltage value of the second voltage signal V_C2 rises to the second preset voltage value, and ... When the sixth control signal TON_MIN changes from high to low and the first control signal TOFF_ED changes from low to high, the second capacitor C2 begins to charge. The conduction time control module 109 is used to output the second control signal TON_ED. When the voltage value of the output voltage signal VOUT of the Boost converter circuit is less than the first preset voltage threshold and the voltage value of the fifth control signal TON_PRE changes from low to high, the second control signal TON_ED changes from low to high. When the voltage value of the output voltage signal VOUT of the Boost converter circuit is not less than the first preset voltage threshold and the sixth control signal TON_MIN changes from high to low, the second control signal TON_ED changes from low to high.

[0019] Before the output voltage of the Boost converter reaches the first preset voltage threshold, the moment when the second control signal TON_ED output by the aforementioned voltage regulation control circuit changes from low to high is determined by the fifth control signal TON_PRE. This ensures that the time required for the voltage value of the third voltage signal VSENSE to rise to the first voltage value is equal to the conduction time of the first switch M1, thus shortening the conduction time of the first switch M1 as the output voltage increases. After the output voltage of the Boost converter reaches the first preset voltage threshold, the moment when the second control signal TON_ED output by the aforementioned voltage regulation control circuit changes from low to high is determined by the sixth control signal TON_MIN. This ensures that the time required for the voltage value of the second voltage signal V_C2 to rise to the second preset voltage threshold is equal to the conduction time of the first switch M1, thus keeping the conduction time of the first switch M1 constant.

[0020] In conjunction with the first aspect, or any of the above possible implementations of the first aspect, in yet another possible implementation, the third input terminal of the first control module 101 is connected to the output terminal g of the second control module 102, the first input terminal j1 of the first conduction time generation module 107 is the first input terminal a1 of the first control module 101, the second input terminal j2 of the first conduction time generation module 107 is the second input terminal a2 of the first control module 101, the input terminal m of the second conduction time generation module 108 is the third input terminal of the first control module 101, the output terminal n of the conduction time control module 109 is the output terminal e of the first control module 101, the first input terminal p1 of the conduction time control module 109 is connected to the output terminal q1 of the first conduction time generation module 107, and the second input terminal p2 of the conduction time control module 109 is connected to the output terminal q2 of the second conduction time generation module 108.

[0021] In conjunction with the first aspect, or any of the possible implementations of the first aspect described above, in yet another possible implementation, the first on-time generation module 107 includes a fifth voltage source S5, an adder A, and a third comparator CMP3; the second on-time generation module 108 includes a second capacitor C2, a sixth voltage source S6, a current source S0, a fourth comparator CMP4, a twelfth switch M12, and a pulse sampler; the on-time control module 109 includes a second AND gate ND2 and a second inverter INV2; the positive input terminal of the third comparator CMP3 is connected to the output terminal of the adder A; the first input terminal of the adder A is connected to the first input terminal j1 of the first on-time generation module 107; the second input terminal of the adder A is connected to the fifth voltage source S5; the negative input terminal of the third comparator CMP3 is connected to the second input terminal j2 of the first on-time generation module 107; the output terminal of the third comparator CMP3 is connected to the output terminal q1 of the first on-time generation module 107; the input terminal of the pulse sampler is connected to the input terminal m of the second on-time generation module 108; and the pulse... The output of the impulse sampler is connected to the gate of the twelfth switch M12. The drain of the twelfth switch M12 is connected to the negative input of the fourth comparator CMP4, one end of the second capacitor C2, and the current source S0. The other end of the second capacitor C2 and the source of the twelfth switch M12 are both connected to the reference ground. The positive input of the fourth comparator CMP4 is connected to the sixth voltage source S6. The output of the fourth comparator CMP4 is connected to the output q2 of the second conduction time generation module 108. The first input of the second AND gate ND2 is connected to the conduction time... The first input terminal p1 of the time control module 109 and the input terminal of the second inverter INV2 are connected to the second input terminal p2 of the time control module 109. The output terminal of the second inverter INV2 is connected to the second input terminal of the second AND gate ND2. The output terminal of the second AND gate ND2 is connected to the output terminal n of the time control module 109. The pulse sampler is used to output the sampled voltage signal. When the first control signal TOFF_ED changes from low level to high level, the sampled voltage signal changes from low level to high level and then changes back to low level.

[0022] In conjunction with the first aspect, or any of the above possible implementations of the first aspect, in yet another possible implementation, the second control module 102 includes a first turn-off time generation module 110, a second turn-off time generation module 111, and a turn-off time control module 112. The first turn-off time generation module 110 includes a third capacitor C3, and the second turn-off time generation module 111 includes a first capacitor C1. The first turn-off time generation module 110 is used to charge the third capacitor C3 based on the voltage value of the output voltage signal VOUT of the Boost converter circuit and to output a third control signal TOFF_PRE. When the voltage value of the fourth voltage signal V_C3 rises to a fourth preset voltage threshold, the third control signal TOFF_PRE abruptly changes from a low level to a high level. The third preset threshold is the voltage value of the input voltage signal VIN of the Boost converter circuit. The second turn-off time generation module 111 is used to output the fourth control signal TOFF_DLY. When the voltage value of the first voltage signal V_C1 output by the first capacitor C1 drops to the third preset voltage threshold, the fourth control signal TOFF_DLY changes from low level to high level. The turn-off time control module 112 is used to output the first control signal TOFF_ED. When the voltage value of the output voltage signal VOUT of the Boost converter circuit is less than the first preset voltage threshold and the third control signal TOFF_PRE changes from low level to high level, the first control signal TOFF_ED changes from low level to high level. When the voltage value of the output voltage signal VOUT of the Boost converter circuit is not less than the first preset voltage threshold and the fourth control signal TOFF_DLY changes from low level to high level, the first control signal TOFF_ED changes from low level to high level.

[0023] Before the output voltage of the Boost converter reaches the first preset voltage threshold, the moment when the first control signal TOFF_ED output by the aforementioned voltage regulation control circuit changes from low to high is determined by the third control signal TOFF_PRE. This ensures that the time required for the voltage value of the fourth voltage signal V_C3 to rise to the fourth preset voltage threshold is the turn-off time of the first switch M1, thus achieving a constant turn-off time for the first switch M1. After the output voltage of the Boost converter reaches the first preset voltage threshold, the moment when the first control signal TOFF_ED output by the aforementioned voltage regulation control circuit changes from low to high is determined by the fourth control signal TOFF_DLY. This ensures that the time required for the voltage value of the first voltage signal V_C1 to drop to the third preset voltage threshold is the turn-off time of the first switch M1, thus extending the turn-off time of the first switch M1 as the output voltage increases.

[0024] In conjunction with the first aspect, or any of the possible implementations of the first aspect described above, in yet another possible implementation, the second input terminal of the second control module 102 is connected to the positive output terminal o1 of the Boost converter circuit, the third input terminal of the second control module 102 is connected to the positive input terminal i1 of the Boost converter circuit, the fourth input terminal of the second control module 102 is connected to the first output terminal h1 of the logic drive module 103, the first input terminal r1 of the second turn-off time generation module 111 is the first input terminal b1 of the second control module 102, the first input terminal u1 of the first turn-off time generation module 110 is the second input terminal of the second control module 102, and the second input terminal u2 of the first turn-off time generation module 110 is the second input terminal of the second control module 102. The third input terminal of block 102, the third input terminal u3 of the first shutdown time generation module 110 is the fourth input terminal of the second control module 102, the first output terminal x1 of the shutdown time control module 112 is the output terminal g of the second control module 102; the output terminal z of the first shutdown time generation module 110 is connected to the first input terminal w1 of the shutdown time control module 112, the output terminal y of the second shutdown time generation module 111 is connected to the second input terminal w2 of the shutdown time control module 112, the third input terminal w3 of the shutdown time control module 112 is connected to the third input terminal u3 of the first shutdown time generation module 110, and the second input terminal r2 of the second shutdown time generation module 111 is connected to the second output terminal x2 of the shutdown time control module 112.

[0025] In conjunction with the first aspect, or any of the above-described possible implementations of the first aspect, in yet another possible implementation, the second turn-off time generation module 111 further includes a first amplifier OP1, a first comparator CMP1, a third switch M3, a fourth switch M4, a fifth switch M5, a sixth switch M6, a seventh switch M7, an eighth switch M8, a first resistor R1, a first voltage source S1, and a second voltage source S2; the negative input terminal of the first amplifier OP1 is connected to the first input terminal R1 of the second turn-off time generation module 111, the positive input terminal of the first amplifier OP1 is connected to the drain of the third switch M3 and one end of the first resistor R1, the output terminal of the first amplifier OP1 is connected to the gate of the third switch M3 and the gate of the fourth switch M4, and the drain of the fourth switch M4 is connected to the drain of the fifth switch M5 and the fifth switch M8. The gate of transistor M5 is connected to the gate of the sixth switch transistor M6. The drain of the sixth switch transistor M6 is connected to the source of the seventh switch transistor M7. The drain of the seventh switch transistor M7 is connected to the drain of the eighth switch transistor M8. One end of the first capacitor C1 is connected to the positive input terminal of the first comparator CMP1. The gate of the seventh switch transistor M7 is connected to the gate of the eighth switch transistor M8 and the second input terminal r2 of the second turn-off time generation module 111. The negative input terminal of the first comparator CMP1 is connected to the first voltage source S1. The output terminal of the first comparator CMP1 is connected to the output terminal y of the second turn-off time generation module 111. The sources of the third switch transistor M3, the fourth switch transistor M4, and the eighth switch transistor M8 are connected to the first voltage source S1. The other end of the first resistor R1, the source of the fifth switch transistor M5, the source of the sixth switch transistor M6, and the other end of the first capacitor C1 are connected to the reference ground.

[0026] In conjunction with the first aspect, or any of the possible implementations of the first aspect described above, in yet another possible implementation, the shutdown time control module 112 includes a first flip-flop SR1, a second flip-flop SR2, a third flip-flop SR3, a first inverter INV1, and a first AND gate ND1; the set terminal of the first flip-flop SR1 is connected to the first input terminal w1 of the shutdown time control module 112, the input terminal of the first inverter INV1 is connected to the second input terminal w2 of the shutdown time control module 112, and the reset terminals of the first flip-flop SR1, the second flip-flop SR2, and the third flip-flop SR3 are connected to the first input terminal w2 of the shutdown time control module 112. The set terminal of flip-flop SR3 is connected to the third input terminal w3 of the turn-off time control module 112. The output terminal of the first flip-flop SR1 is connected to the first input terminal of the first AND gate ND1. The second input terminal of the first AND gate ND1 is connected to the output terminal of the first inverter INV1. The output terminal of the first AND gate ND1 is connected to the set terminal of the second flip-flop SR2 and the reset terminal of the third flip-flop SR3. The output terminal of the second flip-flop SR2 is connected to the first output terminal x1 of the turn-off time control module 112. The output terminal of the third flip-flop SR3 is connected to the second output terminal x2 of the turn-off time control module 112.

[0027] In conjunction with the first aspect, or any of the above possible implementations of the first aspect, in yet another possible implementation, the first turn-off time generation module 110 further includes a second amplifier OP2, a second comparator CMP2, a third voltage source S3, a ninth switch M9, a tenth switch M10, an eleventh switch M11, and a second resistor R2.

[0028] The negative input terminal of the second amplifier OP2 is connected to the first input terminal u1 of the first turn-off time generation module 110. The positive input terminal of the second amplifier OP2 is connected to the drain of the ninth switch M9 and one end of the second resistor R2. The output terminal of the second amplifier OP2 is connected to the gate of the ninth switch M9 and the gate of the tenth switch M10. The drain of the tenth switch M10 is connected to one end of the third capacitor C3, the drain of the eleventh switch M11, and the positive input terminal of the second comparator CMP2. The gate of the eleventh switch M11 is connected to the second input terminal u2 of the first turn-off time generation module 110. The negative input terminal of the second comparator CMP2 is connected to the third input terminal u3 of the first turn-off time generation module 110. The output terminal of the second comparator CMP2 is connected to the output terminal z of the first turn-off time generation module 110.

[0029] The source of the ninth switch M9 and the source of the tenth switch M10 are connected to the third voltage source S3. The other end of the second resistor R2, the other end of the third capacitor C3, and the source of the eleventh switch M11 are connected to the reference ground.

[0030] In conjunction with the first aspect, or any of the possible implementations of the first aspect described above, in yet another possible implementation, the logic driving module 103 includes a first OR gate OR1, a second OR gate OR2, a third OR gate OR3, a fourth OR gate OR4, a fifth OR gate OR5, a third inverter INV3, a first buffer BUF1, and a second buffer BUF2; the first input terminal of the first OR gate OR1 is connected to the second input terminal f2 of the logic driving module 103, the second input terminal of the first OR gate OR1 is connected to the output terminal of the second OR gate OR2, the output terminal of the first OR gate OR1 is connected to the input terminal of the third inverter INV3 and the first input terminal OR4 of the second OR gate OR2, and the second input terminal of the second OR gate OR2 is connected to the first input terminal of the logic driving module 103. Terminal f1, the output of the third inverter INV3 is connected to the input of the first buffer BUF1, the first input of the third OR gate OR3 and the first input of the fifth OR gate OR5, the output of the first buffer BUF1 is connected to the first output of the logic driver module 103 h1; the second input of the third OR gate OR3 is connected to the output of the fourth OR gate OR4, the output of the third OR gate OR3 is connected to the first input of the fourth OR gate OR4 and the second input of the fifth OR gate OR5, the output of the fifth OR gate OR5 is connected to the input of the second buffer BUF2, the output of the second buffer BUF2 is connected to the second output of the logic driver module 103 h2, and the second input of the fourth OR gate OR4 is connected to the third input of the logic driver module 103 f3.

[0031] In conjunction with the first aspect, or any of the above possible implementations of the first aspect, in yet another possible implementation, the Boost converter circuit includes a first switch M1, a second switch M2, an inductor L, a sixth capacitor C6, and a seventh capacitor C7; one end of the inductor L is connected to the positive input terminal i1 of the Boost converter circuit and one end of the sixth capacitor C6, and the other end of the inductor L is connected to the drain of the first switch M1 and the source of the second switch M2; the drain of the second switch M2 is connected to one end of the sixth capacitor C6 and the positive output terminal o1 of the Boost converter circuit; the negative input terminal i2 of the Boost converter circuit, the other end of the sixth capacitor C6, the source of the first switch M1, the other end of the seventh capacitor C7, and the negative output terminal o2 of the Boost converter circuit are all connected to reference ground.

[0032] It is understood that in the Boost converter circuit of this application embodiment, the first switch M1 can be regarded as a power switch and the second switch M2 can be regarded as a synchronous rectification switch.

[0033] Secondly, embodiments of this application provide a voltage regulation control device, which includes the voltage regulation control circuit described in the first aspect or any possible implementation of the first aspect.

[0034] Thirdly, embodiments of this application provide a Boost converter, which includes the voltage regulation control circuit and Boost conversion circuit described in the first aspect or any possible implementation of the first aspect.

[0035] The beneficial effects of the related devices provided in the second and third aspects of this application can be referred to the beneficial effects of the technical solution in the first aspect, and will not be repeated here. Attached Figure Description

[0036] The accompanying drawings used in the description of the embodiments of this application will be briefly introduced below.

[0037] Figure 1 This is a schematic diagram of a voltage regulation control circuit provided in an embodiment of this application;

[0038] Figure 2 This is a schematic diagram of the structure of an error amplification module provided in an embodiment of this application;

[0039] Figure 3 This is a schematic diagram of another voltage regulation control circuit provided in the embodiments of this application;

[0040] Figure 4 This is a schematic diagram of the structure of a first control module provided in an embodiment of this application;

[0041] Figure 5A This is a schematic diagram of the structure of a first shutdown time generation module provided in an embodiment of this application;

[0042] Figure 5B This is a schematic diagram of the structure of a second shutdown time generation module provided in an embodiment of this application;

[0043] Figure 5C This is a schematic diagram of the structure of a shutdown time control module provided in an embodiment of this application;

[0044] Figure 6 This is a schematic diagram of the structure of a logic driving module provided in an embodiment of this application;

[0045] Figure 7 This is a signal waveform diagram provided in an embodiment of this application. Detailed Implementation

[0046] For ease of understanding, some terms used in the embodiments of this application will be explained first.

[0047] Boost converter circuit: A type of switching DC-DC boost circuit. Common circuit structures include asynchronous and synchronous topologies. In the synchronous topology, in addition to the power switch, there is a synchronous rectifier switch, which replaces the diode in the asynchronous topology. When the power switch is on, the inductor in the Boost converter circuit stores energy. When the power switch is off, the inductor and the input terminal together supply power to the output terminal (i.e., release energy), so that the output voltage is greater than the input voltage.

[0048] The above explanations of technical terms can be applied to the embodiments described below.

[0049] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0050] Please see Figure 1 , Figure 1 This is a schematic diagram of a voltage regulator control circuit provided in an embodiment of this application. The voltage regulator control circuit 10 includes a first control module 101, a second control module 102, a logic drive module 103, a current sampling module 104, an error amplification module 105, and a current zero-crossing detection module 106. The first control module 101 includes a second capacitor C2, and the second control module 102 includes a first capacitor C1 and a third capacitor C3. The voltage regulator control circuit 10 can control the switching transistors in the Boost converter circuit 11 to turn on or off, thereby realizing the boost function of the Boost converter circuit 11.

[0051] The Boost converter circuit 11 can be a synchronous topology Boost converter circuit. For example, the Boost converter circuit 11 includes a first switch M1, a second switch M2, an inductor L, a sixth capacitor C6, and a seventh capacitor C7. One end of the inductor L is connected to the positive input terminal i1 of the Boost converter circuit 11 and one end of the sixth capacitor C6. The other end of the inductor L is connected to the drain of the first switch M1 and the source of the second switch M2. The drain of the second switch M2 is connected to one end of the sixth capacitor C6 and the positive output terminal o1 of the Boost converter circuit 11. The negative input terminal i2 of the Boost converter circuit 11, the other end of the sixth capacitor C6, the source of the first switch M1, the other end of the seventh capacitor C7, and the negative output terminal o2 of the Boost converter circuit 11 are all connected to reference ground. It can be understood that the first switch M1 can be considered a power switch, and the second switch M2 can be considered a synchronous rectification switch.

[0052] The first control module 101 outputs the second control signal TON_ED. When the output voltage signal VOUT of the Boost converter circuit 11 (i.e., the output voltage Vout) is less than the first preset voltage threshold and the voltage value of the third voltage signal VSENSE, converted from the first current signal I_M1 flowing through the first switch M1 in the Boost converter circuit 11, rises to the first voltage value, the voltage value of the second control signal TON_ED changes abruptly from low to high. When the output voltage Vout of the Boost converter circuit 11 is not less than the first preset voltage threshold and the voltage value of the second voltage signal V_C2 output by the second capacitor C2 rises to the second preset voltage threshold, the voltage value of the second control signal TON_ED changes abruptly from low to high. The logic drive module 103 controls the first switch M1 in the Boost converter circuit 11 to turn off when the voltage value of the second control signal TON_ED changes abruptly from low to high. The output voltage Vout of the Boost converter circuit 11 increases, the first voltage value decreases, and the charging speed of the second capacitor C2 remains unchanged.

[0053] Understandably, when the load changes from heavy to light, the output current Iout of the Boost converter circuit 11 gradually decreases, and the output voltage Vout is disturbed and gradually increases. Before the output voltage Vout reaches the first preset voltage threshold, the time it takes for the voltage value of the third voltage signal VSENSE to rise to the first voltage value is the turn-on time of the first switch M1; after the output voltage Vout reaches the first preset voltage threshold, the time it takes for the voltage value of the second voltage signal V_C2 to rise to the second preset voltage threshold is the turn-on time of the first switch M1. Since the first voltage value decreases as the output voltage Vout increases, the charging speed of the second capacitor C2 does not change with the output voltage Vout. As the output voltage Vout gradually increases, the turn-on time of the first switch M1 gradually shortens to a fixed time and then remains constant.

[0054] The second control module 102 is used to output the first control signal TOFF_ED. When the output voltage Vout of the Boost converter circuit 11 is less than the first preset voltage threshold and the voltage value of the fourth voltage signal V_C3 output by the third capacitor C3 rises to the fourth preset voltage threshold, the voltage value of the first control signal TOFF_ED changes abruptly from low level to high level; when the output voltage signal VOUT of the Boost converter circuit 11 is not less than the first preset voltage threshold and the voltage value of the first voltage signal V_C1 output by the first capacitor C1 drops to the third preset voltage threshold, the voltage value of the first control signal TOFF_ED changes abruptly from low level to high level. The logic drive module 103 is used to control the first switch M1 to turn on when the voltage value of the first control signal TOFF_ED changes abruptly from low level to high level. As the output voltage Vout of the Boost converter circuit 11 increases, the charging speed of the third capacitor C3 remains unchanged, while the discharging speed of the first capacitor C1 slows down.

[0055] Understandably, when the connected load changes from heavy to light, the output voltage Vout of the Boost converter circuit 11 will be disturbed and gradually increase. Before the output voltage Vout reaches the first preset voltage threshold, the time it takes for the voltage value of the fourth voltage signal V_C3 to rise to the fourth preset voltage threshold is the turn-off time of the first switch M1; after the output voltage Vout reaches the first preset voltage threshold, the time it takes for the voltage value of the first voltage signal V_C1 to drop to the third preset voltage threshold is the turn-off time of the first switch M1. Since the charging speed of the third capacitor C3 does not change with the output voltage Vout, the discharging speed of the first capacitor C1 slows down as the output voltage Vout increases. During the process of the output voltage Vout gradually increasing, the turn-off time of the first switch M1 remains constant for a period of time, and then gradually extends until the output voltage Vout remains stable.

[0056] Therefore, when the connected load changes from heavy load to light load, the output voltage Vout of the Boost converter circuit 11 in this embodiment is gradually disturbed and increases. Before the output voltage Vout reaches the first preset threshold, the Boost converter circuit 11 operates under the control of the voltage regulation control circuit 10 based on the constant off time (CFT) control mode. After the output voltage Vout reaches the first preset threshold, the Boost converter circuit 11 operates under the control of the voltage regulation control circuit 10 based on the constant on time (COT) control mode, continuously reducing the duty cycle of the first switching transistor M1, thereby reducing the output voltage ripple when the Boost converter circuit 11 is working.

[0057] It should be noted that, in this field, there are various circuit structures for controlling the charging or discharging speed of a capacitor based on voltage changes. In the embodiments of this application... Figure 1The connection relationship between the modules in the voltage regulation control circuit 10 shown is only an example. Any equivalent modifications or substitutions made by those skilled in the art based on the above description of the functionality of each module should be covered within the protection scope of this application.

[0058] The following text is based on Figure 1 The working principle of the voltage regulation control circuit 10 will be further explained.

[0059] like Figure 1 As shown, the first input terminal a1 of the first control module 101 is connected to the drain of the first switching transistor M1 in the Boost converter circuit 11 through the current sampling module 104. The second input terminal a2 of the first control module 101 and the first input terminal b1 of the second control module 102 are connected to the output terminal c of the error amplifier module 105. The input terminal d of the error amplifier module 105 is connected to the positive output terminal o1 of the Boost converter circuit 11. The output terminal e of the first control module 101 is connected to the first input terminal f1 of the logic drive module 103. The output terminal g of the second control module 102 is connected to the second input terminal f2 of the logic drive module 103.

[0060] It should be noted that the current sampling module 104 is used to convert the first current signal I_M1 into the third voltage signal VSENSE. After the first switch M1 starts conducting, the current value of the first current signal I_M1 gradually increases, and the voltage value of the third voltage signal VSENSE gradually increases. The error amplification module 105 is used to output the error signal VEA. As the output voltage Vout of the Boost converter circuit 11 increases, the voltage value of the output error signal VEA decreases. The magnitude of the decrease in the voltage value of the output error signal VEA is greater than the magnitude of the increase in the output voltage Vout of the Boost converter circuit 11.

[0061] Considering that the output voltage Vout of the Boost converter circuit 11 increases only slightly due to disturbances when the load changes from heavy to light, the error amplification module 105 can amplify the extent to which the output voltage Vout increases due to disturbances. This allows the voltage regulation control circuit 10 to adjust the duty cycle of the first switching transistor M1 according to load changes, thereby reducing the output voltage ripple of the Boost converter circuit 11 during operation. For ease of understanding, the circuit structure of the error amplification module 105 is illustrated below with an example. Please refer to [link to example]. Figure 2 , Figure 2 This is a schematic diagram of the structure of an error amplification module provided in an embodiment of this application.

[0062] like Figure 2As shown, the error amplification module 105 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a third amplifier EA, a fourth capacitor C4, a fifth capacitor C5, and a fourth voltage source S4. Specifically, one end of the third resistor R3 is connected to the input terminal d of the error amplification module 105, one end of the fourth capacitor C4 is connected to the output terminal c of the error amplification module 105, the other end of the third resistor R3 is connected to the negative input terminal of the third amplifier EA and one end of the fourth resistor R4, the positive input terminal of the third amplifier EA is connected to the fourth voltage source S4, the other end of the fourth resistor R4 is connected to reference ground, the output terminal of the third amplifier EA is connected to one end of the fifth resistor R5 and one end of the fourth capacitor C4, the other end of the fifth resistor R5 is connected to one end of the fifth capacitor C5, the other end of the fifth capacitor C5 is connected to the other end of the fourth capacitor C4, and the other end of the fourth capacitor C4 is connected to reference ground.

[0063] The second amplifier EA compares the first reference voltage signal VREF1 output from the fourth voltage source S4 with the voltage signal across the fourth resistor R4. The comparison result output by the third amplifier EA is compensated by a loop compensation circuit composed of the fifth resistor R5, the fourth capacitor C4, and the fifth capacitor C5 to obtain the error signal VEA. It can be understood that the voltage signal across the fourth resistor R4 can be considered as a voltage divider signal VFB of the output voltage Vout of the Boost converter circuit 11. The voltage value of the error signal VEA is the amplified value of the difference between the voltage value of the first reference voltage signal VREF1 and the voltage value of the voltage divider signal VFB. When the output voltage Vout increases, the voltage across the fourth resistor R4 (i.e., the voltage value of the voltage divider signal VFB) will increase; since the voltage value of the first reference voltage signal VREF1 remains unchanged, the voltage value of the error signal VEA will decrease.

[0064] Furthermore, Figure 1 In the voltage regulation control circuit 10 shown, the first output terminal h1 of the logic drive module 103 is connected to the gate of the first switch M1, the second output terminal h2 of the logic drive module 103 is connected to the gate of the second switch M2, and the third input terminal f3 of the logic drive module 103 is connected to the source of the second switch M2 in the Boost converter circuit 11 through the current zero-crossing detection module 106. It should be noted that the current zero-crossing detection module 106 outputs a zero-crossing signal ZERO. When the second current signal I_M2 flowing through the second switch M2 becomes zero, the zero-crossing signal ZERO changes abruptly from low to high. The logic drive module 103 is used to control the second switch M2 to turn off when the first switch M1 is in the on state. The logic drive module 103 is also used to control the second switch M2 to turn on when the first switch M1 is in the off state and the voltage value of the zero-crossing signal ZERO is low, and to control the second switch M2 to turn off when the first switch M1 is in the off state and the voltage value of the zero-crossing signal ZERO changes abruptly from low to high.

[0065] Understandably, the logic drive module 103 receives the second control signal TON_ED output by the first control module 101, the first control signal TOFF_ED output by the second control module 102, and the zero-crossing signal ZERO output by the current zero-crossing detection module 106. It also outputs the seventh control signal M1_ON and the eighth control signal M2_ON to control the turn-on or turn-off of the first switch M1 and the second switch M2, respectively. Considering that when the connected load changes from heavy load to light load, the output current Iout of the Boost converter circuit 11 gradually decreases, and the current flowing through the inductor L is no longer continuous, i.e., it changes from continuous operation mode to intermittent operation mode, the current flowing through the second switch M2 (which can be considered a synchronous rectifier) ​​is equal to zero for a period of time when the first switch M1 is turned off. The logic drive module 103 can control the second switch M2 to turn off based on the current zero-crossing detection module 106 when the first switch M1 is turned off and the current flowing through the second switch M2 is zero, to prevent current backflow.

[0066] In one alternative embodiment, Figure 1 The third input terminal of the first control module 101 is connected to the output terminal g of the second control module 102. The second input terminal of the second control module 102 is connected to the positive output terminal o1 of the Boost converter circuit 11. The third input terminal of the second control module 102 is connected to the positive input terminal i1 of the Boost converter circuit 11. The fourth input terminal of the second control module 102 is connected to the first output terminal h1 of the logic drive module 103. The first control module 101 includes a first on-time generation module 107, a second on-time generation module 108, and an on-time control module 109. The second on-time generation module 108 includes a second capacitor C2. The second control module 102 includes a first off-time generation module 110, a second off-time generation module 111, and an off-time control module 112. The first off-time generation module 110 includes a third capacitor C3, and the second off-time generation module 111 includes a first capacitor C1. For better understanding, please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a schematic diagram of another voltage regulation control circuit provided in the embodiments of this application.

[0067] Figure 3 The first input terminal p1 of the conduction time control module 109 in the first control module 101 shown is connected to the output terminal q1 of the first conduction time generation module 107, and the second input terminal p2 of the conduction time control module 109 is connected to the output terminal q2 of the second conduction time generation module 108. Combined with... Figure 1 and Figure 3It can be seen that the first input terminal j1 of the first conduction time generation module 107 is the first input terminal a1 of the first control module 101, the second input terminal j2 of the first conduction time generation module 107 is the second input terminal a2 of the first control module 101, the input terminal m of the second conduction time generation module 108 is the third input terminal of the first control module 101, and the output terminal n of the conduction time control module 109 is the output terminal e of the first control module 101.

[0068] Specifically, the first conduction time generation module 107 is used to output the fifth control signal TON_PRE. When the voltage value of the third voltage signal VSENSE rises to the first voltage value, the voltage value of the fifth control signal TON_PRE changes abruptly from low to high. The second conduction time generation module 108 is used to output the sixth control signal TON_MIN. When the voltage value of the second voltage signal V_C2 rises to the second preset voltage value, the sixth control signal TON_MIN changes abruptly from high to low. When the first control signal TOFF_ED changes from low to high, the second capacitor C2 begins to charge. Electrical; the conduction time control module 109 is used to output the second control signal TON_ED. When the voltage value of the output voltage signal VOUT of the Boost converter circuit 11 is less than the first preset voltage threshold and the voltage value of the fifth control signal TON_PRE changes from low level to high level, the second control signal TON_ED changes from low level to high level. When the output voltage Vout of the Boost converter circuit 11 is not less than the first preset voltage threshold and the sixth control signal TON_MIN changes from high level to low level, the second control signal TON_ED changes from low level to high level.

[0069] Understandably, when the load changes from heavy to light, before the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold, the moment when the voltage value of the second control signal TON_ED output by the turn-on time control module 109 changes from low to high is determined by the fifth control signal TON_PRE. This means that the time it takes for the voltage value of the third voltage signal VSENSE to rise to the first voltage value is the turn-on time of the first switch M1, thus shortening the turn-on time of the first switch M1 as the output voltage Vout increases. After the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold, the time it takes for the voltage value of the second control signal TON_ED output by the turn-on time control module 109 to change from low to high is determined by the sixth control signal TON_MIN. This means that the time it takes for the voltage value of the second voltage signal V_C2 to rise to the second preset voltage threshold is the turn-on time of the first switch M1, thus keeping the turn-on time of the first switch M1 constant.

[0070] For ease of understanding, the following text will discuss... Figure 3The circuit structure of each module in the first control module 101 is further illustrated with examples. Please refer to [link / reference]. Figure 4 , Figure 4 This is a schematic diagram of the structure of a first control module provided in an embodiment of this application.

[0071] Figure 4 The first on-time generation module 107 in the first control module 101 shown includes a fifth voltage source S5 and a third comparator CMP3. The positive input terminal of the third comparator CMP3 is connected to the output terminal of adder A. The first input terminal of adder A is connected to the first input terminal j1 of the first on-time generation module 107. The second input terminal of adder A is connected to the fifth voltage source S5. The negative input terminal of the third comparator CMP3 is connected to the second input terminal j2 of the first on-time generation module 107. The output terminal of the third comparator CMP3 is connected to the output terminal q1 of the first on-time generation module 107.

[0072] The positive input signal of the third comparator CMP3 is a triangular wave signal RIPPLE, which is formed by superimposing the third voltage signal VSENSE and the fifth voltage signal VDC output from the fifth voltage source S5. The third comparator CMP3 is used to compare the voltage value of the triangular wave signal RIPPLE with the voltage value of the error signal VEA, and outputs the fifth control signal TON_PRE.

[0073] It is understandable that the voltage value of the error signal VEA is related to the output voltage Vout of the Boost converter circuit 11. In practical applications, when the output voltage Vout equals the first preset voltage threshold, the voltage value of the error signal VEA is equal to the voltage value of the fifth voltage signal VDC.

[0074] Before the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold, the voltage value of the error signal VEA is greater than the voltage value of the fifth voltage signal VDC. After the first switch M1 starts to conduct, the current flowing through the first switch M1 gradually increases, and the voltage value of the third voltage signal VSENSE gradually increases until the voltage value of the third voltage signal VSENSE rises to the first voltage value. At this point, the voltage value of the fifth control signal TON_PRE changes abruptly from low to high. Therefore, it can be seen that... Figure 3The first voltage value in the described embodiment can be understood as the difference between the voltage value of the error signal VEA and the voltage value of the fifth voltage signal VDC. When the first switch M1 switches from the on state to the off state, the current flowing through the first switch M1 decreases rapidly, and the voltage value of the third voltage signal VSENSE decreases rapidly, i.e., it is less than the first voltage value. At this time, the voltage value of the fifth control signal TON_PRE changes abruptly from high level to low level, and the voltage value of the second control signal TON_ED will not change abruptly again until the first switch M1 is turned on again and the voltage value of the third voltage signal VSENSE rises to the first voltage value.

[0075] After the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold, the voltage value of the error signal VEA is always less than the voltage value of the fifth voltage signal VDC. Regardless of whether the first switch M1 is turned on, the fifth control signal TON_PRE is always at a high level.

[0076] Figure 4 The second on-time generation module 108 in the first control module 101 shown includes a second capacitor C2, a sixth voltage source S6, a current source S0, a fourth comparator CMP4, a twelfth switch M12, and a pulse sampler. The input terminal of the pulse sampler is connected to the input terminal m of the second on-time generation module 108. The output terminal of the pulse sampler is connected to the gate of the twelfth switch M12. The drain of the twelfth switch M12 is connected to the negative input terminal of the fourth comparator CMP4, one end of the second capacitor C2, and the current source S0. The other end of the second capacitor C2 and the source of the twelfth switch M12 are both connected to reference ground. The positive input terminal of the fourth comparator CMP4 is connected to the sixth voltage source S6, and the output terminal of the fourth comparator CMP4 is connected to the output terminal q2 of the second on-time generation module 108.

[0077] It should be noted that the pulse sampler is used to output a sampled voltage signal. When the first control signal TOFF_ED changes from low to high (the first switch M3 starts to conduct), the sampled voltage signal changes from low to high and then back to low. The sampled voltage signal can be understood as a short pulse signal.

[0078] The fourth comparator CMP4 compares the second reference voltage signal VREF2 from the sixth voltage source S6 with the second voltage signal V_C2 output from the second capacitor C2, and outputs the sixth control signal TON_MIN. After the first switch M1 turns on, the twelfth switch M12 turns on and then quickly turns off. When the twelfth switch M12 turns on, the second capacitor C2 is in a discharging state, and the second voltage signal V_C2 decreases rapidly, i.e., it is always less than the voltage value of the second reference voltage signal VREF2. The sixth control signal TON_MIN changes from low to high. When the twelfth switch M12 turns off, the current source S0 charges the second capacitor C2. After the second voltage signal V_C2 gradually rises to the voltage value of the second reference voltage signal VREF2, the sixth control signal TON_MIN changes from high to low. Therefore, it can be seen that... Figure 3 The second preset voltage threshold in the described embodiment can be the voltage value of the second reference voltage signal VREF2. When the first switch M1 switches from the on state to the off state, the first control signal TOFF_ED is always low, the sampled voltage signal is always low, the twelfth switch M12 is always in the off state, and the sixth control signal TON_MIN is always low until the first switch M1 is turned on again, at which point the sixth control signal TON_MIN will change abruptly again.

[0079] Figure 4 The on-time control module 109 in the first control module 101 shown includes a second AND gate ND2 and a second inverter INV2. The first input of the second AND gate ND2 is connected to the first input p1 of the on-time control module 109, the input of the second inverter INV2 is connected to the second input p2 of the on-time control module 109, the output of the second inverter INV2 is connected to the second input of the second AND gate ND2, and the output of the second AND gate ND2 is connected to the output n of the on-time control module 109. The second AND gate ND2 is used to output the second control signal TON_ED based on the inverted signal of the sixth control signal TON_MIN and the fifth control signal TON_PRE.

[0080] Based on the working principles of the first conduction time generation module 107 and the second conduction time generation module 108, before the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold (i.e., before the voltage value of the error signal VEA reaches the voltage value of the fifth voltage signal VDC), when the first switch M1 starts to conduct, the voltage value of the fifth control signal TON_PRE remains low for a period of time before suddenly changing to high, while the sixth control signal TON_MIN quickly changes from low to high and remains high for a period of time before suddenly changing to low. In other words, when the voltage value of the sixth control signal TON_MIN is high, the voltage value of the fifth control signal TON_PRE has not yet reached a high level; when the voltage value of the fifth control signal TON_PRE reaches a high level, the voltage value of the sixth control signal TON_MIN is already low. As can be seen from the working principle of the second AND gate ND2 in the conduction time control module 109, the second control signal TON_ED will only change from low to high when the voltage value of the fifth control signal TON_PRE changes from low to high, so that the logic drive module 103 can drive the first switch M1 to turn off. When the first switch M1 switches from the on state to the off state, the voltage value of the fifth control signal TON_PRE changes from high to low, while the sixth control signal TON_MIN remains low, and the second control signal TON_ED changes from high to low.

[0081] Therefore, before the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold, Figure 3 In the described embodiment, the moment when the voltage value of the second control signal TON_ED changes from low to high (i.e., the turn-off moment of the first switch M1) is determined by the fifth control signal TON_PRE. This makes the time taken for the voltage value of the third voltage signal VSENSE to rise to the first voltage value (i.e., the difference between the voltage value of the error signal VEA and the voltage value of the fifth voltage signal VDC) the turn-on time of the first switch M1, thus realizing that the turn-on time of the first switch M1 shortens as the output voltage Vout increases.

[0082] Furthermore, after the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold (i.e., after the voltage value of the error signal VEA reaches the voltage value of the fifth voltage signal VDC), when the first switch M1 starts to conduct, the voltage value of the fifth control signal TON_PRE remains at a high level, and the sixth control signal TON_MIN still rapidly changes from a low level to a high level, remains at a high level for a period of time, and then changes to a low level. As can be seen from the working principle of the second AND gate ND2, the voltage value of the second control signal TON_ED will change from a low level to a high level only when the sixth control signal TON_MIN changes from a high level to a low level, so that the logic drive module 103 can drive the first switch M1 to turn off. When the first switch M1 switches from the on state to the off state, the voltage value of the fifth control signal TON_PRE remains high, while the sixth control signal TON_MIN remains low, and the second control signal TON_ED remains high. The voltage value of the second control signal TON_ED will not change from high to low until the first switch M1 is turned on again.

[0083] Therefore, after the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold, Figure 3 In the described embodiment, the moment when the voltage value of the second control signal TON_ED abruptly changes from low to high (i.e., the turn-off moment of the first switch M1) is determined by the sixth control signal TON_MIN. This ensures that the time required for the voltage value of the second voltage signal V_C2 to rise to the second preset voltage threshold is the turn-on time of the first switch M1, thus achieving a constant turn-on time for the first switch M1. Optionally, the time required for the voltage value of the second voltage signal V_C2 to rise to the second preset voltage threshold (i.e., the voltage value of the second reference voltage signal VREF2) can be the minimum turn-on time of the first switch M1.

[0084] Furthermore, Figure 3In the second control module 102 shown, the first input terminal r1 of the second turn-off time generation module 111 is the first input terminal b1 of the second control module 102; the first input terminal u1 of the first turn-off time generation module 110 is the second input terminal of the second control module 102; the second input terminal u2 of the first turn-off time generation module 110 is the third input terminal of the second control module 102; the third input terminal u3 of the first turn-off time generation module 110 is the fourth input terminal of the second control module 102; and the first output terminal of the turn-off time control module 112 is... x1 is the output terminal g of the second control module 102; the output terminal z of the first shutdown time generation module 110 is connected to the first input terminal w1 of the shutdown time control module 112; the output terminal y of the second shutdown time generation module 111 is connected to the second input terminal w2 of the shutdown time control module 112; the third input terminal w3 of the shutdown time control module 112 is connected to the third input terminal u3 of the first shutdown time generation module 110; and the second input terminal r2 of the second shutdown time generation module 111 is connected to the second output terminal x2 of the shutdown time control module 112.

[0085] Specifically, the first turn-off time generation module 110 is used to charge the third capacitor C3 based on the voltage value of the output voltage signal VOUT of the Boost converter circuit 11 and to output the third control signal TOFF_PRE. When the voltage value of the fourth voltage signal V_C3 rises to the fourth preset voltage threshold, the third control signal TOFF_PRE changes from low level to high level. The third preset threshold is the voltage value of the input voltage signal VIN of the Boost converter circuit 11. The second turn-off time generation module 111 is used to output the fourth control signal TOFF_DLY. When the voltage value of the first voltage signal V_C1 output by the first capacitor C1 drops to the third preset voltage threshold, the third control signal TOFF_DLY changes from low level to high level. The fourth control signal TOFF_DLY changes from low to high. The off-time control module 112 outputs the first control signal TOFF_ED. When the voltage value of the output voltage signal VOUT of the Boost converter circuit 11 is less than the first preset voltage threshold and the third control signal TOFF_PRE changes from low to high, the first control signal TOFF_ED changes from low to high. When the voltage value of the output voltage signal VOUT of the Boost converter circuit 11 is not less than the first preset voltage threshold and the fourth control signal TOFF_DLY changes from low to high, the first control signal TOFF_ED changes from low to high.

[0086] Understandably, when the load changes from heavy to light, before the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold, the moment when the first control signal TOFF_ED output by the turn-off time control module 112 changes from low to high is determined by the third control signal TOFF_PRE. This means that the time it takes for the voltage value of the fourth voltage signal V_C3 to rise to the fourth preset voltage threshold is the turn-off time of the first switch M1, thus ensuring a constant turn-off time for the first switch M1. After the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold, the moment when the first control signal TOFF_ED output by the turn-off time control module 112 changes from low to high is determined by the fourth control signal TOFF_DLY. This means that the time it takes for the voltage value of the first voltage signal V_C1 to drop to the third preset voltage threshold is the turn-off time of the first switch M1, thus extending the turn-off time of the first switch M1 as the output voltage increases.

[0087] For ease of understanding, the following text will discuss... Figure 3 The circuit structure of the first shutdown time generation module 110 in the second control module 102 shown is further illustrated with an example. Please refer to [link / reference]. Figure 5A , Figure 5A This is a schematic diagram of the structure of a first shutdown time generation module provided in an embodiment of this application.

[0088] like Figure 5A As shown, the first turn-off time generation module 110 includes a third capacitor C3, a second amplifier OP2, a second comparator CMP2, a third voltage source S3, a ninth switch M9, a tenth switch M10, an eleventh switch M11, and a second resistor R2. Combined with... Figure 3 and Figure 5A It can be seen that the negative input terminal of the second amplifier OP2 is connected to the first input terminal u1 of the first turn-off time generation module 110, the positive input terminal of the second amplifier OP2 is connected to the drain of the ninth switch M9 and one end of the second resistor R2, the output terminal of the second amplifier OP2 is connected to the gate of the ninth switch M9 and the gate of the tenth switch M10, the drain of the tenth switch M10 is connected to one end of the third capacitor C3, the drain of the eleventh switch M11 and the positive input terminal of the second comparator CMP2, the gate of the eleventh switch M11 is connected to the second input terminal u2 of the first turn-off time generation module 110, the negative input terminal of the second comparator CMP2 is connected to the third input terminal u3 of the first turn-off time generation module 110, the output terminal of the second comparator CMP2 is connected to the output terminal z of the first turn-off time generation module 110, the source of the ninth switch M9 and the source of the tenth switch M10 are connected to the third voltage source S3, and the other end of the second resistor R2, the other end of the third capacitor C3 and the source of the eleventh switch M11 are connected to the reference ground.

[0089] Understandably, the second comparator CMP2 in the first turn-off time generation module 110 is used to compare the fourth voltage signal V_C3 output by the second capacitor C2 with the input voltage signal VIN of the Boost converter circuit 11, and output the third control signal TOFF_PRE.

[0090] When the seventh control signal M1_ON output by the logic driver module 103 is low, the first switch M1 is in the off state. The third current signal I_M10 flowing through the tenth switch M10 charges the third capacitor C3. The fourth voltage signal V_C3 output by the third capacitor C3 has a voltage value V. c3 As the voltage gradually rises to reach the input voltage Vin, the voltage value of the third control signal TOFF_PRE abruptly changes from low to high. When the seventh control signal M1_ON is high, the first switch M1 switches from the off state to the on state, the third capacitor C3 is in the discharging state, and the voltage value of the fourth voltage signal V_C3 is V. c3 The voltage drops rapidly, remaining consistently below the input voltage Vin. At this point, the voltage value of the third control signal TOFF_PRE abruptly changes from high to low, and remains low until the first switch M1 is turned off again and the voltage value of the fourth voltage signal V_C3 drops to V. c3 The voltage value of the third control signal TOFF_PRE will only change abruptly again when the input voltage Vin is reached. Therefore, Figure 3 The fourth preset voltage threshold in the described embodiment can be the input voltage Vin of the Boost converter circuit 11.

[0091] Specifically, the second amplifier OP2, the ninth switch M9, and the second resistor R2 are connected in a negative feedback configuration. The ninth switch M9 and the tenth switch M10 form a current mirror, meaning the tenth switch M10 mirrors the current flowing through the ninth switch M9. Since the input voltage at the negative input terminal of the second amplifier OP2 is the input voltage Vout of the Boost converter circuit 11, the current value I of the third current signal I_M10 flowing through the tenth switch M10 is... M10 The input voltage Vout and the resistance value R2 of the second resistor satisfy formula (1):

[0092] I M10 =Vout / R2 (1)

[0093] When the third current signal I_M10 charges the third capacitor C3, the voltage value V of the fourth voltage signal V_C3... c3 The charging time t of the third capacitor C3 c3 The relationship between the capacitance value C3 of the third capacitor C3 and the capacitance value C3 satisfies the following formula (2):

[0094] IM10 *t c3 =C3*V c3 (2)

[0095] Combining formulas (1) and (2), we can see that the voltage value C of the fourth voltage signal V_C3 is... c3 The first time t1 required to reach the input voltage Vin is represented by the following formula (3):

[0096]

[0097] Based on the above, in practical applications, when the load connected to the Boost converter circuit 11 changes from heavy load to light load, the output voltage Vout of the Boost converter circuit 11 is less affected by the disturbance and the input voltage Vin remains unchanged. Therefore, according to formula (3), no matter how the load connected to the Boost converter circuit 11 changes, the first time t1 can be regarded as constant, that is to say, the charging speed of the third capacitor C3 remains constant.

[0098] For ease of understanding, the following text will discuss... Figure 3 The circuit structures of the second turn-off time generation module 111 and the turn-off time control module 112 in the second control module 102 shown are further illustrated with examples. Please refer to [link to example]. Figure 5B , Figure 5B This is a schematic diagram of the structure of a second shutdown time generation module provided in an embodiment of this application.

[0099] like Figure 5B As shown, the second turn-off time generation module 111 includes a first capacitor C1, a first amplifier OP1, a first comparator CMP1, a third switch M3, a fourth switch M4, a fifth switch M5, a sixth switch M6, a seventh switch M7, an eighth switch M8, a first resistor R1, a first voltage source S1, and a second voltage source S2. Combined with... Figure 3 and Figure 5BIt can be seen that the negative input terminal of the first amplifier OP1 is connected to the first input terminal r1 of the second turn-off time generation module 111; the positive input terminal of the first amplifier OP1 is connected to the drain of the third switch M3 and one end of the first resistor R1; the output terminal of the first amplifier OP1 is connected to the gate of the third switch M3 and the gate of the fourth switch M4; the drain of the fourth switch M4 is connected to the drain of the fifth switch M5, the gate of the fifth switch M5, and the gate of the sixth switch M6; the drain of the sixth switch M6 is connected to the source of the seventh switch M7; the drain of the seventh switch M7 is connected to the drain of the eighth switch M8; and the first capacitor C1... The positive input terminal of the first comparator CMP1 is connected to the positive input terminal of the first comparator CMP1. The gate of the seventh switch M7 is connected to the gate of the eighth switch M8 and the second input terminal r2 of the second turn-off time generation module 111. The negative input terminal of the first comparator CMP1 is connected to the first voltage source S1. The output terminal of the first comparator CMP1 is connected to the output terminal y of the second turn-off time generation module 111. The sources of the third switch M3, the fourth switch M4, and the eighth switch M8 are connected to the first voltage source S1. The other end of the first resistor R1, the source of the fifth switch M5, the source of the sixth switch M6, and the other end of the first capacitor C1 are connected to the reference ground. The first comparator CMP1 is used to compare the first voltage signal V_C1 output by the first capacitor C1 with the third reference voltage signal VREF3 output by the second voltage source S2, and outputs the fourth control signal TOFF_DLY.

[0100] Please see Figure 5C , Figure 5C This is a schematic diagram of the structure of a shutdown time control module provided in an embodiment of this application.

[0101] like Figure 5C As shown, the turn-off time control module 112 includes a first flip-flop SR1, a second flip-flop SR2, a third flip-flop SR3, a first inverter INV1, and a first AND gate ND1. Combined with... Figure 3 and Figure 5CIt can be seen that the set terminal of the first flip-flop SR1 is connected to the first input terminal w1 of the turn-off time control module 112, the input terminal of the first inverter INV1 is connected to the second input terminal w2 of the turn-off time control module 112, the reset terminal of the first flip-flop SR1, the reset terminal of the second flip-flop SR2, and the set terminal of the third flip-flop SR3 are connected to the third input terminal w3 of the turn-off time control module 112, the output terminal of the first flip-flop SR1 is connected to the first input terminal of the first AND gate ND1, the second input terminal of the first AND gate ND1 is connected to the output terminal of the first inverter INV1, the output terminal of the first AND gate ND1 is connected to the set terminal of the second flip-flop SR2 and the reset terminal of the third flip-flop SR3, the output terminal of the second flip-flop SR2 is connected to the first output terminal x1 of the turn-off time control module 112, and the output terminal of the third flip-flop SR3 is connected to the second output terminal x2 of the turn-off time control module 112.

[0102] Combination Figure 3 , Figure 5B and Figure 5C It is known that the second turn-off time generation module 111 receives the sixth voltage signal INA output by the turn-off time control module 112. Based on the error signal VEA output by the error amplification module 105 and the sixth voltage signal INA, the second turn-off time generation module 111 outputs the fourth control signal TOFF_DLY. The turn-off time control module 112 outputs the first control signal TOFF_ED and the sixth voltage signal INA based on the third control signal TOFF_PRE, the fourth control signal TOFF_DLY, and the seventh control signal M1_ON output by the logic drive module 103.

[0103] When the seventh control signal M1_ON changes from low to high, the first switch M1 starts to conduct. Figure 5C As we know from the working principle of the third flip-flop SR3, the sixth voltage signal INA is always at a high level. Therefore, Figure 5B In the second turn-off time generation module 111 shown, the eighth switch M8 is turned off and the seventh switch M7 is turned on. The first capacitor C1 begins to discharge. The current value of the fourth current signal I_M6 flowing through the sixth switch M6 can be regarded as the pull-down current. When the voltage value of the first voltage signal V_C1 output by the first capacitor C1 drops to the voltage value of the third reference voltage signal VREF3, the fourth control signal TOFF_DLY changes abruptly from high level to low level. This can be understood as... Figure 3 In the described embodiment, the third preset voltage threshold can be the voltage value of the third reference voltage signal VREF3.

[0104] Specifically, the first amplifier OP1, the third switch M3, and the first resistor R1 are connected in a negative feedback configuration. The third switch M3 and the fourth switch M4 form a current mirror, and the fifth switch M5 and the sixth switch M6 form another current mirror, meaning the sixth switch M6 mirrors the current flowing through the third switch M3. Since the input voltage at the negative input terminal of the second amplifier OP2 is the voltage value V of the error signal VEA... ea Then the current value I of the fourth current signal I_M6 flowing through the sixth switch transistor M6 M6 The voltage value Vea of ​​the error signal VEA and the resistance value R1 of the first resistor R1 satisfy formula (4):

[0105] I M6 =V ea / R1 (4)

[0106] When the first capacitor C1 discharges, the voltage value V of the first voltage signal V_C1 is... c1 The discharge time t of the first capacitor C1 c1 The relationship between the capacitance value C1 of the first capacitor C1 and the capacitance value C1 is satisfied by the following formula (5):

[0107] I M6 *t c1 =C1*V c1 (5)

[0108] Combining formulas (4) and (5), we can see that the voltage value V of the first voltage signal V_C1 is... c1 The voltage value V dropped to the third reference voltage signal VREF3 s2 The second time t2 used is represented by the following formula (6):

[0109]

[0110] As can be seen from formula (6), the discharge rate of the first capacitor C1 is related to the error signal VEA, and the voltage value V of the error signal VEA is... ea The smaller the value, the larger the second time t2.

[0111] based on Figure 3 As can be seen from the working principle of the first control module 101 in the described embodiment, the conduction time t of the first switching transistor M1 on With the voltage value V of the error signal VEA ea It decreases as it decreases. Understandably, in practical applications, this can be achieved by setting... Figure 5B The voltage value V of the third reference voltage signal VREF3 in the second turn-off time generation module 111 shown. S2 This ensures that the second time t2 is always greater than the conduction time t of the first switch M1. onThat is, during the period when the first switch M1 is in the on state, the voltage value of the fourth control signal TOFF_DLY is always high. Based on the working principles of the first turn-off time generation module 110 and the second turn-off time generation module 111, when the seventh control signal M1_ON is high, the first switch M1 is in the on state, the voltage value of the third control signal TOFF_PRE is always low, and the voltage value of the fourth control signal TOFF_DLY is always high. The first control signal TOFF_ED output by the turn-off time control module 112 is always low. When the seventh control signal M1_ON abruptly changes from high to low, the first switch M1 begins to turn off. The third control signal TOFF_PRE remains low for a period of time (equal to the first time t1) before abruptly changing to high. The fourth control signal TOFF_DLY remains high for a period of time (equal to the second time t2 and the on-time t). on The difference between them suddenly becomes low.

[0112] The first time interval t1 is a fixed value, and the second time interval t2 varies with the voltage value V of the error signal VEA. ea Decrease and increase are understandable in practical applications. Figure 3 When the output voltage Vout of the Boost converter circuit 11 in the described embodiment is equal to the first preset voltage threshold, the second time t2 and the conduction time t on The difference between them is equal to the first time t1.

[0113] Therefore, before the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold, the voltage value Vea of ​​the error signal VEA is relatively large, the second time t2 is relatively small, and the conduction time t on The second time t2 is relatively large compared to the conduction time t. on The difference between them is less than the first time t1, that is, when the first switch M1 starts to turn off, and the fourth control signal TOFF_DLY changes from high to low, the third control signal TOFF_PRE has not yet changed from low to high. Therefore, the first control signal TOFF_ED remains low and the sixth voltage signal INA remains high until the third control signal TOFF_PRE changes from high to high, at which point the first control signal TOFF_ED will change from low to high, and the voltage value of the sixth voltage signal INV will change from high to low. At this time, Figure 5BIn the second turn-off time generation module 111, the eighth switch M8 is turned on and the seventh switch M7 is turned off. The fifth current signal I_M8 flowing through the eighth switch M8 quickly charges the first capacitor C1, and the fourth control signal TOFF_DLY changes from low to high. After the seventh control signal M1_ON output by the logic drive module 103 changes from low to high to control the first switch M1 to turn on again, the voltage values ​​of the first control signal TOFF_ED, the sixth voltage signal INV, and the fourth control signal TOFF_DLY change abruptly again.

[0114] Therefore, before the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold, the moment when the first control signal TOFF_ED changes from low level to high level is determined by the third control signal TOFF_PRE, so that the time t1 taken for the voltage value of the fourth voltage signal V_C3 to rise to the input voltage Vin is the turn-off time of the first switch M1, thus achieving a constant turn-off time for the first switch M1.

[0115] Furthermore, after the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold, since the voltage value Vea of ​​the error signal VEA is small, the second time t2 is large, and the conduction time t on The second time t2 is relatively small compared to the conduction time t. on The difference between them is greater than the first time interval t1. That is, when the first switch M1 starts to turn off and the third control signal TOFF_PRE changes from low to high, the fourth control signal TOFF_DLY has not yet changed from high to low. When the third control signal TOFF_PRE and the fourth control signal TOFF_DLY are both high, the first control signal TOFF_ED is still low and the sixth voltage signal INA is still high. Only when the fourth control signal TOFF_DLY changes from low to high will the first control signal TOFF_ED change from low to high, and only then will the voltage value of the sixth voltage signal INV change from high to low.

[0116] Therefore, after the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold, the moment when the first control signal TOFF_ED changes from low to high is determined by the fourth control signal TOFF_DLY. This makes the time (i.e., the second time t2 and the on-time t) required for the voltage value of the first voltage signal V_C1 to drop to the third preset voltage threshold (i.e., the voltage value of the third reference voltage signal VREF3) when the first switch M1 is in the off state determined by the time (i.e., the time t2 and the on-time t). on The difference between the two values ​​is the turn-off time of the first switch M1, so that the turn-off time of the first switch M1 is extended as the output voltage increases.

[0117] Optionally, after the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold, the conduction time t of the first switching transistor M1 is... on This can be the minimum conduction time. In practical applications, the minimum conduction time is very small. Therefore, the second time t2 and the conduction time t on The difference between them can be regarded as equal to the second time t2. Therefore, the turn-off time of the first switch M1 can be regarded as equal to the time t2 taken for the voltage value of the first voltage signal V_C1 to drop to the third preset voltage threshold (i.e. the voltage value of the third reference voltage signal VREF3).

[0118] For ease of understanding, the following text will discuss... Figure 3 The circuit structure of the logic driver module 103 shown is further illustrated with examples. Please refer to [link / reference]. Figure 6 , Figure 6 This is a schematic diagram of the structure of a logic driving module provided in an embodiment of this application.

[0119] like Figure 6 As shown, the logic drive module 103 includes a first OR gate OR1, a second OR gate OR2, a third OR gate OR3, a fourth OR gate OR1, a fifth OR gate OR5, a third inverter INV3, a first buffer BUF1, and a second buffer BUF2. Combined with... Figure 3 and Figure 6 It can be seen that the first input terminal of the first OR gate OR1 is connected to the second input terminal f2 of the logic driver module 103, the second input terminal of the first OR gate OR1 is connected to the output terminal of the second OR gate OR2, the output terminal of the first OR gate OR1 is connected to the input terminal of the third inverter INV3 and the first input terminal OR1 of the second OR gate OR2, the second input terminal of the second OR gate OR2 is connected to the first input terminal f1 of the logic driver module 103, and the output terminal of the third inverter INV3 is connected to the input terminal of the first buffer BUF1, the first input terminal of the third OR gate OR3, and the first input terminal of the fifth OR gate OR5. The output of the first buffer BUF1 is connected to the first output h1 of the logic driver module 103; the second input of the third OR gate OR3 is connected to the output of the fourth OR gate OR1; the output of the third OR gate OR3 is connected to the first input of the fourth OR gate OR1 and the second input of the fifth OR gate OR5; the output of the fifth OR gate OR5 is connected to the input of the second buffer BUF2; the output of the second buffer BUF2 is connected to the second output h2 of the logic driver module 103; and the second input of the fourth OR gate OR1 is connected to the third input f3 of the logic driver module 103.

[0120] Assuming that in the initial state, the voltage value of the second control signal TON_ED is low and the voltage value of the first control signal TOFF_ED is high, then after being amplified by the first buffer BUF1, the voltage value of the seventh control signal M1_ON is high, and after being amplified by the second buffer BUF2, the voltage value of the eighth control signal M2_ON is low. At this time, the first switch M1 is in the on state, the second switch M2 is in the off state, the voltage value of the second control signal TON_ED is still low, and the voltage value of the first control signal TOFF_ED changes abruptly from high to low. After a period of time, under the control of the first control module 101, the voltage value of the second control signal TON_ED abruptly changes from low to high, while the voltage value of the first control signal TOFF_ED remains high and the voltage value of the zero-crossing signal ZERO remains low. Then, the voltage value of the seventh control signal M1_ON abruptly changes from high to low, and the voltage value of the eighth control signal M2_ON abruptly changes from low to high. The first switch M1 switches from the on state to the off state, and the second switch M2 switches from the off state to the on state. The voltage value of the second control signal TON_ED abruptly changes from high to low, while the voltage value of the first control signal TOFF_ED remains low. After the second switch M2 is turned on, the current flowing through the second switch M2 gradually decreases.

[0121] Before the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold (i.e., in continuous conduction mode), the current flowing through the second switch M2 will not drop to zero, and the voltage value of the zero-crossing signal ZERO will always be low. Therefore, the voltage value of the seventh control signal M1_ON remains low, and the voltage value of the eighth control signal M2_ON remains high. Then, under the control of the second control module 102, the voltage value of the first control signal TOFF_ED changes abruptly from low to high, while the voltage value of the second control signal TON_ED remains low. Then, the voltage value of the seventh control signal M1_ON changes abruptly from low to high, and the voltage value of the eighth control signal M2_ON changes abruptly from high to low. The first switch M1 then switches from the off state to the on state, and the second switch M2 switches from the on state to the off state.

[0122] After the output voltage Vout of the Boost converter circuit 11 reaches the first preset voltage threshold (i.e., in intermittent conduction mode), the current flowing through the second switch M2 drops to zero, and the voltage value of the zero-crossing signal ZERO changes abruptly from low to high when the current is zero. Therefore, after the second switch M2 is turned on, the voltage value of the zero-crossing signal ZERO remains low for a period of time, the voltage value of the seventh control signal M1_ON remains low, and the voltage value of the eighth control signal M2_ON remains high. When the voltage value of the zero-crossing signal ZERO changes abruptly from low to high, the voltage value of the seventh control signal M1_ON remains low, while the voltage value of the eighth control signal M2_ON changes abruptly from high to low. The first switch M1 remains off, while the second switch M2 switches from on to off (to prevent current backflow). The first switch M1 will only switch from the off state to the on state after the voltage value of the first control signal TOFF_ED changes from low to high under the control of the off time control module 112 (the principle can be found in the above-mentioned change process of related signals in the continuous on mode, which will not be repeated here).

[0123] Therefore, Figure 3 The voltage regulator control circuit 10 in the described embodiment involves the coordinated action of multiple signals when controlling the switching transistors in the Boost converter circuit. To better understand the working principle of the voltage regulator control circuit 10, the following explanation is based on the waveform diagrams of the signals. Please refer to [link to relevant documentation]. Figure 7 , Figure 7 This is a signal waveform diagram provided in an embodiment of this application.

[0124] Waveform diagrams 701-715 are the waveforms of the output current signal IOUT, the current signal I_L of the inductor L, the output voltage signal VOUT, the fifth voltage signal VDC, the error signal VEA, the fifth control signal TON_PRE, the sixth control signal TON_MIN, the second control signal TON_ED, the third control signal TOFF_PRE, the sixth voltage signal INA, the fourth control signal TOFF_DLY, the first control signal TOFF_ED, the zero-crossing signal ZERO, the seventh control signal M1_ON, and the eighth control signal M2_ON, respectively.

[0125] Based on the foregoing, in practical applications, Figure 3When the output voltage Vout of the Boost converter circuit 11 in the described embodiment is equal to the first preset threshold, the voltage value of the error signal VEA in the first control module 101 is equal to the voltage value of the fifth voltage signal VDC. The second time taken for the voltage value of the first voltage signal V_C1 output by the first capacitor C1 in the second control module 102 to drop to the voltage value of the third reference voltage signal VREF3 is equal to the conduction time t of the first switch M1. on The difference between them is equal to the first time when the voltage value of the fourth voltage signal V_C3 output by the third capacitor C3 rises to the output voltage Vin.

[0126] Therefore, when the load changes from heavy to light, the output voltage Vout of the Boost converter circuit 11 is disturbed and gradually increases. Before the output voltage Vout reaches the first preset voltage threshold (i.e., before the voltage value of the error signal VEA reaches the voltage value of the fifth voltage signal VDC), the second control signal TON_ED changes with the fifth control signal TON_PRE, and the first control signal TOFF_ED changes with the third control signal TOFF_PRE. That is, the voltage value of the second control signal TON_ED will change from low to high when the fifth control signal TON_PRE changes from low to high, and the first switch M1 will start to turn off under the control of the logic drive module 103. Similarly, the first control signal TOFF_ED will change from low to high when the third control signal TOFF_PRE changes from low to high, and the first switch M1 will start to turn on under the control of the logic drive module 103. Therefore, under the control of the voltage regulation control circuit 10, the turn-off time t of the first switch M1 in the Boost converter circuit 11 is... off The conduction time t remains constant on As the output voltage Vout increases, the duty cycle of the first switching transistor M1 gradually decreases to reduce the output voltage ripple when the Boost converter circuit 11 is working.

[0127] After the output voltage Vout reaches the first preset voltage threshold (i.e., after the voltage value of the error signal VEA reaches the voltage value of the fifth voltage signal VDC), the second control signal TON_ED changes with the sixth control signal TON_MIN, and the first control signal TOFF_ED changes with the fourth control signal TOFF_DLY. Specifically, the voltage value of the second control signal TON_ED will only change from low to high when the sixth control signal TON_MIN changes from high to low, and the first switch M1 will only begin to turn off under the control of the logic drive module 103. Similarly, the first control signal TOFF_ED will only change from low to high when the fourth control signal TOFF_DLY changes from low to high, and the first switch M1 will only begin to turn on under the control of the logic drive module 103. Therefore, under the control of the voltage regulation control circuit 10, the conduction time t of the first switch M1 in the Boost converter circuit 11 is... on The turn-off time t remains constant (can be the minimum conduction time). off As the output voltage Vout increases, the duty cycle of the first switching transistor M1 is further reduced to further reduce the output voltage ripple when the Boost converter circuit 11 is working.

[0128] Therefore, when the load changes from heavy to light, the Boost converter circuit 11, under the control of the voltage regulation control circuit 10, can seamlessly switch from the constant off-time (CFT) control mode to the constant on-time (COT) control mode, using the voltage value of the error signal Vea as the switching point. This continuously reduces the duty cycle of the first switching transistor M1, thereby reducing the output voltage ripple of the Boost converter circuit 11. It is easy to understand that when the load changes from light to heavy, the Boost converter circuit 11, under the control of the voltage regulation control circuit 10, can seamlessly switch from the constant on-time (COT) control mode to the constant off-time (CFT) control mode, using the voltage value of the error signal Vea as the switching point. This continuously increases the duty cycle of the first switching transistor M1, thereby reducing the output voltage ripple of the Boost converter circuit 11.

[0129] In summary, the voltage regulation control circuit 10 provided in this application embodiment can control the Boost converter circuit 11 to operate in a single-cycle control mode within the full load range, and adjust the duty cycle of the first switching transistor, thereby reducing the output voltage ripple of the Boost converter circuit 11 when operating within the full load range, so as to be suitable for application scenarios with high requirements for output voltage ripple.

[0130] In the embodiments of this application, "multiple" refers to two or more. Furthermore, unless otherwise stated, "first" in the embodiments of this application is used only for naming purposes and is not used to define the order, timing, priority, or importance of multiple objects, such as a first control signal, a first switching transistor, etc. This rule also applies to "second," "third," and "fourth," etc.

[0131] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A voltage regulation control circuit, characterized in that, The voltage regulation control circuit includes a first control module (101), a second control module (102), and a logic drive module (103); the second control module (102) includes a first capacitor (C1), wherein: The first control module (101) and the logic drive module (103) are used to control the conduction time of the first switch (M1) in the Boost converter circuit to remain unchanged when the voltage value of the output voltage signal (VOUT) of the boost converter circuit is not less than the first preset voltage threshold. The second control module (102) is used to output a first control signal (TOFF_ED). When the voltage value of the output voltage signal (VOUT) of the Boost converter circuit is not less than the first preset voltage threshold and the voltage value of the first voltage signal (V_C1) output by the first capacitor (C1) drops to the third preset voltage threshold, the voltage value of the first control signal (TOFF_ED) changes abruptly from low level to high level; the voltage value of the output voltage signal (VOUT) of the Boost converter circuit increases, and the discharge speed of the first capacitor (C1) slows down; The logic driving module (103) is used to control the first switch (M1) to turn on when the voltage value of the first control signal (TOFF_ED) changes from low level to high level; The first control module (101) includes a second capacitor (C2), wherein: The first control module (101) is used to output a second control signal (TON_ED). When the voltage value of the output voltage signal (VOUT) of the Boost converter circuit is not less than the first preset voltage threshold and the voltage value of the second voltage signal (V_C2) output by the second capacitor (C2) rises to the second preset voltage threshold, the voltage value of the second control signal (TON_ED) changes abruptly from low level to high level; the voltage value of the output voltage signal (VOUT) of the Boost converter circuit increases, and the charging speed of the second capacitor (C2) remains unchanged. The logic drive module (103) is used to control the first switch (M1) in the Boost converter circuit to turn off when the voltage value of the second control signal (TON_ED) changes abruptly from low level to high level.

2. The voltage regulation control circuit according to claim 1, characterized in that, The second control module (102) also includes a third capacitor (C3), wherein: When the output voltage signal (VOUT) of the Boost converter circuit is less than the first preset voltage threshold and the voltage value of the third voltage signal (VSENSE) obtained by converting the first current signal (I_M1) flowing through the first switch (M1) in the Boost converter circuit rises to the first voltage value, the voltage value of the second control signal (TON_ED) changes abruptly from low level to high level; the output voltage signal (VOUT) of the Boost converter circuit increases, and the first voltage value decreases; When the voltage value of the output voltage signal (VOUT) of the Boost converter circuit is less than the first preset voltage threshold and the voltage value of the fourth voltage signal (V_C3) output by the third capacitor (C3) rises to the fourth preset voltage threshold, the voltage value of the first control signal (TOFF_ED) changes abruptly from low level to high level; the voltage value of the output voltage signal (VOUT) of the Boost converter circuit increases, and the charging speed of the third capacitor (C3) remains unchanged.

3. The voltage regulation control circuit according to claim 2, characterized in that, The voltage regulation control circuit also includes a current sampling module (104) and an error amplification module (105). The first input terminal (a1) of the first control module (101) is connected to the drain of the first switching transistor (M1) in the Boost converter circuit through the current sampling module (104). The second input terminal (a2) of the first control module (101) and the first input terminal (b1) of the second control module (102) are connected to the output terminal (c) of the error amplification module (105). The input terminal (d) of the error amplification module (105) is connected to the positive output terminal (o1) of the Boost converter circuit. The output terminal (e) of the first control module (101) is connected to the first input terminal (f1) of the logic driving module (103). The output terminal (g) of the second control module (102) is connected to the second input terminal (f2) of the logic driving module (103). The current sampling module (104) is used to convert the first current signal (I_M1) into the third voltage signal (VSENSE). When the current value of the first current signal (I_M1) increases, the voltage value of the third voltage signal (VSENSE) increases. The error amplification module (105) is used to output the error signal (VEA). When the voltage value of the output voltage signal (VOUT) of the Boost converter circuit increases, the voltage value of the output error signal (VEA) decreases.

4. The voltage regulation control circuit according to claim 3, characterized in that, The voltage regulation control circuit also includes a current zero-crossing detection module (106). The third input terminal (f3) of the logic driving module (103) is connected to the source of the second switch (M2) in the Boost converter circuit through the current zero-crossing detection module (106). The first output terminal (h1) of the logic driving module (103) is connected to the gate of the first switch (M1). The second output terminal (h2) of the logic driving module (103) is connected to the gate of the second switch (M2). The current zero-crossing detection module (106) is used to output a zero-crossing signal (ZERO). When the second current signal (I_M2) flowing through the second switch (M2) becomes zero, the zero-crossing signal (ZERO) changes from a low level to a high level. The logic driving module (103) is used to control the second switch (M2) to turn off when the first switch (M1) is in the on state. The logic driving module (103) is used to control the second switch (M2) to turn on when the first switch (M1) is in the off state and the voltage value of the zero-crossing signal (ZERO) is low, and to control the second switch (M2) to turn off when the first switch (M1) is in the off state and the voltage value of the zero-crossing signal (ZERO) changes from a low level to a high level.

5. The voltage regulation control circuit according to claim 3 or 4, characterized in that, The second control module (102) includes a first shutdown time generation module (110), a second shutdown time generation module (111), and a shutdown time control module (112). The first shutdown time generation module (110) includes the third capacitor (C3), and the second shutdown time generation module (111) includes the first capacitor (C1). The first off-time generation module (110) is used to charge the third capacitor (C3) based on the voltage value of the output voltage signal (VOUT) of the Boost converter circuit and output a third control signal (TOFF_PRE). When the voltage value of the fourth voltage signal (V_C3) rises to the fourth preset voltage threshold, the third control signal (TOFF_PRE) changes from low level to high level. The second turn-off time generation module (111) is used to output a fourth control signal (TOFF_DLY). When the voltage value of the first voltage signal (V_C1) output by the first capacitor (C1) drops to the third preset voltage threshold, the fourth control signal (TOFF_DLY) changes from low level to high level. The third preset voltage threshold is the voltage value of the input voltage signal (VIN) of the Boost converter circuit. The shutdown time control module (112) is used to output the first control signal (TOFF_ED). When the voltage value of the output voltage signal (VOUT) of the Boost converter circuit is less than the first preset voltage threshold and the third control signal (TOFF_PRE) changes from low level to high level, the first control signal (TOFF_ED) changes from low level to high level. When the voltage value of the output voltage signal (VOUT) of the Boost converter circuit is not less than the first preset voltage threshold and the fourth control signal (TOFF_DLY) changes from low level to high level, the first control signal (TOFF_ED) changes from low level to high level.

6. The voltage regulation control circuit according to claim 5, characterized in that: The second input terminal of the second control module (102) is connected to the positive output terminal (o1) of the Boost converter circuit, the third input terminal of the second control module (102) is connected to the positive input terminal (i1) of the Boost converter circuit, the fourth input terminal of the second control module (102) is connected to the first output terminal (h1) of the logic drive module (103), the first input terminal (r1) of the second turn-off time generation module (111) is the first input terminal (b1) of the second control module (102), the first input terminal (u1) of the first turn-off time generation module (110) is the second input terminal of the second control module (102), the second input terminal (u2) of the first turn-off time generation module (110) is the third input terminal of the second control module (102), the third input terminal (u3) of the first turn-off time generation module (110) is the fourth input terminal of the second control module (102), and the first output terminal (x1) of the turn-off time control module (112) is the output terminal (g) of the second control module (102). The output terminal (z) of the first shutdown time generation module (110) is connected to the first input terminal (w1) of the shutdown time control module (112), the output terminal (y) of the second shutdown time generation module (111) is connected to the second input terminal (w2) of the shutdown time control module (112), the third input terminal (w3) of the shutdown time control module (112) is connected to the third input terminal (u3) of the first shutdown time generation module (110), and the second input terminal (r2) of the second shutdown time generation module (111) is connected to the second output terminal (x2) of the shutdown time control module (112).

7. The voltage regulation control circuit according to claim 6, characterized in that, The second turn-off time generation module (111) further includes a first amplifier (OP1), a first comparator (CMP1), a third switch (M3), a fourth switch (M4), a fifth switch (M5), a sixth switch (M6), a seventh switch (M7), an eighth switch (M8), a first resistor (R1), a first voltage source (S1), and a second voltage source (S2); The negative input terminal of the first amplifier (OP1) is connected to the first input terminal (r1) of the second turn-off time generation module (111). The positive input terminal of the first amplifier (OP1) is connected to the drain of the third switch (M3) and one end of the first resistor (R1). The output terminal of the first amplifier (OP1) is connected to the gate of the third switch (M3) and the gate of the fourth switch (M4). The drain of the fourth switch (M4) is connected to the drain of the fifth switch (M5), the gate of the fifth switch (M5), and the gate of the sixth switch (M6). The drain of the sixth switch (M6) is connected to... The source of the seventh switch (M7) is connected to the source of the eighth switch (M8), the drain of the seventh switch (M7) is connected to the drain of the eighth switch (M8), one end of the first capacitor (C1) is connected to the positive input terminal of the first comparator (CMP1), the gate of the seventh switch (M7) is connected to the gate of the eighth switch (M8) and the second input terminal (r2) of the second turn-off time generation module (111), the negative input terminal of the first comparator (CMP1) is connected to the first voltage source (S1), and the output terminal of the first comparator (CMP1) is connected to the output terminal (y) of the second turn-off time generation module (111). The source of the third switch (M3), the source of the fourth switch (M4), and the source of the eighth switch (M8) are connected to the first voltage source (S1), and the other end of the first resistor (R1), the source of the fifth switch (M5), the source of the sixth switch (M6), and the other end of the first capacitor (C1) are connected to the reference ground.

8. The voltage regulation control circuit according to claim 7, characterized in that, The shutdown time control module (112) includes a first flip-flop (SR1), a second flip-flop (SR2), a third flip-flop (SR3), a first inverter (INV1), and a first AND gate (ND1). The set terminal of the first flip-flop (SR1) is connected to the first input terminal (w1) of the shutdown time control module (112), the input terminal of the first inverter (INV1) is connected to the second input terminal (w2) of the shutdown time control module (112), the reset terminal of the first flip-flop (SR1), the reset terminal of the second flip-flop (SR2), and the set terminal of the third flip-flop (SR3) are connected to the third input terminal (w3) of the shutdown time control module (112), the output terminal of the first flip-flop (SR1) is connected to the first input terminal of the first AND gate (ND1), the second input terminal of the first AND gate (ND1) is connected to the output terminal of the first inverter (INV1), the output terminal of the first AND gate (ND1) is connected to the set terminal of the second flip-flop (SR2) and the reset terminal of the third flip-flop (SR3), the output terminal of the second flip-flop (SR2) is connected to the first output terminal (x1) of the shutdown time control module (112), and the output terminal of the third flip-flop (SR3) is connected to the second output terminal (x2) of the shutdown time control module (112).

9. The voltage regulation control circuit according to claim 6, characterized in that, The first turn-off time generation module (110) also includes a second amplifier (OP2), a second comparator (CMP2), a third voltage source (S3), a ninth switch (M9), a tenth switch (M10), an eleventh switch (M11), and a second resistor (R2). The negative input terminal of the second amplifier (OP2) is connected to the first input terminal (u1) of the first turn-off time generation module (110). The positive input terminal of the second amplifier (OP2) is connected to the drain of the ninth switch (M9) and one end of the second resistor (R2). The output terminal of the second amplifier (OP2) is connected to the gate of the ninth switch (M9) and the gate of the tenth switch (M10). The drain of the tenth switch (M10) is connected to one end of the third capacitor (C3), the drain of the eleventh switch (M11), and the positive input terminal of the second comparator (CMP2). The gate of the eleventh switch (M11) is connected to the second input terminal (u2) of the first turn-off time generation module (110). The negative input terminal of the second comparator (CMP2) is connected to the third input terminal (u3) of the first turn-off time generation module (110). The output terminal of the second comparator (CMP2) is connected to the output terminal (z) of the first turn-off time generation module (110). The source of the ninth switch (M9) and the source of the tenth switch (M10) are connected to the third voltage source (S3), and the other end of the second resistor (R2), the other end of the third capacitor (C3), and the source of the eleventh switch (M11) are connected to reference ground.

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