Image sensor pixel structure and image sensor

Abstract

The application provides an image sensor pixel structure, comprising a plurality of arrayed pixel units, each pixel unit comprising: a semiconductor substrate having opposite first and second surfaces; a photoelectric conversion region extending into the semiconductor substrate from the first surface to form a photoelectric conversion element; a floating diffusion region extending into the semiconductor substrate from the first surface; and a transfer transistor coupled between the photoelectric conversion region and the floating diffusion region, the transfer transistor comprising a transfer gate, wherein the extension path of the transfer gate passes through the center point of the first surface, and the extension direction of the transfer gate forms an angle Q with the first diagonal direction of the first surface, 0°≤Q<5°. The application also provides an image sensor. In the application, the pixel array is rotated by a certain angle, the transfer gate is arranged in the diagonal direction of the pixel unit surface, the area of the transfer gate is increased in the lateral length, and the problems of short channel effect and narrow channel effect caused by the too small size of the transfer gate are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of CMOS image sensors, and in particular to an image sensor pixel structure and an image sensor comprising the same. BACKGROUND

[0002] At present, with the rapid development of the intelligent era, the camera is a well-known term for consumers, and the level of shooting performance is directly related to the CMOS image sensor (CIS) chip. With the improvement of the pixel level of the CMOS image sensor, the single pixel size is getting smaller and smaller, so that the area available for placing the gate of the transfer transistor on the surface of the single pixel is very limited. The reduction of the size of the gate of the transfer transistor will bring technical problems of short channel effect (SCE) and narrow channel effect (NCE), which will further cause charge leakage and other more problems. SUMMARY

[0003] Therefore, the present application provides an image sensor pixel structure and an image sensor comprising the same.

[0004] The present application provides an image sensor pixel structure, comprising a plurality of arrayed pixel units, each pixel unit comprising:

[0005] a semiconductor substrate having opposite first and second surfaces;

[0006] a photoelectric conversion region extending from the first surface into the semiconductor substrate to form a photoelectric conversion element;

[0007] a floating diffusion region extending from the first surface into the semiconductor substrate;

[0008] a transfer transistor coupled between the photoelectric conversion region and the floating diffusion region, the transfer transistor comprising a transfer gate, wherein the extension path of the transfer gate passes through the center point of the first surface, and the extension direction of the transfer gate forms an angle Q with the first diagonal direction of the first surface, 0°≤Q<5°.

[0009] Optionally, the transfer gate is a planar gate.

[0010] Optionally, the transfer gate is a slot gate extending from the first surface into the semiconductor substrate.

[0011] Optionally, a trench isolation region is provided between adjacent pixel units, and the slot gate extends to the trench isolation region, wherein the depth of the slot gate located in the trench isolation region is greater than the depth of the slot gate located in the pixel unit.

[0012] Optionally, the extending direction of the transfer gate is a first diagonal direction of the first surface.

[0013] Optionally, the transfer gates of each pixel unit in the first diagonal direction are connected together.

[0014] Optionally, the pixel unit further comprises a reset transistor and a readout circuit, and two adjacent pixel units share one reset transistor and one readout circuit.

[0015] Optionally, the reset transistor is located at the side of any one of the two pixel units sharing the reset transistor; the readout circuit comprises an amplification transistor and a row selection transistor, and the amplification transistor and the row selection transistor are located between the two pixel units sharing the readout circuit.

[0016] Optionally, the reset transistor is located at the side away from each other of the two pixel units sharing the reset transistor; the readout circuit comprises an amplification transistor and a row selection transistor, and the amplification transistor and the row selection transistor are located between the two pixel units sharing the readout circuit; the pixel unit further comprises a gain control transistor, two adjacent pixel units share one gain control transistor, and the gain control transistor is located at the side of any one of the two pixel units sharing the gain control transistor.

[0017] The application further provides an image sensor comprising the image sensor pixel structure.

[0018] Compared with the prior art, the application has at least one of the following outstanding advantages:

[0019] The pixel array is rotated by a certain angle in the application, so that the gate of the transfer transistor is arranged in the diagonal direction of the pixel area, the area of the transfer gate is increased in the horizontal length, the problem of short channel effect and narrow channel effect caused by too small size of the transfer gate is solved, the gate of the transfer transistor is designed as a saddle-shaped slot gate, the area of the transfer gate is also increased in the vertical depth, the transfer gates of adjacent pixel units in the first diagonal direction of the pixel unit are connected with each other to increase the gate width to the maximum, and the transfer gates connected with each other are arranged in the two shared pixel structures, so that the area for placing the transfer gate can be further saved, and the placement area of other components in the two shared pixel structures can be increased. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a partial structure schematic view of an image sensor pixel structure provided by the application;

[0021] Figure 2 is Figure 1 is a cross-sectional structure schematic view of the image sensor pixel structure shown in the figure along the direction of C-C';

[0022] Figure 3 is a top view structural schematic diagram of an image sensor pixel structure shown in Figure 1

[0023] Figure 4 is another top view structural schematic diagram of an image sensor pixel structure shown in Figure 1

[0024] Figure 5 is a sectional view structural schematic diagram of an image sensor pixel structure shown in Figure 1

[0025] Figure 6 is a partial structural schematic diagram of another image sensor pixel structure provided by the present application;

[0026] Figure 7 is a circuit structural schematic diagram of an image sensor pixel structure provided by the present application;

[0027] Figure 8 is a partial structural schematic diagram of an image sensor pixel structure shown in Figure 7

[0028] Figure 9 is a circuit structural schematic diagram of another image sensor pixel structure provided by the present application;

[0029] Figure 10 is a partial structural schematic diagram of an image sensor pixel structure shown in Figure 9

[0030] Figure 11 is a timing diagram of an image sensor pixel structure provided by the present application. DETAILED DESCRIPTION

[0031] In order to make the above objectives, features and advantages of the present application more apparent, further description will be given to the present application in conjunction with the accompanying drawings and examples.

[0032] As in the detailed description of the embodiments of the present application, the sectional views of the device structures will be partially enlarged without the general proportion for the convenience of description, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual manufacture.

[0033] ​​​​​For the sake of convenience, spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device described is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Likewise, if a device is turned over, elements described as "above" other elements or features would then be oriented "below" the other elements or features. Thus, the spatially relative terms are intended to encompass the various and ordinary orientations of the device in use.

[0034] It is to be noted that the drawings provided in the embodiments are only schematic and are intended to provide the basic understanding of the application. In reality, the shape, size, and number of components shown in the drawings can be varied to suit specific implementation requirements. The layout of the components can also be more complex.

[0035] The application provides an image sensor pixel structure, comprising a plurality of arrayed pixel units, each pixel unit comprising a structure as shown in Figures 1-3 , Figure 1 is a partial structure schematic diagram of an image sensor pixel structure provided by the application, Figure 2 is Figure 1 a cross-sectional structure schematic diagram of the image sensor pixel structure shown in Figure 3 is Figure 1 a top view structure schematic diagram of the image sensor pixel structure shown in. As shown in the figure, each pixel unit comprises: a semiconductor substrate 101 having opposite first and second faces X and Y; a photoelectric conversion region 102 extending into the semiconductor substrate 101 from the first face X to form a photoelectric conversion element 110; a floating diffusion region 103 extending into the semiconductor substrate 101 from the first face X; a transfer transistor 104 coupled between the photoelectric conversion region 102 and the floating diffusion region 103, the transfer transistor 104 comprising a transfer gate 120, the extension path of the transfer gate 120 passing through the center point of the first face X, the extension direction of the transfer gate 120 forming an angle Q with the first diagonal direction A1 of the first face X, and 0°≤Q<5°.

[0036] It should be noted that the photoelectric conversion region 102 in Figure 2 is Figure 1 the photoelectric conversion region AA in Figure 3 , Figure 2 the floating diffusion region 103 in Figure 3 is the FD inFigure 2 The transmission gate 120 in the middle is Figure 3 The transmission gate (TX gate) will be referred to by its abbreviation for ease of description and will not be elaborated further.

[0037] Optionally, the photosensitive surface of the pixel is the second side of the semiconductor substrate, that is, in this embodiment of the invention, the image sensor pixel structure is a back-illuminated image sensor.

[0038] Optionally, in this embodiment of the invention, the transfer gate (TX gate) is a trench gate extending from the first surface into the semiconductor substrate. From a process perspective, setting the transfer gate (TX gate) as a trench gate structure makes it easier to control its aspect ratio, thereby simplifying the process flow and ensuring process accuracy. Furthermore, the trench gate located between the photoelectric conversion region and the floating diffusion region can isolate the current leakage path between them, thereby improving the physical isolation effect. Of course, optionally, the transfer gate (TX gate) can also be a planar gate structure commonly used in the prior art.

[0039] Understandable, such as Figure 3 As shown, in this embodiment of the invention, the first surface X includes a first diagonal direction A1 and a second diagonal direction A2, wherein the second diagonal direction A2 is the direction in which the photoelectric conversion area and the floating diffusion area are arranged sequentially in a pixel unit, and the first diagonal direction A1 is perpendicular to the second diagonal direction A2.

[0040] The extension direction of the transmission gate TX gate forms an angle Q with the first diagonal direction A1 of the first surface X, where 0° ≤ Q < 5°, thereby increasing the lateral length of the transmission gate and improving the area of ​​the transmission gate TX gate; further optionally, such as Figure 4 As shown, Figure 4 yes Figure 1 The diagram shows another top view of the image sensor pixel structure. When Q = 0, that is, when the extension direction of the transmission gate TX gate is the same as the first diagonal direction A1 of the first surface X, the lateral length of the transmission gate TX gate reaches its maximum value in the pixel unit, which further increases the area of ​​the transmission gate TX gate.

[0041] In existing technologies, the transfer gate of a pixel unit is often positioned at the corner of the photoelectric conversion region at an angle. As the size of a single pixel unit in an image sensor further decreases, the transfer gate at the corner of the photoelectric conversion region suffers from charge leakage due to short-channel and narrow-channel effects, affecting the image sensor's performance. However, in this embodiment of the invention, by extending the transfer gate through the center point of the semiconductor substrate surface of each pixel unit and extending it as diagonally as possible from the semiconductor substrate surface, the area of ​​the transfer gate is increased in lateral length, thereby solving the problems of charge leakage caused by short-channel and narrow-channel effects.

[0042] With reference to Figures 1-5 , Figure 5 is Figure 1 the cross-sectional structure of the image sensor pixel structure along the B-B' direction. In the embodiment of the present application, a trench isolation region (STI) is further arranged between adjacent pixel units, Figure 2 in 105, Figure 1 and 3 STI in -5, the TX gate extends to the trench isolation region STI, wherein the depth of the trench gate located in the trench isolation region STI is greater than the depth of the trench gate located in the pixel unit, so that the transmission gate forms a saddle-shaped structure as shown in Figure 5 .

[0043] It can be understood that, by setting the gate of the transmission transistor as a trench gate, the longitudinal depth of the transmission gate can be increased as much as possible without affecting the performance of the image sensor, that is, the area of the transmission gate is further increased; and by controlling the etching rates of the pixel unit and the trench isolation region STI to be different, the depth of the trench gate located in the trench isolation region 105 is greater than the depth of the trench gate located in the pixel unit, without affecting the functions of other components in the pixel unit, and the area of the trench gate located in the trench isolation region 105 is increased, and the overall area of the transmission gate in a single pixel is also increased.

[0044] In some embodiments, as shown in Figure 6 , the transmission gates in each pixel unit located in the first diagonal direction A1 are connected together, that is, each pixel unit located in the first diagonal direction A1 forms a pixel row, and shares the same row selection control signal, so that the gate width ratio of the transmission gate TX gate is further increased, and the process flow is also simplified, thereby saving costs.

[0045] In other embodiments, the technical solution of connecting the transmission gates in each pixel unit located in the first diagonal direction together can be applied to a two-shared pixel structure, thereby increasing the area of the transmission gate in the two-shared pixel structure. Referring to Figure 7 , Figure 7 is a circuit structure schematic diagram of an image sensor pixel structure provided by the present application, in the embodiment, the pixel unit further includes a reset transistor RST and a readout circuit, wherein the transmission gate is connected to a transmission control signal tx, the gate of the reset transistor RST is connected to a reset signal rst, and two adjacent pixel units share one reset transistor RST and one readout circuit, so that the transmission gates of the pixel units on each pixel row of the two-shared pixel structure are connected to each other, and each pixel row of the pixel units receives the same transmission control signal tx, the area for placing the transmission gate can be further saved, thereby the placement area of other components in the two-shared pixel structure can be increased, and the circuit design layout has more possibilities.

[0046] Specifically, the device structure layout is as shown in Figure 8 , Figure 8 is Figure 7 a partial structure diagram of the image sensor pixel structure as shown in the figure. The pixel unit (0, 0) and the pixel unit (0, 1) share a reset transistor RST, and the reset transistor RST is located at the side of any one of the two pixel units sharing the same reset transistor, that is, the reset transistor RST can be located at the side of the pixel unit (0, 0) or the side of the pixel unit (0, 1); the readout circuit includes an amplification transistor SF and a row selection transistor RS, and the amplification transistor SF and the row selection transistor RS are located between the two pixel units sharing the same readout circuit, such as Figure 8 between the pixel unit (0, 0) and the pixel unit (0, 1) in the figure. More specifically, the drain of the reset transistor RST is connected to a power supply end, the drain of the amplification transistor SF is connected to the power supply end, the source of the reset transistor RST, the gate of the amplification transistor SF and the source of the transfer transistor TX are connected to a floating diffusion region FD, the source of the amplification transistor SF is connected to the drain of the row selection transistor RS, the gate of the row selection transistor RS is connected to a row selection signal rs, and the source of the row selection transistor RS is used as an output end of the pixel circuit to output a pixel signal.

[0047] Optionally, in some embodiments, the pixel unit further includes a gain control transistor DCG connected between the reset transistor RST and the floating diffusion region, the gate of the gain control transistor DCG is connected to a gain control signal dcg, and two adjacent pixel units share one gain control transistor DCG. As shown in Figure 9 , 10 , Figure 9 is a circuit structure diagram of another image sensor pixel structure provided by the present application, Figure 10 is Figure 9 a partial structure diagram of the image sensor pixel structure as shown in the figure. Among them, the reset transistor RST is located at the side away from each other of the two pixel units sharing the same reset transistor; the amplification transistor SF and the row selection transistor RS are located between the two pixel units sharing the same readout circuit; and the gain control transistor DCG is located at the side of any one of the two pixel units sharing the same gain control transistor. In addition to the circuit connection relationship caused by the gain control transistor being connected between the reset transistor and the floating diffusion region, the more specific circuit connection relationship is the same as the above-mentioned embodiment, which will not be repeated here.

[0048] Further, the circuit timing diagram of the image sensor pixel structure of the embodiment of the present application is as shown in Figure 11 , for reference Figures 9-11For example, taking the pixel column on Pix<0> as an example, the pixel unit (0, 0) and the pixel unit (0, 1) share the same reset transistor RST0, the gain control transistor DCG0, the amplification transistor SF0 and the row selection transistor RS0, the reset transistor RST0 receives the reset signal rst<0>, the gain control transistor DCG0 receives the gain control dcg<0>, the row selection transistor RS0 receives the row selection signal rs<0>, the transfer gate of the pixel unit (0, 0) receives the transfer control signal txa<0>, and the transfer gate of the pixel unit (0, 1) receives the transfer control signal txb<0>; similarly, the pixel unit (0, 2) and the pixel unit (0, 3) share the same reset transistor RST1, the gain control transistor DCG1, the amplification transistor SF1 and the row selection transistor RS1, the reset transistor RST1 receives the reset signal rst<1>, the gain control transistor DCG1 receives the gain control dcg<1>, the row selection transistor RS1 receives the row selection signal rs<1>, the transfer gate of the pixel unit (0, 2) receives the transfer control signal txa<1>, and the transfer gate of the pixel unit (0, 3) receives the transfer control signal txb<1>. In Figure 10 Row0 PixA represents the readout of the pixel row where the pixel unit (0, 0) is located, Row0 PixB represents the readout of the pixel row where the pixel unit (0, 1) is located, Row1 PixA represents the readout of the pixel row where the pixel unit (0, 2) is located, and Row1 PixA represents the readout of the pixel row where the pixel unit (0, 3) is located.

[0049] In some embodiments, the process manufacturing method of the image sensor pixel structure specifically comprises the following steps:

[0050] S1: providing a semiconductor substrate having opposite first and second surfaces.

[0051] Optionally, the semiconductor substrate is a silicon substrate.

[0052] S2: forming a trench isolation region on the semiconductor substrate.

[0053] The step of forming the trench isolation region on the semiconductor substrate mainly comprises shallow trench etching, oxide filling and oxide planarization. Specifically, the trench isolation region pattern is exposed on the photoresist on the silicon substrate by photolithography, a shallow trench is formed on the silicon substrate by etching process, silicon oxide is deposited in the shallow trench to form the trench isolation region, in this embodiment, the silicon oxide can be deposited in the shallow trench by chemical vapor deposition process, and finally it is planarized by chemical mechanical polishing or nitride removal process.

[0054] S3: forming a transfer gate of a transfer transistor on a first surface of a semiconductor substrate, wherein an extension path of the transfer gate passes through a center point of the first surface, and an extension direction of the transfer gate forms an angle Q with a first diagonal direction of the first surface, 0°≤Q<5°.

[0055] Optionally, the transfer gate of the transfer transistor can be a planar gate or a slot gate. The planar gate is a conventional process for integrated circuit manufacturing, which is not described herein. The steps of forming the slot gate specifically include: the transfer gate pattern is located at the intersection of each trench isolation region. Because it is a linear pattern, it can be directly photoetched here, or a deposition-etching-deposition process can be used to reduce the photoetching cost and improve the gate formation accuracy. For photoetching, the transfer gate pattern is exposed on the photoresist on the silicon substrate by photoetching, a shallow trench is formed on the silicon substrate by an etching process, and polycrystalline silicon is deposited in the shallow trench to form a slot gate. In this embodiment, the polycrystalline silicon can be deposited in the shallow trench by a chemical vapor deposition process. The silicon substrate is dry etched, and the etching conditions are adjusted to make the selectivity ratio of silicon to silicon oxide between 1-10. The above selectivity ratio can be selected according to the device design, which is not limited herein.

[0056] Optionally, the transfer gate is also formed in the trench isolation region, and finally a saddle-shaped slot gate structure is formed. In this embodiment, by adjusting the etching rate in the trench isolation region to be greater than the etching rate in the pixel unit during the slot gate etching process and the slot gate structure formatting process, a saddle-shaped slot gate structure can be formed, and the area of the slot gate in the trench isolation region is increased.

[0057] S4: forming a photoelectric conversion region on one side of the transfer gate and a floating diffusion region on the other side to form a pixel unit.

[0058] A patterned photoresist is used as a mask for ion implantation process, including P-type ion implantation and N-type ion implantation, to form a photoelectric conversion region and a floating diffusion region. The slot gate between the photoelectric conversion region and the floating diffusion region can isolate the current leakage channel therebetween, thereby improving the physical isolation effect.

[0059] In the present application, by rotating the pixel array by a certain angle, the gate of the transfer transistor is arranged in the diagonal direction of the pixel region, the area of the transfer gate is increased in the lateral length, and the problems of short channel effect and narrow channel effect caused by the small size of the transfer gate are solved. Further, the gate of the transfer transistor is designed as a saddle-shaped slot gate, and the area of the transfer gate is also increased in the vertical depth. Meanwhile, the transfer gates of adjacent pixel units in the first diagonal direction of the pixel unit are connected to each other to increase the gate width to the maximum. The connected transfer gates are arranged in the two-shared pixel structure, which can further save the area for placing the transfer gates, thereby increasing the placement area of other components in the two-shared pixel structure.

[0060] The above description is further detailed in connection with specific preferred embodiments of the present application, and it is not to be construed that the specific implementation of the present application is limited to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, and all of them should be considered as falling within the protection scope of the present application.

Claims

1. An image sensor pixel structure, characterized by, The image sensor pixel structure comprises a plurality of pixel units arranged in an array, each of the pixel units comprising: a semiconductor substrate having opposite first and second faces; a photoelectric conversion region extending from the first face into the semiconductor substrate to form a photoelectric conversion element; a floating diffusion region extending from the first face into the semiconductor substrate; a transfer transistor coupled between the photoelectric conversion region and the floating diffusion region, the transfer transistor comprising a transfer gate, wherein an extension path of the transfer gate passes through a center point of the first face, and an extension direction of the transfer gate forms an angle Q with a first diagonal direction of the first face, 0°≤Q<5°.

2. The pixel structure of claim 1, wherein, The transfer gate is a planar gate.

3. The pixel structure of claim 1, wherein, The transfer gate is a trench gate extending from the first face into the semiconductor substrate.

4. The pixel structure of claim 3, wherein, A trench isolation region is provided between adjacent pixel units, and the trench gate extends into the trench isolation region, wherein a depth of the trench gate in the trench isolation region is greater than a depth of the trench gate in the pixel unit.

5. The pixel structure of claim 1, wherein, The extension direction of the transfer gate is the first diagonal direction of the first face.

6. A pixel structure as claimed in any one of claims 1-5, characterized in that The transfer gates of each pixel unit in the first diagonal direction are integrated.

7. The pixel structure of claim 6, wherein, The pixel unit further comprises a reset transistor and a readout circuit, and two adjacent pixel units share one reset transistor and one readout circuit.

8. The pixel structure of claim 7, wherein, The reset transistor is located at a side of any one of the two pixel units sharing the same reset transistor. The readout circuit comprises an amplification transistor and a row selection transistor, and the amplification transistor and the row selection transistor are located between the two pixel units sharing the same readout circuit.

9. The pixel structure of claim 7, wherein, The reset transistor is located at a side of the two pixel units sharing the same reset transistor, which are away from each other. The readout circuit comprises an amplification transistor and a row selection transistor, and the amplification transistor and the row selection transistor are located between the two pixel units sharing the same readout circuit. The pixel unit further comprises a gain control transistor, and two adjacent pixel units share one gain control transistor, and the gain control transistor is located at a side of any one of the two pixel units sharing the same gain control transistor.

10. An image sensor, comprising: The image sensor pixel structure comprises a plurality of pixel units arranged in an array, each of the pixel units comprising: a semiconductor substrate having opposite first and second faces; a photoelectric conversion region extending from the first face into the semiconductor substrate to form a photoelectric conversion element; a floating diffusion region extending from the first face into the semiconductor substrate; a transfer transistor coupled between the photoelectric conversion region and the floating diffusion region, the transfer transistor comprising a transfer gate, wherein an extension path of the transfer gate passes through a center point of the first face, and an extension direction of the transfer gate forms an angle Q with a first diagonal direction of the first face, 0°≤Q<5°. The transfer gate is a planar gate. The transfer gate is a trench gate extending from the first face into the semiconductor substrate. A trench isolation region is provided between adjacent pixel units, and the trench gate extends into the trench isolation region, wherein a depth of the trench gate in the trench isolation region is greater than a depth of the trench gate in the pixel unit. The extension direction of the transfer gate is the first diagonal direction of the first face. The transfer gates of each pixel unit in the first diagonal direction are integrated. The pixel unit further comprises a reset transistor and a readout circuit, and two adjacent pixel units share one reset transistor and one readout circuit. The reset transistor is located at a side of any one of the two pixel units sharing the same reset transistor. The readout circuit comprises an amplification transistor and a row selection transistor, and the amplification transistor and the row selection transistor are located between the two pixel units sharing the same readout circuit. The reset transistor is located at a side of the two pixel units sharing the same reset transistor, which are away from each other. The readout circuit comprises an amplification transistor and a row selection transistor, and the amplification transistor and the row selection transistor are located between the two pixel units sharing the same readout circuit. The pixel unit further comprises a gain control transistor, and two adjacent pixel units share one gain control transistor, and the gain control transistor is located at a side of any one of the two pixel units sharing the same gain control transistor.

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