Pixel Circuit, Pixel Driving Method, and Display Device

Abstract

The present disclosure provides a pixel circuit, a pixel driving method, and a display device. The pixel circuit includes an energy storage control circuit, an energy storage circuit, a first initialization circuit, a driving circuit, and a light-emitting element; the first initialization circuit writes a first initial voltage to a control terminal of the driving circuit under the control of a first initialization control signal; the energy storage control circuit connects a second end of the energy storage circuit to a first voltage terminal under the control of an energy storage control signal during a refresh frame, and is configured to disconnect the second end of the energy storage circuit from the first voltage terminal under the control of the energy storage control signal during an initialization stage included in a hold frame and a data writing stage included in the hold frame. The present disclosure reduces the brightness difference between the refresh frame and the hold frame, and improves the Flicker phenomenon during low-frequency display or variable-frequency driving.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a pixel driving method, and a display device. Background Art

[0002] In the related art, an Organic Light Emitting Diode (OLED) display has the advantages of good flexibility, self-luminescence, thinness, low power consumption, fast response speed, wide viewing angle, etc., and thus is widely used in various fields and has broad development prospects. Summary of the Invention

[0003] In one aspect, an embodiment of the present disclosure provides a pixel circuit, including an energy storage control circuit, an energy storage circuit, a first initialization circuit, a second initialization circuit, a driving circuit, and a light emitting element; a display period of the pixel circuit includes a refresh frame and at least one hold frame, and the refresh frame and the hold frame respectively include an initialization stage, a data writing stage, and a light emitting stage;

[0004] The first initialization circuit is respectively electrically connected to a first initialization control line, a first initial voltage terminal, and a control terminal of the driving circuit, and is configured to write a first initial voltage provided by the first initial voltage terminal into the control terminal of the driving circuit under the control of a first initialization control signal provided by the first initialization control line;

[0005] A first end of the energy storage circuit is electrically connected to the control terminal of the driving circuit, and the energy storage circuit is configured to store electrical energy;

[0006] The energy storage control circuit is respectively electrically connected to an energy storage control line, a second end of the energy storage circuit, and a first voltage terminal, and is configured to control, in the refresh frame, a connection between the second end of the energy storage circuit and the first voltage terminal under the control of an energy storage control signal provided by the energy storage control line, and is configured to control, in the initialization stage included in the hold frame and the data writing stage included in the hold frame, a disconnection between the second end of the energy storage circuit and the first voltage terminal under the control of the energy storage control signal;

[0007] The driving circuit is electrically connected to a first pole of the light emitting element; the driving circuit is configured to drive the light emitting element under the control of a potential of its control terminal;

[0008] A second pole of the light emitting element is electrically connected to a second voltage terminal.

[0009] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit;

[0010] The second initialization circuit is electrically connected to a second initialization control line, a second initial voltage terminal, and a first pole of the light-emitting element respectively, and is configured to write a second initial voltage provided by the second initial voltage terminal into the first pole of the light-emitting element under the control of a second initialization control signal provided by the second initialization control line.

[0011] Optionally, the pixel circuit according to at least one embodiment of the present disclosure includes a first light-emitting control circuit and a second light-emitting control circuit; a second end of the driving circuit is electrically connected to the first pole of the light-emitting element through the second light-emitting control circuit;

[0012] The first light-emitting control circuit is electrically connected to a light-emitting control line, the first voltage terminal, and a first end of the driving circuit respectively, and is configured to control connection or disconnection between the first voltage terminal and the first end of the driving circuit under the control of a light-emitting control signal provided by the light-emitting control line;

[0013] The second light-emitting control circuit is electrically connected to the light-emitting control line, the second end of the driving circuit, and the first pole of the light-emitting element respectively, and is configured to control connection or disconnection between the second end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal.

[0014] Optionally, the energy storage control line includes the light-emitting control line and a connection / disconnection control line; the energy storage control circuit includes a first control sub-circuit and a second control sub-circuit;

[0015] The second control sub-circuit is electrically connected to the connection / disconnection control line, the first voltage terminal, and a second end of the energy storage circuit respectively, and is configured to control connection or disconnection between the first voltage terminal and the second end of the energy storage circuit under the control of a connection / disconnection control signal provided by the connection / disconnection control line;

[0016] The first control sub-circuit is electrically connected to the light-emitting control line, the first voltage terminal, and the second end of the energy storage circuit respectively, and is configured to respond to the control of the second control sub-circuit and control connection or disconnection between the first voltage terminal and the second end of the energy storage circuit under the control of the light-emitting control signal.

[0017] Optionally, the energy storage control circuit includes a first transistor;

[0018] A control pole of the first transistor is electrically connected to the energy storage control line, a first pole of the first transistor is electrically connected to the first voltage terminal, and a second pole of the first transistor is electrically connected to the second end of the energy storage circuit.

[0019] Optionally, the first control sub-circuit includes a first transistor, and the second control sub-circuit includes a second transistor;

[0020] The control electrode of the first transistor is electrically connected to the light-emitting control line, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the second terminal of the energy storage circuit;

[0021] The control electrode of the second transistor is electrically connected to the on-off control line, the first electrode of the second transistor is electrically connected to the first voltage terminal, and the second electrode of the second transistor is electrically connected to the second terminal of the energy storage circuit.

[0022] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit and a compensation control circuit;

[0023] The data writing circuit is respectively electrically connected to the writing control line, the data line and the first terminal of the driving circuit, and is configured to write the data voltage provided by the data line into the first terminal of the driving circuit under the control of the writing control signal provided by the writing control line;

[0024] The compensation control circuit is respectively electrically connected to the compensation control line, the control terminal of the driving circuit and the second terminal of the driving circuit, and is configured to control the connection or disconnection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the compensation control signal provided by the compensation control line.

[0025] Optionally, the transistors included in the second initialization circuit and the transistors included in the data writing circuit are both p-type transistors, or the transistors included in the second initialization circuit and the transistors included in the data writing circuit are both n-type transistors;

[0026] The writing control line and the second initialization control line are connected to the same control signal.

[0027] Optionally, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor;

[0028] The control electrode of the third transistor is electrically connected to the first initialization control line, the first electrode of the third transistor is electrically connected to the first initial voltage terminal, and the second electrode of the third transistor is electrically connected to the control terminal of the driving circuit;

[0029] The control electrode of the fourth transistor is electrically connected to the second initialization control line, the first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light-emitting element.

[0030] Optionally, the first light-emitting control circuit includes a fifth transistor, the second light-emitting control circuit includes a sixth transistor, and the energy storage circuit includes a storage capacitor;

[0031] The control electrode of the fifth transistor is electrically connected to the light-emitting control line, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first end of the driving circuit;

[0032] The control electrode of the sixth transistor is electrically connected to the light-emitting control line, the first electrode of the sixth transistor is electrically connected to the second end of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element;

[0033] The first end of the storage capacitor is electrically connected to the control end of the driving circuit, and the second end of the storage capacitor is the second end of the energy storage circuit.

[0034] Optionally, the data writing circuit includes a seventh transistor, and the compensation control circuit includes an eighth transistor;

[0035] The control electrode of the seventh transistor is electrically connected to the writing control line, the first electrode of the seventh transistor is electrically connected to the data line, and the second electrode of the seventh transistor is electrically connected to the first end of the driving circuit;

[0036] The control electrode of the eighth transistor is electrically connected to the compensation control line, the first electrode of the eighth transistor is electrically connected to the control end of the driving circuit, and the second electrode of the eighth transistor is electrically connected to the second end of the driving circuit.

[0037] In a second aspect, an embodiment of the present disclosure provides a pixel driving method, which is applied to the above pixel circuit. The display period includes a refresh frame and at least one holding frame; the refresh frame and the holding frame respectively include an initialization stage, a data writing stage, and a light-emitting stage; the pixel driving method includes:

[0038] In the refresh frame, the energy storage control circuit controls, under the control of the energy storage control signal, the connection between the second end of the energy storage circuit and the first voltage terminal;

[0039] In the initialization stage included in the holding frame and the data writing stage included in the holding frame, the energy storage control circuit controls, under the control of the energy storage control signal, the disconnection between the second end of the energy storage circuit and the first voltage terminal;

[0040] In the light-emitting stage included in the holding frame, the energy storage control circuit controls, under the control of the energy storage control signal, the connection between the second end of the energy storage circuit and the first voltage terminal.

[0041] Optionally, the pixel circuit further includes a second initialization circuit, a data writing circuit, and a compensation control circuit; the pixel driving method further includes:

[0042] In the initialization stage, a first initialization circuit writes a first initial voltage to a control terminal of the driving circuit under the control of a first initialization control signal, so that at the start of the data writing stage, the driving circuit can be controlled by the potential of its control terminal to connect a first end of the driving circuit to a second end of the driving circuit;

[0043] In the data writing stage, a second initialization circuit writes a second initial voltage to a first pole of the light-emitting element under the control of a second initialization control signal to reset the first pole of the light-emitting element;

[0044] In the data writing stage included in the refresh frame, a data line provides a data voltage, and a data writing circuit writes the data voltage to a first end of the driving circuit under the control of a writing control signal; a compensation control circuit controls the connection between a control terminal of the driving circuit and a second end of the driving circuit under the control of a compensation control signal.

[0045] Optionally, the energy storage control circuit includes a first control sub-circuit and a second control sub-circuit; the pixel driving method includes:

[0046] In a refresh frame, the second control sub-circuit controls the connection between a second end of the energy storage circuit and the first voltage terminal under the control of a on-off control signal;

[0047] In the initialization stage and the data writing stage included in the holding frame, the first control sub-circuit controls the disconnection between a second end of the energy storage circuit and the first voltage terminal under the control of a light-emitting control signal; the second control sub-circuit controls the disconnection between a second end of the energy storage circuit and the first voltage terminal under the control of a on-off control signal;

[0048] In the light-emitting stage included in the holding frame, the first control sub-circuit controls the connection between a second end of the energy storage circuit and the first voltage terminal under the control of a light-emitting control signal.

[0049] In a third aspect, an embodiment of the present disclosure provides a display device including the above pixel circuit. Description of the Drawings

[0050] Figure 1 is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0051] Figure 2 is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0052] Figure 3 is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0053] Figure 4 It is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0054] Figure 5 It is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0055] Figure 6 It is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0056] Figure 7 It is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0057] Figure 8 It is as described in the present disclosure Figure 7 The working timing diagram of at least one embodiment of the pixel circuit shown in the refresh frame;

[0058] Figure 9 It is as described in the present disclosure Figure 7 The working timing diagram of at least one embodiment of the pixel circuit shown in the hold frame;

[0059] Figure 10 It is as described in the present disclosure Figure 7 The working timing diagram of at least one embodiment of the pixel circuit shown in the hold frame;

[0060] Figure 11 It is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0061] Figure 12 It is as described in the present disclosure Figure 11 The working timing diagram of at least one embodiment of the pixel circuit shown in the hold frame;

[0062] Figure 13 It is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0063] Figure 14 It is as described in the present disclosure Figure 13 The working timing diagram of at least one embodiment of the pixel circuit shown in the refresh frame;

[0064] Figure 15 It is as described in the present disclosure Figure 13 The working timing diagram of at least one embodiment of the pixel circuit shown in the hold frame;

[0065] Figure 16 It is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0066] Figure 17 It is as described in the present disclosure Figure 16 The working timing diagram of at least one embodiment of the pixel circuit shown in the refresh frame;

[0067] Figure 18 is the operating timing diagram of at least one embodiment of the pixel circuit as Figure 16 shown for maintaining a frame. Detailed implementation mode

[0068] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0069] As Figure 1 shown, the pixel circuit described in the embodiments of the present disclosure includes an energy storage control circuit 11, an energy storage circuit 12, a first initialization circuit 13, a driving circuit 15, and a light emitting element 10; the display cycle of the pixel circuit includes a refresh frame and at least one hold frame, and the refresh frame and the hold frame respectively include an initialization stage, a data writing stage, and a light emitting stage;

[0070] The first initialization circuit 13 is respectively electrically connected to a first initialization control line NS(N - 1), a first initial voltage terminal I1, and a control end of the driving circuit 15, and is configured to write a first initial voltage Vi1 provided by the first initial voltage terminal I1 into the control end of the driving circuit 15 under the control of a first initialization control signal provided by the first initialization control line NS(N - 1) to reset the control end of the driving circuit 15.

[0071] A first end of the energy storage circuit 12 is electrically connected to the control end of the driving circuit 15, and the energy storage circuit 12 is configured to store electrical energy.

[0072] The energy storage control circuit 11 is respectively electrically connected to an energy storage control line S(N), a second end of the energy storage circuit 12, and a first voltage terminal V1, and is configured to control the connection between the second end of the energy storage circuit 12 and the first voltage terminal V1 under the control of an energy storage control signal provided by the energy storage control line S(N) during the refresh frame, and is configured to control the disconnection between the second end of the energy storage circuit 12 and the first voltage terminal V1 under the control of the energy storage control signal during the initialization stage and the data writing stage included in the hold frame.

[0073] The driving circuit 15 is electrically connected to a first pole of the light emitting element 10, and the driving circuit 15 is configured to drive the light emitting element 10 under the control of the potential of its control end.

[0074] A second pole of the light emitting element 10 is electrically connected to a second voltage terminal V2.

[0075] In at least one embodiment of the present disclosure, the first voltage terminal V1 may be a high voltage terminal, the second voltage terminal V2 may be a low voltage terminal, and the light-emitting element 10 may be an OLED (organic light-emitting diode), but is not limited thereto.

[0076] As described in the present disclosure Figure 1 When the embodiment of the pixel circuit shown is in operation, the display period may include a refresh frame and at least one hold frame; the hold frame and the refresh frame each include an initialization stage, a data writing stage, and a light-emitting stage;

[0077] In the refresh frame, under the control of a charge storage control signal, the charge storage control circuit 11 controls the connection between the second terminal of the charge storage circuit 12 and the first voltage terminal V1, and at this time the pixel circuit operates normally;

[0078] In the initialization stage included in the hold frame and the data writing stage included in the hold frame, under the control of a charge storage control signal, the charge storage control circuit 11 controls the disconnection between the second terminal of the charge storage circuit 12 and the first voltage terminal V1 to avoid charging and discharging the charge storage circuit 12 and causing the voltage stored in the charge storage circuit 12 to be rewritten;

[0079] In the initialization stage included in the hold frame, under the control of a first initialization control signal, the first initialization circuit 13 writes a first initial voltage Vi1 to the control terminal of the driving circuit 15, so that at the start of the data writing stage, the driving circuit 15 can control the connection between the first terminal and the second terminal of the driving circuit 15 under the control of the potential of its control terminal;

[0080] In the light-emitting stage included in the hold frame, under the control of a charge storage control signal, the charge storage control circuit 11 controls the connection between the second terminal of the charge storage circuit 12 and the first voltage terminal V1.

[0081] As described in the present disclosure Figure 1 When the embodiment of the pixel circuit shown is in operation, in both the refresh frame and the hold frame, the control terminal of the driving circuit 15 is reset, thereby reducing the brightness difference between the refresh frame and the hold frame and improving the Flicker phenomenon during low-frequency display or variable-frequency driving. And the pixel circuit described in the embodiment of the present disclosure can achieve low-frequency driving and reduce the power consumption of the IC (integrated circuit).

[0082] In related technologies, in order to reduce power consumption, LTPO (Low Temperature Polycrystalline Oxide) technology has been increasingly widely used. In a related display device, when using an LTPO pixel circuit to reduce leakage, a Flicker phenomenon is still visually observable during low-frequency display and variable-frequency driving. Based on this, in the embodiments of the present disclosure, by resetting the control terminal of the driving circuit 15 in both the refresh frame and the hold frame, the Flicker phenomenon during low-frequency display or variable-frequency driving is improved.

[0083] As Figure 2 shown, based on the embodiment of the pixel circuit as Figure 1 shown, the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit 14;

[0084] The second initialization circuit 14 is respectively electrically connected to a second initialization control line P0, a second initial voltage terminal I2, and a first pole of the light-emitting element 10, and is configured to write a second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first pole of the light-emitting element 10 under the control of a second initialization control signal provided by the second initialization control line P0.

[0085] As in the present disclosure Figure 2 shown, when the pixel circuit according to at least one embodiment of the present disclosure is operating, during the data writing stage included in the hold frame, the second initialization circuit 14 writes the second initial voltage Vi2 into the first pole of the light-emitting element 10 under the control of the second initialization control signal to reset the first pole of the light-emitting element 10.

[0086] As in the present disclosure Figure 2 shown, when the pixel circuit according to at least one embodiment of the present disclosure is operating, in both the refresh frame and the hold frame, the first pole of the light-emitting element 10 is reset, thereby reducing the brightness difference between the refresh frame and the hold frame and improving the Flicker phenomenon during low-frequency display or variable-frequency driving.

[0087] In at least one embodiment of the present disclosure, the second initialization circuit 14 writes the second initial voltage Vi2 into the first pole of the light-emitting element 10 under the control of the second initialization control signal to reset the first pole of the light-emitting element 10, which can control the light-emitting element 10 not to emit light, but not limited thereto.

[0088] As Figure 3 shown, based on the embodiment of the pixel circuit as Figure 2 shown, the pixel circuit according to at least one embodiment of the present disclosure further includes a first light-emitting control circuit 21 and a second light-emitting control circuit 22; a second end of the driving circuit 15 is electrically connected to the first pole of the light-emitting element 10 through the second light-emitting control circuit 22;

[0089] The first light-emitting control circuit 21 is electrically connected to the light-emitting control line E1, the first voltage terminal V1, and the first end of the driving circuit 15 respectively, and is configured to control the connection or disconnection between the first voltage terminal V1 and the first end of the driving circuit 15 under the control of the light-emitting control signal provided by the light-emitting control line E1;

[0090] The second light-emitting control circuit 22 is electrically connected to the light-emitting control line E1, the second end of the driving circuit 15, and the first pole of the light-emitting element 10 respectively, and is configured to control the connection or disconnection between the second end of the driving circuit 15 and the first pole of the light-emitting element 10 under the control of the light-emitting control signal.

[0091] At least one embodiment of the pixel circuit as disclosed in the present disclosure Figure 3 When working, in the light-emitting stage, the first light-emitting control circuit 21 controls the connection between the first voltage terminal V1 and the first end of the driving circuit 15 under the control of the light-emitting control signal, and the second light-emitting control circuit 22 controls the connection between the second end of the driving circuit 15 and the first pole of the light-emitting element 10 under the control of the light-emitting control signal.

[0092] In at least one embodiment of the present disclosure, as Figure 4 shown, based on at least one embodiment of the pixel circuit as Figure 3 shown, the energy storage control line includes the light-emitting control line E1 and the on-off control line Tc; the energy storage control circuit includes a first control sub-circuit 31 and a second control sub-circuit 32;

[0093] The second control sub-circuit 32 is electrically connected to the on-off control line Tc, the first voltage terminal V1, and the second end of the energy storage circuit 12 respectively, and is configured to control the connection or disconnection between the first voltage terminal V1 and the second end of the energy storage circuit 12 under the control of the on-off control signal provided by the on-off control line Tc;

[0094] The first control sub-circuit 31 is electrically connected to the light-emitting control line E1, the first voltage terminal V1, and the second end of the energy storage circuit 12 respectively, and is configured to respond to the control of the second control sub-circuit 32 and control the connection or disconnection between the first voltage terminal V1 and the second end of the energy storage circuit 12 under the control of the light-emitting control signal. At least one embodiment of the pixel circuit as disclosed in the present disclosure Figure 4 When working, the display period may include a refresh frame and at least one hold frame; the refresh frame and the hold frame respectively include an initialization stage, a data writing stage, and a light-emitting stage;

[0095] In the refresh frame, under the control of the on-off control signal, the second control sub-circuit 32 controls the connection between the first voltage terminal V1 and the second terminal of the energy storage circuit 12, and at this time, the pixel circuit operates normally;

[0096] In the initialization stage included in the holding frame and the data writing stage included in the holding frame, under the control of the on-off control signal, the second control sub-circuit 32 controls the disconnection between the first voltage terminal V1 and the second terminal of the energy storage circuit 12, and the first control sub-circuit 31 controls the disconnection between the first voltage terminal V1 and the second terminal of the energy storage circuit 12 under the control of the light emission control signal, so as to avoid charging and discharging the energy storage circuit 12 and causing the voltage stored in the energy storage circuit 12 to be rewritten;

[0097] In the initialization stage included in the holding frame, the first initialization circuit 13 writes the first initial voltage Vi1 to the control terminal of the driving circuit 15 under the control of the first initialization control signal, so that at the start of the data writing stage, the driving circuit 15 can control the connection between the first terminal and the second terminal of the driving circuit 15 under the control of the potential at its control terminal;

[0098] In the data writing stage included in the holding frame, the second initialization circuit 14 writes the second initial voltage Vi2 to the first pole of the light emitting element 10 under the control of the second initialization control signal to reset the light emitting element 10;

[0099] In the light emission stage included in the holding frame, the first control sub-circuit 31 controls the connection between the first voltage terminal V1 and the second terminal of the energy storage circuit 12 under the control of the light emission control signal.

[0100] As described in the present disclosure Figure 4 In at least one embodiment of the pixel circuit shown in the figure, when it works, the first control sub-circuit 31 responds to the control of the second control sub-circuit 32 and controls the connection or disconnection between the first voltage terminal V1 and the second terminal of the energy storage circuit 12 under the control of the light emission control signal;

[0101] Specifically, when the second control sub-circuit 32 controls the disconnection between the first voltage terminal V1 and the second terminal of the energy storage circuit 12 under the control of the on-off control signal, the first control sub-circuit 31 can control the connection or disconnection between the first voltage terminal V1 and the second terminal of the energy storage circuit 12 under the control of the light emission control signal;

[0102] When the second control sub - circuit 32 controls the connection between the first voltage terminal V1 and the second terminal of the energy - storage circuit 12, the first control sub - circuit 31 cannot control the connection or disconnection between the first voltage terminal V1 and the second terminal of the energy - storage circuit 12.

[0103] Optionally, the energy - storage control circuit includes a first transistor;

[0104] The control electrode of the first transistor is electrically connected to the energy - storage control line, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the second terminal of the energy - storage circuit.

[0105] Optionally, the first control sub - circuit includes a first transistor, and the second control sub - circuit includes a second transistor;

[0106] The control electrode of the first transistor is electrically connected to the light - emitting control line, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the second terminal of the energy - storage circuit;

[0107] The control electrode of the second transistor is electrically connected to the on - off control line, the first electrode of the second transistor is electrically connected to the first voltage terminal, and the second electrode of the second transistor is electrically connected to the second terminal of the energy - storage circuit.

[0108] The pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit and a compensation control circuit;

[0109] The data writing circuit is electrically connected to the writing control line, the data line, and the first terminal of the driving circuit respectively, and is configured to write the data voltage provided by the data line into the first terminal of the driving circuit under the control of the writing control signal provided by the writing control line for data voltage writing;

[0110] The compensation control circuit is electrically connected to the compensation control line, the control terminal of the driving circuit, and the second terminal of the driving circuit respectively, and is configured to control the connection or disconnection between the control terminal and the second terminal of the driving circuit under the control of the compensation control signal provided by the compensation control line for threshold voltage compensation.

[0111] As Figure 5 shown, on the basis of at least one embodiment of the pixel circuit shown in Figure 3 the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 41 and a compensation control circuit 42;

[0112] The data writing circuit 41 is electrically connected to the write control line PS(N), the data line D1, and the first end of the driving circuit 15 respectively, and is configured to write the data voltage Vdata provided by the data line D1 into the first end of the driving circuit 15 under the control of the write control signal provided by the write control line PS(N) for data voltage writing.

[0113] The compensation control circuit 42 is electrically connected to the compensation control line NS(N), the control end of the driving circuit 15, and the second end of the driving circuit 15 respectively, and is configured to control the connection or disconnection between the control end of the driving circuit 15 and the second end of the driving circuit 15 under the control of the compensation control signal provided by the compensation control line NS(N) for threshold voltage compensation.

[0114] The present disclosure Figure 5 When at least one embodiment of the pixel circuit shown is operating,

[0115] In the data writing stage included in the refresh frame, the data line D1 provides a data voltage, and the data writing circuit 41 writes the data voltage Vdata into the first end of the driving circuit 15 under the control of the write control signal; the compensation control circuit 42 controls the connection between the control end of the driving circuit 15 and the second end of the driving circuit 15 under the control of the compensation control signal.

[0116] As Figure 6 shown, based on at least one embodiment of the pixel circuit shown, at least one embodiment of the pixel circuit according to the present disclosure further includes a data writing circuit 41 and a compensation control circuit 42; Figure 4 The data writing circuit 41 is electrically connected to the write control line PS(N), the data line D1, and the first end of the driving circuit 15 respectively, and is configured to write the data voltage Vdata provided by the data line D1 into the first end of the driving circuit 15 under the control of the write control signal provided by the write control line PS(N) for data voltage writing.

[0117] The data writing circuit 41 is electrically connected to the write control line PS(N), the data line D1, and the first end of the driving circuit 15 respectively, and is configured to write the data voltage Vdata provided by the data line D1 into the first end of the driving circuit 15 under the control of the write control signal provided by the write control line PS(N) for data voltage writing.

[0118] The compensation control circuit 42 is electrically connected to the compensation control line NS(N), the control end of the driving circuit 15, and the second end of the driving circuit 15 respectively, and is configured to control the connection or disconnection between the control end of the driving circuit 15 and the second end of the driving circuit 15 under the control of the compensation control signal provided by the compensation control line NS(N) for threshold voltage compensation.

[0119] The present disclosure Figure 5 When at least one embodiment of the pixel circuit shown is operating,

[0120] In the data writing stage included in the refresh frame, the data line D1 provides a data voltage, and under the control of the write control signal, the data writing circuit 41 writes the data voltage Vdata into the first end of the driving circuit; the compensation control circuit 42 controls the connection between the control end and the second end of the driving circuit 15 under the control of the compensation control signal.

[0121] Optionally, the transistors included in the second initialization circuit and the transistors included in the data writing circuit are both p-type transistors, or the transistors included in the second initialization circuit and the transistors included in the data writing circuit are both n-type transistors;

[0122] The write control line and the second initialization control line can be connected to the same control signal.

[0123] Optionally, the first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor;

[0124] The control electrode of the third transistor is electrically connected to the first initialization control line, the first electrode of the third transistor is electrically connected to the first initial voltage terminal, and the second electrode of the third transistor is electrically connected to the control end of the driving circuit;

[0125] The control electrode of the fourth transistor is electrically connected to the second initialization control line, the first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light-emitting element.

[0126] Optionally, the first light-emitting control circuit includes a fifth transistor, the second light-emitting control circuit includes a sixth transistor, and the energy storage circuit includes a storage capacitor;

[0127] The control electrode of the fifth transistor is electrically connected to the light-emitting control line, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first end of the driving circuit;

[0128] The control electrode of the sixth transistor is electrically connected to the light-emitting control line, the first electrode of the sixth transistor is electrically connected to the second end of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element;

[0129] The first end of the storage capacitor is electrically connected to the control end of the driving circuit, and the second end of the storage capacitor is the second end of the energy storage circuit.

[0130] Optionally, the data writing circuit includes a seventh transistor, and the compensation control circuit includes an eighth transistor;

[0131] The control electrode of the seventh transistor is electrically connected to the write control line, the first electrode of the seventh transistor is electrically connected to the data line, and the second electrode of the seventh transistor is electrically connected to the first end of the driving circuit;

[0132] The control electrode of the eighth transistor is electrically connected to the compensation control line, the first electrode of the eighth transistor is electrically connected to the control end of the driving circuit, and the second electrode of the eighth transistor is electrically connected to the second end of the driving circuit.

[0133] As Figure 7 shown, based on at least one embodiment of the pixel circuit shown in Figure 5 the energy storage control circuit 11 includes a first transistor T1, the first initialization circuit 13 includes a third transistor T3, and the second initialization circuit 14 includes a fourth transistor T4; the energy storage circuit 12 includes a storage capacitor C1; the driving circuit 15 includes a driving transistor T0; the light-emitting element is an organic light-emitting diode O1;

[0134] The gate of the first transistor T1 is electrically connected to the energy storage control line S(N), the source of the first transistor T1 is electrically connected to the high voltage terminal ELVDD, and the drain of the first transistor T1 is electrically connected to the second end of the storage capacitor C1; the first end of the storage capacitor C1 is electrically connected to the gate of the driving transistor T0;

[0135] The gate of the third transistor T3 is electrically connected to the first initialization control line NS(N - 1), the source of the third transistor T3 is electrically connected to the first initial voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the gate of the driving transistor T0;

[0136] The gate of the fourth transistor T4 is electrically connected to the write control line PS(N), the source of the fourth transistor T4 is electrically connected to the second initial voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the anode of the organic light-emitting diode O1;

[0137] The first light emission control circuit 21 includes a fifth transistor T5, and the second light emission control circuit 22 includes a sixth transistor T6;

[0138] The gate of the fifth transistor T5 is electrically connected to the light emission control line E1, the source of the fifth transistor T5 is electrically connected to the high voltage terminal ELVDD, and the drain of the fifth transistor T5 is electrically connected to the source of the driving transistor T0;

[0139] The gate of the sixth transistor T6 is electrically connected to the light emission control line E1, the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the drain of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1;

[0140] The data writing circuit 41 includes a seventh transistor T7, and the compensation control circuit 42 includes an eighth transistor T8;

[0141] The gate of the seventh transistor T7 is electrically connected to the writing control line PS(N), the source of the seventh transistor T7 is electrically connected to the data line D1, and the drain of the seventh transistor T7 is electrically connected to the source of the driving transistor T0;

[0142] The gate of the eighth transistor T8 is electrically connected to the compensation control line NS(N), the source of the eighth transistor T8 is electrically connected to the gate of the driving transistor T0, and the drain of the eighth transistor T8 is electrically connected to the drain of the driving transistor T0;

[0143] The cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS.

[0144] In Figure 7 In at least one embodiment of the pixel circuit shown, T1, T3, and T8 are all n-type thin film transistors, and T0, T4, T5, T6, and T7 are all p-type thin film transistors.

[0145] In Figure 7 Co is the parasitic capacitance between the anode and the cathode of O1, and the first node N1 is electrically connected to the gate of T0.

[0146] As Figure 8 shown, in the refresh frame F1, when at least one embodiment of the pixel circuit shown in Figure 7 works, S(N) provides a high voltage signal and T1 is turned on. At this time, Figure 7 at least one embodiment of the pixel circuit shown is equivalent to a common LTPO (low temperature polycrystalline oxide) 7T1C pixel circuit.

[0147] As Figure 8 shown, when at least one embodiment of the pixel circuit of the present disclosure shown in Figure 7 works,

[0148] In the initialization stage S71 included in the refresh frame F1, NS(N - 1) provides a high - voltage signal, NS(N) provides a low - voltage signal, PS(N) provides a high - voltage signal, E1 provides a high - voltage signal, I1 provides a first initial voltage Vi1, T3 is turned on, T4 is turned off, to write Vi1 to the gate of T0, so that T0 can be turned on at the start of the data writing stage S72 included in the refresh frame; T8 is turned off, T7 is turned off, T5 and T6 are turned off;

[0149] In the data writing stage S72 included in the refresh frame F1, NS(N - 1) provides a low - voltage signal, NS(N) provides a high - voltage signal, PS(N) provides a low - voltage signal, E1 provides a high - voltage signal, T3 is turned off, T4 is turned on, I2 provides a second initial voltage Vi2, to write Vi2 to the anode of O1, to reset the anode of O1; the data line D1 provides a data voltage Vdata; T7 and T8 are turned on; T5 and T6 are turned off;

[0150] At the start of the data writing stage S72 included in the refresh frame F1, T0 is turned on, to charge C1 through Vdata, to change the potential of the first node N1 until the gate potential of T0 becomes Vdata + Vth, and T0 is turned off, where Vth is the threshold voltage of T0;

[0151] In the light - emitting stage S73 included in the refresh frame F1, both NS(N - 1) and NS(N) provide low - voltage signals, PS(N) provides a high - voltage signal, E1 provides a low - voltage signal, T3, T4, T7 and T8 are turned off, T5 and T6 are turned on, and T0 drives O1 to emit light.

[0152] As Figure 9 shown, when at least one embodiment of the pixel circuit as Figure 7 shown in the present disclosure operates,

[0153] In the initialization stage S81 included in the hold frame F2, S(N) provides a low - voltage signal, NS(N - 1) provides a high - voltage signal, NS(N) provides a low - voltage signal, PS(N) provides a high - voltage signal, E1 provides a high - voltage signal, T1 is turned off, I1 provides a first initial voltage Vi1, T3 is turned on, to write Vi1 to the first node N1, so that T0 can be turned on at the start of the data writing stage S82 included in the hold frame; T4 is turned off; T8 is turned off, T7 is turned off, T5 and T6 are turned off;

[0154] In the data writing phase S82 included in the frame F2, S(N) provides a low voltage signal, NS(N-1) provides a low voltage signal, NS(N) provides a high voltage signal, PS(N) provides a low voltage signal, E1 provides a high voltage signal, I2 provides a second initial voltage Vi2, T1 is turned off, T3 is turned off, and T4 is turned on to write Vi2 into the anode of O1, so that the anode of O1 is reset; T7 is turned on; T8 is turned on; T5 and T6 are turned off; in the light-emitting phase S83 included in the frame F2, S(N) provides a high voltage signal, NS(N-1) provides a low voltage signal, NS(N) provides a low voltage signal, PS(N) provides a high voltage signal, E1 provides a low voltage signal, T3, T4, T7 and T8 are turned off, T5 and T6 are turned on, and O1 maintains the light-emitting state.

[0155] This disclosure Figure 7 When at least one embodiment of the pixel circuit shown is in operation, the gate of T0 and the anode of O1 are reset in both the refresh frame and the hold frame, thereby reducing the brightness difference caused by the different resetting of the parasitic capacitance Co of O1 and the different threshold voltage drift process of T0 in the refresh frame and the hold frame.

[0156] like Figure 10 As shown, the present disclosure is Figure 7 When at least one embodiment of the pixel circuit shown is in operation, in a holding frame, the energy storage control signal provided by S(N) may be inverted and have the same bandwidth as the light emission control signal provided by E1.

[0157] In at least one embodiment of the present disclosure, the present disclosure is as follows Figure 7 In at least one embodiment of the pixel circuit shown, when E1 provides a low voltage signal, S(N) needs to provide a high voltage signal for the following reasons:

[0158] If in the light-emitting stage, when T0 drives O1 to emit light, T1 is turned off, the first node N1 is floating, and the potential of the first node N1 is uncertain, which will affect the display. Therefore, when O1 emits light, T1 needs to be turned on.

[0159] At least one embodiment of the pixel circuit shown in FIG11 of the present disclosure is similar to that of the pixel circuit shown in FIG11 of the present disclosure. Figure 7 The difference of at least one embodiment of the pixel driving circuit shown is that T1 is a p-type thin film transistor.

[0160] Figure 12 FIG. 11 is a timing diagram of the operation of at least one embodiment of the pixel circuit of the present disclosure in a hold frame.

[0161] like Figure 13 As shown, in Figure 6Based on at least one embodiment of the pixel circuit shown, the first control sub - circuit includes a first transistor T1, and the second control sub - circuit includes a second transistor T2; the first initialization circuit 13 includes a third transistor T3, and the second initialization circuit includes a fourth transistor T4; the energy storage circuit 12 includes a storage capacitor C1; the driving circuit 15 includes a driving transistor T0; the light - emitting element is an organic light - emitting diode O1;

[0162] The gate of the first transistor T1 is electrically connected to the light - emitting control line E1, the source of the first transistor T1 is electrically connected to the high - voltage terminal ELVDD, and the drain of the first transistor T1 is electrically connected to the second terminal of the storage capacitor C1;

[0163] The gate of the second transistor T2 is electrically connected to the on - off control line Tc, the source of the second transistor T2 is electrically connected to the high - voltage terminal ELVDD, and the drain of the second transistor T2 is electrically connected to the second terminal of the storage capacitor C1;

[0164] The gate of the third transistor T3 is electrically connected to the first initialization control line NS(N - 1), the source of the third transistor T3 is electrically connected to the first initial - voltage terminal I1, and the drain of the third transistor T3 is electrically connected to the gate of the driving transistor T0;

[0165] The gate of the fourth transistor T4 is electrically connected to the write control line PS(N), the source of the fourth transistor T4 is electrically connected to the second initial - voltage terminal I2, and the drain of the fourth transistor T4 is electrically connected to the anode of the organic light - emitting diode O1;

[0166] The first light - emitting control circuit 21 includes a fifth transistor T5, and the second light - emitting control circuit 22 includes a sixth transistor T6;

[0167] The gate of the fifth transistor T5 is electrically connected to the light - emitting control line E1, the source of the fifth transistor T5 is electrically connected to the high - voltage terminal ELVDD, and the drain of the fifth transistor T5 is electrically connected to the source of the driving transistor T0;

[0168] The gate of the sixth transistor T6 is electrically connected to the light - emitting control line E1, the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the drain of the sixth transistor T6 is electrically connected to the anode of the organic light - emitting diode O1;

[0169] The data writing circuit 41 includes a seventh transistor T7, and the compensation control circuit 42 includes an eighth transistor T8;

[0170] The gate of the seventh transistor T7 is electrically connected to the write control line PS(N), the source of the seventh transistor T7 is electrically connected to the data line D1, and the drain of the seventh transistor T7 is electrically connected to the source of the driving transistor T0;

[0171] The gate of the eighth transistor T8 is electrically connected to the compensation control line NS(N), the source of the eighth transistor T8 is electrically connected to the gate of the driving transistor T0, and the drain of the eighth transistor T8 is electrically connected to the drain of the driving transistor T0;

[0172] The cathode of the organic light-emitting diode O1 is electrically connected to the low voltage terminal ELVSS.

[0173] In Figure 13 In at least one embodiment of the pixel circuit shown, T2, T3, and T8 are all n-type thin film transistors, and T0, T1, T4, T5, T6, and T7 are all p-type thin film transistors.

[0174] In Figure 13 Co is the parasitic capacitance between the anode and the cathode of O1, and the first node N1 is electrically connected to the gate of T0.

[0175] In Figure 13 N1 labeled is the first node.

[0176] As Figure 14 shown, Tc provides a high voltage signal and T2 conducts. At this time, Figure 13 At least one embodiment of the pixel circuit shown is equivalent to a common LTPO (low temperature polycrystalline oxide) 7T1C pixel circuit for refreshing the frame.

[0177] As Figure 14 shown, when at least one embodiment of the pixel circuit of the present disclosure as Figure 13 shown operates,

[0178] In the initialization stage S71 included in the refresh frame F1, NS(N - 1) provides a high voltage signal, NS(N) provides a low voltage signal, PS(N) provides a high voltage signal, E1 provides a high voltage signal, I1 provides the first initial voltage Vi1, T3 conducts, T4 turns off, so as to write Vi1 to the gate of T0, so that T0 can conduct at the start of the data writing stage S72 included in the refresh frame; T8 turns off, T7 turns off, T5 and T6 turn off; T1 turns off;

[0179] In the data writing stage S72 included in the refresh frame F1, NS(N-1) provides a low voltage signal, NS(N) provides a high voltage signal, PS(N) provides a low voltage signal, E1 provides a high voltage signal, T3 is turned off, T4 is turned on, I2 provides a second initial voltage Vi2 to write Vi2 to the anode of O1 and reset the anode of O1; the data line D1 provides a data voltage Vdata; T7 and T8 are turned on; T5 and T6 are turned off; T1 is turned off;

[0180] At the start of the data writing stage S72 included in the refresh frame F1, T0 is turned on to charge C1 through Vdata to change the potential of the first node N1 until the gate potential of T0 becomes Vdata+Vth, and then T0 is turned off, where Vth is the threshold voltage of T0;

[0181] In the light emitting stage S73 included in the refresh frame F1, both NS(N-1) and NS(N) provide low voltage signals, PS(N) provides a high voltage signal, E1 provides a low voltage signal, T3, T4, T7 and T8 are turned off, T1, T5 and T6 are turned on, and T0 drives O1 to emit light.

[0182] As Figure 15 shown, when at least one embodiment of the pixel circuit as Figure 13 shown in the present disclosure operates, Tc provides a low voltage signal and T2 is turned off. At this time, the pixel circuit is in the hold frame F2 state;

[0183] In the initialization stage S81 included in the hold frame F2, NS(N-1) provides a high voltage signal, NS(N) provides a low voltage signal, PS(N) provides a high voltage signal, E1 provides a high voltage signal, T1 is turned off, I1 provides a first initial voltage Vi1, T3 is turned on to write Vi1 to the first node N1 so that T0 can be turned on at the start of the data writing stage S82 included in the hold frame; T4 is turned off; T8 is turned off, T7 is turned off, T5 and T6 are turned off;

[0184] In the data writing stage S82 included in the hold frame F2, NS(N-1) provides a low voltage signal, NS(N) provides a high voltage signal, PS(N) provides a low voltage signal, E1 provides a high voltage signal, I2 provides a second initial voltage Vi2, T1 is turned off, T3 is turned off, T4 is turned on to write Vi2 to the anode of O1 to reset the anode of O1; T7 is turned on; T8 is turned on; T5 and T6 are turned off;

[0185] In the light emitting stage S83 included in the hold frame F2, NS(N-1) provides a low voltage signal, NS(N) provides a low voltage signal, PS(N) provides a high voltage signal, E1 provides a low voltage signal, T1 is turned on, T3, T4, T7 and T8 are turned off, T5 and T6 are turned on, and O1 maintains the light emitting state.

[0186] In at least one embodiment of the pixel circuit as Figure 13 shown, during operation, in both the refresh frame and the hold frame, the gate of T0 and the anode of O1 are reset, thereby reducing the brightness difference caused by the different resetting of the parasitic capacitance Co of O1 and the different threshold voltage drift processes of T0 between the refresh frame and the hold frame.

[0187] At least one embodiment of the pixel circuit as shown in 16 of the present disclosure is different from at least one embodiment of the pixel driving circuit as Figure 13 shown in that: T2 is a p-type thin film transistor.

[0188] Figure 17 For at least one embodiment of the pixel circuit as Figure 16 shown, it is a timing diagram of the operation in the refresh frame F1; in the refresh frame F1, Tc provides a low voltage signal to turn on T2.

[0189] Figure 18 For at least one embodiment of the pixel circuit as Figure 16 shown, it is a timing diagram of the operation in the hold frame F2; in the hold frame F2, Tc provides a high voltage signal to turn off T2.

[0190] In at least one embodiment of the pixel circuit as Figure 13 shown, during operation, a light-emitting control line is used to control T1, and there is no need to use an additional GOA (gate on array) circuit to generate an energy storage control signal, which is beneficial to realizing a narrow border.

[0191] In at least one embodiment of the pixel circuit as Figure 13 shown, the on-off control signal provided by Tc does not need to be generated by a GOA circuit, and all the pixel circuits included in the display panel can be connected to the same on-off control signal; the on-off control signal is a signal for controlling refresh or hold. When T2 is off, the pixel circuit is in a hold state; when T2 is on, the pixel circuit is in a refresh state.

[0192] The pixel driving method according to the embodiments of the present disclosure is applied to the above-mentioned pixel circuit. The display period includes a refresh frame and at least one hold frame; the refresh frame and the hold frame respectively include an initialization stage, a data writing stage, and a light-emitting stage; the pixel driving method includes:

[0193] In the refresh frame, under the control of the energy storage control signal, the energy storage control circuit controls the connection between the second end of the energy storage circuit and the first voltage terminal;

[0194] In the initialization stage included in the holding frame and the data writing stage included in the holding frame, under the control of the energy storage control signal, the energy storage control circuit controls the disconnection between the second end of the energy storage circuit and the first voltage terminal;

[0195] In the light emitting stage included in the holding frame, under the control of the energy storage control signal, the energy storage control circuit controls the connection between the second end of the energy storage circuit and the first voltage terminal.

[0196] In at least one embodiment of the present disclosure, the pixel circuit may further include a second initialization circuit, a data writing circuit, and a compensation control circuit; the pixel driving method further includes:

[0197] In the initialization stage, the first initialization circuit writes a first initial voltage to the control terminal of the driving circuit under the control of the first initialization control signal, so that at the start of the data writing stage, the driving circuit can control the connection between the first end and the second end of the driving circuit under the control of the potential of its control terminal;

[0198] In the data writing stage, the second initialization circuit writes a second initial voltage to the first pole of the light emitting element under the control of the second initialization control signal to reset the first pole of the light emitting element;

[0199] In the data writing stage included in the refresh frame, the data line provides a data voltage, and the data writing circuit writes the data voltage to the first end of the driving circuit under the control of the writing control signal; the compensation control circuit controls the connection between the control terminal and the second end of the driving circuit under the control of the compensation control signal.

[0200] In the pixel driving method according to at least one embodiment of the present disclosure, in the refresh frame and the holding frame, the control terminal of the driving circuit and the first pole of the light emitting element are both reset, thereby reducing the brightness difference between the refresh frame and the holding frame and improving the Flicker phenomenon during low-frequency display or variable-frequency driving. And the pixel circuit according to the embodiment of the present disclosure can achieve low-frequency driving and reduce the power consumption of the IC (integrated circuit).

[0201] Optionally, the energy storage control circuit includes a first control sub-circuit and a second control sub-circuit; the pixel driving method according to at least one embodiment of the present disclosure includes:

[0202] In the refresh frame, the second control sub-circuit controls the connection between the second end of the energy storage circuit and the first voltage terminal under the control of the on-off control signal;

[0203] During the initialization stage included in the holding frame and the data writing stage included in the holding frame, under the control of the light emission control signal, the first control sub-circuit controls the disconnection between the second end of the energy storage circuit and the first voltage terminal; under the control of the on-off control signal, the second control sub-circuit controls the disconnection between the second end of the energy storage circuit and the first voltage terminal;

[0204] During the light emission stage included in the holding frame, under the control of the light emission control signal, the first control sub-circuit controls the connection between the second end of the energy storage circuit and the first voltage terminal.

[0205] The display device according to an embodiment of the present disclosure includes the above pixel circuit.

[0206] The display device according to at least one embodiment of the present disclosure may be an AMOLED (Active Matrix Organic Light Emitting Diode) display device, but is not limited thereto.

[0207] The display device provided by the embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0208] The above is the preferred embodiment of the present disclosure. It should be noted that for those of ordinary skill in the art, without departing from the principle described in the present disclosure, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present disclosure.

Claims

1. A pixel circuit, characterized in that, It includes an energy storage control circuit, an energy storage circuit, a first initialization circuit, a second initialization circuit, a driving circuit, and a light-emitting element; the display period of the pixel circuit includes a refresh frame and at least one holding frame, and the refresh frame and the holding frame respectively include an initialization stage, a data writing stage, and a light-emitting stage; The first initialization circuit is electrically connected to a first initialization control line, a first initial voltage terminal, and the control terminal of the driving circuit respectively, and is used for writing the first initial voltage provided by the first initial voltage terminal into the control terminal of the driving circuit under the control of the first initialization control signal provided by the first initialization control line; The first end of the energy storage circuit is electrically connected to the control terminal of the driving circuit, and the energy storage circuit is used for storing electrical energy; The energy storage control circuit is electrically connected to an energy storage control line, the second end of the energy storage circuit, and a first voltage terminal respectively, and is used for, in the refresh frame, controlling the connection between the second end of the energy storage circuit and the first voltage terminal under the control of the energy storage control signal provided by the energy storage control line, and is used for, in the initialization stage included in the holding frame and the data writing stage included in the holding frame, controlling the disconnection between the second end of the energy storage circuit and the first voltage terminal under the control of the energy storage control signal; The driving circuit is electrically connected to the first pole of the light-emitting element; the driving circuit is used for driving the light-emitting element under the control of the potential of its control terminal; The second pole of the light-emitting element is electrically connected to a second voltage terminal.

2. The pixel circuit according to claim 1, wherein It further includes a second initialization circuit; The second initialization circuit is electrically connected to a second initialization control line, a second initial voltage terminal, and the first pole of the light-emitting element respectively, and is used for writing the second initial voltage provided by the second initial voltage terminal into the first pole of the light-emitting element under the control of the second initialization control signal provided by the second initialization control line; 3. The pixel circuit according to claim 1, wherein It further includes a first light-emitting control circuit and a second light-emitting control circuit; the second end of the driving circuit is electrically connected to the first pole of the light-emitting element through the second light-emitting control circuit; The first light-emitting control circuit is electrically connected to a light-emitting control line, the first voltage terminal, and the first end of the driving circuit respectively, and is used for controlling the connection or disconnection between the first voltage terminal and the first end of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control line; The second light-emitting control circuit is electrically connected to the light-emitting control line, the second end of the driving circuit, and the first pole of the light-emitting element respectively, and is used for controlling the connection or disconnection between the second end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal; 4. The pixel circuit according to claim 3, wherein The energy storage control line includes the light-emitting control line and a connection / disconnection control line; the energy storage control circuit includes a first control sub-circuit and a second control sub-circuit; The second control sub-circuit is electrically connected to the connection / disconnection control line, the first voltage terminal, and the second end of the energy storage circuit respectively, and is used for controlling the connection or disconnection between the first voltage terminal and the second end of the energy storage circuit under the control of the connection / disconnection control signal provided by the connection / disconnection control line; The first control sub - circuit is electrically connected to the light - emitting control line, the first voltage terminal, and the second terminal of the energy - storage circuit respectively, and is configured to respond to the control of the second control sub - circuit and control the connection or disconnection between the first voltage terminal and the second terminal of the energy - storage circuit under the control of the light - emitting control signal.

5. The pixel circuit according to claim 1, wherein The energy - storage control circuit includes a first transistor; The control electrode of the first transistor is electrically connected to the energy - storage control line, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the second terminal of the energy - storage circuit.

6. The pixel circuit according to claim 4, wherein The first control sub - circuit includes a first transistor, and the second control sub - circuit includes a second transistor; The control electrode of the first transistor is electrically connected to the light - emitting control line, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the second terminal of the energy - storage circuit; The control electrode of the second transistor is electrically connected to the on - off control line, the first electrode of the second transistor is electrically connected to the first voltage terminal, and the second electrode of the second transistor is electrically connected to the second terminal of the energy - storage circuit.

7. The pixel circuit according to any one of claims 1 to 6, characterized in that, It further includes a data - writing circuit and a compensation control circuit; The data - writing circuit is electrically connected to the writing control line, the data line, and the first terminal of the driving circuit respectively, and is configured to write the data voltage provided by the data line into the first terminal of the driving circuit under the control of the writing control signal provided by the writing control line; The compensation control circuit is electrically connected to the compensation control line, the control terminal of the driving circuit, and the second terminal of the driving circuit respectively, and is configured to control the connection or disconnection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the compensation control signal provided by the compensation control line.

8. The pixel circuit according to claim 7, wherein The transistors included in the second initialization circuit and the transistors included in the data - writing circuit are both p - type transistors, or the transistors included in the second initialization circuit and the transistors included in the data - writing circuit are both n - type transistors; The writing control line and the second initialization control line are connected to the same control signal.

9. The pixel circuit according to claim 2, wherein The first initialization circuit includes a third transistor, and the second initialization circuit includes a fourth transistor; The control electrode of the third transistor is electrically connected to the first initialization control line, the first electrode of the third transistor is electrically connected to the first initial voltage terminal, and the second electrode of the third transistor is electrically connected to the control terminal of the driving circuit; The control electrode of the fourth transistor is electrically connected to the second initialization control line, the first electrode of the fourth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light - emitting element.

10. The pixel circuit according to claim 3, wherein The first light - emitting control circuit includes a fifth transistor, the second light - emitting control circuit includes a sixth transistor, and the energy - storage circuit includes a storage capacitor; The control electrode of the fifth transistor is electrically connected to the light - emitting control line, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first terminal of the driving circuit; The control electrode of the sixth transistor is electrically connected to the light-emitting control line, the first electrode of the sixth transistor is electrically connected to the second end of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element; The first end of the storage capacitor is electrically connected to the control end of the driving circuit, and the second end of the storage capacitor is the second end of the energy storage circuit.

11. The pixel circuit according to claim 7, wherein The data writing circuit includes a seventh transistor, and the compensation control circuit includes an eighth transistor; The control electrode of the seventh transistor is electrically connected to the writing control line, the first electrode of the seventh transistor is electrically connected to the data line, and the second electrode of the seventh transistor is electrically connected to the first end of the driving circuit; The control electrode of the eighth transistor is electrically connected to the compensation control line, the first electrode of the eighth transistor is electrically connected to the control end of the driving circuit, and the second electrode of the eighth transistor is electrically connected to the second end of the driving circuit.

12. A pixel driving method, applied to the pixel circuit according to any one of claims 1 to 11, characterized in that, The display period includes a refresh frame and at least one hold frame; The refresh frame and the hold frame each include an initialization stage, a data writing stage, and a light-emitting stage; the pixel driving method includes: In the refresh frame, the energy storage control circuit, under the control of the energy storage control signal, controls the connection between the second end of the energy storage circuit and the first voltage terminal; In the initialization stage included in the hold frame and the data writing stage included in the hold frame, the energy storage control circuit, under the control of the energy storage control signal, controls the disconnection between the second end of the energy storage circuit and the first voltage terminal; In the light-emitting stage included in the hold frame, the energy storage control circuit, under the control of the energy storage control signal, controls the connection between the second end of the energy storage circuit and the first voltage terminal.

13. The pixel driving method according to claim 12, characterized in that, The pixel circuit further includes a second initialization circuit, a data writing circuit, and a compensation control circuit; the pixel driving method further includes: In the initialization stage, the first initialization circuit, under the control of the first initialization control signal, writes a first initial voltage to the control end of the driving circuit, so that at the start of the data writing stage, the driving circuit can, under the control of the potential at its control end, control the connection between the first end and the second end of the driving circuit; In the data writing stage, the second initialization circuit, under the control of the second initialization control signal, writes a second initial voltage to the first electrode of the light-emitting element to reset the first electrode of the light-emitting element; In the data writing stage included in the refresh frame, the data line provides a data voltage, and the data writing circuit, under the control of the writing control signal, writes the data voltage to the first end of the driving circuit; the compensation control circuit, under the control of the compensation control signal, controls the connection between the control end and the second end of the driving circuit.

14. The pixel driving method according to claim 12 or 13, characterized in that, The energy storage control circuit includes a first control sub-circuit and a second control sub-circuit; the pixel driving method includes: In the refresh frame, the second control sub-circuit, under the control of the on-off control signal, controls the connection between the second end of the energy storage circuit and the first voltage terminal; During the initialization phase included in the holding frame and the data writing phase included in the holding frame, the first control sub-circuit disconnects between the second end of the energy storage circuit and the first voltage terminal under the control of the light emission control signal; the second control sub-circuit disconnects between the second end of the energy storage circuit and the first voltage terminal under the control of the on-off control signal. During the light emission phase included in the holding frame, the first control sub-circuit connects between the second end of the energy storage circuit and the first voltage terminal under the control of the light emission control signal.

15. A display device, characterized in that, A pixel circuit according to any one of claims 1 to 11.

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