A medium and high voltage linear regulator circuit

Abstract

The present invention discloses a medium- and high-voltage linear voltage regulator circuit, which belongs to the field of voltage regulator circuits. The present invention adjusts the floating voltage by connecting a Zener tube or a MOS device pair in parallel between the core low-voltage devices of the error amplifier, thereby ensuring that the error amplifier operates at a medium- and high-voltage level. The present invention does not require an additional pre-step-down module, has a simple circuit structure, and saves chip area and power consumption. Since the charge pump circuit of the pre-step-down module significantly increases the output noise, the present invention does not use the pre-step-down module, and the circuit output accuracy is improved. In addition, the present invention solves the problem of the pre-step-down module worsening the circuit voltage difference. The present invention is integrated in the LDO feedback loop as the core component of the feedback loop. According to the changes in the load or input power supply voltage, it accurately drives the power tube to ensure that the output voltage has sufficient output accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of voltage stabilizer circuits, and in particular to a medium- and high-voltage linear voltage stabilizer circuit. Background Art

[0002] Among power management integrated circuits, low-dropout linear regulators (LDOs) are a widely used voltage regulator circuit. They boast advantages such as simple structure, compact size, low output noise, and no EMI interference. They are of vital importance to the national economy and are ideal for powering critical devices sensitive to power supply noise, such as high-speed, high-precision ADCs / DACs, high-frequency phase-locked loops, and voltage-controlled oscillators. They are also well-suited for applications where board space is critical, such as handheld electronic communication terminals and IoT devices. Therefore, the performance of linear regulator circuits is crucial to the overall performance of electronic equipment.

[0003] In order to ensure the good working performance of the low voltage drop linear regulator, such as Figure 1 As shown in Figure 1, the components within the main loop of the linear regulator (such as the EA module) are mostly low-voltage components. If the linear regulator requires a high-voltage environment (VIN>5V), low-voltage modules such as the EA module will not work.

[0004] Traditional medium and high voltage low dropout linear regulators such as Figure 2 As shown. Based on the low-voltage main LDO, a pre-step-down unit is added, which consists of a charge pump (Charge Pump), a low-pass filter (RLPF, CLPF), and a step-down regulator tube M N The charge pump is used to generate a reasonable bias voltage, which is then used to bias the step-down regulator M after filtering out noise through a low-pass filter. N . M N A medium- and high-voltage NMOS device is used, and its source terminal generates an internal power supply voltage VIN_REG suitable for the low-voltage main LDO.

[0005] Traditional medium and high voltage low dropout linear regulators introduce a pre-step-down unit to meet the needs of medium and high voltage applications for low dropout linear regulators. However, the pre-step-down unit has a relatively complex structure, which increases the chip area and power consumption. The pre-step-down unit has a built-in charge pump circuit, which generates a lot of noise during operation. Even with a built-in low-pass filter, the noise cannot be completely filtered out. This noise is passed through the step-down regulator tube M. N The voltage is transmitted to the main LDO, reducing the accuracy of the output voltage. In addition, the pre-buck unit introduces additional voltage headroom overhead, significantly worsening the voltage drop parameters of the entire circuit. Summary of the Invention

[0006] The object of the present invention is to provide a medium- and high-voltage linear regulator circuit to solve the problems in the background technology.

[0007] In order to solve the above technical problems, the present invention provides a medium- and high-voltage linear regulator circuit.

[0008] Connect a Zener diode or a pair of MOS devices in parallel between the core low-voltage devices of the error amplifier to adjust the floating voltage and ensure that the error amplifier operates at medium and high voltage.

[0009] In one embodiment, the medium- and high-voltage linear regulator circuit includes NMOS transistors MN1 to MN7, PMOS transistors MP1 to MP5, resistors R1 to R3, a Zener transistor D1, and equivalent current sources I1 and I2;

[0010] The source terminals of the PMOS transistors MP1 to MP5 are all connected to the power supply VDD; the drain terminal of the PMOS transistor MP1 is simultaneously connected to the drain terminal and gate terminal of the NMOS transistor MN2; the gate terminal of the PMOS transistor MP1 is simultaneously connected to the gate terminal and drain terminal of the PMOS transistor MP2; the drain terminal of the PMOS transistor MP4 is connected to the drain terminal of the NMOS transistor MN3, and the gate terminal is simultaneously connected to the gate terminal and drain terminal of the PMOS transistor MP3; the gate terminal of the PMOS transistor MP5 is connected to the drain terminal of the PMOS transistor MP4, the drain terminal of the PMOS transistor MP5 is connected to the first terminal of the resistor R1, the second terminal of the resistor R1 is connected to the first terminal of the resistor R2, and the second terminal of the resistor R2 is grounded;

[0011] The gate terminals of the NMOS transistors MN6 and MN7 are commonly connected to a gate voltage VB1, the drain terminal of the NMOS transistor MN6 is connected to the drain terminal of the PMOS transistor MP2, the source terminal of the NMOS transistor MN6 is connected to the drain terminal of the NMOS transistor MN4, the drain terminal of the NMOS transistor MN7 is connected to the drain terminal of the PMOS transistor MP3, the source terminal of the NMOS transistor MN7 is connected to the drain terminal of the NMOS transistor MN5, the gate terminal of the NMOS transistor MN4 is connected to a reference voltage VREF, and the gate terminal of the NMOS transistor MN5 is connected between the second terminal of the resistor R1 and the first terminal of the resistor R2; the source terminals of the NMOS transistors MN4 and MN5 are commonly connected to the input terminal of an equivalent current source I2, and the output terminal of the equivalent current source I2 is grounded;

[0012] The gate terminal of the NMOS transistor MN2 and the gate terminal of the NMOS transistor MN3 are interconnected, and the source terminal of the NMOS transistor MN2 and the source terminal of the NMOS transistor MN3 are commonly connected to the drain terminal of the NMOS transistor MN1 and the output terminal of the equivalent current source I1; the source terminal of the NMOS transistor MN1 is connected to the input terminal of the equivalent current source I1, and the gate terminal of the NMOS transistor MN1 is connected to the gate voltage VB2; the drain terminal of the NMOS transistor MN1 is connected to the positive electrode of the Zener transistor D1, the negative electrode of the Zener transistor D1 is connected to the second terminal of the resistor R3, and the first terminal of the resistor R3 is connected to the power supply VDD.

[0013] In one embodiment, NMOS transistors MN1 to MN7, PMOS transistors MP1 to MP4, resistor R3, Zener transistor D1, and equivalent current sources I1 and I2 constitute an error amplifier; PMOS transistor MP5 is a power transistor; resistors R1 and R2 are feedback resistors; the typical breakdown voltage of the Zener transistor D1 is 5.5V to ensure normal operation of the core components of the error amplifier; NMOS transistors MN6 and MN7 are high-voltage devices, and their gate voltages VB1 are reasonably set to ensure that the drain voltages of the NMOS transistors MN4 and MN5 are within a low voltage range.

[0014] In one embodiment, NMOS transistors MN2 to MN5 and PMOS transistors MP1 to MP4 are low-voltage devices with substrates capable of withstanding medium and high voltages; a floating ground is generated between the source end of the PMOS transistor MP1 and the source end of the NMOS transistor MN2 by connecting a Zener transistor D1 in parallel with a series resistor R3.

[0015] In one embodiment, the medium- and high-voltage linear regulator circuit includes NMOS transistors MN1 to MN9, PMOS transistors MP1 to MP7, resistors R1 to R2, and equivalent current sources I1 and I2;

[0016] The source terminals of the PMOS transistors MP1 to MP5 are all connected to the power supply VDD; the drain terminal of the PMOS transistor MP1 is simultaneously connected to the drain terminal and gate terminal of the NMOS transistor MN2; the gate terminal of the PMOS transistor MP1 is simultaneously connected to the gate terminal and drain terminal of the PMOS transistor MP2; the drain terminal of the PMOS transistor MP4 is connected to the drain terminal of the NMOS transistor MN3, and the gate terminal is simultaneously connected to the gate terminal and drain terminal of the PMOS transistor MP3; the gate terminal of the PMOS transistor MP5 is connected to the drain terminal of the PMOS transistor MP4, the drain terminal of the PMOS transistor MP5 is connected to the first terminal of the resistor R1, the second terminal of the resistor R1 is connected to the first terminal of the resistor R2, and the second terminal of the resistor R2 is grounded;

[0017] The gate terminals of the NMOS transistors MN6 and MN7 are commonly connected to a gate voltage VB1, the drain terminal of the NMOS transistor MN6 is connected to the drain terminal of the PMOS transistor MP2, the source terminal of the NMOS transistor MN6 is connected to the drain terminal of the NMOS transistor MN4, the drain terminal of the NMOS transistor MN7 is connected to the drain terminal of the PMOS transistor MP3, the source terminal of the NMOS transistor MN7 is connected to the drain terminal of the NMOS transistor MN5, the gate terminal of the NMOS transistor MN4 is connected to a reference voltage VREF, and the gate terminal of the NMOS transistor MN5 is connected between the second terminal of the resistor R1 and the first terminal of the resistor R2; the source terminals of the NMOS transistors MN4 and MN5 are commonly connected to the input terminal of an equivalent current source I2, and the output terminal of the equivalent current source I2 is grounded;

[0018] The gate terminal of the NMOS transistor MN2 and the gate terminal of the NMOS transistor MN3 are interconnected, and the source terminal of the NMOS transistor MN2 and the source terminal of the NMOS transistor MN3 are commonly connected to the drain terminal of the NMOS transistor MN1 and the output terminal of the equivalent current source I1; the source terminal of the NMOS transistor MN1 is connected to the input terminal of the equivalent current source I1, and the gate terminal of the NMOS transistor MN1 is connected to the gate voltage VB2;

[0019] The source terminal of the PMOS transistor MP7 is connected to the power supply VDD, and the gate terminal and the drain terminal are commonly connected to the source terminal of the PMOS transistor MP6; the gate terminal and the drain terminal of the PMOS transistor MP6 are commonly connected to the drain terminal of the NMOS transistor MN9, the gate terminal of the NMOS transistor MN9 is connected to its own drain terminal, and the source terminal is simultaneously connected to the drain terminal and the gate terminal of the NMOS transistor MN8. The source terminal of the NMOS transistor MN8 is connected to the drain terminal of the NMOS transistor MN1; the source terminal of the NMOS transistor MN2 and the source terminal of the NMOS transistor MN3 are commonly connected to the source terminal of the NMOS transistor MN8.

[0020] In one embodiment, the relative voltage of the floating ground is changed by adjusting the width-to-length ratio of the four devices.

[0021] In one embodiment, NMOS transistors MN1 to MN9, PMOS transistors MP1 to MP4, PMOS transistors MP6 to MP7, and equivalent current sources I1 and I2 constitute an error amplifier; PMOS transistor MP5 is a power transistor; resistors R1 and R2 are feedback resistors; NMOS transistors MN6 and MN7 are high-voltage devices, and their gate voltages VB1 are reasonably set to ensure that the drain voltages of NMOS transistors MN4 and MN5 are within a low voltage range.

[0022] In one embodiment, NMOS transistors MN2 to MN5 and PMOS transistors MP1 to MP4 are low-voltage devices with substrate resistance to medium and high voltages; a floating ground is generated between the source end of the PMOS transistor MP1 and the source end of the NMOS transistor MN2 by connecting PMOS transistors MP6 to MP7 and NMOS transistors MN8 to MN9 in parallel.

[0023] The present invention provides a medium- and high-voltage linear regulator circuit, which has the following beneficial effects:

[0024] (1) No additional pre-step-down module is required, the circuit structure is simple, and chip area and power consumption are saved;

[0025] (2) Since the charge pump circuit of the pre-step-down module significantly increases the output noise, the present invention does not use the pre-step-down module, and the circuit output accuracy is improved;

[0026] (3) The problem of the pre-step-down module worsening the circuit voltage difference is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1It is a structural diagram of a linear regulator.

[0028] Figure 2 It is a structural diagram of a traditional medium and high voltage linear regulator circuit.

[0029] Figure 3 It is a structural diagram of a medium- and high-voltage linear regulator circuit provided in Example 1 of the present invention.

[0030] Figure 4 1 is a schematic structural diagram of a medium- and high-voltage linear regulator circuit provided in a second embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following is a detailed description of a medium- and high-voltage linear regulator circuit according to the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of illustrating the embodiments of the present invention.

[0032] Example 1

[0033] Embodiment 1 of the present invention provides an implementation of a medium- and high-voltage linear regulator circuit, including NMOS transistors MN1 to MN7, PMOS transistors MP1 to MP5, resistors R1 to R3, a Zener transistor D1, and equivalent current sources I1 and I2.

[0034] The source terminals of the PMOS transistors MP1 to MP5 are all connected to the power supply VDD; the drain terminal of the PMOS transistor MP1 is simultaneously connected to the drain terminal and gate terminal of the NMOS transistor MN2; the gate terminal of the PMOS transistor MP1 is simultaneously connected to the gate terminal and drain terminal of the PMOS transistor MP2; the drain terminal of the PMOS transistor MP4 is connected to the drain terminal of the NMOS transistor MN3, and the gate terminal is simultaneously connected to the gate terminal and drain terminal of the PMOS transistor MP3; the gate terminal of the PMOS transistor MP5 is connected to the drain terminal of the PMOS transistor MP4, the drain terminal of the PMOS transistor MP5 is connected to the first terminal of the resistor R1, the second terminal of the resistor R1 is connected to the first terminal of the resistor R2, and the second terminal of the resistor R2 is grounded.

[0035] The gate terminals of the NMOS transistors MN6 and MN7 are commonly connected to a gate voltage VB1, the drain terminal of the NMOS transistor MN6 is connected to the drain terminal of the PMOS transistor MP2, the source terminal of the NMOS transistor MN6 is connected to the drain terminal of the NMOS transistor MN4, the drain terminal of the NMOS transistor MN7 is connected to the drain terminal of the PMOS transistor MP3, the source terminal of the NMOS transistor MN7 is connected to the drain terminal of the NMOS transistor MN5, the gate terminal of the NMOS transistor MN4 is connected to a reference voltage VREF, and the gate terminal of the NMOS transistor MN5 is connected between the second terminal of the resistor R1 and the first terminal of the resistor R2; the source terminals of the NMOS transistors MN4 and MN5 are commonly connected to the input terminal of an equivalent current source I2, and the output terminal of the equivalent current source I2 is grounded.

[0036] The gate terminal of the NMOS transistor MN2 and the gate terminal of the NMOS transistor MN3 are interconnected, and the source terminal of the NMOS transistor MN2 and the source terminal of the NMOS transistor MN3 are commonly connected to the drain terminal of the NMOS transistor MN1 and the output terminal of the equivalent current source I1; the source terminal of the NMOS transistor MN1 is connected to the input terminal of the equivalent current source I1, and the gate terminal of the NMOS transistor MN1 is connected to the gate voltage VB2; the drain terminal of the NMOS transistor MN1 is connected to the positive electrode of the Zener transistor D1, the negative electrode of the Zener transistor D1 is connected to the second terminal of the resistor R3, and the first terminal of the resistor R3 is connected to the power supply VDD.

[0037] The error amplifier (EA) consists of NMOS transistors MN1-MN7, PMOS transistors MP1-MP4, resistor R3, Zener diode D1, and equivalent current sources I1 and I2. PMOS transistor MP5 is a power transistor, and resistors R1 and R2 serve as feedback resistors. To ensure the performance of the EA, the core components, NMOS transistors MN2-MN5 and PMOS transistors MP1-MP4, are low-voltage devices with substrates capable of withstanding medium and high voltages. To accommodate medium and high voltage applications, a Zener diode D1 with a series resistor R3 is connected in parallel between the source terminals of PMOS transistor MP1 and NMOS transistor MN2 to create a floating ground. Since Zener diode D1 has a typical breakdown voltage of approximately 5.5V, this ensures the normal operation of the core EA components. NMOS transistors MN6 and MN7 are high-voltage devices, and their gate voltages VB1 are appropriately set to ensure that the drain voltages of NMOS transistors MN4 and MN5 remain within the low-voltage range.

[0038] Example 2

[0039] The second embodiment of the present invention provides another implementation of a medium- and high-voltage linear regulator circuit, which uses low-voltage PMOS transistors MP6-MP7 and NMOS transistors MN8-MN9 whose substrates can withstand medium- and high-voltage conditions to replace the resistor R3 and Zener transistor D1 in the first embodiment, thereby producing a similar floating function.

[0040] The source terminal of the PMOS transistor MP7 is connected to the power supply VDD, and the gate and drain terminals are commonly connected to the source terminal of the PMOS transistor MP6; the gate and drain terminals of the PMOS transistor MP6 are commonly connected to the drain terminal of the NMOS transistor MN9, the gate terminal of the NMOS transistor MN9 is connected to its own drain terminal, and the source terminal is simultaneously connected to the drain terminal and the gate terminal of the NMOS transistor MN8, and the source terminal of the NMOS transistor MN8 is connected to the drain terminal of the NMOS transistor MN1; the source terminals of the NMOS transistor MN2 and the source terminals of the NMOS transistor MN3 are commonly connected to the source terminal of the NMOS transistor MN8.

[0041] The second embodiment does not require Zener diodes, thus reducing circuit production costs. By adjusting the width-to-length ratio of the four devices (i.e., MP6:MP7:MN8:MN9), the relative voltage of the floating ground can be changed, thereby broadening the application scope of the present invention.

[0042] The present invention is integrated into the LDO feedback loop and, as the core component of the feedback loop, accurately drives the power tube according to changes in the load or input power supply voltage to ensure that the output voltage has sufficient output accuracy.

[0043] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A medium- and high-voltage linear regulator circuit, characterized in that: The medium- and high-voltage linear regulator circuit includes NMOS transistors MN1 to MN7, PMOS transistors MP1 to MP5, resistors R1 to R3, a Zener transistor D1, and equivalent current sources I1 and I2; The source terminals of the PMOS transistors MP1 to MP5 are all connected to the power supply VDD; the drain terminal of the PMOS transistor MP1 is simultaneously connected to the drain terminal and gate terminal of the NMOS transistor MN2; the gate terminal of the PMOS transistor MP1 is simultaneously connected to the gate terminal and drain terminal of the PMOS transistor MP2; the drain terminal of the PMOS transistor MP4 is connected to the drain terminal of the NMOS transistor MN3; the gate terminal of the PMOS transistor MP4 is simultaneously connected to the gate terminal and drain terminal of the PMOS transistor MP3; the gate terminal of the PMOS transistor MP5 is connected to the drain terminal of the PMOS transistor MP4; the drain terminal of the PMOS transistor MP5 is connected to the first terminal of the resistor R1; the second terminal of the resistor R1 is connected to the first terminal of the resistor R2; and the second terminal of the resistor R2 is grounded; The gate terminals of the NMOS transistors MN6 and MN7 are commonly connected to a gate voltage VB1, the drain terminal of the NMOS transistor MN6 is connected to the drain terminal of the PMOS transistor MP2, the source terminal of the NMOS transistor MN6 is connected to the drain terminal of the NMOS transistor MN4, the drain terminal of the NMOS transistor MN7 is connected to the drain terminal of the PMOS transistor MP3, the source terminal of the NMOS transistor MN7 is connected to the drain terminal of the NMOS transistor MN5, the gate terminal of the NMOS transistor MN4 is connected to a reference voltage VREF, and the gate terminal of the NMOS transistor MN5 is connected between the second terminal of the resistor R1 and the first terminal of the resistor R2; the source terminals of the NMOS transistors MN4 and MN5 are commonly connected to the input terminal of an equivalent current source I2, and the output terminal of the equivalent current source I2 is grounded; The gate terminal of the NMOS transistor MN2 and the gate terminal of the NMOS transistor MN3 are interconnected, and the source terminal of the NMOS transistor MN2 and the source terminal of the NMOS transistor MN3 are commonly connected to the drain terminal of the NMOS transistor MN1 and the output terminal of the equivalent current source I1; the source terminal of the NMOS transistor MN1 is connected to the input terminal of the equivalent current source I1, and the gate terminal of the NMOS transistor MN1 is connected to the gate voltage VB2; the drain terminal of the NMOS transistor MN1 is connected to the positive electrode of the Zener transistor D1, and the negative electrode of the Zener transistor D1 is connected to the second terminal of the resistor R3, and the first terminal of the resistor R3 is connected to the power supply VDD; NMOS transistors MN1 to MN7, PMOS transistors MP1 to MP4, resistor R3, Zener transistor D1, and equivalent current sources I1 and I2 constitute an error amplifier; PMOS transistor MP5 is a power transistor; resistors R1 and R2 are feedback resistors.

2. The medium- and high-voltage linear regulator circuit according to claim 1, wherein: The typical breakdown voltage of the Zener tube D1 is 5.5V to ensure the normal operation of the core components of the error amplifier; the NMOS tubes MN6 and MN7 are high-voltage devices, and their gate voltages VB1 are reasonably set to ensure that the drain voltages of the NMOS tubes MN4 and MN5 are within the low voltage range.

3. A medium- and high-voltage linear regulator circuit, characterized in that: The medium- and high-voltage linear regulator circuit includes NMOS transistors MN1 to MN9, PMOS transistors MP1 to MP7, resistors R1 to R2, and equivalent current sources I1 and I2; The source terminals of the PMOS transistors MP1 to MP5 are all connected to the power supply VDD; the drain terminal of the PMOS transistor MP1 is simultaneously connected to the drain terminal and gate terminal of the NMOS transistor MN2; the gate terminal of the PMOS transistor MP1 is simultaneously connected to the gate terminal and drain terminal of the PMOS transistor MP2; the drain terminal of the PMOS transistor MP4 is connected to the drain terminal of the NMOS transistor MN3; the gate terminal of the PMOS transistor MP4 is simultaneously connected to the gate terminal and drain terminal of the PMOS transistor MP3; the gate terminal of the PMOS transistor MP5 is connected to the drain terminal of the PMOS transistor MP4; the drain terminal of the PMOS transistor MP5 is connected to the first terminal of the resistor R1; the second terminal of the resistor R1 is connected to the first terminal of the resistor R2; and the second terminal of the resistor R2 is grounded; The gate terminals of the NMOS transistors MN6 and MN7 are commonly connected to a gate voltage VB1, the drain terminal of the NMOS transistor MN6 is connected to the drain terminal of the PMOS transistor MP2, the source terminal of the NMOS transistor MN6 is connected to the drain terminal of the NMOS transistor MN4, the drain terminal of the NMOS transistor MN7 is connected to the drain terminal of the PMOS transistor MP3, the source terminal of the NMOS transistor MN7 is connected to the drain terminal of the NMOS transistor MN5, the gate terminal of the NMOS transistor MN4 is connected to a reference voltage VREF, and the gate terminal of the NMOS transistor MN5 is connected between the second terminal of the resistor R1 and the first terminal of the resistor R2; the source terminals of the NMOS transistors MN4 and MN5 are commonly connected to the input terminal of an equivalent current source I2, and the output terminal of the equivalent current source I2 is grounded; The gate terminal of the NMOS transistor MN2 and the gate terminal of the NMOS transistor MN3 are interconnected, and the source terminal of the NMOS transistor MN2 and the source terminal of the NMOS transistor MN3 are commonly connected to the drain terminal of the NMOS transistor MN1 and the output terminal of the equivalent current source I1; the source terminal of the NMOS transistor MN1 is connected to the input terminal of the equivalent current source I1, and the gate terminal of the NMOS transistor MN1 is connected to the gate voltage VB2; The source terminal of the PMOS transistor MP7 is connected to the power supply VDD, and the gate and drain terminals are commonly connected to the source terminal of the PMOS transistor MP6. The gate and drain terminals of the PMOS transistor MP6 are commonly connected to the drain terminal of the NMOS transistor MN9. The gate terminal of the NMOS transistor MN9 is connected to its own drain terminal. The source terminal is simultaneously connected to the drain terminal and the gate terminal of the NMOS transistor MN8. The source terminal of the NMOS transistor MN8 is connected to the drain terminal of the NMOS transistor MN1. The source terminals of the NMOS transistors MN2 and MN3 are commonly connected to the source terminal of the NMOS transistor MN8. NMOS transistors MN1 to MN9, PMOS transistors MP1 to MP4, PMOS transistors MP6 to MP7, and equivalent current sources I1 and I2 constitute an error amplifier; PMOS transistor MP5 is a power transistor; resistors R1 and R2 are feedback resistors.

4. The medium- and high-voltage linear regulator circuit according to claim 3, wherein: By adjusting the width-to-length ratio of the four devices, the relative voltage of the floating ground is changed.

5. The medium- and high-voltage linear regulator circuit according to claim 3, wherein: The NMOS transistors MN6 and MN7 are high-voltage devices, and their gate voltages VB1 are reasonably set to ensure that the drain voltages of the NMOS transistors MN4 and MN5 are within a low voltage range.

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