A multiplier hardware architecture for post-quantum cryptography algorithms

Abstract

The present invention provides a multiplier hardware architecture for post-quantum cryptography algorithms. A first-layer Karatsuba module is connected to three second-layer Karatsuba modules, each of which is further connected to three third-layer Karatsuba modules. The third layer is connected to Schoolbook multiplication modules. The Schoolbook modules perform low-, medium-, and high-order subpolynomial multiplications in parallel. The first and second-layer Karatsuba modules sum and modulo the high and low bits of the input polynomial, while the third layer performs operations on the low, medium, and high bits, respectively. This invention reduces the number of subpolynomial multiplications, improves computational speed, and reduces hardware resource consumption through a streamlined design.

Description

Technical Field

[0001] The present invention relates to the field of multiplier hardware design, and in particular to a multiplier hardware architecture for post-quantum cryptographic algorithms. Background Art

[0002] In recent years, breakthroughs have been made in quantum technology research, meaning that quantum computing will soon be applied to a wide range of fields. However, the development of quantum computing will have an unprecedented impact on traditional cryptographic systems. Quantum computers replace traditional computer bits with qubits, which have two states: 0 and 1. These qubits can share their states with other spatially independent qubits, enabling efficient parallel computing. The introduction of the Shor and Grover algorithms demonstrates that quantum computers can break traditional public-key cryptography algorithms in polynomial time, significantly weakening the security of block encryption algorithms. Therefore, research on post-quantum cryptography algorithms is urgently needed to ensure information security in the post-quantum era.

[0003] Streamlined NTRU Prime is a post-quantum cryptographic algorithm that achieves the IND-CCA2 security level and utilizes a key encapsulation mechanism (KEM). The Streamlined NTRU Prime algorithm structure is similar to the original NTRU algorithm, but it removes the ring structure to reduce the attack surface, thereby enhancing the algorithm's anti-attack capabilities and improving security. Streamlined NTRU Prime is the first complete algorithm in the NTRU Prime family of algorithms. This algorithm features smaller ciphertexts and faster encapsulation and decapsulation speeds, but its key generation is slower. The algorithm is divided into two layers: the inner layer uses an asymmetric encryption algorithm, and the outer layer uses a key encapsulation algorithm.

[0004] The relevant symbols of the StreamlinedNTRU Prime algorithm can be expressed as follows: Assume that there are p, q and w, p and q are prime numbers, and w is a positive integer. Where 2p≥3w, q≥16w+1 and x p -x-1 is in the polynomial ring Irreducible polynomials on . and Representative Ring and

[0005] In the StreamlinedNTRU Prime algorithm, there are mainly two types of polynomial multiplication operations, one is Polynomials and Multiplication of polynomials, another for two Multiplication of polynomials. Each coefficient of the polynomial is a signed 13-bit binary number, and Each coefficient of the polynomial is a signed 2-bit binary number. The polynomial coefficients only take values ​​in the range {-1, 0, 1}, so Polynomial coefficients and The product of polynomial coefficients has only three possible values. Polynomials can be viewed as a special kind of polynomial, which is equivalent to More stringent restrictions are placed on the polynomial coefficients.

[0006] Compared to software implementations, hardware-based implementations of the StreamlinedNTRU Prime algorithm offer significant advantages in resource consumption, security, power consumption, and speed. They can be applied to both traditional high-performance devices and resource-constrained IoT devices. The operations performed in the algorithm's key generation, encapsulation, and decapsulation stages are primarily polynomials. Polynomial multiplication is used repeatedly throughout these three stages, and the multiplication unit is the most resource-intensive module in the system. Therefore, selecting an appropriate polynomial multiplication algorithm is crucial for improving the efficiency of the StreamlinedNTRU Prime algorithm and reducing the power consumption and resource consumption of its hardware implementation.

[0007] Peng proposed a polynomial multiplication module design based on the Schoolbook algorithm. Although this design is relatively simple, it suffers from slow computation speed and low operating frequency. In scenarios with higher performance requirements, this solution's advantages are limited, and it's difficult to match the speed of peripheral hardware devices.

[0008] Therefore, how to provide a low-resource consumption, high-performance polynomial multiplication hardware architecture for the StreamlinedNTRU Prime algorithm has become an urgent problem to be solved by researchers in this field. Summary of the Invention

[0009] In order to overcome the deficiencies of the prior art, the object of the present invention is to provide a multiplier hardware architecture for post-quantum cryptographic algorithms.

[0010] To achieve the above object, the present invention provides the following solutions:

[0011] A multiplier hardware architecture for a post-quantum cryptographic algorithm, comprising: a first-layer Karatsuba module, multiple second-layer Karatsuba modules, a third-layer Karatsuba module, and a Schoolbook multiplication module; the first-layer Karatsuba module is respectively connected to three second-layer Karatsuba modules, each second-layer Karatsuba module is respectively connected to three third-layer Karatsuba modules; and each third-layer Karatsuba module is connected to one Schoolbook multiplication module;

[0012] The Schoolbook multiplication module is used to perform multiplication operations of three sub-polynomials in parallel, and complete low-order, middle-order and high-order multiplication operations in parallel; the first-layer Karatsuba module and the second-layer Karatsuba module are both used to sum the high-order and low-order corresponding coefficients of the two input polynomials, and perform modulo operations on the summed results; the third-layer Karatsuba module is used to be responsible for low-order, middle-order and high-order multiplication operations respectively.

[0013] Preferably, the internal implementation principles of the Karatsuba modules in the same layer are the same; the input and output port bit widths of the Karatsuba modules in the same layer are different.

[0014] Preferably, each Karatsuba module includes four dual-port RAMs, namely RAM_0, RAM_1, RAM_2 and RAM_result. RAM_0, RAM_1 and RAM_2 are respectively used to temporarily store data input to the lower-level Karatsuba module or Schoolbook module, and RAM_result stores the calculation results generated by the lower-level module.

[0015] Preferably, the Schoolbook module is provided with three RAMs, which are respectively used to store data generated by low bits, middle bits and high bits. The RAM adopts a dual-port design, and both ports can perform read and write operations.

[0016] Preferably, the input end of the Schoolbook module includes a clock signal clock, a reset signal reset, low-bit input data din_0, middle-bit input data din_1, and high-bit input data din_2; the output end of the Schoolbook module includes a completion signal done, an output valid signal dout_valid, low-bit output data dout_0, middle-bit output data dout_1, and high-bit output data dout_2.

[0017] Preferably, the input end of the first-layer Karatsuba module includes a clock signal clock, a polynomial A(x) input din_a, a polynomial B(x) input din_b, a reset signal reset and a start signal start; the output end of the first-layer Karatsuba module includes a completion signal done, a calculation result output dout and an output valid signal dout_valid.

[0018] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0019] The present invention provides a multiplier hardware architecture for a post-quantum cryptographic algorithm, comprising: a first-layer Karatsuba module, multiple second-layer Karatsuba modules, a third-layer Karatsuba module and a Schoolbook multiplication module; the first-layer Karatsuba module is respectively connected to three second-layer Karatsuba modules, each second-layer Karatsuba module is respectively connected to three third-layer Karatsuba modules; each third-layer Karatsuba module is connected to one Schoolbook multiplication module; the Schoolbook multiplication module is used to perform multiplication operations on three sub-polynomials in parallel, and complete low-bit, middle-bit and high-bit multiplication operations in parallel; the first-layer Karatsuba module and the second-layer Karatsuba module are both used to sum the high-bit and low-bit corresponding bit coefficients of two input polynomials, and perform a modulo operation on the summed result; the third-layer Karatsuba module is used to be responsible for low-bit, middle-bit and high-bit multiplication operations, respectively. The present invention is based on a multiplier using the three-layer Karatsuba algorithm and the Schoolbook algorithm. The three-layer Karatsuba algorithm effectively reduces the number of subpolynomial multiplications during the calculation process, thereby improving the computational speed of polynomial multiplication. Furthermore, the multiplier's hardware architecture is streamlined, reducing hardware resource consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A schematic diagram of the core module hierarchy of the multiplier hardware architecture provided by an embodiment of the present invention;

[0022] Figure 2A schematic diagram of the Schoolbook algorithm provided by an embodiment of the present invention;

[0023] Figure 3 A schematic diagram of the Schoolbook module structure provided in an embodiment of the present invention;

[0024] Figure 4 A schematic diagram of the top-level Karatsuba module structure provided by an embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of the third-layer Karatsuba module structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0027] The present invention aims to provide a multiplier hardware architecture for post-quantum cryptography algorithms. This multiplier is based on the three-layer Karatsuba algorithm and the Schoolbook algorithm. The three-layer Karatsuba algorithm effectively reduces the number of subpolynomial multiplications during the computation process, thereby increasing the computational speed of polynomial multiplication. The multiplier hardware architecture is streamlined, reducing hardware resource consumption.

[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] like Figure 1 As shown, the present invention is a polynomial multiplier hardware architecture suitable for the StreamlinedNTRU Prime algorithm, which mainly includes a first-layer Karatsuba module (the top-layer Karatsuba module in the figure), multiple second-layer Karatsuba modules, a third-layer Karatsuba module and a Schoolbook multiplication module.

[0030] Among them, the Schoolbook module is the hardware implementation of the Schoolbook algorithm. The schematic diagram of the Schoolbook algorithm is as follows Figure 2 As shown in the figure, it is a schematic diagram of the product of two cubic polynomials. Assume that there are two polynomials A(x) and B(x), and the product of the two polynomials is represented by C(x). k, calculate all the original polynomials A(x) and B(x) that can generate x k The product combination of , and the cumulative results, traversing all k to get the final product result. To calculate the power x 3 Taking the branch as an example, the coefficient product results a3×b0, a2×b1, a1×b2 and a0×b3 are summed to obtain the power x in the target result C(x). 3 The coefficients of x. It can be seen that each coefficient involved in the multiplication operation can generate x k Therefore, we only need to accumulate the operation results to get the target power x k The final coefficients are output directly.

[0031] Among them, the Karatsuba module is the hardware implementation of the Karatsuba algorithm. The Karatsuba algorithm is faster than the Schoolbook algorithm. The algorithm improves the computational efficiency by reducing the number of multiplications of sub-polynomials during the operation. For the StreamlinedNTRU Prime algorithm, the single-layer Karatsuba algorithm divides the polynomial into two parts, and the number of coefficients in each part is The number of coefficients for 3 times is The multiplication result of two p-order polynomials can be obtained by performing polynomial multiplication operations and a small amount of addition and subtraction operations.

[0032] Applying the multi-layer Karatsuba algorithm can further reduce the granularity of the sub-polynomials, and the calculation speed is improved compared to the single-layer Karatsuba algorithm. Assume that the polynomials A(x) and B(x) can be expressed as:

[0033]

[0034] When p is an even number, A(x) can be split into A0 and A1, and B(x) can be split into B0 and B1. A0, A1, B0, and B1 can be expressed as:

[0035]

[0036] Then A(x) and B(x) can be expressed as:

[0037]

[0038] Define three polynomials T0, T1 and T2:

[0039]

[0040] Then the result of polynomial multiplication can be expressed as

[0041] When p is an odd number, A(x) can be split into A0 and A1, and B(x) can be split into B0 and B1. A0, A1, B0, and B1 can be expressed as:

[0042]

[0043] Then A(x) and B(x) can be expressed as:

[0044]

[0045] The result of polynomial multiplication can be expressed as C(x)=T0+(T1-T0-T2)x (p+1) / 2 +T2x p+1 .

[0046] When the number of terms p in a polynomial is even, the polynomial can be evenly divided into two parts, and the number of terms in A0, A1, B0, and B1 is p / 2. When p is odd, the polynomials A0 and B0 have (p+1) / 2 terms, while A1 and B1 have (p-1) / 2 terms.

[0047] The Karatsuba algorithm is used to calculate the polynomial multiplication result C(x). Only three polynomial multiplication operations T0, T1 and T2 with coefficients of the order p / 2 are required. If the traditional polynomial multiplication method is used, the result can be expressed as C(x) = A0B0 + (A0B1 + A1B0)x p / 2 +A1B1x p , where the product of A0B0, A0B1, and A1B0 and A1B1 needs to be calculated separately. The Karatsuba algorithm is equivalent to using the T1-T0-T2 operation instead of A0B1+A1B0 in the traditional algorithm. T1-T0-T2 only requires one multiplication operation to obtain the value of T1, and then reuses the already calculated T0 and T2 to perform the subtraction operation of the polynomials T0, T1, and T2 to obtain the same result as A0B1+A1B0.

[0048] like Figure 3 The figure shows the structure of the Schoolbook module. The module inputs include the clock signal clock, the reset signal reset, the low-order input data din_0, the middle-order input data din_1, and the high-order input data din_2. The outputs include the completion signal done, the output valid signal dout_valid, the low-order output data dout_0, the middle-order output data dout_1, and the high-order output data dout_2. The low-order and high-order input data are used to calculate T0 and T2, while the middle-order input data is used to calculate the more complex T1. Taking the Schoolbook multiplication module of the single-layer Karatsuba algorithm as an example, assuming that A(x) is The polynomial, B(x) is Polynomial, the coefficients of the polynomials A0 and B0 used to calculate T0 belong to and Therefore, the bit widths of the corresponding input data ports are set to 13 bits and 2 bits respectively. Polynomials and The product of the polynomials is Polynomial, then each coefficient of the product belongs to Therefore, the output port width is set to 13 bits. The calculation principle of T2 is the same as that of T0, so its input and output port widths are the same as T0. The middle bit input data is the sum of the high and low bit corresponding coefficients of the two polynomials, so it is necessary to pre-calculate the coefficient sum in the upper layer Karatsuba module and input the calculation result into the Schoolbook multiplication module through the din_1 port. The range of coefficient summation is {-2, -1, 0, 1, 2}, so it needs to be represented by a 3-bit binary number. The corresponding input port widths for calculating T1 are 13 bits and 3 bits, and the output port width is 13 bits. The multiplication module completes the multiplication of two coefficients and accumulates the products of the same power. The accumulated operation result may no longer belong to Therefore, it is necessary to perform a modulo operation on the result t. The modulo operation rules are:

[0049]

[0050] The accumulated result of each time is input into the modulo operation unit, and the modulo operation unit processes the result according to the modulo operation rules, and finally outputs a The polynomial coefficients are processed and stored in RAM for caching. Since the low-order, middle-order, and high-order multiplications are performed in parallel in the multiplication module, three RAMs are designed to store the low-order, middle-order, and high-order data, respectively. The RAMs use a dual-port design, both of which can be read and written. When the output valid signal dout_valid is high, the result data in the RAM is output from dout_0, dout_1, and dout_2, respectively. After the output is complete, dout_valid is set to 0, the completion signal done is set to 1, and the state machine jumps to the idle state, waiting for input data and the rising edge of the clock.

[0051] like Figure 4This is a schematic diagram of the top-level Karatsuba module structure. The input of the top-level Karatsuba module includes the clock signal clock, the polynomial A(x) input din_a, the polynomial B(x) input din_b, the reset signal reset, and the start signal start. The output includes the completion signal done, the calculation result output dout, and the output valid signal dout_valid. The sub-problems divided by the top-level Karatsuba module are further decomposed and passed downward by the second-level Karatsuba module. The three second-level Karatsuba modules Karatsuba_0, Karatsuba_1, and Karatsuba_2 are used to calculate T0, T1, and T2, respectively. The calculation of T1 is more complicated. The top-level Karatsuba module needs to complete the sum operations of A0+A1 and B0+B1. For two The sum of polynomials A0 and A1 needs to be modulo-calculated according to the rules to ensure that the data input to the Karatsuba_1 module belongs to The coefficient of . And the two The coefficients of the sum of polynomials B0 and B1 take values ​​in the range {-2, -1, 0, 1, 2}, so they must be represented using 3-bit binary numbers. Therefore, the input data port widths of Karatsuba_1 are 13 bits and 3 bits, respectively, while the input data port widths of Karatsuba_0 and Karatsuba_2 are 13 bits and 2 bits, respectively. The Karatsuba modules require a significant amount of RAM for data caching. RAM_0, RAM_1, and RAM_2 are used to cache data input to Karatsuba_0, Karatsuba_1, and Karatsuba_2, respectively. RAM_result, under the control of a finite state machine, temporarily stores the calculation results of the three two-layer Karatsuba modules. RAM_0, RAM_1, RAM_2 and RAM_result all adopt dual-port design. Port a and port b can be used for read and write operations. The port widths of RAM_0, RAM_1 and RAM_2 correspond to Karatsuba_0, Karatsuba_1 and Karatsuba_2. Since the output data of the three second-layer Karatsuba modules all belong to The input and output port widths of RAM_result are both 13 bits. Finally, the data in RAM_result needs to be taken modulo q and output from the dout port. Once the output is complete, the done signal is set to 1, and the state machine jumps to the idle state to wait for the next operation.

[0052] like Figure 5The third-layer Karatsuba module structure diagram is shown in Figure 1. The core of the module is the Schoolbook multiplication module. The input and output port settings of the third-layer Karatsuba module are similar to those of the top-layer Karatsuba module, but the input port bit width is slightly different. Because the coefficients of the corresponding positions of the sub-polynomials need to be summed before calculating the intermediate bit multiplication, The polynomial coefficients range from {-1, 0, 1}, so a 2-bit signed binary number is required. The result of adding the coefficients of the polynomials is in the range of {-2, -1, 0, 1, 2}, which requires a 3-bit signed binary number representation. In the second-layer Karatsuba_1 module, it is necessary to perform an accumulation operation on two polynomials with coefficients in the range of {-2, -1, 0, 1, 2}, and the range of the coefficients of the calculated results is {-4, -3, -2, -1, 0, 1, 2, 3, 4}, so a 4-bit signed binary number representation is required. Therefore, there are three types of Karatsuba modules with 2-bit, 3-bit and 4-bit input bit widths in the third layer. The implementation principles of Karatsuba modules with different bit widths are the same and the output port bit width is 13 bits. The present invention takes the 2-bit bit width Karatsuba module as an example. In the third-layer Karatsuba module, it is necessary to call the Schoolbook multiplication module to complete the low-bit, middle-bit and high-bit multiplication operations. Like the top-level module, RAM_0, RAM_1, RAM_2, and RAM_result are all dual-port RAMs, and their functions are identical to those described in the top-level module. Because the three parts of the multiplication operation are independent, the Schoolbook multiplication module can perform the three parts of the calculation in parallel and output the results to RAM_result for temporary storage. Finally, the data in RAM_result needs to be subjected to a modulo-q operation and output from the dout port. Once the output is complete, the done signal is set to 1, and the state machine transitions to the idle state, awaiting the next operation.

[0053] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should be considered within the scope of protection of the present invention.

[0054] What are the technical problems that this invention aims to solve and what are its advantages compared with the existing technology?

[0055] The key generation, encapsulation, and decapsulation phases of the StreamlinedNTRU Prime algorithm primarily operate on polynomials. Polynomial multiplication is used repeatedly throughout these three stages, significantly impacting the performance of the StreamlinedNTRU Prime algorithm. This paper presents a multiplier based on the three-layer Karatsuba algorithm and the Schoolbook algorithm. The use of the three-layer Karatsuba algorithm effectively reduces the number of sub-polynomial multiplications during the computational process, thereby improving the computational speed of polynomial multiplication. The multiplier's hardware architecture is streamlined, reducing hardware resource consumption.

[0056] The present invention is applicable to the hardware implementation of the polynomial multiplier of the Streamlined NTRU Prime algorithm and has the following advantages:

[0057] 1. This paper utilizes the three-layer Karatsuba algorithm and the Schoolbook algorithm to perform polynomial multiplication. The three-layer Karatsuba algorithm converts the multiplication of two original polynomials into the multiplication of multiple sub-polynomials, effectively reducing the cost of multiplication and thus improving the computational speed. The sub-polynomial multiplication is implemented in the Schoolbook module, which has a simple structure and can effectively reduce hardware resource consumption.

[0058] 2. Both the Karatsuba and Schoolbook modules of the present invention use dual-port RAM for data caching. The modules are designed with three RAMs for temporarily storing high-order, mid-order, and low-order inputs, respectively, and one RAM for caching calculation results, effectively improving storage efficiency.

[0059] 3. The hardware design of the present invention has high module reusability. When the security level of the algorithm needs to be adjusted, only the port width of some modules needs to be adjusted without redesigning, which can reduce development costs.

[0060] 4. The hardware design of the present invention has high parallelism and can make full use of existing hardware resources to complete in parallel the operations that can be executed in parallel during the polynomial multiplication process, thereby improving computing efficiency.

[0061] 5. The polynomial multiplier hardware for the StreamlinedNTRU Prime algorithm proposed in this invention has high scalability, high computing speed, low resource consumption and other advantages, and can meet the performance and power consumption requirements of IoT terminal devices.

[0062] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0063] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concept of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims

1. A multiplier hardware architecture for post-quantum cryptography, characterized in that: include: A first-layer Karatsuba module, multiple second-layer Karatsuba modules, a third-layer Karatsuba module, and a Schoolbook multiplication module; the first-layer Karatsuba module is respectively connected to three second-layer Karatsuba modules, each second-layer Karatsuba module is respectively connected to three third-layer Karatsuba modules; each third-layer Karatsuba module is connected to one Schoolbook multiplication module; The Schoolbook multiplication module is used to perform multiplication operations of three sub-polynomials in parallel, and complete low-order, middle-order and high-order multiplication operations in parallel; the first-layer Karatsuba module and the second-layer Karatsuba module are both used to sum the high-order and low-order corresponding coefficients of the two input polynomials, and perform modulo operations on the summed results; the third-layer Karatsuba module is used to be responsible for low-order, middle-order and high-order multiplication operations respectively.

2. The multiplier hardware architecture for post-quantum cryptography according to claim 1, characterized in that: The internal implementation principles of the Karatsuba modules in the same layer are the same; the input and output port widths of the Karatsuba modules in the same layer are different.

3. The multiplier hardware architecture for post-quantum cryptography according to claim 1, characterized in that: Each Karatsuba module includes four dual-port RAMs, namely RAM_0, RAM_1, RAM_2 and RAM_result. RAM_0, RAM_1 and RAM_2 are respectively used to temporarily store data input to the lower module, and RAM_result stores the calculation results generated by the lower module.

4. The multiplier hardware architecture for post-quantum cryptography according to claim 1, characterized in that: The Schoolbook module is provided with three RAMs, which are used to store data generated by low bits, middle bits and high bits respectively. The RAM adopts a dual-port design, and both ports can perform read and write operations.

5. The multiplier hardware architecture for post-quantum cryptography according to claim 1, characterized in that: The input end of the Schoolbook module includes a clock signal clock, a reset signal reset, low-bit input data din_0, middle-bit input data din_1, and high-bit input data din_2; the output end of the Schoolbook module includes a completion signal done, an output valid signal dout_valid, low-bit output data dout_0, middle-bit output data dout_1, and high-bit output data dout_2.

6. The multiplier hardware architecture for post-quantum cryptography according to claim 1, characterized in that: The input end of the first layer Karatsuba module includes the clock signal clock, polynomial Input din_a, polynomial Input din_b, reset signal reset and start signal start; the output end of the first layer Karatsuba module includes completion signal done, calculation result output dout and output valid signal dout_valid.

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