Method for OPC difference checking of target layer layout area

Abstract

The application provides an OPC difference checking method for a target layer layout area, provides multiple first layouts, the multiple first layouts are original layouts with similar graphic shapes, each first layout comprises a target layer layout, a first mask layer graphic corresponding to each target layer layout is obtained by using the target layer layout, a second layout is obtained by merging each first layout, a third layout only comprising the target layer layout area in the second layout is screened out, an exposure profile on a photoresist of the third layout is obtained by using the third layout, a first mask layer graphic with an edge placement error greater than a limit value is marked by comparing each first mask layer graphic with the exposure profile of the third layout, and a difference reason of the marked first mask layer graphic and the corresponding target layer layout is analyzed. The application can achieve the effect of comparing and analyzing multiple mask layer graphics by using only a single layout file.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for checking OPC differences in a target layer layout region. Background Technology

[0002] In the process of exploring various product processes, multiple MPW (Multi-Project Wafer) systems are often required for the research and verification of various process parameters. One important task of OPC (Optical Proximity Correction) is to compare the MBOPC (Model-Based Optical Proximity Correction) correction results of different models to see if they meet specific requirements. However, as the node increases, this process may even require comparing the correction results of multiple model versions. Processing and checking multiple identical or similar layout files often consumes a lot of manpower and resources for repeated checks of similar patterns.

[0003] Existing inspection methods mainly use XOR (or non-logical operation) and other means to compare the differences between the original layout (drawn), target layer (target layer), and mask layer of similar graphics. However, in addition to displaying the differences, it is still necessary to set up simulation calculations in other interfaces to further determine the differences between simulation results.

[0004] To address the aforementioned issues, a novel OPC difference detection method for the target layer map region is required. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an OPC difference checking method for the target layer layout region, which solves the problem that an important task of OPC in the prior art is to compare the MBOPC (Model-Based Optical Proximity Correction) correction results of different models to see if they meet specific requirements. However, as the node increases, this process may even require comparing the correction results of multiple models. Processing and checking multiple identical or similar layout files often consumes a lot of manpower and resources for repeated checks of similar graphics.

[0006] To achieve the above and other related objectives, the present invention provides a method for checking OPC differences in a target layer layout region, comprising:

[0007] Step 1: Provide multiple versions of the first image. The multiple versions of the first image are original images with similar graphic shapes. Each first image includes a target layer image. Use the target layer image of each version to obtain its corresponding first photomask layer graphic.

[0008] Step 2: Merge the first version of each version to obtain a second version;

[0009] Step 3: Select the third layout in the second layout that only includes the target layer layout area, and use the third layout to obtain its exposed outline on the photoresist;

[0010] Step 4: Compare the exposed outlines of the first photomask layer pattern in each version with the third version, and mark the first photomask layer pattern whose edge placement error is greater than the limit value.

[0011] Step 5: Analyze the reasons for the differences between the marked first photomask layer image and its corresponding target layer version image.

[0012] Preferably, the first layout in step one includes a logic device layout and an SRAM layout.

[0013] Preferably, the target layer layout in step one is an SRAM layout.

[0014] Preferably, the target layer layout in step one is a logic device layout.

[0015] Preferably, the first layout in step one is a GDS file.

[0016] Preferably, in step one, the analysis script is used to obtain the first photomask layer pattern corresponding to each version of the target layer layout.

[0017] Preferably, the method for merging each version of the first map to obtain a second map in step two includes: using calibre software to perform Boolean, layer extraction and merging operations to obtain a second map that simultaneously possesses multiple versions of the first map.

[0018] Preferably, the second version in step two is a single GDS file.

[0019] Preferably, in step three, the optical proximity correction model is used to simulate the exposed contour of the third pattern on the photoresist.

[0020] Preferably, in step four, the first photomask layer pattern with an edge placement error greater than the limit value is marked using the inspection module added to the analysis script.

[0021] Preferably, the limitation value in step four is -10 to 20 nanometers.

[0022] As described above, the OPC difference checking method for the target layer layout region of the present invention has the following beneficial effects:

[0023] This invention can achieve the effect of comparing and analyzing multiple mask layer patterns using only a single pattern file. Attached Figure Description

[0024] Figure 1The diagram shown is a schematic diagram of the OPC difference detection method of the present invention.

[0025] Figure 2 The diagram shows two versions of the target layer layout to be merged according to an embodiment of the present invention.

[0026] Figure 3 Displayed as Figure 2 A schematic diagram of the merged target layer layouts from the two versions. Detailed Implementation

[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] Please see Figure 1 This invention provides a method for checking OPC differences in a target layer layout region, comprising:

[0029] Step 1: Provide multiple versions of the first layout. These first layouts are original layouts with similar graphic shapes. Each first layout includes a target layer layout. The corresponding first photomask layer pattern is obtained using each target layer layout. The photomask layer pattern is a pattern modified from the original layout for photomask fabrication. For example, two versions of the first layout are provided, where the logic device layouts have small differences or are completely identical, and the SRAM layouts have large differences (e.g., ...). Figure 2 (As shown), then the SRAM layout is the target layout.

[0030] In an embodiment of the present invention, the first layout in step one includes a logic device layout and an SRAM layout. It should be noted that the first layout here may also include other types of layouts, which are not specifically limited here.

[0031] In an embodiment of the present invention, the target layer layout in step one is an SRAM layout. Changes in the SRAM layout have a significant impact on the device. Therefore, in actual processes, the target layer layout is preferably an SRAM layout.

[0032] In an embodiment of the present invention, the target layer layout in step one is the logic device layout. Changes in the logic device layout have little impact on the device, but in actual processes, OPC difference checks can also be performed on the logic device layout.

[0033] It should be noted that the target layer layout here can also be other types of layouts well known to those skilled in the art.

[0034] In an embodiment of the present invention, the first layout in step one is a GDS file.

[0035] In an embodiment of the present invention, step one involves using an analysis script to obtain the first mask layer graphic corresponding to each target layer layout. That is, existing technologies use analysis scripts to compare the differences between the original layout (drawn), target layer (Target layer), and mask layer of similar graphics using XOR (or non-logical operations), but in addition to displaying the differences, simulation calculations are still needed in other interfaces to further determine the differences between the simulation results.

[0036] Step 2: Merge the first version of each image to obtain a second version.

[0037] In an embodiment of the present invention, the method of merging each version of the first layout to obtain a second layout in step two includes: using calibre software to perform Boolean, layer extraction and merging operations to obtain a second layout that simultaneously has multiple versions of the first layout.

[0038] In an embodiment of the present invention, the second layout in step two is a single GDS file.

[0039] Step 3, please refer to Figure 3 The third image, which only includes the target layer area, is selected from the second image, and its exposed outline on the photoresist is obtained using the third image.

[0040] In an embodiment of the present invention, step three uses an optical proximity correction model to simulate the post-exposure profile of the third pattern on the photoresist.

[0041] Step 4: Compare the exposed outlines of the first photomask layer pattern and the third photomask layer pattern for each version, and mark the first photomask layer pattern whose edge placement error of the exposed outline of the first photomask layer pattern and the third photomask layer pattern is greater than the limit value.

[0042] In an embodiment of the present invention, in step four, the first photomask layer pattern with an edge placement error greater than the limit value is marked using an inspection module added to the analysis script. The edge placement error (EPE) is the difference between the edge of the photoresist pattern after exposure and the design pattern as simulated by the lithography software.

[0043] In an embodiment of the present invention, the limit value in step four is -10 to 20 nanometers.

[0044] Step 5: Analyze the reasons for the differences between the marked first photomask layer pattern and its corresponding target layer version pattern. For example, by comparison, it was found that due to the change in the contact hole layer, the S-shaped pattern was not selected, which caused it to be corrected according to the requirements of the logic device area, resulting in the difference.

[0045] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] In summary, this invention can achieve the effect of comparing and analyzing multiple mask layer patterns using only a single pattern file. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0047] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for checking OPC differences in a target layer map region, characterized in that, At least including: Step 1: Provide multiple versions of the first image. The multiple versions of the first image are original images with similar graphic shapes. Each first image includes a target layer image. Use the target layer image of each version to obtain its corresponding first photomask layer graphic. Step 2: Merge the first version of each version to obtain a second version; Step 3: Select the third layout in the second layout that only includes the target layer layout area, and use the third layout to obtain its exposed outline on the photoresist; Step 4: Compare the exposed outlines of the first photomask layer pattern in each version with the third version, and mark the first photomask layer pattern whose edge placement error is greater than the limit value. Step 5: Analyze the reasons for the differences between the marked first photomask layer pattern and its corresponding target layer layout.

2. The OPC difference inspection method for the target layer map region according to claim 1, characterized in that: The first layout in step one includes the logic device layout and the SRAM layout.

3. The OPC difference inspection method for the target layer layout region according to claim 1, characterized in that: The target layer layout mentioned in step one is an SRAM layout.

4. The OPC difference inspection method for the target layer layout region according to claim 1, characterized in that: The target layer layout mentioned in step one is a logic device layout.

5. The OPC difference inspection method for the target layer layout region according to claim 1, characterized in that: The first layout in step one is a GDS file.

6. The OPC difference inspection method for the target layer layout region according to claim 1, characterized in that: In step one, the analysis script is used to obtain the first mask layer pattern corresponding to the target layer layout of each version.

7. The OPC difference inspection method for the target layer map region according to claim 1, characterized in that: The method for merging each version of the first map to obtain a second map in step two includes: using calibre software to perform Boolean, layer extraction, and merging operations to obtain a second map that simultaneously possesses multiple versions of the first map.

8. The OPC difference inspection method for the target layer layout region according to claim 1 or 5, characterized in that: The second version of the image in step two is a single GDS file.

9. The OPC difference inspection method for the target layer layout region according to claim 1, characterized in that: In step three, the optical proximity correction model is used to simulate the post-exposure profile of the third pattern on the photoresist.

10. The OPC difference inspection method for the target layer layout region according to claim 6, characterized in that: In step four, the first photomask layer pattern with an edge placement error greater than the limit value is marked using the inspection module added to the analysis script.

11. The OPC difference inspection method for the target layer layout region according to claim 1, characterized in that: The limit value in step four is -10 to 20 nanometers.

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