Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate comprises a substrate and a driving structure layer arranged on the substrate, the driving structure layer comprises: arrayed pixel circuits, the arrayed pixel circuits comprise: a plurality of power supply lines; the pixel circuit further comprises: a capacitor, the capacitor comprises: a first electrode plate and a second electrode plate; the plurality of power supply lines comprise: a plurality of first power supply connection lines (VLA) located on the first conductive layer and a plurality of second power supply connection lines (VLA) located on the second conductive layer, the second conductive layer is located on the side of the first conductive layer away from the substrate, the first power supply connection lines (VLA) and the second power supply connection lines (VLB) extend along the first direction, the plurality of first power supply connection lines (VLA) and the plurality of second power supply connection lines (VLB) are arranged along the second direction; two adjacent first power supply connection lines (VLA) are connected through a connecting part located on the first conductive layer, and the connecting part is at least partially overlapped with the projection of the second electrode plate on the substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light emitting elements and controlled by thin film transistors (TFT) have become the mainstream products in the current display field. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0004] In a first aspect, the present disclosure provides a display substrate, comprising: a substrate and a driving structure layer disposed on the substrate, the driving structure layer comprising: an array of pixel circuits, the array of pixel circuits comprising: a plurality of power lines configured to provide a power signal; and the pixel circuit further comprising: a capacitor, the capacitor comprising: a first electrode plate and a second electrode plate located on a side of the first electrode plate away from the substrate;

[0005] The plurality of power lines comprises: a plurality of first power connection lines located in the first conductive layer and a plurality of second power connection lines located in the second conductive layer, the second conductive layer being located on a side of the first conductive layer away from the substrate, the first power connection lines and the second power connection lines extending along a first direction, the plurality of first power connection lines and the plurality of second power connection lines being arranged along a second direction, the first direction and the second direction intersecting;

[0006] Two adjacent first power connection lines are connected by a connection part located in the first conductive layer, and the connection part at least partially overlaps the second electrode plate in the orthographic projection of the substrate.

[0007] In some possible implementations, the first power connection line and the second power connection line of the same pixel circuit are connected, and the orthographic projection of the first power connection line on the substrate covers the orthographic projection of the second power connection line on the substrate.

[0008] In some possible implementation manners, the display panel further includes a light-emitting structure layer arranged on a side of the driving structure layer away from the base, and the light-emitting structure layer includes a plurality of light-emitting elements; the light-emitting elements are connected to the pixel circuit; at least one light-emitting element includes an anode, an organic light-emitting layer and a cathode arranged in sequence on the driving structure layer; the anode of the light-emitting element includes an anode main body part and an anode connecting part; a projection of an effective light-emitting area of the light-emitting element on the base is located inside a projection of the corresponding anode main body part on the base; and the anode connecting part is connected to the pixel circuit and the anode main body part, respectively.

[0009] The light-emitting elements include a first light-emitting element, a second light-emitting element, a third light-emitting element and a fourth light-emitting element; the first light-emitting element emits red light, the second light-emitting element emits blue light, and the third light-emitting element and the fourth light-emitting element emit green light.

[0010] The anode main body part of the first light-emitting element and the anode main body part of the second light-emitting element are hexagons, and the area of the anode main body part of the second light-emitting element is greater than that of the anode main body part of the first light-emitting element; the anode main body part of the third light-emitting element and the anode main body part of the fourth light-emitting element are pentagons, and the anode main body part of the third light-emitting element is symmetrical to the anode main body part of the fourth light-emitting element about a virtual straight line extending along the second direction.

[0011] In some possible implementation manners, the pixel circuit includes a first pixel circuit to a fourth pixel circuit, wherein the first pixel circuit is a pixel circuit connected to the first light-emitting element, the second pixel circuit is a pixel circuit connected to the second light-emitting element, the third pixel circuit is a pixel circuit connected to the third light-emitting element, and the fourth pixel circuit is a pixel circuit connected to the fourth light-emitting element.

[0012] The connecting part includes a first power supply connecting part overlapping a projection of a second plate of the first pixel circuit on the base and a second power supply connecting part overlapping a projection of a second plate of the fourth pixel circuit on the base; the first power supply connecting part and the second power supply connecting part extend along the second direction, and a virtual straight line extending along the second direction passes through the first power supply connecting part and the second power supply connecting part, respectively.

[0013] In some possible implementation manners, the pixel circuit includes a driving transistor; the driving structure layer further includes a first electrode block of the second pixel circuit; the first electrode block is located on the second conductive layer and connected to a second power supply connecting line of the second pixel circuit.

[0014] For the second pixel circuit, the orthogonal projection of the first electrode block on the substrate at least partially overlaps the orthogonal projection of the gate electrode of the driving transistor and the second plate on the substrate.

[0015] In some possible implementation manners, the pixel circuit further includes a first reset transistor and a compensation transistor; and the driving structure layer further includes a second electrode block of the fourth pixel circuit, the second electrode block being located in the second conductive layer and connected with the second power connection line of the fourth pixel circuit.

[0016] For the fourth pixel circuit, the orthogonal projection of the second electrode block on the substrate at least partially overlaps the orthogonal projection of the first electrode of the first reset transistor, the gate electrode of the compensation transistor and the gate electrode of the driving transistor on the substrate.

[0017] In some possible implementation manners, the second electrode block of the fourth pixel circuit and the second power connection line of the fourth pixel circuit form a closed loop.

[0018] The second electrode block includes a first electrode connection part, a second electrode connection part and a third electrode connection part.

[0019] The first electrode connection part extends along the second direction and is connected with the second power connection line of the fourth pixel circuit and the second electrode connection part.

[0020] The second electrode connection part extends along the first direction and is connected with the third electrode connection part.

[0021] The third electrode connection part extends along the second direction and is connected with the second power connection line of the fourth pixel circuit.

[0022] In some possible implementation manners, the driving structure layer further includes a third electrode block of the third pixel circuit, the third electrode block being located in the second conductive layer and connected with the second power connection line of the third pixel circuit.

[0023] For the third pixel circuit, the orthogonal projection of the third electrode block on the substrate at least partially overlaps the orthogonal projection of the gate electrode of the compensation transistor and the gate electrode of the driving transistor on the substrate.

[0024] In some possible implementation manners, the pixel circuit further includes a second reset transistor, and the driving structure layer further includes a fourth electrode block of the fourth pixel circuit, the fourth electrode block being located in the second conductive layer and connected with the second power connection line of the fourth pixel circuit.

[0025] For the fourth pixel circuit, the orthogonal projection of the fourth electrode block on the substrate at least partially overlaps the orthogonal projection of the gate electrode and the first electrode of the second reset transistor on the substrate.

[0026] In some possible implementation manners, the array-arranged pixel circuits further include a plurality of data lines located at the second conductive layer, the data lines extending along the first direction;

[0027] The anode main body part of the second light emitting element has a projection on the substrate that at least partially overlaps with a projection on the substrate of a first electrode block of the second pixel circuit and a second electrode block of the fourth pixel circuit, the projection on the substrate of the first electrode block is located on one side of a bisector of the anode main body part of the second light emitting element extending along the first direction, the projection on the substrate of the second electrode block is located on the other side of the bisector, and a projection on the substrate of the data line partially overlaps with a projection on the substrate of the bisector of the anode main body part of the second light emitting element extending along the first direction.

[0028] In some possible implementation manners, the anode main body part of the third light emitting element has a projection on the substrate that covers a projection on the substrate of a third electrode block of the third pixel circuit, and the projection on the substrate of the anode main body part of the third light emitting element partially overlaps with a projection on the substrate of the second power supply connection line; the second power supply connection line of the third pixel circuit is located on one side of a bisector of the anode main body part of the third light emitting element extending along the first direction.

[0029] In some possible implementation manners, the anode main body part of the fourth light emitting element has a projection on the substrate that covers a projection on the substrate of a fourth electrode block of the fourth pixel circuit, and the projection on the substrate of the anode main body part of the fourth light emitting element partially overlaps with a projection on the substrate of the second power supply connection line; the second power supply connection line of the fourth pixel circuit is located on one side of a bisector of the anode main body part of the fourth light emitting element extending along the first direction.

[0030] In some possible implementation manners, the projection on the substrate of the anode main body part of the second light emitting element does not overlap with a projection on the substrate of a hollow region, the hollow region being a region enclosed by the second electrode block and the second power supply connection line.

[0031] In some possible implementation manners, a distance between a boundary of the anode main body part of the second light emitting element and a boundary of the first electrode block covered by the anode main body part of the second light emitting element is greater than or equal to 0.5 microns and less than or equal to 1 micron, and a distance between the boundary of the anode main body part of the second light emitting element and a boundary of the second electrode connection part of the second electrode block covered by the anode main body part of the second light emitting element is greater than or equal to 0.5 microns and less than or equal to 1 micron.

[0032] A distance between a boundary of the anode main portion of the third light emitting element and a boundary of the third electrode block covered by the anode main portion of the third light emitting element is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer;

[0033] A distance between a boundary of the anode main portion of the fourth light emitting element and a boundary of the fourth electrode block covered by the anode main portion of the fourth light emitting element is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer.

[0034] In some possible implementation manners, the array-arranged pixel circuit further includes a plurality of reset signal lines, a plurality of scan signal lines, a plurality of light emitting signal lines, a plurality of first initial signal lines, and a plurality of second initial signal lines; the reset signal lines, the scan signal lines, and the light emitting signal lines are arranged in the same layer as the first electrode plate, and the first initial signal lines and the second initial signal lines are arranged in the same layer as the second electrode plate.

[0035] The plurality of reset signal lines, the plurality of scan signal lines, the plurality of light emitting signal lines, the plurality of first initial signal lines, and the plurality of second initial signal lines extend along a second direction and are arranged along a first direction.

[0036] The pixel circuit includes a first reset signal end, a second reset signal end, a first initial signal end, a second initial signal end, a scan signal end, a light emitting signal end, and a data signal end, where the first reset signal end and the second reset signal end are electrically connected to different reset signal lines respectively, the scan signal end is electrically connected to a scan signal line, the light emitting signal end is electrically connected to a light emitting signal line, the first initial signal end is electrically connected to a first initial signal line, the second initial signal end is electrically connected to a second initial signal line, and the data signal end is electrically connected to a data signal line.

[0037] In some possible implementation manners, the pixel circuit includes a plurality of transistors, and the driving structure layer includes a semiconductor layer, a first insulating layer, a third conductive layer, a second insulating layer, a fourth conductive layer, a third insulating layer, a first conductive layer, a fourth insulating layer, and a second conductive layer, which are sequentially stacked on the substrate.

[0038] The semiconductor layer includes an active layer of the plurality of transistors of at least one pixel circuit.

[0039] The third conductive layer includes a reset signal line, a scan signal line, a light emitting signal line, a first electrode plate, and a gate electrode of the plurality of transistors.

[0040] The fourth conductive layer includes a first initial signal line, a second initial signal line, and a second electrode plate.

[0041] The first conductive layer includes a first power supply connection line, a first power supply connection portion, a second power supply connection portion, and a connection block.

[0042] The second conductive layer comprises a second power supply connection line, a data signal line, a first electrode block, a second electrode block, a third electrode block, and a fourth electrode block.

[0043] In some possible implementation manners, the driving structure layer further comprises a plurality of reset connection lines located in the second conductive layer, the reset connection lines extend along a first direction, and the plurality of reset connection lines are arranged along a second direction.

[0044] The reset connection line is electrically connected to the plurality of first initial signal lines through a connection block located in the first conductive layer, and a projection of the reset connection line on the substrate at least partially overlaps with a projection of the anode main body part of the first light emitting element along a first direction.

[0045] In some possible implementation manners, pixel circuits adjacent to the pixel circuit in the same row are a first adjacent pixel circuit and a second adjacent pixel circuit, a first electrode of a first reset transistor of the pixel circuit is connected to a first electrode of a first reset transistor of the first adjacent pixel circuit through a semiconductor layer, and a first electrode of a second reset transistor of the pixel circuit is connected to a first electrode of a second reset transistor of the second adjacent pixel circuit through a semiconductor layer.

[0046] The first initial signal line is connected to the first electrode of the first reset transistor of the pixel circuit and the first reset transistor of the first adjacent pixel circuit through a via, and the second initial signal line is connected to the first electrode of the second reset transistor of the pixel circuit and the second reset transistor of the second adjacent pixel circuit through a via.

[0047] In some possible implementation manners, the reset signal line and the scan signal line of the pixel circuit are located on the same side of the first electrode plate of the pixel circuit, the reset signal line is located on a side of the scan signal line away from the first electrode plate of the pixel circuit, and the light emitting signal line of the pixel circuit is located on a side of the first electrode plate of the pixel circuit away from the scan signal line.

[0048] The second initial signal line of the pixel circuit is located between the first initial signal line of the next row of pixel circuits and the second electrode plate of the next row of pixel circuits, and is located on a side of the second electrode plate of the pixel circuit away from the first initial signal line of the pixel circuit.

[0049] In some possible implementation manners, the reset connection line comprises a first protruding part extending towards one side of the reset connection line along the second direction and a second protruding part extending towards the other side of the reset connection line.

[0050] The first protruding part and the second protruding part both overlap with a virtual straight line extending along the second direction, and the projections of the first protruding part and the second protruding part on the substrate both partially overlap with a projection of the anode main body part of the first light emitting element.

[0051] In some possible implementation manners, the pixel circuit further includes a write transistor, a first light-emitting control transistor, and a second light-emitting control transistor.

[0052] The first electrode and the second electrode of the first reset transistor, the first electrode of the compensation transistor, the first electrode of the first light-emitting control transistor, the second electrode of the second light-emitting transistor, the first electrode and the second electrode of the second reset transistor are located on one side of the first power connection line of the pixel circuit close to the first power connection line of the previous column of pixel circuits, and the first electrode of the write transistor is located on one side of the first power connection line of the pixel circuit close to the first power connection line of the next column of pixel circuits.

[0053] The first electrode and the second electrode of the first reset transistor and the first electrode of the compensation transistor of the first pixel circuit are located on a first side of the first power connection part, and the second electrode of the second light-emitting control transistor and the first electrode and the second electrode of the second reset transistor are located on a second side of the first power connection part.

[0054] The first electrode and the second electrode of the first reset transistor and the first electrode of the compensation transistor of the fourth pixel circuit are located on a first side of the second power connection part, and the second electrode of the second light-emitting control transistor and the first electrode and the second electrode of the second reset transistor are located on a second side of the second power connection part.

[0055] In some possible implementation manners, the reset connection line is located on one side of the second power connection line of the pixel circuit away from the data signal line.

[0056] The data signal line of the pixel circuit is located between the second power connection line of the pixel circuit and the second power connection line of the adjacent pixel circuit.

[0057] In some possible implementation manners, the first power connection line and the second power connection line of the pixel circuit include a first boundary and a second boundary.

[0058] The distance between the first boundary of the first power connection line and the first boundary of the second power connection line is greater than or equal to 0.5 microns and less than or equal to 1 micron.

[0059] The distance between the second boundary of the first power connection line and the second boundary of the second power connection line is greater than or equal to 0.5 microns and less than or equal to 1 micron.

[0060] In a second aspect, the present disclosure further provides a display device, including the display substrate.

[0061] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0062] The accompanying drawings are used to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0063] FIG. 1A A structure schematic view of a film layer in which a second electrode plate is located and a first conductive layer in a display substrate provided by an embodiment of the present disclosure is shown in FIG. 1;

[0064] FIG. 1B A structure schematic view of a film layer in which a second electrode plate is located and a first conductive layer in a display substrate provided by an embodiment of the present disclosure is shown in FIG. 1; FIG. 2

[0065] FIG. 2 A structure schematic view of a first conductive layer and a second conductive layer in a display substrate provided by an embodiment of the present disclosure is shown in FIG. 2;

[0066] FIG. 3A An equivalent circuit schematic view of a pixel circuit is shown in FIG. 3;

[0067] FIG. 3B An equivalent circuit schematic view of another pixel circuit is shown in FIG. 4;

[0068] FIG. 4 A structure schematic view of a second conductive layer and an anode layer of a display substrate provided by an exemplary embodiment is shown in FIG. 5;

[0069] FIG. 5A A schematic view of a pixel circuit after a semiconductor layer pattern is formed is provided in FIG. 6; FIG. 3A

[0070] A schematic view of a pixel circuit after a semiconductor layer pattern is formed is provided in FIG. 6; FIG. 5B FIG. 3A FIG. 2 A schematic view of a pixel circuit after a semiconductor layer pattern is formed is provided in FIG. 6;

[0071] FIG. 5C A schematic view of a pixel circuit after a semiconductor layer pattern is formed is provided in FIG. 6; FIG. 3B

[0072] A schematic view of a third conductive layer pattern of a pixel circuit provided by an embodiment of the present disclosure is shown in FIG. 7; FIG. 6A FIG. 3A A schematic view of a third conductive layer pattern of a pixel circuit provided by an embodiment of the present disclosure is shown in FIG. 7;

[0073] FIG. 6B FIG. 3B A schematic view of a third conductive layer pattern of a pixel circuit provided by an embodiment of the present disclosure is shown in FIG. 7;

[0074] FIG. 7A A schematic view of a third conductive layer pattern of a pixel circuit provided by an embodiment of the present disclosure is shown in FIG. 7; FIG. 3A A schematic view of a third conductive layer pattern of a pixel circuit provided by an embodiment of the present disclosure is shown in FIG. 7;​​​​​

[0075] FIG. 7B provided FIG. 3A schematic view of the pixel circuit after formation of the third conductive layer pattern FIG. 2 ;

[0076] FIG. 7C provided FIG. 3B schematic view of the pixel circuit after formation of the third conductive layer pattern

[0077] FIG. 8 provided FIG. 3A and FIG. 3B schematic view of the fourth conductive layer pattern of the pixel circuit

[0078] FIG. 9A provided FIG. 3A schematic view of the pixel circuit after formation of the fourth conductive layer pattern FIG. 9B provided FIG. 3A schematic view of the pixel circuit after formation of the fourth conductive layer pattern FIG. 2 ;

[0079] FIG. 9C provided FIG. 3B schematic view of the pixel circuit after formation of the fourth conductive layer pattern

[0080] FIG. 10A provided FIG. 3A schematic view of the third insulating layer pattern of the pixel circuit

[0081] FIG. 10B provided FIG. 3A schematic view of the third insulating layer pattern of the pixel circuit FIG. 2 ;

[0082] FIG. 10C provided FIG. 3B schematic view of the third insulating layer pattern of the pixel circuit

[0083] FIG. 11A provided FIG. 3A schematic view of the pixel circuit after formation of the third insulating layer pattern FIG. 11B provided FIG. 3A schematic view of the pixel circuit after formation of the third insulating layer pattern FIG. 2 ;

[0084] FIG. 11C provided FIG. 3B schematic view of the pixel circuit after formation of the third insulating layer pattern

[0085] FIG. 12A provided FIG. 3A schematic view of the first conductive layer pattern of the pixel circuit

[0086] FIG. 12BFor FIG. 3A schematic view of a first conductive layer pattern of a pixel circuit provided FIG. 2 ;

[0087] FIG. 12C For FIG. 3B schematic view of a first conductive layer pattern of a pixel circuit provided

[0088] FIG. 13A For FIG. 3A schematic view of a first conductive layer pattern of a pixel circuit provided FIG. 13B For FIG. 3A schematic view of a first conductive layer pattern of a pixel circuit provided FIG. 2 ;

[0089] FIG. 13C For FIG. 3B schematic view of a first conductive layer pattern of a pixel circuit provided

[0090] FIG. 14A For FIG. 3A and FIG. 3B schematic view of a fourth insulating layer pattern of a pixel circuit provided

[0091] FIG. 14B For FIG. 3A schematic view of a fourth insulating layer pattern of a pixel circuit provided

[0092] FIG. 15A For FIG. 3A schematic view of a fourth insulating layer pattern of a pixel circuit provided FIG. 15B For FIG. 3A schematic view of a fourth insulating layer pattern of a pixel circuit provided FIG. 2 ;

[0093] FIG. 15C For FIG. 3B schematic view of a fourth insulating layer pattern of a pixel circuit provided

[0094] FIG. 16A For FIG. 3A and FIG. 3B schematic view of a second conductive layer pattern of a pixel circuit provided

[0095] FIG. 16B For FIG. 3A schematic view of a second conductive layer pattern of a pixel circuit provided

[0096] FIG. 17A For FIG. 3A schematic view of a second conductive layer pattern of a pixel circuit provided

[0097] FIG. 17B For FIG. 3AA schematic view of the pixel circuit after the second conductive layer pattern is provided FIG. 2 ;

[0098] FIG. 17C A schematic view of the pixel circuit after the second conductive layer pattern is provided FIG. 3B ;

[0099] FIG. 18 A schematic view of the anode layer pattern

[0100] FIG. 19A A schematic view of the anode layer pattern

[0101] FIG. 19B A schematic view of the anode layer pattern FIG. 2 ;

[0102] FIG. 19C A schematic view of the anode layer pattern

[0103] FIG. 20 A schematic view of the pixel definition layer pattern

[0104] FIG. 21A A schematic view of the pixel definition layer pattern

[0105] FIG. 21B A schematic view of the pixel definition layer pattern FIG. 2 ;

[0106] FIG. 21C A schematic view of the pixel definition layer pattern DETAILED DESCRIPTION

[0107] In order to make the objects, technical solutions and advantages of the present disclosure clearer, below the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments can be implemented in multiple different forms. One of ordinary skill in the art can easily understand the fact that the means and content can be changed into various forms without departing from the purpose of the present disclosure and the scope thereof. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed structures

[0108] In the drawings, the size, the thickness, or the region of each component is sometimes exaggerated, and sometimes shrunk for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to such a scale. The drawings are schematic views showing ideal examples, and the present disclosure is not limited to shapes or values shown in the drawings.

[0109] In this specification, ordinal numbers such as "first", "second", and "third" are used to avoid confusion among components, and are not used to limit the number in the specification.

[0110] In this specification, terms of "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like that indicate the orientation or positional relationship are used to describe the positional relationship of components with reference to the drawings, for the convenience of this specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed depending on the situation.

[0111] In this specification, unless explicitly stated and limited otherwise, the terms "mount", "connected", and "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or communication between two elements. The specific meaning of the above terms in the present disclosure can be understood by those skilled in the art according to the specific circumstances.

[0112] In this specification, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0113] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other.

[0114] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0115] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0116] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0117] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0118] The display substrate includes pixel circuits and power lines that provide power signals to the pixel circuits. The loss of power lines during transmission can affect the display uniformity of the display substrate.

[0119] FIG. 1A This is a schematic diagram of the structure of the film layer containing the second electrode plate and the first conductive layer in the display substrate provided in this embodiment of the disclosure. FIG. 1B This is a schematic diagram of the structure of the film layer containing the second electrode plate and the first conductive layer in the display substrate provided in the embodiments of this disclosure. FIG. 2 , FIG. 2 This is a schematic diagram of the structure of the first conductive layer and the second conductive layer in the display substrate provided in an embodiment of this disclosure. FIG. 1A , FIG. 1B and FIG. 2 As shown, the display substrate provided in this embodiment may include: a substrate and a driving structure layer disposed on the substrate. The driving structure layer includes: an array of pixel circuits P. The array of pixel circuits includes: multiple power lines configured to provide power signals. The pixel circuits also include: a capacitor, which includes: a first electrode plate and a second electrode plate C2 located on the side of the first electrode plate away from the substrate.

[0120] In one exemplary embodiment, such as FIG. 3AAs shown, the plurality of power lines include a plurality of first power connection lines VLA located at the first conductive layer and a plurality of second power connection lines VLB located at the second conductive layer, the second conductive layer being located at a side of the first conductive layer away from the substrate.

[0121] In an example embodiment, the first power connection lines VLA and the second power connection lines VLB extend along a first direction, the plurality of first power connection lines VLA and the plurality of second power connection lines VLB are arranged along a second direction, and the first direction and the second direction intersect.

[0122] In the present disclosure, two adjacent first power connection lines VLA are connected by a connection portion located at the first conductive layer, and the connection portion at least partially overlaps the projection of the second electrode plate C2 on the substrate.

[0123] In an example embodiment, the display substrate can be a Low Temperature Polycrystalline Oxide (LTPO) display substrate or a Low Temperature Poly-silicon (LTPS) display substrate.

[0124] In an example embodiment, at least one power line continuously provides a high-level signal.

[0125] In an example embodiment, the substrate can be a rigid substrate or a flexible substrate, wherein the rigid substrate can be, but is not limited to, one or more of glass, conductive foil; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

[0126] The display substrate provided by the embodiments of the present disclosure includes a substrate and a driving structure layer arranged on the substrate. The driving structure layer includes: pixel circuits arranged in an array. The pixel circuits include: a plurality of power lines configured to provide a power signal. The pixel circuits further include: a capacitor including: a first electrode plate and a second electrode plate located on a side of the first electrode plate away from the substrate. The plurality of power lines include: a plurality of first power connection lines located on a first conductive layer and a plurality of second power connection lines located on a second conductive layer. The second conductive layer is located on a side of the first conductive layer away from the substrate. The first power connection lines and the second power connection lines extend along a first direction. The plurality of first power connection lines and the plurality of second power connection lines are arranged along a second direction. The first direction and the second direction intersect. Two adjacent first power connection lines are connected by a connection part located on the first conductive layer. The connection part is at least partially overlapped with the second electrode plate in the projection of the substrate. The present disclosure reduces the loss of the power lines in the transmission process by connecting the two adjacent first power connection lines by the connection part located on the first conductive layer, thereby improving the display uniformity of the display substrate.

[0127] In an example embodiment, as shown in FIG. 3A 、 FIG. 3A and FIG. 3A , the first power connection line VLA and the second power connection line VLB of the same pixel circuit are connected, and the projection of the first power connection line VLA on the substrate covers the projection of the second power connection line VLB on the substrate.

[0128] In an example embodiment, the projection of the first power connection line on the substrate of the same pixel circuit covers the projection of the second power connection line on the substrate, which can avoid the second power connection line exceeding the first power connection line due to the alignment deviation in the process, and can improve the optical fingerprint recognition effect of the display substrate.

[0129] In an example embodiment, the first power connection line and the second power connection line of the pixel circuit include: a first boundary and a second boundary.

[0130] In an example embodiment, the distance between the first boundary of the first power connection line and the first boundary of the second power connection line is greater than or equal to 0.5 microns and less than or equal to 1 micron.

[0131] In an example embodiment, the distance between the second boundary of the first power connection line and the second boundary of the second power connection line is greater than or equal to 0.5 microns and less than or equal to 1 micron.

[0132] In an example embodiment, the display substrate can further include: a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate. The light-emitting structure layer includes: a plurality of light-emitting elements. The light-emitting elements are connected to the pixel circuits.

[0133] In an example embodiment, the light emitting element can be an organic electroluminescent diode (OLED) or a quantum dot light emitting diode (QLED). Among them, the OLED can include a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked

[0134] In an example embodiment, the organic light emitting layer can include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked. In an example embodiment, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole block layer of all sub-pixels can be a common layer connected together, the emitting layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the electron block layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0135] In an example embodiment, the pixel circuit can be 7T1C or 8T1C, and the present disclosure does not make any limitation thereto.

[0136] In an example embodiment, FIG. 3A is an equivalent circuit schematic diagram of a pixel circuit. FIG. 3B is described by taking 7T1C as an example. As shown in FIG. 3B , the pixel circuit can include 7 transistors (first transistor T1 to seventh transistor T7), 1 capacitor C, and 9 signal terminals (data signal terminal Data, scanning signal terminal Gate, first reset signal terminal Reset1, second reset signal terminal Reset2, light emitting signal terminal EM, first initial signal terminal Vinit1, second initial signal terminal Vinit2, first power terminal VDD, and second power terminal VSS). Among them, the capacitor C includes a first plate C1 and a second plate C2. The transistor includes an active layer, a gate electrode, a first electrode, and a second electrode.

[0137] In an example embodiment, as FIG. 3BAs shown, the first plate of the capacitor C is connected with the first power supply end VDD, and the second plate of the capacitor C is connected with the first node N1. The gate electrode of the first transistor T1 is connected with the first reset signal end Reset1, the first electrode of the first transistor T1 is connected with the first initial signal end Vinit1, and the second electrode of the first transistor is connected with the first node N1. The gate electrode of the second transistor T2 is connected with the scanning signal end Gate, the first electrode of the second transistor T2 is connected with the first node N1, and the second electrode of the second transistor T2 is connected with the second node N2. The gate electrode of the third transistor T3 is connected with the first node N1, the first electrode of the third transistor T3 is connected with the third node N3, and the second electrode of the third transistor T3 is connected with the second node N2. The gate electrode of the fourth transistor T4 is connected with the scanning signal end Gate, the first electrode of the fourth transistor T4 is connected with the data signal end Data, and the second electrode of the fourth transistor T4 is connected with the third node N3. The gate electrode of the fifth transistor T5 is connected with the emission signal end EM, the first electrode of the fifth transistor T5 is connected with the first power supply end VDD, and the second electrode of the fifth transistor T5 is connected with the third node N3. The gate electrode of the sixth transistor T6 is connected with the emission signal end EM, the first electrode of the sixth transistor T6 is connected with the second node N2, and the second electrode of the sixth transistor T6 is connected with the first electrode of the light emitting element. The gate electrode of the seventh transistor T7 is connected with the scanning signal end Gate, the first electrode of the seventh transistor T7 is connected with the second initial signal end Vinit2, and the second electrode of the seventh transistor T7 is connected with the first electrode of the light emitting element. The second electrode of the light emitting element is connected with the second power supply end VSS.

[0138] In an exemplary embodiment, the first transistor T1 can be referred to as a first reset transistor, and when the first reset signal end Reset1 inputs a valid level signal, the first transistor T1 transmits an initialization voltage to the first node N1 to initialize the charge amount of the first node N1.

[0139] In an exemplary embodiment, the second transistor T2 can be referred to as a compensation transistor, and when the scanning signal end Gate inputs a valid level signal, the second transistor T2 transmits the signal of the second node N2 to the first node N1 to compensate the signal of the first node N1.

[0140] In an exemplary embodiment, the third transistor T3 can be referred to as a driving transistor, and the third transistor T3 determines a driving current flowing between the first power supply end VDD and the second power supply end VSS according to the potential difference between the gate electrode and the first electrode.

[0141] In an exemplary embodiment, the fourth transistor T4 can be referred to as a write transistor or the like, and when the scanning signal end Gate inputs a valid level signal, the fourth transistor T4 inputs the data voltage of the data signal end Data to the pixel circuit.

[0142] In an example embodiment, the fifth transistor T5 can be referred to as a first light-emitting control transistor, and the sixth transistor T6 can be referred to as a second light-emitting control transistor. When the light-emitting signal end EM inputs a valid level signal, the fifth transistor T5 and the sixth transistor T6 make the light-emitting element emit light by forming a driving current path between the first power supply end VDD and the second power supply end VSS.

[0143] In an example embodiment, the seventh transistor T7 can be referred to as a second reset transistor, and when the second reset signal end Reset2 inputs a valid level signal, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light-emitting element to initialize the charge amount of the first electrode of the light-emitting element.

[0144] In an example embodiment, the signal of the first power supply end VDD is a high level signal continuously provided, and the signal of the second power supply end VSS is a low level signal.

[0145] In an example embodiment, the first transistor T1 to the seventh transistor T7 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product.

[0146] In an example embodiment, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0147] The working process of the pixel circuit will be described below by taking the seven transistors in the pixel circuit in FIG. 8 as P-type transistors as an example. FIG. 3B

[0148] In an example embodiment, the working process of the pixel circuit can include:

[0149] ​In the first stage, referred to as a reset stage, the signals of the first reset signal terminal Reset1 and the second reset signal terminal Reset2 are low level signals, and the signals of the scan signal terminal Gate and the light emitting signal terminal EM are high level signals. The signal of the first reset signal terminal Reset1 is a low level signal, the first transistor T1 is turned on, the signal of the first initial signal terminal Vinit1 is provided to the first node N1, the capacitor C is initialized, and the original data voltage in the capacitor C is cleared. The signal of the second reset signal terminal Reset2 is a low level signal, the seventh transistor T7 is turned on, the signal of the second initial signal terminal Vinit2 is provided to the first electrode of the light emitting element L, the first electrode of the light emitting element L is initialized, and the original data voltage in the first electrode of the light emitting element L is cleared. The signals of the scan signal terminal Gate and the light emitting signal terminal EM are high level signals, the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off. In this stage, the light emitting element L does not emit light.

[0150] In the second stage, referred to as a data writing stage or a threshold compensation stage, the signal of the scan signal terminal Gate is a low level signal, the signals of the first reset signal terminal Reset1, the second reset signal terminal Reset2 and the light emitting signal terminal EM are high level signals, and the data signal terminal Data outputs a data voltage. In this stage, the third transistor T3 is turned on because the first node N1 is a low level signal. The signal of the scan signal terminal Gate is a low level signal, the second transistor T2 and the fourth transistor T4 are turned on, the data voltage output by the data signal terminal Data is provided to the first node N1 through the third node N3, the turned-on third transistor T3, the second node N2 and the turned-on second transistor T2, and the difference between the data voltage output by the data signal terminal Data and the threshold voltage of the third transistor T3 is charged into the capacitor C, until the voltage of the first node N1 is Vd-|Vth|, Vd is the data voltage output by the data signal terminal Data, and Vth is the threshold voltage of the third transistor T3. The signals of the first reset signal terminal Reset1 and the second reset signal terminal Reset2 are high level signals, the first transistor T1 and the seventh transistor T7 are turned off. The signal of the light emitting signal terminal EM is a high level signal, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0151] The third stage, known as the light-emitting stage, involves a low-level signal at the light-emitting signal terminal EM, while the signals at the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the scan signal terminal Gate are all high-level signals. With the light-emitting signal terminal EM low, the fifth transistor T5 and the sixth transistor T6 are turned on. The power supply voltage output from the first power supply terminal VDD provides a driving voltage to the first electrode of the light-emitting element L through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element L to emit light.

[0152] During the pixel circuit driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd - |Vth|, the driving current of the third transistor T3 is:

[0153] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0154] Where I is the driving current flowing through the third transistor T3, which is also the driving current driving the light-emitting element L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal terminal Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0155] In one exemplary embodiment, FIG. 3A This is a schematic diagram of the equivalent circuit of another pixel circuit. FIG. 3B This explanation uses 8T1C as an example. FIG. 3A As shown, the pixel circuit may include 8 transistors (transistor T1 to transistor T8), 1 capacitor C, and 11 signal terminals (data signal terminal Data, scan signal terminal Gate, first reset signal terminal Reset1, second reset signal terminal Reset2, light emission signal terminal EM, first initial signal terminal Vinit1, second initial signal terminal Vinit2, first control terminal S1, second control terminal S2, first power supply terminal VDD, and second power supply terminal VSS). The capacitor C includes a first plate C1 and a second plate C2. FIG. 3B The provided pixel circuit and FIG. 4 The pixel circuit provided differs in that an eighth transistor T8 is added, wherein the gate electrode of the eighth transistor T8 is electrically connected to the first control terminal S1, the first electrode of the eighth transistor T8 is electrically connected to the second control terminal S2, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3.

[0156] In an example embodiment, the first control terminal S1 can be a first reset signal terminal Reset1.

[0157] In an example embodiment, the second control terminal S2 can be a first initial signal terminal Vinit1, or can be a second initial signal terminal Vinit2, or can be another signal terminal, and the present disclosure does not make any limitation in this regard.

[0158] In an example embodiment, the eighth transistor T8 can be referred to as a third reset transistor, which transmits the initialization voltage to the third node N3 to initialize the charge amount of the third node N3 when the first control terminal S1 inputs a valid level signal.

[0159] FIG. 4 The working process of the pixel circuit provided is different from that of the pixel circuit provided in FIG. 4 The working process of the pixel circuit provided is different from that of the pixel circuit provided in FIG. 4 The eighth transistor T8 in the pixel circuit provided is turned on to initialize the third node N3.

[0160] In an example embodiment, the at least one light emitting element comprises: an anode, an organic light emitting layer and a cathode which are sequentially stacked on the driving structure layer. The effective light emitting area of the light emitting element is located inside the orthographic projection of the corresponding anode main body part on the substrate.

[0161] In an example embodiment, the anode of the light emitting element comprises: an anode main body part and an anode connecting part; the anode connecting part is connected with the pixel circuit and the anode main body part respectively.

[0162] In an example embodiment, the light emitting element comprises: a first light emitting element, a second light emitting element, a third light emitting element and a fourth light emitting element; the first light emitting element emits red light, the second light emitting element emits blue light, and the third light emitting element and the fourth light emitting element emit green light.

[0163] FIG. 4 The structure schematic diagram of the second conductive layer and the anode layer of the display substrate provided in an example embodiment is shown, wherein the anode layer is the film layer where the anode is located, FIG. 1A The anode RA of the first light emitting element, the anode BA of the second light emitting element, the anode GA1 of the third light emitting element and the anode GA2 of the fourth light emitting element are included.

[0164] In an example embodiment, as FIG. 1B shown, the shapes of the anode main body part of the first light emitting element and the anode main body part of the second light emitting element are hexagonal, and the area of the anode main body part of the second light emitting element is greater than that of the anode main body part of the first light emitting element.

[0165] In an example embodiment, as shown in FIG. 1, the shape of the anode main portion of the third light emitting element and the anode main portion of the fourth light emitting element is a pentagon, and the anode main portion of the third light emitting element and the anode main portion of the fourth light emitting element are symmetrical about a virtual straight line extending in the second direction. FIG. 2 In an example embodiment, as shown in FIG. 1, the shape of the anode main portion of the third light emitting element and the anode main portion of the fourth light emitting element is a pentagon, and the anode main portion of the third light emitting element and the anode main portion of the fourth light emitting element are symmetrical about a virtual straight line extending in the second direction.

[0166] In an example embodiment, the shape of the anode main portion of the third light emitting element and the anode main portion of the fourth light emitting element can include an acute angle, the acute angle included in the shape of the anode main portion of the third light emitting element opens upward, and the acute angle included in the shape of the anode main portion of the fourth light emitting element opens downward.

[0167] In an example embodiment, as shown in FIG. 1, the light emitting elements in the same row are arranged in a first arrangement manner or a second arrangement manner, the first arrangement manner is that the first light emitting element, the third light emitting element, the second light emitting element, and the fourth light emitting element are sequentially arranged in the second direction, and the second arrangement manner is that the second light emitting element, the fourth light emitting element, the first light emitting element, and the third light emitting element are sequentially arranged in the second direction, wherein the first light emitting element and the second light emitting element of adjacent rows are located in the same column, and the third light emitting element and the fourth light emitting element of adjacent rows are located in the same column. FIG. 2 In an example embodiment, the pixel circuit includes a first pixel circuit to a fourth pixel circuit, wherein the first pixel circuit is a pixel circuit connected with the first light emitting element, the second pixel circuit is a pixel circuit connected with the second light emitting element, the third pixel circuit is a pixel circuit connected with the third light emitting element, and the fourth pixel circuit is a pixel circuit connected with the fourth light emitting element.

[0168] In an example embodiment, the first electrode and the second electrode of the first reset transistor, the first electrode of the compensation transistor, the first electrode of the first light emitting control transistor, the second electrode of the second light emitting transistor, the first electrode and the second electrode of the second reset transistor are located on one side of the first power connection line of the pixel circuit close to the first power connection line of the previous column of pixel circuits, and the first electrode of the write transistor is located on the other side of the first power connection line of the pixel circuit close to the first power connection line of the next column of pixel circuits.

[0169] In an example embodiment, the first electrode and the second electrode of the first reset transistor and the first electrode of the compensation transistor of the first pixel circuit are located on the first side of the first power connection portion, and the second electrode of the second light emitting control transistor and the first electrode and the second electrode of the second reset transistor are located on the second side of the first power connection portion.

[0170]

[0171] ​In one exemplary embodiment, the first and second terminals of the first reset transistor and the first terminal of the compensation transistor of the fourth pixel circuit are located on the first side of the second power connection portion, and the second terminal of the second light-emitting control transistor and the first and second terminals of the second reset transistor are located on the second side of the second power connection portion.

[0172] In one exemplary embodiment, such as FIG. 4 and FIG. 2 As shown, the connection portion may include: a first power connection portion VL1 that overlaps with the orthographic projection of the second electrode plate of the first pixel circuit on the substrate and a second power connection portion VL2 that overlaps with the orthographic projection of the second electrode plate of the fourth pixel circuit on the substrate.

[0173] In one exemplary embodiment, such as FIG. 4 and FIG. 1A As shown, a virtual straight line extending along the second direction passes through the first power connection part and the second power connection part respectively.

[0174] In one exemplary embodiment, such as FIG. 1B and FIG. 5A through FIG. 21C As shown, the first power connection part VL1 and the second power connection part VL2 extend along the second direction and are arranged in the same layer as the first power connection line.

[0175] In one exemplary embodiment, such as FIG. 5A through FIG. 21C As shown, the connection portion may further include: a third power connection portion VL3 overlapping with the orthographic projection of the second electrode plate of the second pixel circuit onto the substrate, or a third power connection portion VL3 overlapping with the orthographic projection of the second substrate of the third pixel circuit onto the substrate. FIG. 5A through FIG. 5C The following description uses a third power connection portion VL3, which overlaps with the orthographic projection of the second substrate onto the substrate and the third pixel circuit, as an example. The connection portion arrangement provided in this embodiment of the present disclosure includes a ring between adjacent first power connection lines of the first conductive layer, which can prevent the gate electrode of the driving transistor from being interfered with by external signals and improve the reliability of the display substrate.

[0176] In one exemplary embodiment, such as FIG. 5A and FIG. 3A As shown, at least one pixel circuit has a first via V1 on the second plate of the capacitor, which exposes the first plate of the capacitor.

[0177] In one exemplary embodiment, such as FIG. 5B and FIG. 3A As shown, the first power supply line of the pixel circuit is connected to the second plate of the capacitor.

[0178] In one exemplary embodiment, such as FIG. 2 and FIG. 5CAs shown in FIG. 1, the second plate of the capacitor of the adjacent pixel circuit in the same row is electrically connected. The electrical connection of the second plate of the capacitor of the adjacent pixel circuit in the same row reduces the loss of the power supply line in the transmission process, and improves the display uniformity of the display substrate.

[0179] In an example embodiment, as shown in FIG. 1, the driving structure layer further comprises a first electrode block BL1 of the second pixel circuit, wherein the first electrode block BL1 is located in the second conductive layer and connected with the second power supply connection line of the second pixel circuit. FIG. 3B and FIG. 5A through FIG. 5C As shown in FIG. 1, the driving structure layer further comprises a second electrode block BL2 of the fourth pixel circuit, wherein the second electrode block BL2 is located in the second conductive layer and connected with the second power supply connection line of the fourth pixel circuit.

[0180] In an example embodiment, for the second pixel circuit, the orthographic projection of the first electrode block on the substrate at least partially overlaps with the orthographic projection on the substrate of the gate electrode of the driving transistor and the second plate.

[0181] In the present disclosure, the first electrode block BL1 can ensure the flatness of the anode of the second light emitting element, and can improve the display effect of the display substrate.

[0182] In an example embodiment, as shown in FIG. 1, the driving structure layer further comprises a second electrode block BL2 of the fourth pixel circuit, wherein the second electrode block BL2 is located in the second conductive layer and connected with the second power supply connection line of the fourth pixel circuit. FIG. 5A and FIG. 5B As shown in FIG. 1, the driving structure layer further comprises a second electrode block BL2 of the fourth pixel circuit, wherein the second electrode block BL2 is located in the second conductive layer and connected with the second power supply connection line of the fourth pixel circuit.

[0183] In an example embodiment, for the fourth pixel circuit, the orthographic projection of the second electrode block on the substrate at least partially overlaps with the orthographic projection on the substrate of the first electrode of the first reset transistor, the gate electrode of the compensation transistor and the gate electrode of the driving transistor.

[0184] In the present disclosure, the second electrode block BL2 can ensure the flatness of the anode of the fourth light emitting element, and can improve the display effect of the display substrate.

[0185] In an example embodiment, as shown in FIG. 1, the driving structure layer further comprises a second electrode block BL2 of the fourth pixel circuit, wherein the second electrode block BL2 is located in the second conductive layer and connected with the second power supply connection line of the fourth pixel circuit. FIG. 5B and FIG. 5A As shown in FIG. 1, the driving structure layer further comprises a second electrode block BL2 of the fourth pixel circuit, wherein the second electrode block BL2 is located in the second conductive layer and connected with the second power supply connection line of the fourth pixel circuit.

[0186] In an example embodiment, the first electrode connecting part BL2A extends along the second direction and is connected with the second power supply connection line VLB and the second electrode connecting part BL2B of the fourth pixel circuit; the second electrode connecting part BL2B extends along the first direction and is connected with the third electrode connecting part BL2C; and the third electrode connecting part BL2C extends along the second direction and is connected with the second power supply connection line VLB of the fourth pixel circuit.

[0187] In an example embodiment, as shown in FIG. 5B and FIG. 5A The driving structure layer further includes a third electrode block BL3 of the third pixel circuit, the third electrode block BL3 is located in the second conductive layer and is connected with the second power supply connection line of the third pixel circuit.

[0188] In an example embodiment, for the third pixel circuit, the orthographic projection of the third electrode block on the substrate partially overlaps the orthographic projection of the gate electrode of the compensation transistor and the gate electrode of the driving transistor on the substrate.

[0189] In the present disclosure, the arrangement of the third electrode block BL3 can ensure the flatness of the anode of the third light emitting element and improve the display effect of the display substrate.

[0190] In an example embodiment, as shown in FIG. 5B and FIG. 5C The driving structure layer further includes a fourth electrode block BL4 of the fourth pixel circuit, the fourth electrode block BL4 is located in the second conductive layer.

[0191] In an example embodiment, for the fourth pixel circuit, the orthographic projection of the fourth electrode block on the substrate partially overlaps the orthographic projection of the gate electrode and the first electrode of the second reset transistor on the substrate.

[0192] In the present disclosure, the arrangement of the fourth electrode block BL4 can ensure the flatness of the anode of the fourth light emitting element and improve the display effect of the display substrate.

[0193] In an example embodiment, as shown in FIG. 5A and FIG. 5C The display substrate further includes a plurality of data lines DL located in the second conductive layer, the data lines DL extend along the first direction.

[0194] In an example embodiment, the orthographic projection of the anode main part of the second light emitting element on the substrate at least partially overlaps the orthographic projection of the first electrode block BL1 of the second pixel circuit and the second electrode block BL2 of the fourth pixel circuit on the substrate. The orthographic projection of the first electrode block BL1 on the substrate is located on one side of the bisector of the anode main part of the second light emitting element extending along the first direction, the orthographic projection of the second electrode block BL2 on the substrate is located on the other side of the bisector, and the orthographic projection of the data line DL on the substrate partially overlaps the orthographic projection of the bisector of the anode main part of the second light emitting element extending along the first direction on the substrate.

[0195] In one exemplary embodiment, the orthographic projection of the anode body portion of the third light-emitting element onto the substrate overlaps the orthographic projection of the third electrode block BL3 located in the third pixel circuit onto the substrate. The orthographic projection of the anode body portion of the third light-emitting element onto the substrate partially overlaps with the orthographic projection of the second power connection line onto the substrate; wherein the second power connection line of the third pixel circuit is located on one side of the bisector of the anode body portion of the third light-emitting element extending along the first direction.

[0196] In one exemplary embodiment, the orthographic projection of the anode body portion of the fourth light-emitting element onto the substrate covers the orthographic projection of the fourth electrode block BL4 located in the fourth pixel circuit onto the substrate, and the orthographic projection of the anode body portion of the fourth light-emitting element onto the substrate partially overlaps with the orthographic projection of the second power connection line onto the substrate; wherein, the second power connection line of the fourth pixel circuit is located on one side of the bisector of the anode body portion of the fourth light-emitting element extending along the first direction.

[0197] In one exemplary embodiment, such as FIG. 6A through FIG. 6B As shown, the orthographic projection of the anode body of the second light-emitting element on the substrate does not overlap with the orthographic projection of the hollow region on the substrate. The hollow region is the area enclosed by the second electrode block BL2 and the second power supply connection line VLB.

[0198] In one exemplary embodiment, such as FIG. 7A through 7C As shown, the distance between the boundary of the anode body of the second light-emitting element and the boundary of the first electrode block BL1 covered by the anode body of the second light-emitting element is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer, and the distance between the boundary of the anode body of the second light-emitting element and the boundary of the second electrode connection part BL2B of the second electrode block BL2 covered by the anode body of the second light-emitting element is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer.

[0199] In one exemplary embodiment, such as FIG. 6A As shown, the distance between the boundary of the anode body of the third light-emitting element and the boundary of the third electrode block BL3 covered by the anode body of the third light-emitting element is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer.

[0200] In one exemplary embodiment, such as FIG. 3A As shown, the distance between the boundary of the anode body of the fourth light-emitting element and the boundary of the fourth electrode block BL4 covered by the anode body of the fourth light-emitting element is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer.

[0201] In one exemplary embodiment, such as FIG. 6B , FIG. 3B and FIG. 7AAs shown, the arrayed pixel circuit further includes a plurality of reset signal lines, a plurality of scan signal lines, a plurality of light-emitting signal lines, a plurality of first initial signal lines INL1 and a plurality of second initial signal lines INL2; the reset signal lines, the scan signal lines and the light-emitting signal lines are arranged in the same layer as the first electrode plate, and the first initial signal lines and the second initial signal lines are arranged in the same layer as the second electrode plate.

[0202] In an example embodiment, the plurality of reset signal lines, the plurality of scan signal lines, the plurality of light-emitting signal lines, the plurality of first initial signal lines and the plurality of second initial signal lines extend along the second direction and are arranged along the first direction.

[0203] The pixel circuit includes a first reset signal end, a second reset signal end, a first initial signal end, a second initial signal end, a scan signal end, a light-emitting signal end and a data signal end, wherein the first reset signal end and the second reset signal end are electrically connected to different reset signal lines respectively, the scan signal end is electrically connected to a scan signal line, the light-emitting signal end is electrically connected to a light-emitting signal line, the first initial signal end is electrically connected to a first initial signal line, the second initial signal end is electrically connected to a second initial signal line, and the data signal end is electrically connected to a data signal line.

[0204] In an example embodiment, the pixel circuit includes a plurality of transistors. The driving structure layer can include a semiconductor layer, a first insulating layer, a third conductive layer, a second insulating layer, a fourth conductive layer, a third insulating layer, a first conductive layer, a fourth insulating layer and a second conductive layer, which are sequentially stacked on the substrate.

[0205] In an example embodiment, the semiconductor layer can include an active layer of the plurality of transistors of at least one pixel circuit.

[0206] In an example embodiment, the third conductive layer can include a reset signal line, a scan signal line, a light-emitting signal line and a gate electrode of the plurality of transistors.

[0207] In an example embodiment, the fourth conductive layer includes a first initial signal line, a second initial signal line and a second electrode plate.

[0208] In an example embodiment, the first conductive layer includes a first power connection line, a first power connection part, a second power connection part and a connection block.

[0209] In an example embodiment, the second conductive layer includes a second power connection line, a data signal line, a first electrode block, a second electrode block, a third electrode block and a fourth electrode block.

[0210] In an example embodiment, the light-emitting structure layer can include an anode layer, a pixel definition layer, an organic material layer and a cathode layer.

[0211] In an example embodiment, the anode layer can include an anode of the light emitting element.

[0212] In an example embodiment, the organic material layer can include an organic light emitting layer of the light emitting element.

[0213] In an example embodiment, the cathode layer can include a cathode of the light emitting element.

[0214] In an example embodiment, as shown in FIG. 3A and FIG. 7B the arrayed pixel circuits further include a plurality of reset connection lines ICL in the second conductive layer, the reset connection lines extending along the first direction, and the plurality of reset connection lines being arranged along the second direction.

[0215] In an example embodiment, as shown in FIG. 3A and FIG. 2 the reset connection line is electrically connected to the plurality of first initial signal lines through a connection block in the first conductive layer, and a projection of the reset connection line on the base at least partially overlaps with a projection of a first anode main body portion of the first light emitting element on the base along the first direction. The connection block can be a first electrode of the first reset transistor.

[0216] In an example embodiment, the semiconductor layers of adjacent pixel circuits can be spaced apart or can be connected to each other.

[0217] When the semiconductor layers of adjacent pixel circuits are connected to each other, the pixel circuit and a first adjacent pixel circuit in the same row and adjacent to the pixel circuit are respectively a first adjacent pixel circuit and a second adjacent pixel circuit, a first electrode of the first reset transistor of the pixel circuit is connected to a first electrode of the first reset transistor of the first adjacent pixel circuit through the semiconductor layer, and a first electrode of the second reset transistor of the pixel circuit is connected to a first electrode of the second reset transistor of the second adjacent pixel circuit through the semiconductor layer.

[0218] When the semiconductor layers of adjacent pixel circuits are connected to each other, the first initial signal line is connected to the first electrode of the first reset transistor of the first adjacent pixel circuit through a via.

[0219] When the semiconductor layers of adjacent pixel circuits are connected to each other, the second initial signal line is connected to the first electrode of the second reset transistor of the second adjacent pixel circuit through a via.

[0220] In an example embodiment, as shown in FIG. 7C and FIG. 3BAs shown, the reset connection line includes a first protruding portion extending toward one side of the reset connection line along the second direction and a second protruding portion extending toward the other side of the reset connection line along the second direction. The first protruding portion and the second protruding portion both overlap with a virtual straight line extending along the second direction, and the projections of the first protruding portion and the second protruding portion on the substrate both overlap with the projection of the anode main portion of the first light emitting element on the substrate.

[0221] In an example embodiment, the reset connection line is located on the side of the second power connection line of the pixel circuit away from the data signal line; the data signal line of the pixel circuit is located between the second power connection line of the pixel circuit and the second power connection line of the adjacent pixel circuit.

[0222] The structure of the display substrate is described below by taking the preparation process of the display substrate as an example. The “patterning process” in the present disclosure includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, and stripping of photoresist. The deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition, the coating can use any one or more of spraying and spin coating, and the etching can use any one or more of dry etching and wet etching. The “film” refers to a thin film of a certain material formed on a substrate by deposition or coating process. If the “film” does not need to be patterned during the entire manufacturing process, the “film” can also be referred to as a “layer”. If the “film” needs to be patterned during the entire manufacturing process, it is referred to as a “film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one “pattern”. The “A and B are disposed in the same layer” in the present disclosure means that A and B are formed at the same time by the same patterning process.

[0223] FIG. 7A A schematic diagram of the preparation process of the display substrate is provided for an example embodiment. As shown, the preparation process of the display substrate provided by an example embodiment can include: FIG. 7B

[0224] (1) forming a semiconductor layer pattern on the substrate, including: depositing a semiconductor film on the substrate, and patterning the semiconductor film by a patterning process to form a semiconductor layer pattern, as shown in FIG. 7A FIG. 7B provided for the pixel circuit after the semiconductor layer pattern is formed. As shown, FIG. 6A FIG. 3A provided for the pixel circuit after the semiconductor layer pattern is formed. As shown, FIG. 6B FIG. 6A provided for the pixel circuit after the semiconductor layer pattern is formed. As shown, FIG. 3B FIG. 6A provided for the pixel circuit after the semiconductor layer pattern is formed. As shown, FIG. 6B is described by taking two rows and four columns of pixel circuits P as an example, FIG. 6B and​​​​​FIG. 6A The difference is that, FIG. 6B The semiconductor layers of adjacent pixel circuits are spaced apart, FIG. 6B The semiconductor layers of adjacent pixel circuits are connected to each other. FIG. 6A The first electrode of the first transistor of the pixel circuit is connected to the first electrode of the first transistor of the first adjacent pixel circuit, and the first electrode of the seventh transistor of the pixel circuit is connected to the first electrode of the seventh transistor of the second adjacent pixel circuit.

[0225] In an exemplary embodiment, as shown in FIG. 6B and FIG. 7A The semiconductor layer includes: an active layer T11 of the first transistor, an active layer T21 of the second transistor, an active layer T31 of the third transistor, an active layer T41 of the fourth transistor, an active layer T51 of the fifth transistor, an active layer T61 of the sixth transistor, and an active layer T71 of the seventh transistor of at least one pixel circuit. In an exemplary embodiment, the active layer T11 of the first transistor to the active layer T71 of the seventh transistor are integrally formed.

[0226] In an exemplary embodiment, FIG. 7C The semiconductor layer in FIG. 8 The difference between the semiconductor layer in FIG. 9A through 9C The semiconductor layer of the pixel circuit further includes: an active layer T81 of the eighth transistor. In an exemplary embodiment, the active layer T11 of the first transistor to the active layer T81 of the eighth transistor are integrally formed.

[0227] (2) Forming a third conductive layer pattern, including: on the substrate on which the aforementioned pattern is formed, sequentially depositing a first insulating thin film and a third conductive thin film, and patterning the first insulating thin film and the third conductive thin film through a patterning process to form a first insulating layer pattern and a third conductive layer pattern on the first insulating layer, as shown in FIG. 8 and FIG. 3A The third conductive layer pattern of the pixel circuit provided by FIG. 3B is shown in FIG. 9A The schematic diagram of the third conductive layer pattern of the pixel circuit provided by FIG. 3A is shown in FIG. 9B The schematic diagram of the pixel circuit provided by FIG. 3A after forming the third conductive layer pattern, FIG. 2 is shown in FIG. 9C The schematic diagram of the pixel circuit provided by FIG. 3B after forming the third conductive layer pattern, FIG. 9A is shown in FIG. 9B The schematic diagram of the pixel circuit provided by FIG. 9A after forming the third conductive layer pattern. FIG. 9B and FIG. 8 The difference is that,FIG. 9A through 9C The semiconductor layers of adjacent pixel circuits are spaced apart, FIG. 8 The semiconductor layers of adjacent pixel circuits are connected to each other.

[0228] In an exemplary embodiment, as FIG. 9A through 9C shown, FIG. 8 The third conductive layer of the pixel circuit provided can include a plurality of reset signal lines RL, a plurality of scan signal lines GL, a plurality of light-emitting signal lines EL, and a first plate C1 of a capacitor, a gate electrode T12 of a first transistor, a gate electrode T22 of a second transistor, a gate electrode T32 of a third transistor, a gate electrode T42 of a fourth transistor, a gate electrode T52 of a fifth transistor, a gate electrode T62 of a sixth transistor, and a gate electrode T72 of a seventh transistor of at least one pixel circuit.

[0229] In an exemplary embodiment, FIG. 9A through 9C and FIG. 10A through FIG. 10C differ in that, FIG. 11A through 11C The third conductive layer of the pixel circuit provided further includes a first control line SL, and the first control line SL is electrically connected to the first control end of the pixel circuit.

[0230] In an exemplary embodiment, as FIG. 10A and FIG. 3A shown, the reset signal line RL and the scan signal line GL of the pixel circuit are located on the same side of the first plate C1 of the pixel circuit, and the reset signal line RL is located on the side of the scan signal line GL away from the first plate C1 of the pixel circuit, and the light-emitting signal line EL of the pixel circuit is located on the side of the first plate C2 of the pixel circuit away from the scan signal line GL.

[0231] In an exemplary embodiment, as FIG. 10B shown, the first control line SL is located between the light-emitting signal line EL of the pixel circuit and the reset signal line RL of the next row of pixel circuits.

[0232] In an exemplary embodiment, as FIG. 3A and FIG. 2 shown, for the pixel circuit, the gate electrode T12 of the first transistor and the reset signal line RL of the pixel circuit are in an integral molding structure, the gate electrode T72 of the seventh transistor and the reset signal line RL of the next row of pixel circuits are in an integral molding structure, the gate electrode T22 of the second transistor and the gate electrode T42 of the fourth transistor are in an integral molding structure with the scan signal line GL of the pixel circuit, the gate electrode T32 of the third transistor and the first plate C1 of the capacitor are in an integral molding structure, and the gate electrode T52 of the fifth transistor and the gate electrode T62 of the sixth transistor are in an integral molding structure with the light-emitting signal line EL of the pixel circuit.

[0233] In an example embodiment, the gate electrode T12 of the first transistor is arranged across the active layer of the first transistor, the gate electrode T22 of the second transistor is arranged across the active layer of the second transistor, the gate electrode T32 of the third transistor is arranged across the active layer of the third transistor, the gate electrode T42 of the fourth transistor is arranged across the active layer of the fourth transistor, the gate electrode T52 of the fifth transistor is arranged across the active layer of the fifth transistor, the gate electrode T62 of the sixth transistor is arranged across the active layer of the first transistor, and the gate electrode T72 of the seventh transistor is arranged across the active layer of the seventh transistor, that is, the extension direction of the gate electrode of at least one transistor is perpendicular to the extension direction of the active layer.

[0234] In an example embodiment, as shown in FIG. 10C , the gate electrode T82 of the eighth transistor and the first control line SL are integrally formed. The gate electrode T82 of the eighth transistor is arranged across the active layer of the eighth transistor.

[0235] In an example embodiment, as shown in FIG. 3B and FIG. 11A , the gate electrode of the second transistor of at least one pixel circuit comprises a first control part and a second control part connected to each other, wherein the first control part extends in the second direction, and the second control part extends in the first direction.

[0236] In an example embodiment, the present process further comprises a conductorization process. The conductorization process is that after forming the first conductive layer pattern, the semiconductor layer in the area shielded by the gate electrodes of the plurality of transistors (i.e. the area where the semiconductor layer overlaps with the gate electrode) is used as the channel region of the transistor, and the semiconductor layer in the area not shielded by the first conductive layer is processed into a conductorized layer to form a conductorized source-drain connection part. As shown in FIG. 3A and 7B , the active layer of the conductorized sixth transistor is multiplexed as the first electrode T63 of the sixth transistor, the second electrode T24 of the second transistor, and the second electrode T34 of the third transistor, and the active layer of the conductorized fifth transistor is multiplexed as the second electrode T54 of the fifth transistor, the first electrode T33 of the third transistor, and the second electrode T44 of the fourth transistor. As shown in FIG. 11B , the active layer of the conductorized sixth transistor is multiplexed as the first electrode T63 of the sixth transistor, the second electrode T24 of the second transistor, and the second electrode T34 of the third transistor, and the active layer of the conductorized fifth transistor is multiplexed as the second electrode T54 of the fifth transistor, the first electrode T3 of the third transistor, the second electrode T44 of the fourth transistor, and the second electrode T84 of the eighth transistor.

[0237] (3) forming a fourth conductive layer pattern, comprising: sequentially depositing a second insulating thin film and a fourth conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the second insulating thin film and the fourth conductive thin film by a patterning process to form a second insulating layer pattern and a fourth conductive layer pattern on the second insulating layer, as shown in FIG. 3A and FIG. 2 , FIG. 11C , FIG. 3B and FIG. 10A , FIG. 10B , FIG. 10A , FIG. 10B , FIG. 11A , FIG. 11B , FIG. 11A , FIG. 11B . FIG. 10A and FIG. 10B differ in that, FIG. 10C the semiconductor layers of adjacent pixel circuits are spaced apart, FIG. 10A the semiconductor layers of adjacent pixel circuits are connected to each other.

[0238] In an exemplary embodiment, as shown in FIG. 10B and FIG. 10A , the fourth conductive layer can include a plurality of first initial signal lines INL1, a plurality of second initial signal lines INL2, and a shielding electrode CL and a second plate C2.

[0239] In an exemplary embodiment, as shown in FIG. 10B and FIG. 12A through FIG. 12C , the first initial signal line INL1 connected to the pixel circuit is located on one side of the shielding electrode SL of the pixel circuit, and the second plate C2 of the capacitor of the pixel circuit is located on the side of the shielding electrode SL of the pixel circuit away from the first initial signal line INL1 connected to the pixel circuit.

[0240] In an exemplary embodiment, as shown in FIG. 13A through FIG. 13C and FIG. 12A , the second initial signal line INL2 of the pixel circuit is located between the first initial signal line INL1 of the next row of pixel circuits and the second plate C2 of the next row of pixel circuits, and is located on the side of the second plate C2 of the pixel circuit away from the first initial signal line of the pixel circuit.

[0241] In an exemplary embodiment, the second plate C2 of the capacitor of at least one pixel circuit is provided with a first via V1 exposing the first plate of the capacitor, wherein the orthographic projection of the first plate C1 of the capacitor on the substrate and the orthographic projection of the second plate C2 of the capacitor on the substrate partially overlap.

[0242] In an example embodiment, the normal projection of the shielding electrode SL on the substrate partially overlaps with the normal projection of the active layer of the first transistor and the active layer of the second transistor on the substrate. The partial overlap of the normal projection of the shielding electrode SL on the substrate with the normal projection of the active layer of the second transistor on the substrate can ensure the stability of the current of the second transistor, and improve the display effect of the display panel.

[0243] In an example embodiment, the shielding electrode SL can include a first shielding electrode part SL1, a second shielding electrode part SL2 and a third shielding electrode part SL3 integrally formed.

[0244] In an example embodiment, the first shielding electrode part SL1 extends along the first direction and is connected with the second shielding electrode part SL2, and the normal projection of the first shielding electrode part SL1 on the substrate partially overlaps with the normal projection of the active layer of the first transistor on the substrate.

[0245] In an example embodiment, the second shielding electrode part SL2 extends along the second direction and is connected with the third shielding electrode part SL3.

[0246] In an example embodiment, the third shielding electrode part SL3 extends along the first direction and the normal projection thereof on the substrate partially overlaps with the normal projection of the active layer of the second transistor on the substrate.

[0247] (4) Forming a third insulating layer pattern, including: depositing a third insulating thin film on the substrate on which the aforementioned pattern is formed, and patterning the third insulating thin film by a patterning process to form a third insulating layer pattern covering the aforementioned pattern, the third insulating layer being provided with a plurality of via hole patterns, such as FIG. 3A and FIG. 12B shown, FIG. 3A for FIG. 2 a schematic diagram of the third insulating layer pattern of the pixel circuit provided by FIG. 12C for FIG. 3B a schematic diagram of the third insulating layer pattern of the pixel circuit provided by FIG. 13A , FIG. 3A for FIG. 13B a schematic diagram of the third insulating layer pattern of the pixel circuit provided by FIG. 3A for FIG. 2 a schematic diagram of the pixel circuit provided by FIG. 13C for FIG. 3B a schematic diagram of the pixel circuit provided by FIG. 12A , FIG. 12B for FIG. 12A a schematic diagram of the pixel circuit provided by FIG. 12B and FIG. 13ADifferent from the first aspect, FIG. 13B the semiconductor layers of the adjacent pixel circuits are spaced apart, FIG. 13A the semiconductor layers of the adjacent pixel circuits are connected to each other. FIG. 13B and FIG. 12A Different from the first aspect, FIG. 12B the semiconductor layers of the adjacent pixel circuits are spaced apart, FIG. 12A the semiconductor layers of the adjacent pixel circuits are connected to each other.

[0248] In an example embodiment, as shown in FIG. 12A and FIG. 12C The plurality of via patterns include: a second via V2 to a seventh via V7 penetrating through the first insulating layer, the second insulating layer and the third insulating layer, an eighth via V8 penetrating through the second insulating layer and the third insulating layer, and a ninth via V9 to a twelfth via V12 arranged on the third insulating layer.

[0249] In an example embodiment, FIG. 12A compared with FIG. 12B and FIG. 14A through FIG. 14B The plurality of via patterns further include: a thirteenth via V13 penetrating through the first insulating layer, the second insulating layer and the third insulating layer.

[0250] In an example embodiment, the first via covers the orthographic projection of the eighth via V8 on the substrate.

[0251] In an example embodiment, the second via V2 exposes the active layer of the first transistor, the third via V3 exposes the active layer of the second transistor, the fourth via V4 exposes the active layer of the fourth transistor, the fifth via V5 exposes the active layer of the fifth transistor, the sixth via V6 exposes the active layer of the sixth transistor, the seventh via V7 exposes the active layer of the seventh transistor, the eighth via V8 exposes the first plate of the capacitor, the ninth via V9 exposes the first initial signal line of the pixel circuit, the tenth via V10 exposes the shielding electrode, the eleventh via V11 exposes the second plate of the capacitor, the twelfth via V12 exposes the second initial signal line of the pixel circuit, and the thirteenth via V13 exposes the active layer of the eighth transistor.

[0252] FIG. 15A through FIG. 15C In the first aspect, the second via of the pixel circuit is a different via from the second via of the first adjacent pixel circuit, and the seventh via of the pixel circuit is a different via from the seventh via of the second adjacent pixel circuit, FIG. 14A In the first aspect, the second via of the pixel circuit is the same via as the second via of the first adjacent pixel circuit, and the seventh via of the pixel circuit is the same via as the seventh via of the second adjacent pixel circuit.

[0253] (5) forming the first conductive layer pattern, comprising: depositing a first conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the first conductive thin film by a patterning process to form the first conductive layer pattern, such as ​ and ​ shown in FIGS. ​ , ​ a schematic diagram of the first conductive layer pattern of the pixel circuit provided in ​ , ​ a schematic diagram of the first conductive layer pattern of the pixel circuit provided in ​ , ​ a schematic diagram of the first conductive layer pattern of the pixel circuit provided in ​ , ​ a schematic diagram of the pixel circuit after the first conductive layer pattern is formed provided in ​ , ​ a schematic diagram of the pixel circuit after the first conductive layer pattern is formed provided in ​ , ​ a schematic diagram of the pixel circuit after the first conductive layer pattern is formed provided in ​ , ​ a schematic diagram of the pixel circuit after the first conductive layer pattern is formed provided in ​ and ​ the difference is that, ​ the semiconductor layers of adjacent pixel circuits are spaced apart, ​ the semiconductor layers of adjacent pixel circuits are connected to each other. ​ and ​ the difference is that, ​ the semiconductor layers of adjacent pixel circuits are spaced apart, ​ the semiconductor layers of adjacent pixel circuits are connected to each other.

[0254] In an exemplary embodiment, as shown in ​ and ​ the third conductive layer can include: a first power connection line VLA, a first electrode T13 and a second electrode T14 of the first transistor, a first electrode T23 of the second transistor, a first electrode T43 of the fourth transistor, a first electrode T53 of the fifth transistor, a second electrode T64 of the sixth transistor, a first electrode T73 and a second electrode T74 of the seventh transistor, a first power connection part VL1 and a second power connection part VL2.

[0255] In an exemplary embodiment, ​ the first electrode T13 of the first transistor in the pixel circuit and the first adjacent pixel circuit is a different electrode, and the first electrode T73 of the seventh transistor in the pixel circuit and the second adjacent pixel circuit is a different electrode, ​The first electrode T13 of the first transistor in the pixel circuit and the first transistor in the first adjacent pixel circuit is the same electrode, and the first electrode T73 of the seventh transistor in the pixel circuit and the seventh transistor in the second adjacent pixel circuit is the same electrode.

[0256] In an example embodiment, ​ Compared with ​ and ​ The third conductive layer can further include: the first electrode T83 of the eighth transistor.

[0257] In an example embodiment, the first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, the first electrode T53 of the fifth transistor, the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor are located on one side of the first power connection line VLA of the pixel circuit close to the first power connection line of the previous column of pixel circuits, and the first electrode T43 of the fourth transistor is located on one side of the first power connection line VLA of the pixel circuit close to the first power connection line VLA of the next column of pixel circuits.

[0258] In an example embodiment, the second electrode T14 of the first transistor and the first electrode T23 of the second transistor are an integral molded structure, the second electrode T64 of the sixth transistor and the second electrode T74 of the seventh transistor are an integral molded structure, and the first electrode T53 of the fifth transistor and the first power connection line VLA are an integral molded structure. The first electrode of the eighth transistor and the first electrode of the first transistor of the next row of pixel circuits are an integral molded structure.

[0259] In an example embodiment, the first electrode T13 of the first transistor, the first electrode T23 of the second transistor, the first electrode T73 of the seventh transistor, and the first electrode T83 of the eighth transistor all extend in the first direction.

[0260] In an example embodiment, the first power connection portion VL1 extends in the second direction, and the second power connection portion VL2 extends in the second direction.

[0261] In an example embodiment, for the first pixel circuit, the first electrode T13 and the second electrode T14 of the first transistor and the first electrode T23 of the second transistor are located on the first side of the first power connection portion VL1, and the second electrode T64 of the sixth transistor and the first electrode T73 and the second electrode T74 of the seventh transistor are located on the second side of the first power connection portion VL1.

[0262] In one exemplary embodiment, for the fourth pixel circuit, the first electrode T13 and the second electrode T14 of the first transistor and the first electrode T23 of the second transistor are located on the first side of the second power connection portion VL2, and the second electrode T64 of the sixth transistor and the first electrode T73 and the second electrode T74 of the seventh transistor are located on the second side of the second power connection portion VL2.

[0263] In one exemplary embodiment, for the first pixel circuit, the orthographic projection of the first power connection portion VL1 on the substrate at least partially overlaps with the orthographic projection of the second plate of the capacitor on the substrate.

[0264] In one exemplary embodiment, for the fourth pixel circuit, the orthographic projection of the second power connection portion VL2 on the substrate at least partially overlaps with the orthographic projection of the second plate of the capacitor on the substrate.

[0265] In one exemplary embodiment, the first electrode T13 of the first transistor is connected to the active layer of the first transistor through a second via and to the first initial signal line of the pixel circuit through a ninth via; the first electrode T23 of the second transistor is connected to the active layer of the second transistor through a third via and to the first electrode plate through an eighth via; the first electrode T43 of the fourth transistor is connected to the active layer of the fourth transistor through a fourth via; the first power supply connection line of the pixel circuit is connected to the active layer of the fifth transistor through a fifth via, to the shielding electrode through a tenth via, and to the second electrode plate through an eleventh via; the second electrode T64 of the sixth transistor is connected to the active layer of the sixth transistor through a sixth via; the first electrode T73 of the seventh transistor is connected to the active layer of the seventh transistor through a seventh via and to the second initial signal line of the pixel circuit through a twelfth via; and the first electrode T83 of the eighth transistor is connected to the active layer of the eighth transistor through a thirteenth via.

[0266] (6) Forming a fourth insulating layer pattern includes: depositing a fourth insulating film on a substrate having the aforementioned pattern, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer pattern covering the aforementioned pattern. The fourth insulating layer has multiple via patterns, such as... ​ as well as ​ As shown, ​ for FIG. 3A and FIG. 3B A schematic diagram of the fourth insulating layer pattern of the provided pixel circuit. FIG. 14B for FIG. 3A Another schematic diagram of the fourth insulating layer pattern of the provided pixel circuit. FIG. 15A for FIG. 3A The provided pixel circuitry forms the fourth insulating layer pattern in diagram one. FIG. 15B for FIG. 3A Schematic diagram of the pixel circuit forming the fourth insulating layer patternFIG. 2 , FIG. 15C , FIG. 3B A schematic diagram of the pixel circuit after forming the fourth insulating layer pattern is provided. FIG. 14A , FIG. 14B The difference is that, FIG. 14A In the semiconductor layer of the adjacent pixel circuit is spaced apart, FIG. 14B In the semiconductor layer of the adjacent pixel circuit is connected to each other. FIG. 15A , FIG. 15B The difference is that, FIG. 15A In the semiconductor layer of the adjacent pixel circuit is spaced apart, FIG. 15B The semiconductor layer of the adjacent pixel circuit is connected to each other.

[0267] In an exemplary embodiment, as shown in FIG. 14A , FIG. 14B The plurality of via patterns includes a fourteenth via V14 to a sixteenth via V16 on the fourth insulating layer in at least one pixel circuit.

[0268] In an exemplary embodiment, as shown in FIG. 14A The plurality of via patterns further includes a seventeenth via V17 on the fourth insulating layer.

[0269] In an exemplary embodiment, the fourteenth via V14 exposes the first electrode of the fourth transistor, the fifteenth via V1 exposes the first power connection line, the sixteenth via V16 exposes the second electrode of the sixth transistor, and the seventeenth via B17 exposes the first electrode of the first transistor of the first pixel circuit and the second pixel circuit.

[0270] (7) Forming a second conductive layer pattern, comprising: depositing a second conductive thin film on the substrate formed in the foregoing pattern, patterning the second conductive thin film by a patterning process, forming a second conductive layer pattern, as shown in FIG. 16A to FIG. 16B , FIG. 17A to FIG. 17C , FIG. 16A , FIG. 3A , FIG. 3B A schematic diagram of the second conductive layer pattern of the pixel circuit provided, FIG. 16B , FIG. 3A Another schematic diagram of the second conductive layer pattern of the pixel circuit provided, FIG. 17A , FIG. 3A A schematic diagram of the pixel circuit after forming the second conductive layer pattern, FIG. 17B , FIG. 3A A schematic diagram of the pixel circuit after forming the second conductive layer pattern FIG. 2 , FIG. 17C A schematic diagram of the pixel circuit after forming the second conductive layer pattern. FIG. 3B , FIG. 16A , FIG. 16BThe difference is that FIG. 16A In the semiconductor layer of the adjacent pixel circuit is spaced apart, FIG. 16B In the semiconductor layer of the adjacent pixel circuit is connected to each other. FIG. 17A And FIG. 17B The difference is that FIG. 17A In the semiconductor layer of the adjacent pixel circuit is spaced apart, FIG. 17B The semiconductor layer of the adjacent pixel circuit is connected to each other.

[0271] In an exemplary embodiment, as shown in FIG. 16A And FIG. 16B The fourth conductive layer can include a plurality of second power supply connection lines VLB, a plurality of data signal lines DL, a connection electrode VL, a first electrode block BL1, a second electrode block BL2, a third electrode block BL3 and a fourth electrode block BL4.

[0272] In an exemplary embodiment, FIG. 16A And FIG. 16B In contrast, the fourth conductive layer further includes a plurality of reset connection lines ICL.

[0273] In an exemplary embodiment, the reset connection line ICL is located on the side of the second power supply connection line VLB of the pixel circuit away from the data signal line DL.

[0274] In an exemplary embodiment, the reset connection line ICL extends in a first direction, and the plurality of reset connection lines ICL are arranged in a second direction.

[0275] In an exemplary embodiment, the reset connection line ICL can include a T-shaped structure, wherein the T-shaped structure serves to pad the anode of the first light emitting element.

[0276] In an exemplary embodiment, the connection electrode VL is located on the side of the second power supply connection line VLB away from the data signal line DL.

[0277] In an exemplary embodiment, the connection electrode VL can be square in shape.

[0278] In an exemplary embodiment, the data signal line DL of the pixel circuit is located between the second power supply connection line VLB of the pixel circuit and the second power supply connection line VLB of the adjacent pixel circuit.

[0279] In an exemplary embodiment, the data signal line DL is connected to the first electrode of the fourth transistor through a fourteenth via, the second power supply connection line VLB is connected to the first power supply connection line through a fifteenth via, the connection electrode VL is connected to the second electrode of the sixth transistor through a sixteenth via, and the reset connection line is connected to the first electrode of the first transistor of the first pixel circuit and the second pixel circuit through a seventeenth via.

[0280] In one exemplary embodiment, the minimum distance between the second power connection line VLB of the pixel circuit and the data signal line DL is greater than or equal to 4 micrometers. Setting this minimum distance between the second power connection line VLB and the data signal line DL can reduce the risk of short circuits between the power signals on the power lines and the data signals on the data signals on the data signals during the manufacturing process of the display substrate, thereby improving the reliability of the display substrate.

[0281] In one exemplary embodiment, the second electrode block located in the fourth pixel circuit and the second power supply connection line of the fourth pixel circuit form a closed loop. The closed loop between the second electrode block BL2 of the fourth pixel circuit and the second power supply connection line increases the area of ​​the display substrate without metal obstruction, improves the light transmittance of the display substrate, and enhances the optical fingerprint recognition capability.

[0282] In one exemplary embodiment, such as FIG. 16A and FIG. 16B As shown, the second electrode block BL2 may include: a first electrode connection portion BL2A, a second electrode connection portion BL2B, and a third electrode connection portion BL2C. The first electrode connection portion BL2A ​​extends along a second direction and is connected to the second electrode connection portion BL2B via a second power supply connection line connected to the fourth pixel circuit; the second electrode connection portion BL2B extends along a first direction and is connected to the third electrode connection portion BL2C; the third electrode connection portion BL2C extends along a second direction and is connected to the second power supply connection line.

[0283] In one exemplary embodiment, the arrangement of the first electrode block BL1 and the second electrode block BL2 can ensure the flatness of the anode of the second light-emitting element, thereby improving the display effect of the display substrate. In one exemplary embodiment, for the second pixel circuit, the orthographic projection of the first electrode block BL1 on the substrate overlaps with the orthographic projections of the shielding electrode, the gate electrode of the second transistor, and the second plate of the capacitor on the substrate.

[0284] In one exemplary embodiment, for the fourth pixel circuit, the orthographic projection of the second electrode block BL2 on the substrate at least partially overlaps with the orthographic projections of the first electrode of the first transistor, the shielding electrode, the gate electrode of the second transistor, and the gate electrode of the third transistor on the substrate. This at least partial overlap between the orthographic projection of the second electrode block on the substrate and the orthographic projections of the gate electrodes of the second and third transistors can shield the second and third transistors from interference from external electric fields, thereby improving the reliability of the display substrate.

[0285] In one exemplary embodiment, the arrangement of the third electrode block BL3 can ensure the flatness of the anode of the third light-emitting element, thereby improving the display effect of the display substrate.

[0286] In an example embodiment, the third electrode block BL3 can be square-shaped.

[0287] In an example embodiment, for the third pixel circuit, the orthographic projection of the third electrode block BL3 on the substrate partially overlaps with the orthographic projection of the gate electrode of the second transistor and the gate electrode of the third transistor on the substrate. The partial overlap of the orthographic projection of the third electrode block BL3 on the substrate with the orthographic projection of the gate electrode of the third transistor on the substrate can shield the influence of the external electric field on the third transistor.

[0288] In an example embodiment, the fourth electrode block BL4 can be configured to ensure the flatness of the anode of the fourth light emitting element, and to improve the display effect of the display substrate.

[0289] In an example embodiment, the fourth electrode block BL4 can be square-shaped.

[0290] In an example embodiment, for the fourth pixel circuit, the orthographic projection of the fourth electrode block BL4 on the substrate partially overlaps with the orthographic projection of the gate electrode of the seventh transistor and the first electrode on the substrate.

[0291] In an example embodiment, the second electrode connecting portion BL2B is configured to pad the right side of the anode of the second light emitting element.

[0292] In an example embodiment, since the orthographic projection of the third electrode block on the substrate covers the gate electrode of the driving transistor of the third pixel circuit, the orthographic projection of the third electrode connecting portion BL3C on the substrate covers the gate electrode of the driving transistor of the fourth pixel circuit, and the display uniformity of the third light emitting element and the fourth light emitting element can be maintained.

[0293] (8) Forming the anode layer, including: coating a flat film on the substrate on which the pattern is formed, patterning the flat film to form a flat layer pattern, depositing a transparent conductive film on the substrate on which the pattern is formed, patterning the transparent conductive film by a patterning process to form an anode layer pattern, as shown in FIG. 18 and FIG. 19A to FIG. 19C , FIG. 18 is a schematic diagram of the anode layer pattern, FIG. 19A is a schematic diagram after forming the anode layer pattern, FIG. 19B is a schematic diagram after forming the anode layer pattern, FIG. 2 , FIG. 19C is a schematic diagram after forming the anode layer pattern. FIG. 19A and FIG. 9B The difference is that, FIG. 19A in the semiconductor layer of the adjacent pixel circuit is spaced apart, FIG. 19B the semiconductor layers of the adjacent pixel circuits are connected to each other. FIG. 19A to 19C The difference is that,FIG. 19A and FIG. 19B the pixel circuit in FIG. 3A provides the pixel circuit, FIG. 19C the pixel circuit in FIG. 3B provides the pixel circuit.

[0294] In an exemplary embodiment, the anode layer can include: an anode RA of the first light emitting element, an anode BA of the second light emitting element, an anode GA1 of the third light emitting element, and a second anode GA2 of the fourth light emitting element.

[0295] In an exemplary embodiment, the reset connection line is located at a center line position of the anode main body portion of the first light emitting element.

[0296] In an exemplary embodiment, the data signal line is located at a center line position of the anode main body portion of the second light emitting element.

[0297] In an exemplary embodiment, the anode connection portion of the first light emitting element at least partially overlaps the normal projection of the connection electrode of the first pixel circuit on the substrate, and is connected to the third connection electrode of the first pixel circuit.

[0298] In an exemplary embodiment, the anode connection portion of the second light emitting element at least partially overlaps the normal projection of the connection electrode of the second pixel circuit on the substrate, and is connected to the connection electrode of the second pixel circuit.

[0299] In an exemplary embodiment, the normal projection of the anode main body portion of the second light emitting element on the substrate at least partially overlaps the normal projection of the first electrode block of the second pixel circuit and the second electrode block of the fourth pixel circuit on the substrate.

[0300] In an exemplary embodiment, the distance between the boundary of the anode main body portion of the second light emitting element and the boundary of the first electrode block covered by the anode main body portion of the second light emitting element is greater than or equal to 0.5 microns and less than or equal to 1 micron.

[0301] In an exemplary embodiment, the distance between the boundary of the anode of the second light emitting element and the boundary of the second electrode connection portion of the second electrode block covered by the anode main body portion of the second light emitting element is greater than or equal to 0.5 microns and less than or equal to 1 micron.

[0302] In an exemplary embodiment, the normal projection of the anode main body portion of the third light emitting element on the substrate covers the normal projection of the third electrode block of the third pixel circuit on the substrate.

[0303] In an exemplary embodiment, the normal projection of the anode main body portion of the third light emitting element on the substrate also partially overlaps the normal projection of the second power supply connection line on the substrate.

[0304] In one example embodiment, the distance between the boundary of the anode main portion of the third light emitting element and the boundary of the third electrode block covered by the anode main portion of the third light emitting element is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer.

[0305] In one example embodiment, the anode connecting portion of the third light emitting element at least partially overlaps the connection electrode of the third pixel circuit on the substrate, and is connected to the connection electrode of the third pixel circuit.

[0306] In one example embodiment, the anode main portion of the fourth light emitting element on the substrate overlaps the fourth electrode block of the fourth pixel circuit on the substrate.

[0307] In one example embodiment, the anode main portion of the fourth light emitting element on the substrate also partially overlaps the second power supply connection line on the substrate.

[0308] In one example embodiment, the anode connecting portion of the fourth light emitting element at least partially overlaps the connection electrode of the fourth pixel circuit on the substrate, and is connected to the connection electrode of the fourth pixel circuit.

[0309] In one example embodiment, the distance between the boundary of the anode main portion of the fourth light emitting element and the boundary of the fourth electrode block covered by the anode main portion of the fourth light emitting element is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer.

[0310] (9) forming a pixel definition layer, comprising: depositing a pixel definition film on the substrate on which the pattern is formed, patterning the pixel definition film by a patterning process, forming a pixel definition layer pattern exposing the anode of the light emitting element, as shown in FIG. 20 and FIG. 21A to FIG. 21C , FIG. 20 is a schematic diagram of the pixel definition layer pattern, FIG. 21A is a schematic diagram after forming the pixel definition layer pattern, FIG. 21B is a schematic diagram after forming the pixel definition layer pattern FIG. 2 , FIG. 21C is a schematic diagram after forming the pixel definition layer pattern. FIG. 21A and FIG. 21B The difference is that, FIG. 21A the semiconductor layers of adjacent pixel circuits are spaced apart in FIG. 21B the semiconductor layers of adjacent pixel circuits are connected to each other. FIG. 21A to 21C The difference is that, FIG. 21A and FIG. 21B the pixel circuit in FIG. 3A the pixel circuit provided in FIG. 21C the pixel circuit in FIG. 3BA pixel circuit is provided.

[0311] In an exemplary embodiment, the pixel definition layer can include an eighteenth via hole V18 exposing an anode of the light emitting element.

[0312] (10) forming the organic material layer and the cathode layer, comprising: coating an organic light emitting material on the substrate with the pattern formed, patterning the organic light emitting material by a patterning process to form an organic material layer pattern, depositing a sixth conductive thin film on the substrate with the organic material layer pattern formed, patterning the sixth conductive thin film by a patterning process to form a cathode layer.

[0313] In an exemplary embodiment, the organic material layer can include an organic light emitting layer of the light emitting element.

[0314] In an exemplary embodiment, the cathode layer can include a cathode of the light emitting element.

[0315] In an exemplary embodiment, the semiconductor layer can be an amorphous silicon layer, a polysilicon layer, or can be a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, or can be a double layer, or can be a multi-layer.

[0316] In an exemplary embodiment, the first conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material with conductivity, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the first conductive layer can be made of molybdenum.

[0317] In an exemplary embodiment, the second conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material with conductivity, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the second conductive layer can be made of molybdenum.

[0318] In an exemplary embodiment, the third conductive layer can employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an electrically conductive alloy material as described above, such as an aluminum neodymium alloy (AlNd) or a molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the third conductive layer can be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0319] In an exemplary embodiment, the fourth conductive layer can employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an electrically conductive alloy material as described above, such as an aluminum neodymium alloy (AlNd) or a molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the fourth conductive layer can be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0320] In an exemplary embodiment, the anode layer can employ a transparent conductive material, such as any one or more of indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), and indium zinc tin oxide (IZTO).

[0321] In an exemplary embodiment, the cathode layer can employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an electrically conductive alloy material as described above, such as an aluminum neodymium alloy (AlNd) or a molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the fourth conductive layer can be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0322] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The first insulating layer can be referred to as a first gate insulating layer, the second insulating layer can be referred to as a second gate insulating layer, and the third insulating layer can be referred to as an interlayer insulating layer.

[0323] In an exemplary embodiment, the planarization layer can employ an organic material,

[0324] The display substrate provided by the embodiments of the present disclosure can be applied to any resolution display product.

[0325] The embodiments of the present disclosure also provide a display device, which can include a display substrate.

[0326] The display substrate is provided by any one of the foregoing embodiments, and has similar principles and effects, which will not be described here again.

[0327] In an exemplary embodiment, the display device can be a liquid crystal display (LCD) or an organic light emitting diode (OLED) display device. The display device can be a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function.

[0328] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0329] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe embodiments of the present disclosure. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or an intervening element can be present.

[0330] Although the embodiments disclosed in the present disclosure are as described above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, comprising: A substrate, a driving structure layer disposed on the substrate, and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, the driving structure layer comprising: an array of pixel circuits, the array of pixel circuits comprising: a plurality of power supply lines configured to provide a power supply signal; the pixel circuit further comprising: a capacitor comprising: a first plate and a second plate disposed on a side of the first plate away from the substrate; The light-emitting structure layer comprises: a plurality of light-emitting elements; the light-emitting elements are connected with the pixel circuits, and at least one light-emitting element comprises: an anode, an organic light-emitting layer, and a cathode which are sequentially stacked on the driving structure layer; the anode of the light-emitting element comprises: an anode main body portion and an anode connecting portion, and a projection of an effective light-emitting area of the light-emitting element on the substrate is located inside a projection of the corresponding anode main body portion on the substrate, and the anode connecting portion is connected with the pixel circuit and the anode main body portion, respectively; The plurality of power supply lines comprises: a plurality of first power supply connecting lines disposed on the first conductive layer and a plurality of second power supply connecting lines disposed on the second conductive layer, the second conductive layer is disposed on a side of the first conductive layer away from the substrate, the first power supply connecting lines and the second power supply connecting lines extend along a first direction, and the plurality of first power supply connecting lines and the plurality of second power supply connecting lines are arranged along a second direction, the first direction and the second direction intersect; Two adjacent first power supply connecting lines are connected by a connecting portion disposed on the first conductive layer, and a projection of the connecting portion on the substrate at least partially overlaps with a projection of the second plate on the substrate. 2.The display substrate of claim 1, wherein, The first power supply connecting line and the second power supply connecting line of the same pixel circuit are connected, and a projection of the first power supply connecting line on the substrate covers a projection of the second power supply connecting line on the substrate. 3.The display substrate according to claim 1 or 2, wherein, The light-emitting element comprises: a first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element; the first light-emitting element emits red light, the second light-emitting element emits blue light, and the third light-emitting element and the fourth light-emitting element emit green light; The shapes of the anode main body portions of the first light-emitting element and the second light-emitting element are hexagons, and the area of the anode main body portion of the second light-emitting element is greater than that of the anode main body portion of the first light-emitting element, the shapes of the anode main body portions of the third light-emitting element and the fourth light-emitting element are pentagons, and the anode main body portion of the third light-emitting element and the anode main body portion of the fourth light-emitting element are symmetrical about a virtual straight line extending along the second direction. 4.The display substrate of claim 3, wherein, The pixel circuit comprises: a first pixel circuit to a fourth pixel circuit, wherein the first pixel circuit is a pixel circuit connected with the first light-emitting element, the second pixel circuit is a pixel circuit connected with the second light-emitting element, the third pixel circuit is a pixel circuit connected with the third light-emitting element, and the fourth pixel circuit is a pixel circuit connected with the fourth light-emitting element. The connection part comprises a first power connection part overlapping the second plate of the first pixel circuit in the orthogonal projection of the substrate and a second power connection part overlapping the second plate of the fourth pixel circuit in the orthogonal projection of the substrate; the first power connection part and the second power connection part extend along the second direction, and a virtual straight line extending along the second direction passes through the first power connection part and the second power connection part respectively. 5.The display substrate of claim 4, wherein, The pixel circuit comprises a driving transistor; the driving structure layer further comprises a first electrode block of the second pixel circuit; the first electrode block is located in the second conductive layer and connected with the second power connection line of the second pixel circuit. For the second pixel circuit, the orthogonal projection of the first electrode block on the substrate partially overlaps the orthogonal projection of the gate electrode of the driving transistor and the second plate on the substrate. 6.The display substrate of claim 5, wherein, The pixel circuit further comprises a first reset transistor and a compensation transistor; the driving structure layer further comprises a second electrode block of the fourth pixel circuit, the second electrode block is located in the second conductive layer and connected with the second power connection line of the fourth pixel circuit; For the fourth pixel circuit, the orthogonal projection of the second electrode block on the substrate at least partially overlaps the orthogonal projection of the first electrode of the first reset transistor, the gate electrode of the compensation transistor and the gate electrode of the driving transistor on the substrate. 7.The display substrate of claim 6, wherein, The second electrode block of the fourth pixel circuit forms a closed loop with the second power connection line of the fourth pixel circuit; The second electrode block comprises a first electrode connection part, a second electrode connection part and a third electrode connection part; The first electrode connection part extends along the second direction and is connected with the second electrode connection part and the second power connection line of the fourth pixel circuit; The second electrode connection part extends along the first direction and is connected with the third electrode connection part; The third electrode connection part extends along the second direction and is connected with the second power connection line of the fourth pixel circuit. 8.The display substrate according to claim 6 or 7, wherein The driving structure layer further comprises a third electrode block of the third pixel circuit, the third electrode block is located in the second conductive layer and connected with the second power connection line of the third pixel circuit; For the third pixel circuit, the orthogonal projection of the third electrode block on the substrate partially overlaps the orthogonal projection of the gate electrode of the compensation transistor and the gate electrode of the driving transistor on the substrate. 9.The display substrate of claim 8, wherein, The pixel circuit further comprises a second reset transistor, and the driving structure layer further comprises a fourth electrode block of the fourth pixel circuit, the fourth electrode block is located in the second conductive layer and connected with the second power connection line of the fourth pixel circuit; For the fourth pixel circuit, the orthogonal projection of the fourth electrode block on the substrate partially overlaps the orthogonal projection of the gate electrode and the first electrode of the second reset transistor on the substrate. 10.The display substrate of claim 9, wherein, The arrayed pixel circuit further comprises a plurality of data lines located in the second conductive layer, the data lines extend along the first direction; The anode main part of the second light emitting element is partially overlapped with the first electrode block of the second pixel circuit and the second electrode block of the fourth pixel circuit on the substrate; wherein the first electrode block is located on one side of the bisector of the anode main part of the second light emitting element along the first direction, and the second electrode block is located on the other side of the bisector, and the data line is partially overlapped with the bisector of the anode main part of the second light emitting element on the substrate. 11.The display substrate of claim 10, wherein, The anode main part of the third light emitting element is overlapped with the third electrode block of the third pixel circuit on the substrate, and the anode main part of the third light emitting element is partially overlapped with the second power supply connection line on the substrate; wherein the second power supply connection line of the third pixel circuit is located on one side of the bisector of the anode main part of the third light emitting element along the first direction. 12.The display substrate according to claim 10 or 11, wherein The anode main part of the fourth light emitting element is overlapped with the fourth electrode block of the fourth pixel circuit on the substrate, and the anode main part of the fourth light emitting element is partially overlapped with the second power supply connection line on the substrate; wherein the second power supply connection line of the fourth pixel circuit is located on one side of the bisector of the anode main part of the fourth light emitting element along the first direction. 13.The display substrate of claim 10, wherein, The anode main part of the second light emitting element is not overlapped with the hollow area on the substrate, and the hollow area is the area surrounded by the second electrode block and the second power supply connection line. 14.The display substrate of claim 10, wherein, The distance between the boundary of the anode main part of the second light emitting element and the boundary of the first electrode block covered by the anode main part of the second light emitting element is greater than or equal to 0.5 microns and less than or equal to 1 micron, and the distance between the boundary of the anode main part of the second light emitting element and the boundary of the second electrode connection part of the second electrode block covered by the anode main part of the second light emitting element is greater than or equal to 0.5 microns and less than or equal to 1 micron; The distance between the boundary of the anode main part of the third light emitting element and the boundary of the third electrode block covered by the anode main part of the third light emitting element is greater than or equal to 0.5 microns and less than or equal to 1 micron; The distance between the boundary of the anode main part of the fourth light emitting element and the boundary of the fourth electrode block covered by the anode main part of the fourth light emitting element is greater than or equal to 0.5 microns and less than or equal to 1 micron. 15.The display substrate of claim 12, wherein, The arrayed pixel circuits further comprise: a plurality of reset signal lines, a plurality of scanning signal lines, a plurality of light emitting signal lines, a plurality of first initial signal lines and a plurality of second initial signal lines; the reset signal lines, the scanning signal lines and the light emitting signal lines are arranged in the same layer as the first electrode plate, and the first initial signal lines and the second initial signal lines are arranged in the same layer as the second electrode plate; The plurality of reset signal lines, the plurality of scanning signal lines, the plurality of light emitting signal lines, the plurality of first initial signal lines and the plurality of second initial signal lines extend along the second direction and are arranged along the first direction; The pixel circuit comprises a first reset signal terminal, a second reset signal terminal, a first initial signal terminal, a second initial signal terminal, a scanning signal terminal, a light-emitting signal terminal and a data signal terminal, wherein the first reset signal terminal and the second reset signal terminal are respectively electrically connected with different reset signal lines, the scanning signal terminal is electrically connected with a scanning signal line, the light-emitting signal terminal is electrically connected with a light-emitting signal line, the first initial signal terminal is electrically connected with a first initial signal line, the second initial signal terminal is electrically connected with a second initial signal line, and the data signal terminal is electrically connected with a data signal line. 16.The display substrate of claim 15, wherein, The pixel circuit comprises a plurality of transistors, and the driving structure layer comprises a semiconductor layer, a first insulating layer, a third conductive layer, a second insulating layer, a fourth conductive layer, a third insulating layer, a first conductive layer, a fourth insulating layer and a second conductive layer which are sequentially stacked on the substrate; The semiconductor layer comprises an active layer of the plurality of transistors of at least one pixel circuit; The third conductive layer comprises a reset signal line, a scanning signal line, a light-emitting signal line, a first electrode plate and gate electrodes of the plurality of transistors; The fourth conductive layer comprises a first initial signal line, a second initial signal line and a second electrode plate; The first conductive layer comprises a first power supply connection line, a first power supply connection part and a second power supply connection part; The second conductive layer comprises a second power supply connection line, a data signal line, a first electrode block, a second electrode block, a third electrode block and a fourth electrode block. 17.The display substrate of claim 16, wherein, The arrayed pixel circuits further comprise a plurality of reset connection lines on the second conductive layer, wherein the reset connection lines extend along a first direction, and the plurality of reset connection lines are arranged along a second direction; The reset connection lines are electrically connected with the plurality of first initial signal lines through a connection block on the first conductive layer; and a projection of the reset connection lines on the substrate at least partially overlaps with a projection of a first light-emitting element on the substrate along a first direction. 18.The display substrate of claim 16, wherein, The pixel circuit is adjacent to a first adjacent pixel circuit and a second adjacent pixel circuit in the same row; a first electrode of a first reset transistor of the pixel circuit is connected with a first electrode of a first reset transistor of the first adjacent pixel circuit through the semiconductor layer; and a first electrode of a second reset transistor of the pixel circuit is connected with a first electrode of a second reset transistor of the second adjacent pixel circuit through the semiconductor layer. The first initial signal line is connected with the first electrode of the first reset transistor of the pixel circuit and the first reset transistor of the first adjacent pixel circuit through a via; and the second initial signal line is connected with the first electrode of the second reset transistor of the pixel circuit and the second reset transistor of the second adjacent pixel circuit through a via.

19. The display substrate of claim 16, wherein, The reset signal line and the scanning signal line of the pixel circuit are located on the same side of the first electrode plate of the pixel circuit, and the reset signal line is located on the side of the scanning signal line away from the first electrode plate of the pixel circuit; and the light-emitting signal line of the pixel circuit is located on the side of the first electrode plate of the pixel circuit away from the scanning signal line. The second initial signal line of the pixel circuit is located between the first initial signal line of the next row of pixel circuits and the second electrode plate of the next row of pixel circuits, and is located on the side of the second electrode plate of the pixel circuit away from the first initial signal line of the pixel circuit. 20.The display substrate of claim 17, wherein, The reset connection line includes a first protruding portion extending toward one side of the reset connection line in the second direction and a second protruding portion extending toward the other side of the reset connection line in the second direction; The first protruding portion and the second protruding portion each overlap a virtual straight line extending in the second direction, and the first protruding portion and the second protruding portion each overlap a part of a projection of the anode main portion of the first light emitting element on the substrate. 21.The display substrate of claim 16, wherein, The pixel circuit further includes a write transistor, a first light emitting control transistor, and a second light emitting control transistor; The first and second poles of the first reset transistor, the first pole of the compensation transistor, the first pole of the first light emitting control transistor, the second pole of the second light emitting transistor, and the first and second poles of the second reset transistor are located on one side of the first power supply connection line of the pixel circuit close to the first power supply connection line of the previous column of pixel circuits, and the first pole of the write transistor is located on the other side of the first power supply connection line of the pixel circuit close to the first power supply connection line of the next column of pixel circuits; The first and second poles of the first reset transistor and the first pole of the compensation transistor of the first pixel circuit are located on the first side of the first power supply connection portion, and the second pole of the second light emitting control transistor and the first and second poles of the second reset transistor are located on the second side of the first power supply connection portion; The first and second poles of the first reset transistor and the first pole of the compensation transistor of the fourth pixel circuit are located on the first side of the second power supply connection portion, and the second pole of the second light emitting control transistor and the first and second poles of the second reset transistor are located on the second side of the second power supply connection portion.

22. The display substrate of claim 17, wherein, The reset connection line is located on one side of the second power supply connection line of the pixel circuit away from the data signal line; The data signal line of the pixel circuit is located between the second power supply connection line of the pixel circuit and the second power supply connection line of the adjacent pixel circuit.

23. The display substrate of claim 1, wherein, The first and second power supply connection lines of the pixel circuit include first boundaries and second boundaries; The distance between the first boundary of the first power supply connection line and the first boundary of the second power supply connection line is greater than or equal to 0.5 microns and less than or equal to 1 micron; The distance between the second boundary of the first power supply connection line and the second boundary of the second power supply connection line is greater than or equal to 0.5 microns and less than or equal to 1 micron.

24. A display device comprising: The display substrate according to any one of claims 1 to 23.

Images