LDO compensation circuit applied to off-chip capacitor
By introducing a buffer and induced current into the LDO circuit, separating the error amplifier and power transistor, and employing the Miller compensation method, the stability problem of the LDO circuit when the load current increases is solved, thus realizing a low-power and high-stability LDO circuit design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI CHIPANALOG MICROELECTRONICS LTD
- Filing Date
- 2023-08-28
- Publication Date
- 2026-05-12
AI Technical Summary
现有LDO电路在负载电流增大时相位裕度减小，导致系统不稳定，传统方法需增加静态功耗以提高稳定性和瞬态响应。
Introducing a buffer and induced current into the LDO circuit, separating the error amplifier and power transistor, compensating for poles using the Miller compensation method, setting a current-limiting resistor to regulate the load current, improving phase margin and reducing static power consumption.
While ensuring phase margin, the static power consumption of the LDO is reduced, the system stability and load capacity are improved, and circuit damage caused by excessive output current is prevented.
Smart Images
Figure CN117193448B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit technology, specifically to an LDO compensation circuit applied to off-chip capacitors. Background Technology
[0002] In existing technologies, compensation for LDOs (low dropout regulators) is generally divided into Miller compensation (SMC), damping coefficient control compensation (PFCFC), zero-pole tracking frequency compensation (PLFEC), dynamic Miller compensation (DMFC), and pole control Miller compensation (PCFC).
[0003] As is well known, when frequency compensation is applied to feedback systems, positive feedback can cause LDO oscillation, insufficient phase margin can lead to prolonged system settling time, and deteriorated transient response. Therefore, a reliable frequency compensation method is needed to ensure system stability and transient response. To address this problem, existing LDO circuits, such as... Figure 1 As shown, it mainly consists of a first-stage error amplifier and a power transistor. The dominant pole is at the output pole, and the non-dominant pole is at the output of the error amplifier. As the load current increases, the dominant pole gradually shifts at a higher frequency, and the phase margin gradually decreases. When the load current exceeds a certain value, the LDO loop will no longer be stable. Based on this circuit structure, the traditional method is to improve the stability of the linear regulator and increase the transient response speed by modifying the transfer function, but this method requires greater static power consumption. Summary of the Invention
[0004] This invention provides an LDO compensation circuit for off-chip capacitors, which can reduce the static power consumption of the LDO.
[0005] This invention provides an LDO compensation circuit for off-chip capacitors, comprising:
[0006] Error amplifier, buffer, and power transistor;
[0007] The buffer includes an input current for sensing the magnitude of the load current;
[0008] The power transistor includes a power transistor input terminal and a power transistor output terminal;
[0009] The input terminal of the error amplifier is connected to the output reference terminal and the LDO feedback terminal, respectively. The output terminal of the error amplifier is connected to the input terminal of the buffer. The output terminal of the buffer is connected to the input terminal of the power transistor. The output terminal of the power transistor is connected to the LDO feedback terminal.
[0010] Optionally, a first pole may be included between the output of the error amplifier and the input of the buffer.
[0011] Optionally, a second pole is included between the output of the buffer and the input of the power transistor.
[0012] Optionally, a third pole may be included between the power transistor output terminal and the LDO feedback terminal.
[0013] Optionally, it may also include a first resistor and a capacitor connected together, the first resistor being connected to the buffer through the first pole.
[0014] Optionally, a second resistor is also included, wherein the output terminal of the power transistor, the input terminal of the second resistor, the output terminal of the second resistor, and the feedback terminal of the LDO are connected in sequence, and the third pole is located between the output terminal of the power transistor and the input terminal of the second resistor.
[0015] Optionally, the error amplifier adopts an OTA operational amplifier architecture and uses the Miller compensation method to compensate the first pole.
[0016] Optionally, a third resistor may also be included, with one end of the third resistor grounded and the other end connected to the output terminal of the second resistor.
[0017] This invention provides an LDO compensation circuit for off-chip capacitors, comprising: an error amplifier, a buffer, and a power transistor; the buffer includes an input induced current for sensing the magnitude of the load current; the power transistor includes an input terminal and an output terminal; the input terminal of the error amplifier is connected to the output reference terminal and the LDO feedback terminal, the output terminal of the error amplifier is connected to the input terminal of the buffer, the output terminal of the buffer is connected to the input terminal of the power transistor, and the output terminal of the power transistor is connected to the LDO feedback terminal. By setting a buffer and incorporating an induced current within the buffer, the LDO compensation circuit provided by this invention can improve the phase margin of the linear regulator while reducing static power consumption. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic diagram of an LDO circuit in the prior art;
[0020] Figure 2 This is a circuit block diagram of the LDO compensation circuit applied to off-chip capacitors according to the present invention;
[0021] Figure 3This is a circuit diagram of the LDO compensation circuit applied to off-chip capacitors according to the present invention. Detailed Implementation
[0022] The embodiments of this application will now be described in detail with reference to the accompanying drawings.
[0023] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0024] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.
[0025] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0026] The following is combined Figure 2 and Figure 3 This invention describes an LDO compensation circuit for off-chip capacitors.
[0027] The design concept of this invention is as follows: The error amplifier serves as the first-stage operational amplifier, with its input connected to the output reference and the LDO feedback terminal, primarily providing gain. The first-stage operational amplifier contributes a non-dominant pole (first pole P1). If it directly drives the power transistor, the non-dominant pole (first pole P1) will be too close to the dominant pole, resulting in insufficient phase margin of the linear regulator. Therefore, a buffer X1 is used as the second stage. The buffer X1 further away from the non-dominant pole (first pole P1) by copying the output current. This allows the dominant pole to be at a relatively low frequency when the output current is small, and the copied current is also small, thus reducing the current under light load. Under heavy load, the output current is smaller, and the current injected into the buffer X1 is larger. Therefore, the non-dominant pole (second pole P2) of the second stage will move to a higher frequency position compared to the light load condition. This provides a non-dominant pole (second pole P2) that follows the dominant pole. An over-the-air (OTA) op-amp architecture is used for the error amplifier, employing Miller compensation to compensate for the op-amp's own pole (first pole P1). The op-amp's output stage provides a relatively small output impedance, thus providing a non-dominant pole (first pole P1) that is far from the dominant pole, improving the phase margin of the linear regulator. A current-limiting second resistor R2 is added below the second-stage buffer X1. When the output current is too large, the copy current is also large, and the current flowing through the second resistor R2 is also large, thereby increasing the voltage across the second resistor R2. This causes the second-stage buffer X1 to enter the linear region, thereby limiting the gate voltage of the power transistor and thus limiting the output current.
[0028] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.
[0029] like Figure 2 As shown, an LDO compensation circuit for off-chip capacitors includes: an error amplifier, a buffer X1, and a power transistor.
[0030] The buffer X1 includes an input current I for sensing the magnitude of the load current;
[0031] The power transistor includes a power transistor input terminal and a power transistor output terminal;
[0032] The input terminal of the error amplifier is connected to the output reference terminal Vref and the LDO feedback terminal, respectively. The output terminal of the error amplifier is connected to the input terminal of the buffer X1. The output terminal of the buffer X1 is connected to the input terminal of the power transistor. The output terminal of the power transistor is connected to the LDO feedback terminal.
[0033] The solution described in this invention involves adding a buffer to a traditional LDO, separating the error amplifier and the power transistor, and dividing a low-frequency pole (in the prior art) into two high-frequency poles (the first pole P1 and the second pole P2). Simultaneously, an induced current is added to the buffer X1, allowing the second pole P2 to vary according to the load current. This provides low power consumption under light loads while ensuring phase margin under heavy loads.
[0034] In one specific embodiment, a first pole P1 is included between the output of the error amplifier and the input of the buffer.
[0035] In one specific embodiment, a second pole P2 is included between the output of the buffer and the input of the power transistor.
[0036] In one specific embodiment, a third pole P3 is included between the LDO feedback terminal and the input terminal of the error amplifier.
[0037] P1, P2, and P3 correspond to the poles generated by the error amplifier, buffer X1, and power transistor, respectively. The stability of the LDO can be determined by the position of the pole frequencies on the Bode plot.
[0038] In one specific embodiment, it further includes a first resistor R1 and a capacitor C1, the first resistor R1 and the capacitor C1 are connected, and the first resistor R1 is connected to the buffer X1 through the first pole P1.
[0039] In this circuit, adding a large resistor (first resistor R1) and a small capacitor (capacitor C1) to the first-stage error amplifier can provide a zero point in the left half-plane, which can counteract the influence of the second pole P2 and improve the stability of the loop.
[0040] In one specific embodiment, a second resistor R2 is also included. The LDO feedback terminal, the input terminal of the second resistor R2, the output terminal of the second resistor R2, and the input terminal of the error amplifier are connected in sequence. The third pole P3 is located between the output terminal of the power transistor and the input terminal of the second resistor R2.
[0041] In this invention, a current-limiting second resistor R2 is added below the second-stage buffer X1. When the output current is too large, the copy current is also relatively large, and the current flowing through the second resistor R2 is also relatively large, thereby increasing the voltage on the second resistor R2, causing the second-stage buffer X1 to enter the linear region, thereby limiting the gate voltage of the power transistor and thus limiting the output current.
[0042] In one specific embodiment, the error amplifier adopts an OTA operational amplifier architecture and uses the Miller compensation method to compensate for the first pole.
[0043] In one specific embodiment, a third resistor R3 is also included, one end of which is grounded and the other end is connected to the output terminal of the second resistor R2.
[0044] based on Figure 2 The circuit principle in this invention is as follows: Figure 3 As shown, traditional LDOs, due to their compensation methods, have non-dominant poles at relatively high frequencies, resulting in higher quiescent power consumption in the first-stage operational amplifier (error amplifier). To address this issue, this invention incorporates M11, M12, M13, and M14, which sense the load current and channel it to the second pole P2. When the load current is low, the second pole P2 is closer; when the load current is high, it is farther away. Therefore, the second pole P2 can follow the dominant pole's movement, reducing quiescent current under light loads. This invention also includes a fourth resistor R4. When the load current is high, the voltage drop across R4 is also high, thus limiting the gate voltage of power transistor M10 from becoming too low, thereby limiting short-circuit current. In this invention, the first-stage operational amplifier (including M1-M8) adopts an over-the-air (OTA) architecture, which improves the bandwidth of the first pole P1 and enhances the loop stability of the LDO.
[0045] The present invention also discloses the following technical effects:
[0046] This invention solves the problem of insufficient phase margin in LDO compensation circuits under heavy loads, and improves the load-carrying capacity of LDOs.
[0047] This invention introduces current limiting regulation to prevent the risk of circuit damage caused by excessive output current when the external output terminal is short-circuited.
[0048] The LDO compensation circuit of this invention can improve the stability of the LDO, extend its service life, and reduce the possibility of LDO damage.
[0049] This invention can reduce the static power consumption of an LDO while maintaining the same phase margin.
[0050] The method of copying the output current used in this invention can reduce current consumption under light load.
[0051] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the descriptions of the embodiments described later are relatively simple, and relevant parts can be referred to the descriptions of the foregoing embodiments.
[0052] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. An LDO compensation circuit applied to off-chip capacitors, characterized in that, include: Error amplifier, buffer, and power transistor; The buffer includes an input current for sensing the magnitude of the load current; The power transistor includes a power transistor input terminal and a power transistor output terminal; The input terminal of the error amplifier is connected to the output reference terminal and the LDO feedback terminal, respectively. The output terminal of the error amplifier is connected to the input terminal of the buffer. The output terminal of the buffer is connected to the input terminal of the power transistor. The output terminal of the power transistor is connected to the LDO feedback terminal. It also includes a fourth resistor R4. When the load current is relatively large, the voltage drop across the fourth resistor R4 is also relatively large, in order to limit the voltage of the power transistor gate from being too low, thereby limiting the short-circuit current.
2. The LDO compensation circuit applied to off-chip capacitors according to claim 1, characterized in that, The error amplifier has a first pole between its output and the buffer's input.
3. The LDO compensation circuit applied to off-chip capacitors according to claim 1, characterized in that, The buffer includes a second pole between its output and the power transistor's input.
4. The LDO compensation circuit applied to off-chip capacitors according to claim 1, characterized in that, A third pole is included between the output terminal of the power transistor and the feedback terminal of the LDO.
5. The LDO compensation circuit applied to off-chip capacitors according to claim 2, characterized in that, It also includes a first resistor and a capacitor connected together, the first resistor being connected to the buffer through the first pole.
6. The LDO compensation circuit applied to off-chip capacitors according to claim 4, characterized in that, It also includes a second resistor, and the output terminal of the power transistor, the input terminal of the second resistor, the output terminal of the second resistor, and the feedback terminal of the LDO are connected in sequence. The third pole is located between the output terminal of the power transistor and the input terminal of the second resistor.
7. The LDO compensation circuit for off-chip capacitors according to claim 2 or 5, characterized in that, The error amplifier adopts an OTA operational amplifier architecture and uses the Miller compensation method to compensate for the first pole.
8. The LDO compensation circuit for off-chip capacitors according to claim 6, characterized in that, It also includes a third resistor, one end of which is grounded and the other end is connected to the output terminal of the second resistor.