A startup circuit and a bandgap reference circuit

Abstract

The present invention relates to the technical field of radio frequency front-end chips, and discloses a startup circuit and a bandgap reference circuit. The startup circuit includes a power input terminal, a bias voltage setting unit, a first control switch, a current regulating resistor R7, a voltage drop unit, and a second control switch. The bias voltage setting unit and the input terminal of the first control switch are respectively electrically connected to the power input terminal. The bias voltage setting unit provides a bias voltage to the control terminal of the first control switch. The output terminal of the first control switch is electrically connected to the input terminal of the voltage drop unit via the current regulating resistor R7, and the input terminal of the voltage drop unit is electrically connected to the control terminal of the second control switch. In actual use, the startup circuit of the present invention can still be normally shut down when the voltage input to the power input terminal is greater than 2.8V, without affecting the normal use of the bandgap reference circuit using the present invention.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency front-end chips, and in particular to a startup circuit and a bandgap reference circuit. Background Art

[0002] Bandgap reference circuit is a common basic module of RF front-end chips in mobile products and is often used to provide reference voltage. Common bandgap reference circuits are as follows: Figure 1 and Figure 2 As shown, Figure 1 The bandgap reference circuit in the embodiment requires operational amplifier A1 to act as a voltage clamp so that the voltage at electrical node X is the same as the voltage at electrical node Y. However, this makes the circuit relatively complex, and operational amplifier A1 consumes current and increases the chip area.

[0003] To solve Figure 1 The circuit has deficiencies. Figure 2 In the circuit, the PMOS transistors P1-PMOS transistor P4 and the NMOS transistors N1-NMOS transistor N4 form a self-biasing structure. This self-biasing structure replaces the voltage clamping function of operational amplifier A1, saving circuit current and area. Diode D4 is also introduced as a startup circuit to free the circuit from the merging point and allow it to operate at the desired operating point.

[0004] Figure 2 The startup process of the circuit in is as follows: when the circuit voltage VDD>VTH_p2+Vdiode_D4+VTH_n3+Vdiode_D1, which is about 2V, the diode D4 is turned on, and the charging current inside the circuit gradually builds up to the normal working state;

[0005] When the circuit voltage VDD>VGS_p2+Vdiode_D4+VGS_n3+Vdiode_D1, which is about 2.8V, diode D4 will still be turned on. At this time, the circuit has established a normal working state, and diode D4 needs to be turned off. If it is not turned off, it is an unexpected leakage, which will eventually affect the reference voltage of the circuit output. Since the RF front-end chip in mobile products needs to use a wide voltage range of 2.5V to 4.5V, when Figure 2 When the circuit in the present invention is used in the RF front-end chip in mobile products, unexpected leakage may occur. Summary of the Invention

[0006] In view of the shortcomings of the background technology, the present invention provides a startup circuit and a bandgap reference circuit. The technical problem to be solved is that when the existing bandgap reference circuit is used in the RF front-end chip in mobile products, unexpected leakage will occur.

[0007] In order to solve the above technical problems, in the first aspect, the present invention provides a starting circuit, including a power input terminal, a bias voltage setting unit, a first control switch, a current regulating resistor R7, a voltage drop unit and a second control switch; the bias voltage setting unit and the input terminal of the first control switch are respectively electrically connected to the power input terminal; the voltage output terminal of the bias voltage setting unit is electrically connected to the control terminal of the first control switch, and provides a bias voltage to the control terminal of the first control switch; the output terminal of the first control switch is electrically connected to the input terminal of the voltage drop unit through the current regulating resistor R7, the bias voltage is greater than the voltage drop of the voltage drop unit, and the input terminal of the voltage drop unit is electrically connected to the control terminal of the second control switch.

[0008] In a certain embodiment of the first aspect, the bias voltage setting unit includes a current regulating resistor R5 and a diode branch, the diode branch includes at least three diodes connected in series, one end of the current regulating resistor R5 is electrically connected to the power input end, and the other end of the resistor R5 is electrically connected to the control end of the first control switch and the diode branch respectively.

[0009] In a certain embodiment of the first aspect, the voltage drop unit includes a MOS transistor N5 and a second diode branch, the second diode branch includes at least one diode, and when the second diode branch includes more than two diodes, all diodes of the second diode branch are connected in series in sequence, and the drain of the MOS transistor N5 is electrically connected to the gate of the MOS transistor N5, the control end of the second control switch, and the current regulating resistor R7, respectively.

[0010] In a certain embodiment of the first aspect, the diode branch includes a diode D4, a diode D5 and a diode D6, the anode of the diode D4 is electrically connected to the current regulating resistor R5, the cathode of the diode D4 is electrically connected to the anode of the diode D5, the cathode of the diode D5 is electrically connected to the anode of the diode D6, and the cathode of the diode D6 is grounded.

[0011] In a certain embodiment of the first aspect, the first control switch is an NMOS transistor, and the second control switch is an NMOS transistor.

[0012] In a second aspect, the present invention further provides a bandgap reference circuit, comprising MOS transistors P1, P2, P3, P4, P5, P6, N1, N2, N3, N4, resistors R1, R2, R3, R4, diodes D1, D2, D3, and the aforementioned startup circuit;

[0013] The source of the MOS transistor P5, the source of the MOS transistor P1 and the source of the MOS transistor P2 are all electrically connected to the power input terminal;

[0014] The gate of the MOS transistor P5 is electrically connected to the gate of the MOS transistor P1, the gate of the MOS transistor P2, the drain of the MOS transistor P4 and one end of the resistor R2 respectively;

[0015] The drain of the MOS transistor P5 is electrically connected to the source of the MOS transistor P6, and the gate of the MOS transistor P6 is electrically connected to the gate of the MOS transistor P3, the gate of the MOS transistor P4, the other end of the resistor R2, the drain of the MOS transistor N2, and the input end of the second control switch.

[0016] The drain of the MOS transistor P6 is electrically connected to one end of the resistor R4, the gate of the MOS transistor N8, and the output end of the second control switch respectively; the other end of the resistor R4 is electrically connected to the anode of the diode D3, and the cathode of the diode D3 is electrically connected to the source of the MOS transistor N8;

[0017] The drain of the MOS transistor P1 is electrically connected to the source of the MOS transistor P3; the drain of the MOS transistor P3 is electrically connected to one end of the resistor R1, the gate of the MOS transistor N1, and the drain of the MOS transistor N2, respectively; the other end of the resistor R1 is electrically connected to the drain of the MOS transistor N1, the gate of the MOS transistor N3, and the gate of the MOS transistor N4, respectively; the source of the MOS transistor N1 is electrically connected to the drain of the MOS transistor N3; the source of the MOS transistor N3 is electrically connected to the anode of the diode D1; and the cathode of the diode D1 is electrically connected to the source of the MOS transistor N8;

[0018] The drain of the MOS transistor P2 is electrically connected to the source of the MOS transistor P4, the source of the MOS transistor N2 is electrically connected to the drain of the MOS transistor N4, the source of the MOS transistor N4 is electrically connected to one end of the resistor R3, the other end of the resistor R3 is electrically connected to the anode of the diode D2, and the cathode of the diode D2 is electrically connected to the source of the MOS transistor N8.

[0019] When the startup circuit of the present invention is applied to the bandgap reference circuit of the present invention, the working principle of the startup circuit is as follows:

[0020] MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor P4, MOS transistor P5 and MOS transistor P6 also form a current mirror circuit;

[0021] When the power input terminal is connected to the power supply, the first control switch and the second control switch are turned on, and no current flows through the diode D3. The voltage difference between the gate and source of the MOS transistor N6 causes the MOS transistor N6 to be turned on, thereby turning on the MOS transistors P2 and P4, and starting the current mirror circuit. The entire bandgap reference current is internally established to start the current.

[0022] The bandgap reference circuit then generates a larger startup current through its own self-bias positive feedback. As the startup current increases, the voltage at node VBG increases. When the voltage at node VBG rises to a certain level, the voltage between the gate and source of MOS transistor N6 becomes less than zero, thereby turning off MOS transistor N6. This continues until the bandgap reference voltage output by the bandgap reference circuit is fully established and the device operates in a stable state. Therefore, the MOS transistor N6 of the present invention serves as a control device for current conduction and shutdown, and also as a sensing device for sensing shutdown.

[0023] Compared with the prior art, the present invention has the following beneficial effects: in actual use, the startup circuit of the present invention can still be normally shut down when the voltage input to the power input terminal is greater than 2.8V, without affecting the normal use of the bandgap reference circuit using the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A circuit diagram of a first existing bandgap reference circuit;

[0025] Figure 2 is a circuit diagram of a second existing bandgap reference circuit;

[0026] Figure 3 is a structural diagram of a startup circuit in an embodiment;

[0027] Figure 4 is a circuit diagram of a starting circuit in an embodiment;

[0028] Figure 5 is a circuit diagram of a bandgap reference circuit in an embodiment. DETAILED DESCRIPTION

[0029] The present invention will now be described in further detail with reference to the accompanying drawings, which are simplified schematic diagrams that illustrate the basic structure of the present invention in a schematic manner.

[0030] like Figure 3 As shown, a startup circuit includes a power input terminal avdd, a bias voltage setting unit 1, a first control switch 2, a current regulating resistor R7, a voltage drop unit 3, and a second control switch 4; the input terminals of the bias voltage setting unit 1 and the first control switch 2 are electrically connected to the power input terminal avdd, respectively; the voltage output terminal of the bias voltage setting unit 1 is electrically connected to the control terminal of the first control switch 2, providing a bias voltage to the control terminal of the first control switch 2; the output terminal of the first control switch 2 is electrically connected to the input terminal of the voltage drop unit 3 through the current regulating resistor R7, the bias voltage is greater than the voltage drop of the voltage drop unit 3, and the input terminal of the voltage drop unit 3 is electrically connected to the control terminal of the second control switch 4.

[0031] In actual use, the bias voltage output by the bias voltage setting unit 1 is used to drive the first control switch to turn on. By setting the difference between the bias voltage and the voltage drop of the voltage drop unit 3 and adjusting the resistance of the current regulating resistor R7, the current flowing through the current regulating resistor R7 and the voltage drop unit 3 can be adjusted, thereby enabling the operating current of the startup circuit to be low after startup, thereby reducing power consumption. In addition, when the output terminal voltage of the second control switch 2 is lower than the voltage of the input terminal of the voltage drop unit 3, the second control switch 2 is turned on. When the output terminal voltage of the second control switch 2 is higher than the voltage of the input terminal of the voltage drop unit 3, the second control switch 2 is turned off. The turning on and off of the second control switch 2 can be controlled. Figure 2 Startup of the bandgap reference circuit.

[0032] In this embodiment, the bias voltage setting unit 1 includes a current regulating resistor R5 and a diode branch, the diode branch includes at least three diodes connected in series, one end of the current regulating resistor R5 is electrically connected to the power input terminal avdd, and the other end of the resistor R5 is electrically connected to the control terminal of the first control switch 1 and the diode branch respectively.

[0033] In actual use, since the voltage drop of a single diode is about 0.7V, the bias voltage can be adjusted by setting the number of diodes in the diode branch. Figure 4 The diode branch includes diode D4, diode D5 and diode D6 connected in series, and the bias voltage is the voltage drop of the three diodes, which is 2.1V.

[0034] In this embodiment, the voltage drop unit includes a MOS transistor N5 and a second diode branch. The second diode branch includes at least one diode. When the second diode branch includes two or more diodes, all diodes of the second diode branch are connected in series in sequence. The drain of the MOS transistor N5 is electrically connected to the gate of the MOS transistor N5, the control end of the second control switch, and the current regulating resistor R7, respectively.

[0035] In actual use, the voltage at the control end of the second control switch 4 can be adjusted by setting the number of diodes in the second diode branch. However, when setting the number of diodes in the diode branch and the second diode branch, the bias voltage needs to be greater than the voltage drop of the voltage drop unit 3. Figure 4Since the bias voltage is the voltage drop of three diodes, and the second diode branch includes a diode D7, the voltage across the current regulating resistor R7 is 1.4V minus the voltage drop between the control terminal and the output terminal of the first control switch 1 and the voltage drop between the gate and the source of the MOS transistor N5. Since the voltage drop across the current regulating resistor R7 is fixed, the current flowing through the current regulating resistor R7 can be set by setting the resistance value of the current regulating resistor R7, thereby reducing the operating current and power consumption of the startup circuit after startup. Similarly, since the voltage of the power input terminal avdd is known, the voltage drops of the diodes D4, D5, and D6 are known. Therefore, the current flowing through the current regulating resistor R5 can be adjusted by adjusting the resistance value of the current regulating resistor R5, thereby reducing the operating current and power consumption of the startup circuit after startup.

[0036] Specifically, refer to Figure 4 In this embodiment, the first control switch 1 is an NMOS transistor and the second control switch 4 is an NMOS transistor.

[0037] In addition, in this embodiment, by sequentially connecting the first control switch 1, the current regulating resistor R7, and the voltage drop unit 3 in series, the circuit area can be reduced while ensuring that the current flowing through the current regulating resistor R7 is as low as possible. Specifically, the gate-source voltage drop Vgs of the first control switch 1 is calculated as 0.4V. If the current flowing through the current regulating resistor R7 remains unchanged and the first control switch 1 is not required, the resistance of the current regulating resistor R7 needs to be increased by 2M. Compared with adding the first control switch 1, increasing the resistance of the current regulating resistor R7 by 2M requires more circuit area.

[0038] In addition, Figure 4 In the startup circuit shown, the leftmost branch, namely the bias voltage setting unit 1, includes three diodes, namely, diode D4, diode D5, and diode D6. The second branch from left to right includes MOS transistor N7, MOS transistor N5, and diode D7. In actual use, when temperature changes, causing the voltage drops of diodes D4, D5, D6, and D7, and the gate-source voltage drops Vgs of MOS transistors N7 and N5 to change, the voltage drops of diodes D4, D5, D6, and D7, and the gate-source voltage drops Vgs of MOS transistors N7 and N5 all change in the same direction, thereby ensuring that the voltage applied to both ends of the current regulating resistor R7 is stable, thus stabilizing the circuit flowing through the current regulating resistor R7 and ensuring that the absolute value of the current flowing through the current regulating resistor R7 is relatively low in the application environment, meeting the low power consumption requirement.

[0039] Second, as Figure 5As shown, the present invention further provides a bandgap reference circuit, which uses the above-mentioned startup circuit, including MOS transistors P1, MOS transistors P2, MOS transistors P3, MOS transistors P4, MOS transistors P5, MOS transistors P6, MOS transistors N1, MOS transistors N2, MOS transistors N3, MOS transistors N4, resistors R1, resistors R2, resistors R3, resistors R4, diodes D1, diodes D2, diodes D3 and the above-mentioned startup circuit;

[0040] The source of the MOS transistor P5, the source of the MOS transistor P1 and the source of the MOS transistor P2 are all electrically connected to the power input terminal;

[0041] The gate of the MOS transistor P5 is electrically connected to the gate of the MOS transistor P1, the gate of the MOS transistor P2, the drain of the MOS transistor P4 and one end of the resistor R2 respectively;

[0042] The drain of the MOS transistor P5 is electrically connected to the source of the MOS transistor P6, and the gate of the MOS transistor P6 is electrically connected to the gate of the MOS transistor P3, the gate of the MOS transistor P4, the other end of the resistor R2, the drain of the MOS transistor N2, and the input end of the second control switch.

[0043] The drain of the MOS transistor P6 is electrically connected to one end of the resistor R4, the gate of the MOS transistor N8, and the output end of the second control switch respectively; the other end of the resistor R4 is electrically connected to the anode of the diode D3, and the cathode of the diode D3 is electrically connected to the source of the MOS transistor N8;

[0044] The drain of the MOS transistor P1 is electrically connected to the source of the MOS transistor P3; the drain of the MOS transistor P3 is electrically connected to one end of the resistor R1, the gate of the MOS transistor N1, and the drain of the MOS transistor N2, respectively; the other end of the resistor R1 is electrically connected to the drain of the MOS transistor N1, the gate of the MOS transistor N3, and the gate of the MOS transistor N4, respectively; the source of the MOS transistor N1 is electrically connected to the drain of the MOS transistor N3; the source of the MOS transistor N3 is electrically connected to the anode of the diode D1; and the cathode of the diode D1 is electrically connected to the source of the MOS transistor N8;

[0045] The drain of the MOS transistor P2 is electrically connected to the source of the MOS transistor P4, the source of the MOS transistor N2 is electrically connected to the drain of the MOS transistor N4, the source of the MOS transistor N4 is electrically connected to one end of the resistor R3, the other end of the resistor R3 is electrically connected to the anode of the diode D2, and the cathode of the diode D2 is electrically connected to the source of the MOS transistor N8.

[0046] When the startup circuit in this embodiment is applied to the bandgap reference circuit of the present invention, the working process of the bandgap reference circuit is as follows: MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor P4, MOS transistor P5 and MOS transistor P6 also form a current mirror circuit;

[0047] When the power input terminal is connected to the power supply, the first control switch and the second control switch are turned on, and no current flows through the diode D3. The voltage difference between the gate and source of the MOS transistor N6 causes the MOS transistor N6 to be turned on, thereby turning on the MOS transistors P2 and P4, and starting the current mirror circuit. The entire bandgap reference current is internally established to start the current.

[0048] The bandgap reference circuit then generates a larger startup current through its own self-bias positive feedback. As the startup current increases, the voltage at node VBG increases. When the voltage at node VBG rises to a certain level, the voltage between the gate and source of MOS transistor N6 becomes less than zero, thereby turning off MOS transistor N6. This continues until the bandgap reference voltage output by the bandgap reference circuit is fully established and the device operates in a stable state. Therefore, the MOS transistor N6 of the present invention serves as a control device for current conduction and shutdown, and also as a sensing device for sensing shutdown.

[0049] Therefore, in actual use, the startup circuit of the present invention can still be normally shut down when the voltage input to the power input terminal is greater than 2.8V, without affecting the normal use of the bandgap reference circuit of the present invention.

[0050] The above description is for inspiration. Based on the above description, relevant personnel can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the content of the specification, but must be determined according to the scope of the claims.

Claims

1. A bandgap reference circuit, comprising MOS transistors P1, P2, P3, P4, P5, P6, N1, N2, N3, N4, resistors R1, R2, R3, R4, diodes D1, D2, and D3, characterized in that: The device further includes a startup circuit, the startup circuit including a power input terminal, a bias voltage setting unit, a first control switch, a current regulating resistor R7, a voltage drop unit, and a second control switch; the input terminals of the bias voltage setting unit and the first control switch are electrically connected to the power input terminal respectively; The voltage output terminal of the bias voltage setting unit is electrically connected to the control terminal of the first control switch, providing a bias voltage to the control terminal of the first control switch; the output terminal of the first control switch is electrically connected to the input terminal of the voltage drop unit through the current regulating resistor R7, the bias voltage is greater than the voltage drop of the voltage drop unit, and the input terminal of the voltage drop unit is electrically connected to the control terminal of the second control switch; The bias voltage setting unit includes a current regulating resistor R5 and a diode branch, wherein the diode branch includes at least three diodes connected in series, one end of the current regulating resistor R5 is electrically connected to the power input terminal, and the other end of the resistor R5 is electrically connected to the control terminal of the first control switch and the diode branch respectively; The first control switch is an NMOS transistor, and the second control switch is an NMOS transistor; The source of the MOS transistor P5, the source of the MOS transistor P1 and the source of the MOS transistor P2 are all electrically connected to the power input terminal; The gate of the MOS transistor P5 is electrically connected to the gate of the MOS transistor P1, the gate of the MOS transistor P2, the drain of the MOS transistor P4 and one end of the resistor R2 respectively; The drain of the MOS transistor P5 is electrically connected to the source of the MOS transistor P6, and the gate of the MOS transistor P6 is electrically connected to the gate of the MOS transistor P3, the gate of the MOS transistor P4, the other end of the resistor R2, the drain of the MOS transistor N2, and the input end of the second control switch. The drain of the MOS transistor P6 is electrically connected to one end of the resistor R4, the gate of the MOS transistor N8, and the output end of the second control switch respectively; the other end of the resistor R4 is electrically connected to the anode of the diode D3, and the cathode of the diode D3 is electrically connected to the source of the MOS transistor N8; The drain of the MOS transistor P1 is electrically connected to the source of the MOS transistor P3; the drain of the MOS transistor P3 is electrically connected to one end of the resistor R1, the gate of the MOS transistor N1, and the drain of the MOS transistor N2, respectively; the other end of the resistor R1 is electrically connected to the drain of the MOS transistor N1, the gate of the MOS transistor N3, and the gate of the MOS transistor N4, respectively; the source of the MOS transistor N1 is electrically connected to the drain of the MOS transistor N3; the source of the MOS transistor N3 is electrically connected to the anode of the diode D1; and the cathode of the diode D1 is electrically connected to the source of the MOS transistor N8; The drain of the MOS transistor P2 is electrically connected to the source of the MOS transistor P4, the source of the MOS transistor N2 is electrically connected to the drain of the MOS transistor N4, the source of the MOS transistor N4 is electrically connected to one end of the resistor R3, the other end of the resistor R3 is electrically connected to the anode of the diode D2, and the cathode of the diode D2 is electrically connected to the source of the MOS transistor N8.

2. A bandgap reference circuit according to claim 1, characterized in that: The voltage drop unit includes a MOS transistor N5 and a second diode branch. The second diode branch includes at least one diode. When the second diode branch includes two or more diodes, all diodes of the second diode branch are connected in series in sequence. The drain of the MOS transistor N5 is electrically connected to the gate of the MOS transistor N5, the control end of the second control switch, and the current regulating resistor R7, respectively.

3. A bandgap reference circuit according to claim 2, characterized in that: The diode branch includes a diode D4, a diode D5 and a diode D6. The anode of the diode D4 is electrically connected to the current regulating resistor R5, the cathode of the diode D4 is electrically connected to the anode of the diode D5, the cathode of the diode D5 is electrically connected to the anode of the diode D6, and the cathode of the diode D6 is grounded.

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