A calibration circuit for a two-step time-to-digital converter

Abstract

The application discloses a kind of calibration circuits of two-step time digital converter, including source signal module, for generating first timing signal based on the coarse quantization signal of two-step time digital converter and main clock signal, and according to first clock signal generation second clock signal;First-stage correction module includes two correction circuits;Wherein, first path correction circuit is based on first clock signal and first timing signal and carries out preliminary correction, and outputs first preliminary correction signal;Second path correction circuit is based on second clock signal and first timing signal and carries out preliminary correction, and outputs second preliminary correction signal;Second-stage correction module is used to carry out secondary correction to first preliminary correction signal and second preliminary correction signal, and output two groups of calibration digital control code, so as to utilize calibration digital control code and carry out correction operation to coarse quantization count value.The circuit effectively solves the error caused by transmission delay mismatch and traditional coarse quantization module repeated counting, and improves conversion precision.

Description

Technical Field

[0001] This invention belongs to the field of time-to-digital converter technology, and specifically relates to a calibration circuit for a two-step time-to-digital converter. Background Technology

[0002] A Time-to-Digital Converter (TDC) is a functional device that converts time signals into digital signals. It uses a counter to measure and count the time signal, quantizing the measured time interval into a corresponding digital output. A two-step quantization TDC divides the quantization process into two stages: coarse quantization and fine quantization. Coarse quantization is typically implemented using a counter, while fine quantization uses structures such as time delay chains. Specifically, the input signal is first fed into the coarse quantization unit for measurement, and then the residual quantization error from the coarse quantization unit is fed into the fine quantization unit for precise measurement. An ideal two-step TDC quantization architecture and timing are as follows: Figure 1 As shown, first pass through CLK <0> The master clock performs coarse quantization counting on the time signal T, and then the fine quantization module performs fine quantization on the residual error that the coarse quantization module cannot count. t1 is the fine quantization value at the Tstart terminal, t2 is the fine quantization value at the Tstop terminal, and N*Tclk is the coarse quantization count value, that is: T=COUNTER-t1+t2=N*TCLK-t1+t2.

[0003] However, in the traditional coarse quantization module of two-step TDC, the time signal T and CLK... <0> After ANDing, the data is directly input to a counter for coarse quantization. This structure presents a problem in practical transmission scenarios, such as... Figure 2 As shown, when the ZC signal edge is at CLK <0> When high, ZC and CLK <0> AND operations can result in duplicate counts, leading to errors in the coarse quantization count.

[0004] Furthermore, the delays for the time signal T transmitted to the coarse quantization module and the fine quantization module are different; signals ZC and ZF represent the signals T arriving at the coarse quantization module and the fine quantization module, respectively. For example... Figure 3 As shown, ideally, the ZC and ZF edges should coincide. However, in reality, due to propagation delay mismatch, the ZC and ZF edges deviate. Therefore, the delay mismatch on the propagation path will affect both coarse and fine quantization results, thus limiting the overall conversion accuracy to the coarse quantization accuracy. That is, τ1≠τ2, τ3≠τ4. Here, τ1 and τ2 are the propagation delay times of the rising edge of ZC and the falling edge of ZF, respectively, while τ3 and τ4 are the propagation delay times of the falling edge of ZC and the rising edge of ZF.

[0005] like Figure 4As shown in (a), assuming the fine quantization signal ZF edge is used as the reference, when τ1>τ2, and the rising edge of ZC is within the next clock cycle of the falling edge of ZF, the coarse quantization value is counted by 1 less; Figure 4 As shown in (b), when τ1 < τ2, the rising edge of ZC is within the clock cycle preceding the falling edge of ZF, so the coarse quantization value is over-counted by 1; Figure 4 As shown in (c), when τ3 > τ4, and the falling edge of ZC is within the next clock cycle of the rising edge of ZF, the coarse quantization value is over-counted by 1; Figure 4 As shown in (d), when τ3 < τ4, the falling edge of ZC is within the clock preceding the rising edge of ZF, so the coarse quantization value is counted by 1 less.

[0006] It is evident that the existing two-step TDC suffers from transmission delay mismatch and error caused by repeated counting in the traditional coarse quantization module, thus affecting the accuracy of the overall quantization result. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this invention provides a calibration circuit for a two-step time-to-digital converter. The technical problem to be solved by this invention is achieved through the following technical solution:

[0008] This invention provides a calibration circuit for a two-step time-to-digital converter, comprising a source signal module, a first-stage calibration module, and a second-stage calibration module connected in sequence; wherein,

[0009] The source signal module is based on the coarse quantization signal ZC and the master clock signal CLK from the two-step time-to-digital converter. <0> Generate the first timing signal ZC_DTRI, and according to the first clock signal CLK <1> Generate the second clock signal CLK <1> _INV;

[0010] The first-stage correction module includes two correction circuits; wherein, the first correction circuit is based on the first clock signal CLK. <1> The first timing signal ZC_DTRI is used for preliminary calibration, and a first preliminary calibration signal N11 is output; the second calibration circuit is based on the second clock signal CLK. <1> _INV and the first timing signal ZC_DTRI are initially corrected, and a second preliminary correction signal N21 is output;

[0011] The second-level correction module is used to perform secondary correction on the first preliminary correction signal N11 and the second preliminary correction signal N21, and output two sets of calibration digital control codes Mstop<1:0> and Mstart<1:0>, so as to use the calibration digital control codes Mstop<1:0> and Mstart<1:0> to perform correction operation on the coarse quantization count value.

[0012] The beneficial effects of this invention are:

[0013] The calibration circuit of the two-step time-to-digital converter provided by this invention is designed with a source signal module and a two-stage correction module. The output signal of the source signal module enters the first-stage correction module for preliminary correction, and then the second-stage correction module performs secondary correction. The calibration digital control code generated by the second-stage correction module can perform correction operations such as hold, increment, increment, decrement, and decrement on the coarse quantization count value. This circuit effectively solves the errors caused by transmission delay mismatch and repeated counting in the traditional coarse quantization module without increasing the number of fine quantization bits, thus improving the conversion accuracy of the TDC.

[0014] 2. The calibration circuit of the two-step time-to-digital converter provided by the present invention also avoids doubling the finer quantization area or conversion time.

[0015] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0016] Figure 1 This is the ideal two-step TDC quantization architecture and timing diagram;

[0017] Figure 2 This is a timing diagram of error analysis for a traditional two-step TDC coarse quantization module;

[0018] Figure 3 This is a timing diagram of a traditional two-step TDC coarse and fine quantization signal;

[0019] Figure 4 This is a timing diagram for traditional two-step TDC coarse and fine quantization transmission delay error analysis;

[0020] Figure 5 This is a structural block diagram of a calibration circuit for a two-step time-to-digital converter provided in an embodiment of the present invention;

[0021] Figure 6 This is a detailed circuit diagram of a calibration circuit for a two-step time-to-digital converter provided in an embodiment of the present invention;

[0022] Figure 7 This is a timing diagram of the error calibration at the Tstart terminal of the calibration circuit provided in this embodiment of the invention;

[0023] Figure 8 This is a timing diagram of the error calibration at the Tstop terminal of the calibration circuit provided in an embodiment of the present invention. Detailed Implementation

[0024] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0025] Example 1

[0026] Please see Figure 5 , Figure 5This is a structural block diagram of a calibration circuit for a two-step time-to-digital converter provided in an embodiment of the present invention. The calibration circuit for the two-step time-to-digital converter provided in this embodiment includes a source signal module, a first-stage calibration module, and a second-stage calibration module connected in sequence; wherein,

[0027] The source signal module is based on the coarse quantization signal ZC and the master clock signal CLK from the two-step time-to-digital converter. <0> Generate the first timing signal ZC_DTRI, and according to the first clock signal CLK <1> Generate the second clock signal CLK <1> _INV;

[0028] The first-level calibration module includes two calibration circuits; the first calibration circuit is based on the first clock signal CLK. <1> The first timing signal ZC_DTRI is used for initial calibration, and the first initial calibration signal N11 is output; the second calibration circuit is based on the second clock signal CLK. <1> _INV and the first timing signal ZC_DTRI are used for preliminary correction, and the second preliminary correction signal N21 is output;

[0029] The second-level calibration module is used to perform secondary calibration on the first preliminary calibration signal N11 and the second preliminary calibration signal N21, and outputs two sets of calibration digital control codes Mstop<1:0> and Mstart<1:0>, so as to use the calibration digital control codes Mstop<1:0> and Mstart<1:0> to perform calibration operations on the coarse quantization count value.

[0030] Among them, the first clock signal CLK <1> Lagging behind the master clock signal CLK <0> 90 degrees.

[0031] Alternatively, as one implementation method, please refer to Figure 6 , Figure 6 This is a detailed circuit diagram of a calibration circuit for a two-step time-to-digital converter provided in an embodiment of the present invention. The source signal module includes a rising-edge D flip-flop D1 and an inverter I0; wherein...

[0032] The data input of flip-flop D1 is connected to the coarse quantization signal ZC, and the clock input is connected to the master clock signal CLK. <0> So that the coarse quantization signal ZC is synchronized with the master clock signal CLK <0> Perform clock synchronization and output the first timing signal ZC_DTRI through the Q terminal;

[0033] First clock signal CLK <1> The second clock signal CLK is generated by inverter I0. <1> _INV.

[0034] In this embodiment, the first timing signal ZC_DTRI and the first clock signal CLK output by the source signal module are used. <1> Second clock signal CLK <1> The _INV input is sent to the first-level calibration module. After preliminary calibration using two calibration circuits, the second-level calibration module generates a calibration signal. The resulting calibration digital control code can perform operations such as hold, increment, increment, decrement, and decrement on the coarse quantization count value.

[0035] For further details, please continue to see Figure 6 The first correction circuit includes a rising-edge D flip-flop D11 and a double-edge D flip-flop D12; the second correction circuit includes a rising-edge D flip-flop D21 and a double-edge D flip-flop D22.

[0036] The data input of flip-flop D11 is connected to the fine-quantization signal ZF, and the clock input is connected to the first clock signal CLK. <1> So that the fine-quantization signal ZF is synchronized with the first clock signal CLK <1> Perform clock synchronization, and output the second timing signal ZF_DTRI1 to the clock terminal of flip-flop D12 through the Q terminal of flip-flop D11;

[0037] The data terminal of flip-flop D12 is connected to the Q terminal of flip-flop D1, and the Q terminal of flip-flop D12 outputs the first preliminary correction signal N11;

[0038] The data input of flip-flop D21 is connected to the fine-tuning signal ZF, and the clock input is connected to the output of inverter I0, so that the fine-tuning signal ZF is synchronized with the second clock signal CLK. <1> _INV is used for clock synchronization, and the third timing signal ZF_DTRI2 is output from the Q input of flip-flop D21 to the clock input of flip-flop D22;

[0039] The data terminal of flip-flop D22 is connected to the Q terminal of flip-flop D1, and the Q terminal of flip-flop D22 outputs the second preliminary correction signal N21.

[0040] Specifically, the signal generated by the source signal module is transmitted to the first-stage correction module for primary correction. The first clock signal CLK is included in this process. <1> The clock signal ZF_DTRI1 is generated at the clock input of the rising-edge D flip-flop D11, which uses ZF as the data input, in the first calibration circuit. Then, the second timing signal ZF_DTRI1 is input to the clock input of the dual-edge D flip-flop D12, which uses the first timing signal ZC_DTRI as the data input, to generate the first preliminary correction signal N11. Similarly, the second clock signal CLK... <1> The input _INV is fed into the clock terminal of the rising edge D21 of the second correction circuit, which uses ZF as the data terminal, to generate the third timing signal ZF_DTRI2. Then, the third timing signal ZF_DTRI2 is input into the clock terminal of the double-edge D22 of the first timing signal ZC_DTRI, which uses ZC_DTRI as the data terminal, to generate the second preliminary correction signal N21. Finally, the two preliminary correction signals N11 and N21 are input into the second-stage correction module for secondary correction.

[0041] For further details, please continue to see Figure 6 The second-level correction module includes a 2-to-1 selector, two inverters I1 and I2, and two latches L1 and L2;

[0042] The inputs of the 2-to-1 selector are connected to flip-flops D12 respectively. Terminal and flip-flop D22 End; the higher-order F of the quantization result Q The selection terminal of the 2-to-1 selector selects the data trigger D12. The first preliminary correction signal N11 or the trigger D22 output from the terminal. The second preliminary correction signal N21 is output from the terminal, and the calibration signal Mstop is output. <1> ;

[0043] The higher F-order of the quantization result Q It also outputs a calibration signal Mstop via inverter I1. <0> ;

[0044] Calibration signal Mstop <1> and Mstop <0> A set of calibration digital control codes Mstop<1:0> is formed to correct and compensate the coarse quantization count result at the Tstop end of the time signal T;

[0045] The fine-quantization signal ZF is used to generate the inverted signal ZF_INV through inverter I2;

[0046] Latch L1 is connected to the output of a 2-to-1 multiplexer and outputs a calibration signal Mstart based on the control of the fine-quantization signal ZF and its inverted signal ZF_INV. <1> ;

[0047] L2 latches the higher bit F of the fine quantization result.Q Based on the control of the fine-quantization signal ZF and its inverting signal ZF_INV, the calibration signal Mstart is output. <0> ;

[0048] Calibration signal Mstart <1> and Mstart <0> Another set of calibration digital control codes Mstart<1:0> is formed to correct and compensate the coarse quantization count result at the time Tstart end of the time signal T.

[0049] Optionally, in one implementation of the present invention, the latch L1 includes three inverters I3, I4, and I5, a first switch S11, and a second switch S12.

[0050] The input terminal of inverter I3 is connected to the output terminal of a 2-to-1 selector, and the output terminal of inverter I3 is connected to inverters I4 and I5 in sequence through the first switch S11.

[0051] The output of inverter I5 is connected to the common terminal of first switch S11 and inverter I4 via second switch S12;

[0052] The common terminal of inverters I4 and I5 serves as the output of latch L1, outputting the calibration signal Mstart. <1> ;

[0053] Latch L2 includes three inverters I6, I7, and I8, a third switch S21, and a fourth switch S22;

[0054] In this circuit, the input of inverter I6 is connected to the higher bit F of the fine quantization result. Q The output of inverter I6 is connected to inverters I7 and I8 in sequence via the third switch S21;

[0055] The output of inverter I8 is connected to the common terminal of the third switch S21 and inverter I7 via the fourth switch S22;

[0056] The common terminal of inverters I7 and I8 serves as the output of latch L2, outputting the calibration signal Mstart. <0> ;

[0057] The first switch S11, the second switch S12, the third switch S21, and the fourth switch S22 are all controlled by the fine-quantization signal ZF and its inverted signal ZF_INV.

[0058] In this embodiment, inverter I3 in latch L1 and inverter I6 in latch L2 are both time-delay inverters.

[0059] Specifically, due to F QThe ZF edge is at a low level, located at CLK. <0> When the signal is high, the first calibration circuit may experience a ZF edge and the first clock signal CLK. <1> When rising edges are close together, this can cause the D flip-flop D11 to become metastable, resulting in inaccurate output. Similarly, F... Q The ZF edge is at a high level, located at CLK. <0> When the level is low, the second calibration circuit may exhibit a ZF edge and a second clock signal CLK. <1> When the rising edges of _INV are close together, this can cause metastability in the D flip-flop D21, resulting in inaccurate output. To avoid erroneous data caused by the metastability of the D flip-flop on the rising edge of the first-stage correction module, the higher bit F of the finer quantization result is... Q As a 2-to-1 selector, it selects the correct data output. When the ZF edge is at the master clock CLK... <0> High level, the higher bit F of the fine quantization result. Q When the signal is low, the second preliminary correction signal N21 is selected for output. At this time, the ZF edge and CLK are... <1> The _INV edge should be at least Tclk / 4 apart, and the ZC_DTRI and ZF_DTRI2 edges should be at least Tclk / 4 apart to avoid errors caused by the metastability of the D flip-flop. Similarly, when the ZF edge is located at the master clock CLK... <0> Low level, the higher bit F of the fine quantization result. Q When the signal is high, the first preliminary correction signal N11 is selected for output. At this time, the ZF edge and CLK are... <1> The edges must be at least Tclk / 4 apart, and the ZC_DTRI edges and ZF_DTRI1 edges must be at least Tclk / 4 apart to avoid errors caused by metastability of the D flip-flop.

[0060] Therefore, F Q N11 is selected as the selector output signal Mstop for the high level. <1> F Q N21 is selected as the selector output signal Mstop for the low level. <1> F Q The calibration signal Mstop is generated by an inverter. <0> Mstop<1:0> determines the correction and compensation for the coarse quantization count result at the measurement time Tstop end. Since the subsequent calibration and compensation operation is performed after T quantization is completed, the calibration code at the quantization Tstop end will overwrite the calibration code at the Tstart end, so it is necessary to save the calibration code at the Tstart end.

[0061] This invention primarily utilizes a latch with a delay to save the result, specifically by using inverters I3 in latch L1 and I6 in latch L2 as delay inverters. Mstart<1:0> sustains data operations through latches L1 and L2. When ZF changes from low to high, the latch maintains the calibration code at the Tstart terminal and outputs it. Specifically, when ZF is low, switches S11 and S21 are on, and switches S12 and S22 are off, allowing the latch to transmit a signal. When ZF is high, switches S11 and S21 are off, and switches S12 and S22 are on, maintaining the signal output. The latched signal is the calibration code Mstart<1:0> at the Tstart terminal, which determines the correction and compensation of the coarse quantization count result at the Tstart terminal of the time signal. After the entire quantization process is complete, the calibration signals Mstart<1:0> and Mstop<1:0> are transmitted to the coarse quantization unit for calibration and compensation.

[0062] Therefore, this circuit can not only solve the transmission delay error between the ZF signal and the ZC signal, but also avoid the error of repeated counting in the traditional coarse quantization module by using ZC_DTRI and the master clock to AND the signal before transmitting it to the counter.

[0063] Furthermore, after obtaining the two sets of calibration digital control codes Mstop<1:0> and Mstart<1:0>, they can be used to perform a correction operation on the coarse quantization count value, as follows:

[0064] When Mstop<1:0> is 11, the coarse quantization count result at the Tstop terminal is incremented by one; when Mstop<1:0> is 00, the coarse quantization count result at the Tstop terminal is decremented by one; when Mstop<1:0> is 10 or 01, no compensation is performed on the coarse quantization count result at the Tstop terminal.

[0065] When Mstart<1:0> is 11, the coarse quantization count result at Tstart is incremented by one; when Mstop<1:0> is 00, the coarse quantization count result at Tstart is decremented by one; when Mstop<1:0> is 10 or 01, no compensation is applied to the coarse quantization count result at Tstart.

[0066] Where 1 represents a high level and 0 represents a low level;

[0067] The above correction operation is used to compensate for the quantization error at the Tstart and Tstop ends, and the result is accumulated and transmitted to the coarse quantization unit for hold, increment, increment, decrement, and decrement operations.

[0068] Therefore, quantization error compensation at the Tstart and Tstop terminals can be achieved by determining the number of high-level signals present in the calibration signals Mstart<1:0> and Mstart<1:0>. If two high-level signals are present, no compensation is made for the coarse quantization result; if no high-level signals are present but one high-level signal is present, the coarse quantization result is compensated by subtracting two or one; if three or four high-level signals are present, the coarse quantization result is compensated by adding one or two.

[0069] Furthermore, to further illustrate the calibration principle of the calibration circuit provided by this invention, this embodiment also provides calibration timing diagrams for the errors at the Tstart and Tstop terminals, as shown below. Figure 7 and Figure 8 As shown, where, Figure 7 This is a timing diagram of the calibration circuit at the Tstart terminal provided in an embodiment of the present invention. It can be seen that when the falling edge of ZF is located at CLK... <0> When the clock is high, the higher bit F of the fine quantization. Q When the level is low, the second-stage correction module selects the N21 output of the second correction circuit. Assuming Terror1 = τ2 - τ1, through analysis... Figure 7 (a)-7(d) are calibration timing diagrams. The correction circuit proposed in this invention can achieve -Tclk / 2+T SET ——Tclk / 2-T HOLD The error correction is analyzed in detail below:

[0070] like Figure 7 As shown in (a), the falling edge of ZF is located at CLK. <0> When the clock is high, the higher bit F of the fine quantization result. Q The signal is low. When ZC_DTRI toggles to 1 on the rising edge of this clock cycle, the coarse quantization count is increased by 1. When the falling edge of ZF_DTRI2 arrives, the ZC_DTRI signal level is 1, N21 is 0, and F... Q =0. After passing through the two-to-one selector and latch, Mstart<1:0> is 00, which can compensate for the coarse quantization count value by decrementing by one.

[0071] like Figure 7 As shown in (b), the falling edge of ZF is located at CLK. <0> When the clock is high, the higher bit F of the fine quantization result. Q The signal is low. When ZC_DTRI toggles to 1 on the rising edge of the next clock cycle, the coarse quantization count is correct. When the falling edge of ZF_DTRI2 arrives, the ZC_DTRI signal level is 0, N21 is 1, and F... Q =0, after passing through the two-to-one selector and latch, Mstart<1:0> is 10, and no compensation is made for the coarse quantization count value.

[0072] like Figure 7 As shown in (c), the falling edge of ZF is located at CLK. <0> When the clock is low, the higher bit F of the fine quantization result... Q The output is high. When ZC_DTRI toggles to 1 on the rising edge of the next clock cycle, the coarse quantization count is correct. When the falling edge of ZF_DTRI1 arrives, the ZC_DTRI signal level is 1, N21 is 0, and F... Q =1. After passing through the two-to-one selector and latch, Mstart<1:0> is 01, and no compensation is made for the coarse quantization count value.

[0073] like Figure 7 As shown in (d), the falling edge of ZF is located at CLK. <0> When the clock is low, the higher bit F of the fine quantization result... Q The signal is high. When ZC_DTRI toggles to 1 on the rising edge of the second subsequent clock cycle, the coarse quantization count is undercounted by 1. When the falling edge of ZF_DTRI1 arrives, the ZC_DTRI signal level is 0, N21 is 1, and F... Q =1. After passing through the two-to-one selector and latch, Mstart<1:0> becomes 11, and the coarse quantization count value is incremented by one to compensate.

[0074] Figure 8 This is a timing diagram of the calibration circuit at the Tstop terminal provided in an embodiment of the present invention for error calibration. It can be seen that when the rising edge of ZF is located at CLK... <0> When the clock is low, the higher bit F of the fine quantization is... Q When the signal is high, the second-stage correction module selects the N11 output of the first correction circuit. Assuming Terror2 = τ4 - τ3, by analyzing the calibration timing diagrams 8(a)–8(d), the correction circuit proposed in this invention can achieve -Tclk / 2 + T SET ——Tclk / 2-T HOLD The error correction is analyzed in detail below:

[0075] like Figure 8 As shown in (a), the rising edge of ZF is located at CLK. <0> When the clock is high, the higher bit F of the fine quantization result. Q The signal is low. When ZC_DTRI toggles to 0 on the rising edge of this clock cycle, the coarse quantization count is undercounted by 1. When the rising edge of ZF_DTRI2 arrives, the ZC_DTRI signal level is 0, N11 is 1, and F... Q =0, after passing through a 2-to-1 selector, inverter and latch, Mstop<1:0> is 11, and the coarse quantization count value is incremented by one to compensate.

[0076] like Figure 8 As shown in (b), the rising edge of ZF is located at CLK. <0> When the clock is high, the higher bit F of the fine quantization result. QThe signal is low. When ZC_DTRI toggles to 1 on the rising edge of the next clock cycle, the coarse quantization count is correct. When the rising edge of ZF_DTRI2 arrives, the ZC_DTRI signal level is 1, N11 is 0, and F... Q =0. After passing through a 2-to-1 selector, inverter, and latch, Mstop<1:0> is 01, and no compensation is performed on the coarse quantization count value.

[0077] like Figure 8 As shown in (c), the rising edge of ZF is located at CLK. <0> When the clock is low, the higher bit F of the fine quantization result... Q The signal is high. When ZC_DTRI toggles to 1 on the rising edge of the next clock cycle, the coarse quantization count is correct. When the rising edge of ZF_DTRI1 arrives, the ZC_DTRI signal level is 1, N11 is 0, and F... Q =1. After passing through a 2-to-1 selector, inverter, and latch, Mstop<1:0> is 10, and no compensation is performed on the coarse quantization count value.

[0078] like Figure 8 As shown in (d), the rising edge of ZF is located at CLK. <0> When the clock is low, the higher bit F of the fine quantization result... Q The signal is high. When ZC_DTRI toggles to 1 on the rising edge of the second subsequent clock cycle, the coarse quantization count is increased by 1. When the rising edge of ZF_DTRI1 arrives, the ZC_DTRI signal level is 0, N11 is 1, and F... Q =1. After passing through a 2-to-1 selector, inverter, and latch, Mstop<1:0> becomes 00, and the coarse quantization count value is reduced by one to compensate.

[0079] The analysis of the above eight scenarios shows that the correction circuit proposed in this invention not only solves the error caused by repeated counting in traditional coarse quantization modules, but also addresses the transmission delay mismatch error within -Tclk / 2+T. SET To Tclk / 2-T HOLD The two-step TDC within the unit performs correction. When Mstart<1:0> is 11, the coarse quantization count result is incremented by one; when Mstart<1:0> is 00, the coarse quantization count result is decremented by one; when Mstart<1:0> is 10 or 01, no coarse quantization count result is compensated. When Mstart<1:0> is 11, the coarse quantization count result is incremented by one; when Mstop<1:0> is 00, the coarse quantization count result is decremented by one; when Mstop<1:0> is 10 or 01, no coarse quantization count result is compensated. The quantization error compensation results at Tstart and Tstop are accumulated and transmitted to the coarse quantization unit for hold, increment, increment by two, decrement by one, and decrement by two operations.

[0080] After each quantization is completed, a processing circuit can be integrated inside the chip to process the results of the correction circuit.

[0081] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A calibration circuit for a two-step time-to-digital converter, characterized in that, It includes a source signal module, a first-stage correction module, and a second-stage correction module connected in sequence; wherein, The source signal module is based on the coarse quantization signal ZC and the master clock signal CLK from the two-step time-to-digital converter. <0> Generate the first timing signal ZC_DTRI, and according to the first clock signal CLK <1> Generate the second clock signal CLK <1> _INV; The first-stage correction module includes two correction circuits; wherein, the first correction circuit is based on the first clock signal CLK. <1> The first timing signal ZC_DTRI is used for preliminary calibration, and a first preliminary calibration signal N11 is output; the second calibration circuit is based on the second clock signal CLK. <1> _INV and the first timing signal ZC_DTRI are initially corrected, and a second preliminary correction signal N21 is output; The second-level correction module is used to perform secondary correction on the first preliminary correction signal N11 and the second preliminary correction signal N21, and output two sets of calibration digital control codes Mstop<1:0> and Mstart<1:0>, so as to use the calibration digital control codes Mstop<1:0> and Mstart<1:0> to perform correction operation on the coarse quantization count value generated by the coarse quantization signal ZC; The operation of correcting the coarse quantization count value using the calibration digital control codes Mstop<1:0> and Mstart<1:0> includes: When Mstop<1:0> is 11, the coarse quantization count result at the Tstop terminal of the time signal is increased by one; when Mstop<1:0> is 00, the coarse quantization count result at the Tstop terminal of the time signal is decreased by one; when Mstop<1:0> is 10 or 01, no compensation is performed on the coarse quantization count result at the Tstop terminal of the time signal. When Mstart<1:0> is 11, the coarse quantization count result at the Tstart terminal is incremented by one; when Mstop<1:0> is 00, the coarse quantization count result at the Tstart terminal of the time signal is decremented by one; when Mstop<1:0> is 10 or 01, no compensation is performed on the coarse quantization count result at the Tstart terminal of the time signal. Where 1 represents a high level and 0 represents a low level; The above correction operation is used to compensate for the quantization error at the Tstart and Tstop terminals of the time signal, and the result is accumulated and transmitted to the coarse quantization unit for hold, increment, increment, decrement, and decrement operations.

2. The calibration circuit for a two-step time-to-digital converter according to claim 1, characterized in that, The first clock signal CLK <1> Lagging behind the master clock signal CLK <0> 90 degrees.

3. The calibration circuit for a two-step time-to-digital converter according to claim 1, characterized in that, The source signal module includes a rising-edge D flip-flop D1 and an inverter I0; wherein... The data input of the flip-flop D1 is connected to the coarse quantization signal ZC, and the clock input is connected to the main clock signal CLK. <0> So that the coarse quantization signal ZC is synchronized with the master clock signal CLK. <0> Perform clock synchronization and output the first timing signal ZC_DTRI through the Q terminal; First clock signal CLK <1> The inverter I0 generates a second clock signal CLK. <1> _INV.

4. The calibration circuit for a two-step time-to-digital converter according to claim 3, characterized in that, The first correction circuit includes a rising-edge D flip-flop D11 and a double-edge D flip-flop D12; the second correction circuit includes a rising-edge D flip-flop D21 and a double-edge D flip-flop D22; wherein, The data input of the flip-flop D11 is connected to the fine-quantization signal ZF, and the clock input is connected to the first clock signal CLK. <1> So that the fine-quantization signal ZF is synchronized with the first clock signal CLK. <1> Perform clock synchronization, and output the second timing signal ZF_DTRI1 to the clock terminal of the flip-flop D12 through the Q terminal of the flip-flop D11; The data terminal of the flip-flop D12 is connected to the Q terminal of the flip-flop D1, and the data terminal of the flip-flop D12 is connected to the Q terminal of the flip-flop D1. The terminal outputs the first preliminary correction signal N11; The data terminal of the flip-flop D21 is connected to the fine-tuning signal ZF, and the clock terminal is connected to the output of the inverter I0, so that the fine-tuning signal ZF is synchronized with the second clock signal CLK. <1> _INV is used for clock synchronization, and the third timing signal ZF_DTRI2 is output to the clock terminal of the flip-flop D22 through the Q terminal of the flip-flop D21. The data terminal of the flip-flop D22 is connected to the Q terminal of the flip-flop D1, and the data terminal of the flip-flop D22 is connected to the Q terminal of the flip-flop D1. The terminal outputs the second preliminary correction signal N21.

5. The calibration circuit for a two-step time-to-digital converter according to claim 4, characterized in that, The second-stage correction module includes a 2-to-1 selector, two inverters I1 and I2, and two latches L1 and L2; wherein, The input terminals of the two-to-one selector are respectively connected to the flip-flop D12. The terminal and the trigger D22 End; the higher-order F of the quantization result Q The selection terminal of the two-to-one selector is the data trigger D12. The first preliminary correction signal N11 or the trigger D22 output from the terminal. The second preliminary correction signal N21 is output from the terminal, and the calibration signal Mstop is output. <1> ; The higher-order F of the refinement result Q The inverter I1 also outputs a calibration signal Mstop. <0> ; The calibration signal Mstop <1> and Mstop <0> A set of calibration digital control codes Mstop<1:0> is formed to correct and compensate the coarse quantization count result at the Tstop end of the time signal; The refined quantization signal ZF is used to generate the inverted signal ZF_INV through the inverter I2; The latch L1 is connected to the output of the 2-to-1 selector and outputs a calibration signal Mstart based on the control of the fine quantization signal ZF and its inverted signal ZF_INV. <1> ; The latch L2 is connected to the higher bit F of the fine quantization result. Q Based on the control of the fine-quantization signal ZF and its inverting signal ZF_INV, the calibration signal Mstart is output. <0> ; The calibration signal Mstart <1> and Mstart <0> Another set of calibration digital control codes Mstart<1:0> is formed to correct and compensate the coarse quantization count result at the Tstart end of the time signal.

6. The calibration circuit for a two-step time-to-digital converter according to claim 5, characterized in that, When the fine quantization signal ZF is high, the higher bit F of the fine quantization result is... Q If it is low, then use F Q The second preliminary correction signal N21 is selected as the output calibration signal Mstop. <1> ; Accordingly, when the fine quantization signal ZF is low, the higher bit F of the fine quantization result... Q If it is high, then use F Q The first preliminary calibration signal N11 is selected as the output calibration signal Mstop. <1> .

7. The calibration circuit for a two-step time-to-digital converter according to claim 5, characterized in that, The latch L1 includes three inverters I3, I4, and I5, a first switch S11, and a second switch S12. The input terminal of inverter I3 is connected to the output terminal of the two-to-one selector, and the output terminal of inverter I3 is connected to inverters I4 and I5 in sequence through the first switch S11. The output terminal of inverter I5 is connected to the common terminal of the first switch S11 and inverter I4 through the second switch S12; The common terminal of inverters I4 and I5 serves as the output terminal of latch L1, outputting the calibration signal Mstart. <1> ; The latch L2 includes three inverters I6, I7, and I8, a third switch S21, and a fourth switch S22; The input of inverter I6 is connected to the higher bit F of the fine quantization result. Q The output terminal of inverter I6 is connected to inverters I7 and I8 in sequence through the third switch S21; The output terminal of inverter I8 is connected to the common terminal of the third switch S21 and inverter I7 via the fourth switch S22; The common terminal of inverters I7 and I8 serves as the output terminal of latch L2, outputting the calibration signal Mstart. <0> ; The first switch S11, the second switch S12, the third switch S21 and the fourth switch S22 are all controlled by the fine quantization signal ZF and its inverted signal ZF_INV.

8. The calibration circuit for a two-step time-to-digital converter according to claim 7, characterized in that, Both inverters I3 and I6 are time-delay inverters.

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