Semiconductor structure and method of fabricating the same

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductor technology, and aims to solve the technical problem of a large contact resistance between a bit line and a bit line plug. The semiconductor structure comprises a substrate, a first layer structure arranged on the substrate, and a storage unit array. A plurality of word lines are arranged at intervals and extend along a first direction. A plurality of bit lines are arranged at intervals and extend along a second direction. An end of the plurality of bit lines away from the storage unit array forms a step in the first direction, and each bit line is provided with a groove on the surface of the step. The second direction intersects the first direction. A plurality of bit line plugs are arranged at intervals and extend along the first direction. An end of each bit line plug is arranged in the groove of a bit line. By arranging the groove on the surface of the bit line, the contact area of the bit line and the bit line plug is increased, the contact resistance between the bit line and the bit line plug is reduced, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for fabricating the same. Background Technology

[0002] With the development of semiconductor technology, memory, especially dynamic random access memory (DRAM), is widely used in various electronic devices due to its high storage density and fast read / write speed.

[0003] Dynamic random access memory (DRAM) typically includes multiple memory cells. Each memory cell includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line (WL) of the DRAM, and the voltage on the word line controls the transistor's on and off states. One of the transistor's source and drain terminals is electrically connected to the bit line (BL), and the other of the source and drain terminals is electrically connected to the capacitor. Data information is stored or output through the bit line.

[0004] To reduce the size of memory and increase its storage density, capacitors are typically placed horizontally to facilitate the fabrication of capacitors with a larger aspect ratio. Correspondingly, transistors are also placed horizontally, with leads extending from the transistors to bit line plugs for electrical connection to external circuitry. However, the contact resistance between the bit lines and the bit line plugs is relatively high. Summary of the Invention

[0005] In view of the above problems, this disclosure provides a semiconductor structure and a method for fabricating the same, for reducing the contact resistance between bit lines and bit line plugs.

[0006] According to some embodiments, a first aspect of this disclosure provides a semiconductor structure comprising: a substrate on which a first stacked structure is disposed, the first stacked structure including a memory cell array; a plurality of word lines spaced apart and extending along a first direction, the word lines passing through the first stacked structure and electrically connected to the memory cell array; a plurality of bit lines spaced apart and extending along a second direction, the bit lines being disposed beside the first stacked structure and electrically connected to the memory cell array; one end of the plurality of bit lines away from the memory cell array forming a step in the first direction, and each bit line having a groove on the surface of the step, the second direction intersecting the first direction; and a plurality of bit line plugs spaced apart and extending along the first direction, one end of each bit line plug being disposed correspondingly in the groove of one of the bit lines.

[0007] In some possible embodiments, at least one of the multiple bit lines is N-type doped or P-type doped.

[0008] In some possible embodiments, the plurality of said bit line plugs are offset along the second direction.

[0009] In some possible embodiments, the memory cell array includes a plurality of transistors spaced apart along a first direction and spaced apart along a second direction, each transistor extending along a third direction; the third direction is perpendicular to both the first and second directions.

[0010] In some possible embodiments, the transistor includes: a source; a drain, one of the source and the drain being electrically connected to the bit line; a channel, the source, the channel and the drain being arranged sequentially along the third direction; the word line surrounding the channel to form the gate of the transistor; and a dielectric layer disposed between the gate and the channel.

[0011] In some possible embodiments, each of the word lines surrounds a plurality of channels located in the same column along the first direction; the plurality of bit lines are stacked along the first direction and adjacent bit lines are electrically isolated from each other, and each bit line connects to a plurality of drains located in the same row along the second direction.

[0012] In some possible embodiments, the memory cell array further includes a plurality of capacitors, which correspond one-to-one with and are electrically connected to the other of the source and drain terminals of the plurality of transistors.

[0013] In some possible embodiments, the first stacked structure further includes: a plurality of support layers disposed between two adjacent rows of transistors along the first direction; and an isolation layer filling the remaining space of the first stacked structure.

[0014] In some possible embodiments, the support layer is disposed between the sources of two adjacent rows of transistors and between the drains of two adjacent rows of transistors.

[0015] In some possible embodiments, the semiconductor structure further includes: a first insulating layer filled between two adjacent bit lines, a first protective layer covering the bit lines and the first insulating layer, and a second insulating layer filled between two adjacent bit line plugs and covering the first stacked structure; a plurality of spaced word line plugs are disposed in the second insulating layer, and the plurality of word line plugs correspond one-to-one with and are electrically connected to the plurality of word lines.

[0016] The semiconductor structure provided in this disclosure has at least the following advantages:

[0017] The semiconductor structure provided in this disclosure improves the performance of the semiconductor structure by providing a groove on the surface of the bit line and placing one end of the bit line plug in the groove of a bit line. This increases the contact area between the bit line and the bit line plug and reduces the contact resistance between the bit line and the bit line plug.

[0018] According to some embodiments, a second aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0019] A first stacked structure is formed on a substrate, the first stacked structure including a memory cell array;

[0020] Multiple word lines are formed on the substrate at intervals and extending along a first direction. The word lines pass through the first stacked structure and are electrically connected to the memory cell array.

[0021] Multiple bit lines are formed on the substrate at intervals and extending along a second direction. The bit lines are disposed on the side of the first stacked structure and electrically connected to the memory cell array. One end of the multiple bit lines away from the memory cell array forms a step in the first direction, and each bit line has a groove on the surface of the step. The first direction and the second direction intersect each other.

[0022] Multiple bit line plugs are formed at intervals and extend along the first direction, with one end of each bit line plug corresponding to a groove of a bit line.

[0023] In some possible embodiments, a plurality of spaced bit lines extending along a second direction are formed on the substrate. These bit lines are disposed beside the first stacked structure and electrically connected to the memory cell array, including:

[0024] A second stacked structure is formed on the substrate, the second stacked structure being located beside the first stacked structure; the second stacked structure includes a first sacrificial layer and a first active layer alternately disposed in sequence;

[0025] The portion of the first sacrificial layer and the portion of the first active layer that are far from the first stacked structure are removed, and the remaining first active layer forms a step in the first direction to form the bit line;

[0026] Remove the remaining first sacrificial layer.

[0027] In some possible embodiments, after removing the remaining first sacrificial layer, the method further includes:

[0028] The bit line is doped with N-type or P-type doping to reduce its resistance.

[0029] In some possible embodiments, the bit line is made of silicon;

[0030] Performing N-type or P-type doping on the bit line to reduce its resistance includes:

[0031] Under the gas phase conditions of phosphorus oxychloride, phosphorus atoms are doped into the bit line using a thermal diffusion process, and phosphosilicate glass is formed on the surface of the bit line.

[0032] Remove the phosphosilicate glass to expose the doped bit lines.

[0033] In some possible embodiments, the temperature of the thermal diffusion process is 800°C-1000°C;

[0034] The phosphosilicate glass was removed by etching with hydrofluoric acid.

[0035] In some possible embodiments, after forming a plurality of spaced-apart bit line plugs extending along the first direction, with one end of each bit line plug correspondingly disposed in a groove of a bit line, the method further includes:

[0036] A first insulating layer is formed to fill the space between the bit lines, and a first protective layer is formed to cover the bit lines and the first insulating layer.

[0037] A second insulating layer is formed to fill the space between the bit line plugs, and the second insulating layer also covers the first stacked structure;

[0038] A plurality of spaced word line plugs are formed in the second insulating layer, each word line plug being electrically connected to one word line.

[0039] The method for fabricating a semiconductor structure provided in this disclosure has the following advantages:

[0040] The semiconductor structure fabrication method provided in this disclosure increases the contact area between the bit line and the bit line plug by forming a groove on the surface of the bit line and placing one end of the formed bit line plug in the groove of a bit line. This reduces the contact resistance between the bit line and the bit line plug, thereby improving the performance of the semiconductor structure. Furthermore, subsequent vapor-phase doping of the bit line effectively reduces the on-resistance of the bit line, further improving the performance of the semiconductor structure. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a framework diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0043] Figure 2 This is a schematic diagram of the structure at section AA in a semiconductor structure according to an embodiment of the present disclosure;

[0044] Figure 3 This is a schematic diagram of the structure at the BB section in a semiconductor structure according to an embodiment of the present disclosure;

[0045] Figure 4 This is a schematic diagram of the structure at the CC section in a semiconductor structure according to an embodiment of the present disclosure;

[0046] Figure 5 This is another framework diagram of the semiconductor structure in one embodiment of the present disclosure;

[0047] Figure 6 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0048] Figure 7 This is a schematic diagram of the structure at section AA after the formation of the second laminated structure in one embodiment of this disclosure;

[0049] Figure 8 This is a schematic diagram of the structure at the BB section after the formation of the second stacked structure in one embodiment of the present disclosure;

[0050] Figure 9 This is a schematic diagram of the structure at the CC section after the formation of the second stacked structure in one embodiment of the present disclosure;

[0051] Figure 10 This is a schematic diagram of the structure at section AA after the step is formed in one embodiment of the present disclosure;

[0052] Figure 11 This is a schematic diagram of the structure at the CC section after the step is formed in one embodiment of the present disclosure;

[0053] Figure 12 This is a schematic diagram of the structure at section AA after removing the first sacrificial layer in one embodiment of this disclosure;

[0054] Figure 13This is a schematic diagram of the structure at the CC section after removing the first sacrificial layer in one embodiment of this disclosure;

[0055] Figure 14 This is a schematic diagram of the structure at section AA after the groove is formed in one embodiment of the present disclosure;

[0056] Figure 15 This is a schematic diagram of the structure at the CC section after the groove is formed in one embodiment of the present disclosure. Detailed Implementation

[0057] In related technologies, transistors and capacitors are placed horizontally. To connect the transistor to external circuits, a stepped bit line is typically formed at one end of the transistor, and a bit line plug is formed on the stepped bit line to contact it. The bit line and the external circuit are electrically connected through the bit line plug. The extension direction of the bit line and the bit line plug are usually perpendicular. The limited contact area between the bit line and the bit line plug results in a high contact resistance, thus reducing the performance of the semiconductor structure. Furthermore, in stepped bit lines, because each bit line has a horizontal structure and the space between the upper and lower bit lines is filled with insulating material, it is difficult to perform overall doping of the bit line in conventional processes. This leads to high bit line resistance, reduced signal propagation speed, and affects the overall performance of the transistor, thereby reducing the performance of the semiconductor structure.

[0058] In view of this, the present disclosure provides a semiconductor structure and its fabrication method. A groove is formed on the surface of a step on the bit line, and one end of a bit line plug is correspondingly disposed within the groove of one bit line. While maintaining a consistent bit line thickness, this increases the contact area between the bit line and the bit line plug, reducing the contact resistance between them, thereby improving the performance of the semiconductor structure. Furthermore, subsequent etching processes remove the filling structure between the bit lines, leaving them in a suspended state. Vapor phase doping further reduces the resistance of the bit lines themselves, further improving the performance of the semiconductor structure.

[0059] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0060] The first aspect of this disclosure provides a semiconductor structure, which can be a memory device or a non-memory device. The memory device may include Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash memory, Electrically Erasable Programmable Read-Only Memory (EEPROM), Phase Change Random Access Memory (PRAM), or Magnetoresistive Random Access Memory (MRAM). The non-memory device may be a logic device, such as a microprocessor, digital signal processor, or microcontroller, or a similar device. This disclosure uses DRAM as an example for illustration.

[0061] See Figure 1 , Figure 2 , Figure 3 and Figure 4 The semiconductor structure includes a substrate 10, word lines 4, bit lines 1, and bit line plugs 5. The substrate 10 provides a supporting foundation for the structural layers on it. The substrate 10 can be made of semiconductor material, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanide, germanium-on-insulator (GOI), or silicon-on-insulator (SOI).

[0062] A first stacked structure is disposed on the substrate 10. The first stacked structure includes a memory cell array for storing data. Bit line 1 passes through the first stacked structure and is electrically connected to the memory cell array. Word line 4 passes through the first stacked structure and is electrically connected to the memory cell array. Bit line plug 5 is in contact with and electrically connected to bit line 1. Word line 4 is used to control the opening or closing of the memory cell array; bit line 1 is used to write data information to the memory cell array or read data information from the memory cell array; bit line plug 5 is used to electrically connect bit line 1 to peripheral circuitry.

[0063] In some possible embodiments, the memory cell array includes a plurality of transistors 2, which are spaced apart along a first direction and spaced apart along a second direction, with each transistor 2 extending along a third direction; the third direction is perpendicular to both the first and second directions.

[0064] For details, please refer to Figures 1 to 4 The memory cell array includes multiple transistors 2, each extending along a third direction. The multiple transistors 2 are arranged in an array, wherein they are spaced apart not only along a first direction but also along a second direction. The third direction is parallel to the substrate 10, as shown below. Figure 1 The Y direction shown is the first direction, which is perpendicular to the substrate 10, as shown below. Figure 3 The Z-direction shown has the first and second directions intersecting each other, and both the first and second directions are perpendicular to the third direction.

[0065] In some possible examples, the first direction, the second direction, and the third direction are perpendicular to each other; for example, the second direction is as follows: Figure 3 As shown in the X direction, the third direction is as follows Figure 1 The Y direction is shown. This configuration allows for a more compact and optimized arrangement of multiple transistors 2, maximizing the number of transistors 2 and thus increasing the storage density of the memory cell array.

[0066] In some possible embodiments, see Figure 3 and Figure 4 Transistor 2 includes a source, a drain, a channel 21, a dielectric layer 22, and a gate. One of the source and drain is electrically connected to bit line 1; for example, the source is electrically connected to bit line 1. The channel 21 is located between the source and drain, and its two ends are in contact with the source and drain, respectively. The source, channel 21, and drain are arranged sequentially along a third direction. The gate is located on the outer periphery of the channel 21 and is electrically connected to word line 4. A dielectric layer 22 is disposed between the gate and the channel 21.

[0067] In some possible implementations, word lines 4 surround the outer periphery of each channel 21 and are integrally formed along a first direction. Word lines 4 serve as the gate of transistors 2, and a dielectric layer 22 is disposed between word lines 4 and each channel 21; that is, the dielectric layer 22 covers the outer periphery of the channel 21, and the word lines 4 cover the outer periphery of the dielectric layer 22. The word lines 4 can be made of a metal, such as titanium nitride, and the dielectric layer 22 can be made of silicon oxide.

[0068] In the above embodiments, the cross-sectional shape of the channel 21 can be circular, elliptical, square, rectangular, pentagonal, or other shapes, taking a plane perpendicular to the third direction as the cross-section. This disclosure does not limit the cross-sectional shape of the channel 21. The cross-sectional shapes of the channel 21, the source, and the drain can be the same and adapted to maximize the contact area between the channel 21 and the source, and between the channel 21 and the drain.

[0069] from Figure 3 and Figure 4As can be seen from the diagram, transistor 2 is a vertical gate all around (GAA) transistor. A vertical gate all around transistor has a smaller feature size, which effectively increases the integration density of the semiconductor structure while occupying the same substrate area 10. Simultaneously, the gate can control the channel 21 from all four sides, improving the control capability of the channel 21, mitigating the short-channel effect, reducing the operating voltage, and enhancing the performance of the semiconductor structure.

[0070] In some possible embodiments, see Figure 1 and Figure 4 The memory cell array also includes multiple capacitors 3, each capacitor 3 corresponding one-to-one with and electrically connected to the other of the source and drain of multiple transistors 2. The multiple capacitors 3 extend along a third direction and are spaced apart, i.e., the capacitors 3 are horizontally placed on the substrate 10. Each capacitor 3 is electrically connected to one transistor 2. Specifically, one of the source and drain of transistor 2 is connected to bit line 1, and the other of the source and drain is connected to capacitor 3. For example, the source of transistor 2 is electrically connected to bit line 1, and the drain of transistor 2 is electrically connected to capacitor 3.

[0071] In some possible embodiments, see Figure 1 , Figure 3 and Figure 4 The first stacked structure further includes: a plurality of support layers 31, which are disposed between two adjacent rows of transistors 2 along the first direction; and an isolation layer 32, which fills the remaining space of the first stacked structure. The support layers 31 support the transistors 2, preventing them from collapsing and facilitating their stacking in the first direction; the isolation layer 32 electrically isolates the structures in the memory cell array, preventing mutual interference between the structures in the memory cell array.

[0072] Specifically, the support layer 31 is disposed between the sources of two adjacent rows of transistors 2 and between the drains of two adjacent rows of transistors 2. (See also...) Figure 4 A support layer 31 is disposed between the sources of two adjacent rows of transistors 2 along the first direction and between the drains of the two adjacent rows of transistors 2. The support layer 31 disposed in the same layer has a gap along the third direction. The support layer 31 is disposed at both ends of the transistors 2, which can stably support the transistors 2 and facilitate the formation of the channel 21, dielectric layer 22 and gate of the transistors 2. The support layer 31 can be made of silicon oxynitride or silicon nitride, which are relatively hard, not easy to collapse, and not easy to be etched, so as to improve the stability of the first stacked structure.

[0073] Continue reading Figure 1 , Figure 3 and Figure 4The isolation layer 32 fills the remaining space in the first stacked structure; specifically, the isolation layer 32 fills the spaces between the memory cell arrays to provide electrical isolation between the structures within the memory cell arrays. Figure 3 and Figure 4 As shown, an isolation layer 32 is filled between adjacent transistors 2 to prevent mutual interference between the transistors 2. The isolation layer 32 is also filled between adjacent capacitors 3 to prevent mutual interference between the capacitors 3. The isolation layer 32 filled between adjacent transistors 2 and the isolation layer 32 filled between adjacent capacitors 3 can be made of the same or different material. For example, the isolation layer 32 filled between adjacent transistors 2 can be made of silicon oxide, and the isolation layer 32 filled between adjacent capacitors 3 can be made of silicon oxynitride.

[0074] In some possible embodiments, see Figures 1 to 4 In this embodiment of the disclosure, the character line 4 includes multiple lines, and the multiple character lines 4 are along a first direction ( Figure 3 Extending in the Z direction (as shown), and along the second direction ( Figure 3 The spacing is set in the X direction as shown. The above-mentioned isolation layer 32 is filled between adjacent word lines 4 to ensure electrical isolation between adjacent word lines 4 and avoid mutual interference between word lines 4.

[0075] Word lines 4 pass through the first stacked structure and are electrically connected to the memory cell array. Specifically, each word line 4 surrounds multiple channels 21 located in the same column along a first direction, which serve as the gate of transistors 2. Figures 1 to 4 As shown, each word line 4 extends along a first direction and surrounds each channel 21 it passes through, with a dielectric layer 22 filling the space between the word line 4 and the corresponding channel 21. This arrangement optimizes the arrangement of the word lines 4, reduces the space required, and facilitates increasing the number of transistors 2 and capacitors 3 in the memory cell array, thereby improving the storage density of the semiconductor structure.

[0076] In some possible embodiments, see Figures 1 to 4 In this embodiment of the disclosure, bit line 1 includes multiple bit lines 1, which are arranged along a second direction ( Figure 2 Extending along the X direction (as shown), it is along the first direction ( Figure 2 The bit lines 1 are stacked (in the Z direction as shown) and are electrically isolated from each other. Specifically, multiple bit lines 1 are spaced apart along the first direction to ensure electrical isolation between adjacent bit lines 1. Furthermore, a first insulating layer 33 may be filled between adjacent bit lines 1, that is, the bit lines 1 and the first insulating layer 33 are alternately stacked along the first direction. The first insulating layer 33 can not only isolate each bit line 1, but also support each bit line 1, thereby improving the stability of the bit lines 1.

[0077] Bit line 1 is located on the side of the first stacked structure and is electrically connected to the memory cell array. Specifically, for example... Figure 1 and Figure 4 As shown, bit line 1 is located on the left side of the first stacked structure. Each bit line 1 connects to multiple drains located in the same row along the second direction. This arrangement optimizes the arrangement of bit lines 1, reduces space requirements, and facilitates increasing the number of transistors 2 and capacitors 3 in the memory cell array, thereby improving the storage density of the semiconductor structure.

[0078] See Figure 4 The ends of the multiple bit lines 1 furthest from the memory cell array are stepped in a first direction. Specifically, the lengths of the multiple bit lines 1 decrease sequentially in the direction furthest from the substrate 10, so that the multiple bit lines 1 form steps. For each pair of adjacent bit lines 1, a portion of the bit line 1 closer to the substrate 10 is exposed. This portion of the bit line 1 is not blocked by the bit line 1 furthest from the substrate 10, which facilitates the formation of bit line plugs 5 in the exposed portion of the bit line 1, thereby realizing the electrical connection between the bit line 1 and the peripheral circuit.

[0079] Each position line 1 has a groove 23 on the surface of the step. For example... Figure 4 As shown, a step is formed at the left end of multiple bit lines 1, with the step moving upward in a first direction. Each step has a groove 23. Taking the surface perpendicular to the substrate 10 as the cross-section, the cross-sectional shape of the groove 23 can be semi-circular, semi-elliptical, square, or trapezoidal, etc. The cross-sectional shape of the groove 23 is adapted to the cross-sectional shape of the bit line plug 5 so that the bottom wall and side wall of the groove 23 are in contact with the bit line plug 5, thereby increasing the contact area between the groove 23 and the bit line plug 5.

[0080] The bottom dimension of the groove 23 is smaller than the opening dimension of the groove 23 to facilitate the formation of the bit line plug 5 within the groove 23. The bottom of the groove 23 is located within the corresponding bit line 1, and the groove 23 does not penetrate the bit line 1. This configuration results in a larger area of ​​the bit line 1 exposed within the corresponding groove 23. The grooves 23 formed on the surface of the step for each bit line 1 can be identical. This configuration allows multiple grooves 23 to be fabricated simultaneously, simplifying the semiconductor structure fabrication process.

[0081] Continue reading Figure 4 In this embodiment, the bit line plugs 5 include multiple plugs, which extend along a first direction and are spaced apart along a third direction to isolate each plug from the others, thereby preventing interference between bit lines 1. Each bit line plug 5 corresponds one-to-one with and is electrically connected to a plurality of bit lines 1, with one end of each plug 5 disposed within its corresponding groove 23. Specifically, one end of the bit line plug 5 fills the groove 23. This arrangement increases the contact area between the bit line plug 5 and the bit line 1, thereby reducing the contact resistance between the bit line plug 5 and the bit line 1 and improving the performance of the semiconductor structure.

[0082] Among some possible implementations, refer to Figure 1 Multiple bit line plugs 5 are arranged in the same row along the third direction, and the space occupied by the multiple bit line plugs 5 along the second direction is small. See also Figure 4 Along the direction close to transistor 2, the length of multiple bit line plugs 5 gradually decreases so that each bit line plug 5 is flush with the surface of substrate 10, thereby connecting to the peripheral circuit.

[0083] In some other possible implementations, multiple bit line plugs 5 are offset along the second direction. See also Figure 5 The line connecting multiple bit line plugs 5 forms an angle with the second direction. With this arrangement, the distance between adjacent bit line plugs 5 is relatively large, and their mutual interference is relatively small.

[0084] To further improve the performance of the semiconductor structure, at least one of the multiple bit lines 1 in this embodiment is N-type doped or P-type doped. The resistance of the N-type or P-type doped bit line 1 is reduced, thereby reducing the resistance between the bit line plug 5 and the transistor 2. In some possible examples, each bit line 1 is N-type or P-type doped to reduce the resistance of each bit line 1. With this configuration, since the lengths of each bit line 1 are different, reducing the resistance of each bit line 1 can reduce the losses on each bit line 1, making the operating state of each transistor 2 more consistent, reducing the differences between transistors 2, and improving the performance of the semiconductor structure. For example, each bit line 1 is doped with phosphorus atoms, i.e., each bit line 1 is N-type doped.

[0085] In the above embodiments, bit line 1 can be doped using a vapor phase doping process. Since the surface of bit line 1 is exposed, especially the two opposing surfaces of bit line 1 along the first direction, vapor phase doping can simultaneously dope these two surfaces of bit line 1, resulting in deeper doping in bit line 1 and improving the doping efficiency and uniformity of bit line 1.

[0086] Based on an embodiment in which the semiconductor structure includes a first insulating layer 33 filled between two adjacent bit lines 1, the semiconductor structure further includes a first protective layer 34 covering the bit lines 1 and the first insulating layer 33, and a second insulating layer 35 filled between two adjacent bit line plugs 5 and covering the first stacked structure.

[0087] For details, please refer to Figure 4 The first protective layer 34 covers the bit line 1 and the first insulating layer 33, preventing the bit line 1 from being exposed away from the surface of the substrate 10, thus isolating and protecting the bit line 1. The first protective layer 34 is stepped and can be made of silicon nitride or silicon oxynitride. The second insulating layer 35 fills the space between two adjacent bit line plugs 5 to further ensure the insulation performance between the bit line plugs 5. The second insulating layer 35 is made of silicon oxide.

[0088] See Figure 3 The second insulating layer 35 also includes a plurality of spaced-apart word line plugs 6, each corresponding to and electrically connected to a plurality of word lines 4. The word line plugs 6 extend along a first direction and are used to connect the word lines 4 to peripheral circuitry. Each word line 4 has a first surface and a second surface arranged opposite to each other along the first direction. The first surface is the surface of the word line 4 furthest from the substrate 10, and the second surface is the surface of the word line 4 closest to the substrate 10. Each word line plug 6 contacts the first surface of its corresponding word line 4, thereby leading out each word line 4 through different word line plugs 6.

[0089] In summary, the semiconductor structure provided in this embodiment increases the contact area between the bit line 1 and the bit line plug 5 by providing a groove 23 on the surface of the bit line 1 and placing one end of the bit line plug 5 in the groove 23 of a bit line 1, thereby reducing the contact resistance between the bit line 1 and the bit line plug 5 and improving the performance of the semiconductor structure.

[0090] This disclosure also provides a method for fabricating a semiconductor structure, see below. Figure 6 The manufacturing method includes:

[0091] Step S10: Form a first stacked structure on the substrate, the first stacked structure including a memory cell array.

[0092] The substrate 10 can provide a supporting foundation for the structural layers on the substrate 10. The substrate 10 can be made of semiconductor material, such as single-crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanide, germanium-on-insulator, or silicon-on-insulator. A first stacked structure is disposed on the substrate 10, the first stacked structure including a memory cell array, the memory cell array being used to store data.

[0093] In some possible embodiments, see Figures 1 to 5 The memory cell array includes multiple transistors 2, each extending along a third direction. The multiple transistors 2 are arranged in an array; specifically, they are spaced apart not only along a first direction but also along a second direction. The first direction is perpendicular to the substrate 10. Figure 3 The Z-direction shown has the first and second directions intersecting each other, and both the first and second directions are perpendicular to the third direction.

[0094] In some possible examples, the first direction, the second direction, and the third direction are perpendicular to each other; for example, the second direction is as follows: Figure 3 As shown in the X direction, the third direction is as follows Figure 4The Y direction is shown. This configuration allows for a more compact and optimized arrangement of multiple transistors 2, maximizing the number of transistors 2 and thus increasing the storage density of the memory cell array.

[0095] In some possible embodiments, see Figure 3 and Figure 4 The transistor 2 includes a source, a drain, a channel 21, and a gate. The source, channel 21, and drain are arranged sequentially along a third direction. One of the source and drain is electrically connected to the bit line 1. For example, the source is electrically connected to the bit line 1. The gate surrounds the outer periphery of the channel 21 and is electrically connected to the word line 4. A dielectric layer 22 is also disposed between the gate and the channel 21.

[0096] In some possible embodiments, see Figure 1 and Figure 5 The memory cell array also includes multiple capacitors 3, each capacitor 3 corresponding one-to-one with and electrically connected to the other of the source and drain of multiple transistors 2. The multiple capacitors 3 extend along a third direction and are spaced apart, i.e., the capacitors 3 are horizontally placed on the substrate 10. Each capacitor 3 is electrically connected to one transistor 2. Specifically, one of the source and drain of transistor 2 is connected to bit line 1, and the other of the source and drain is connected to capacitor 3. For example, the source of transistor 2 is electrically connected to bit line 1, and the drain of transistor 2 is electrically connected to capacitor 3.

[0097] Step S20: Form multiple word lines spaced apart and extending along a first direction on the substrate. The word lines pass through the first stacked structure and are electrically connected to the memory cell array.

[0098] See Figures 1 to 4 In this embodiment of the disclosure, the character line 4 includes multiple lines, and the multiple character lines 4 are along a first direction ( Figure 3 (as shown) extends along the second direction ( Figure 3 (As shown) The spacing is set. The above-mentioned isolation layer 32 is filled between adjacent word lines 4 to ensure electrical isolation between adjacent word lines 4 and avoid mutual interference between word lines 4.

[0099] Word lines 4 pass through the first stacked structure and are electrically connected to the memory cell array. Specifically, each word line 4 extends along a first direction and surrounds each channel 21 it passes through, with a dielectric layer 22 filling the space between the word line 4 and the corresponding channel 21. This arrangement optimizes the word line arrangement, reduces space requirements, and facilitates increasing the number of transistors 2 and capacitors 3 in the memory cell array, thereby improving the storage density of the semiconductor structure. Furthermore, the word line 4 can also serve as the gate of transistor 2, making transistor 2 a gate all around (GAA) transistor. GAA transistors have smaller feature sizes, effectively increasing the integration density of the semiconductor structure while occupying the same substrate area 10. Simultaneously, the gate can control the channel 21 from all four sides, improving the channel 21 control capability, mitigating short-channel effects, reducing operating voltage, and enhancing the performance of the semiconductor structure.

[0100] In some possible embodiments, see Figure 3 and Figure 4 After forming word line 4, the process also includes forming multiple support layers 31 and isolation layers 32. The support layers 31 are disposed between two adjacent rows of transistors 2 along the first direction, and the isolation layers 32 fill the remaining space of the first stacked structure. The support layers 31 can support the transistors 2, prevent the transistors 2 from collapsing, and facilitate the stacking of transistors 2 in the first direction; the isolation layers 32 can electrically isolate the structures in the memory cell array, avoiding mutual interference between the structures in the memory cell array.

[0101] Specifically, the support layer 31 is formed between the sources of two adjacent rows of transistors 2, and between the drains of two adjacent rows of transistors 2. (See also...) Figure 4 A support layer 31 is disposed between the sources of two adjacent rows of transistors 2 along the first direction and between the drains of the two adjacent rows of transistors 2, and has a gap along the third direction. The support layer 31 is disposed at both ends of the transistors 2, which can stably support the transistors 2 and facilitate the formation of the channel 21 and gate of the transistors 2. The support layer 31 can be made of silicon oxynitride or silicon nitride, which are relatively hard, not easy to collapse, and not easy to be etched, so as to improve the stability of the first stacked structure.

[0102] Continue reading Figure 3 and Figure 4 The isolation layer 32 fills the remaining space in the first stacked structure; specifically, the isolation layer 32 fills the spaces between the memory cell arrays to provide electrical isolation between the structures within the memory cell arrays. Figure 3 and Figure 4As shown, an isolation layer 32 is filled between adjacent transistors 2 to prevent mutual interference between the transistors 2. The isolation layer 32 is also filled between adjacent capacitors 3 to prevent mutual interference between the capacitors 3. The isolation layer 32 filled between adjacent transistors 2 and the isolation layer 32 filled between adjacent capacitors 3 can be made of the same or different material. For example, the isolation layer 32 filled between adjacent transistors 2 can be made of silicon oxide, and the isolation layer 32 filled between adjacent capacitors 3 can be made of silicon oxynitride.

[0103] Step S30: Multiple bit lines are formed on the substrate, spaced apart and extending along the second direction. The bit lines are disposed on the side of the first stacked structure and electrically connected to the memory cell array. A step is formed at the end of the multiple bit lines away from the memory cell array in the first direction, and a groove is provided on the surface of each bit line on the step. The first direction and the second direction intersect each other.

[0104] See Figures 1 to 5 The bit lines 1 comprise multiple lines extending along a second direction and stacked along a first direction, with adjacent bit lines 1 electrically isolated. Specifically, the multiple bit lines 1 are spaced apart along the first direction to ensure electrical isolation between adjacent bit lines 1. The bit lines 1 are located beside the first stacked structure and electrically connected to the memory cell array, with each bit line 1 connected to multiple drains located in the same row along the second direction. This arrangement optimizes the arrangement of the bit lines 1, reduces space requirements, and facilitates increasing the number of transistors 2 and capacitors 3 in the memory cell array, thereby improving the storage density of the semiconductor structure.

[0105] See Figure 4 The ends of the multiple bit lines 1 furthest from the memory cell array are stepped in a first direction. Specifically, the lengths of the multiple bit lines 1 decrease sequentially in the direction furthest from the substrate 10, so that the multiple bit lines 1 form steps. For each pair of adjacent bit lines 1, a portion of the bit line 1 closer to the substrate 10 is exposed. This portion of the bit line 1 is not blocked by the bit line 1 furthest from the substrate 10, which facilitates the formation of bit line plugs 5 in the exposed portion of the bit line 1, thereby realizing the electrical connection between the bit line 1 and the peripheral circuit.

[0106] Each position line 1 has a groove 23 on the surface of the step. For example... Figure 4As shown, steps are formed at the left ends of multiple bit lines 1, with each step extending upwards in a first direction. Each step has a groove 23. Taking the surface perpendicular to the substrate 10 as a cross-section, the cross-sectional shape of the groove 23 can be semi-circular, semi-elliptical, square, or trapezoidal. The cross-sectional shape of the groove 23 is adapted to the cross-sectional shape of the bit line plug 5, so that the bottom and side walls of the groove 23 are in contact with the bit line plug 5, increasing the contact area between the groove 23 and the bit line plug 5. The bottom dimension of the groove 23 is smaller than the opening dimension of the groove 23 to facilitate the subsequent formation of the bit line plug 5 within the groove 23. The bottom of the groove 23 is located within the corresponding bit line 1, and the groove 23 does not penetrate the bit line 1. This configuration results in a larger area of ​​the bit line 1 exposed within the corresponding groove 23. The grooves 23 formed on the surface of each bit line 1 on the step can be identical. This configuration allows multiple grooves 23 to be fabricated simultaneously, simplifying the semiconductor structure fabrication process.

[0107] See also some possible implementations. Figures 7 to 15 Multiple bit lines 1 are formed on the substrate 10, spaced apart and extending along a second direction. The bit lines 1 are disposed beside the first stacked structure and electrically connected to the memory cell array, including:

[0108] Step S31: A second stacked structure is formed on the substrate, the second stacked structure being located beside the first stacked structure; the second stacked structure includes a first sacrificial layer and a first active layer alternately disposed in sequence.

[0109] See Figures 7 to 9 The second stacked structure 40 includes multiple first sacrificial layers 41 and multiple first active layers 42, which are alternately stacked along a first direction. The first direction is perpendicular to the substrate 10. Along this first direction, a first active layer 42 is disposed between two adjacent first sacrificial layers 41, or a first sacrificial layer 41 is disposed between two adjacent first active layers 42, such that the first sacrificial layers 41 and the first active layers 42 are alternately disposed. This arrangement allows the first sacrificial layers 41 to isolate adjacent first active layers 42, facilitating electrical isolation of the first active layers 42 along the first direction. The first active layers 42 are made of silicon, and the first sacrificial layers 41 are made of silicon germanide.

[0110] Specifically, a first active layer 42 and a first sacrificial layer 41 are sequentially and alternately formed on the substrate 10 until the second stacked structure 40 is formed. For example, when forming the second stacked structure 40, a first active layer 42 is formed on the substrate 10, then a first sacrificial layer 41 is formed on the first active layer 42, and then a first active layer 42 is formed on the first sacrificial layer 41. The formation process of the first active layer 42 and the first sacrificial layer 41 is repeated until the required number of first sacrificial layers 41 are formed.

[0111] In some possible implementations, the first sacrificial layer 41 and the first active layer 42 can be formed by a deposition process, which may include chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In other possible implementations, the first sacrificial layer 41 and the first active layer 42 can also be formed by an epitaxy (EPI) process.

[0112] Step S32: Remove a portion of the first sacrificial layer and a portion of the first active layer that are far from the first stacked structure, and form a step in the remaining first active layer in the first direction to form a bit line.

[0113] See Figures 7 to 11 In some possible embodiments, a first mask layer 60 is formed on the second stacked structure 40, and the size of the first mask layer 60 is gradually reduced to etch the first sacrificial layer 41 and the first active layer 42, so that the first active layer 42 forms a step.

[0114] Specifically, in some possible examples, a first mask layer 60 is first formed on the first stacked structure and the second stacked structure 40. The first mask layer 60 is formed on the second stacked structure 40 with the desired pattern. The exposed portion of the second stacked structure 40 is etched down to the bottommost first sacrificial layer 41 and the first active layer 42 using the first mask layer 60 as a mask, so that the bottommost first active layer 42 forms bit line 1. Then, the portion of the first mask layer 60 away from the first stacked structure is removed. Using the removed first mask layer 60 as a mask, the second-to-last first sacrificial layer 41 and the first active layer 42 are etched down to the second-to-last first active layer 42, so that the second-to-last first active layer 42 forms bit line 1; ...; and so on, until the topmost first active layer 42 forms bit line 1. Here, the bottommost layer refers to the layer of the first active layer 42 / first sacrificial layer 41 that is closest to the substrate 10, and the topmost layer refers to the layer of the first active layer 42 / first sacrificial layer 41 that is furthest from the substrate 10.

[0115] Of course, in other examples, a first mask layer 60 is formed on the first stacked structure and the second stacked structure 40. The first mask layer 60 is formed on the second stacked structure 40 with the desired pattern. The exposed portion of the second stacked structure 40, using the first mask layer 60 as a mask, may not be etched to the bottommost first sacrificial layer 41 and the first active layer 42, but rather to the penultimate first sacrificial layer 41 and the first active layer 42. That is, the bottommost first sacrificial layer 41 and the first active layer 42 are still a whole layer structure. The bottommost first sacrificial layer 41 forms bit line 1. The subsequent process is similar to the above example and will not be repeated here.

[0116] Specifically, in some other possible embodiments, a first mask layer 60 may be formed on the first stacked structure and the second stacked structure 40, and the first mask layer 60 with the desired pattern may be formed on the second stacked structure 40, the exposed portion of which is the second stacked structure 40; using the first mask layer 60 as a mask, the topmost first sacrificial layer 41 and the first active layer 42 are etched; the portion of the first mask layer 60 away from the first stacked structure is removed to confine the first mask layer 60; using the confinement of the first mask layer 60 as a mask, the first sacrificial layer 41 and the first active layer 42 are etched from the topmost first sacrificial layer 41 and the first active layer 42 to the next topmost first sacrificial layer 41 and the first active layer 42; the confinement of the first mask layer 60 and the etching process of the first sacrificial layer 41 and the first active layer 42 are repeated until the first sacrificial layer 41 and the first active layer 42 are etched from the topmost first sacrificial layer 41 and the first active layer 42 to the bottommost first sacrificial layer 41 and the first active layer 42, at which point each first active layer 42 forms a bit line 1. In the above manufacturing process, the etching depth can be the same each time, and each etching removes the same thickness of the first sacrificial layer 41 and the first active layer 42, which facilitates the formation of steps.

[0117] It should be noted that, for reference Figure 14 and Figure 15 After removing a portion of the first sacrificial layer 41 and a portion of the first active layer 42 that are far from the first stacked structure, the remaining first active layer 42 forms a step in the first direction to form bit lines 1. Then, each bit line 1 is etched to form a groove 23 on the surface of the step.

[0118] It should be noted that forming the first mask layer 60 on the first and second stacked structures 40 includes first forming the second protective layer 50 on the first and second stacked structures 40, and then forming the first mask layer 60 on the second protective layer 50. The second protective layer 50 is made of a harder material. When etching the second stacked structure 40, the pattern on the first mask layer 60 is first transferred to the second protective layer 50. The patterned second protective layer 50 can better ensure the accuracy of the transferred pattern in the subsequent etching process. Then, etching the second stacked structure 40 with the patterned second protective layer 50 can improve the consistency between the pattern formed in the second stacked structure 40 and the pattern in the first mask layer 60, thereby improving the precision of the semiconductor structure.

[0119] Step S31: Remove the remaining first sacrificial layer.

[0120] See Figures 10 to 13 After bit line 1 is formed, the remaining first sacrificial layer 41 is removed to expose each bit line 1. Specifically, the two surfaces of bit line 1 opposite each other along the first direction, as well as the surface away from the first stacked structure, are exposed. Bit line 1 has more exposed surfaces to facilitate subsequent doping of bit line 1.

[0121] In some possible embodiments, after removing the remaining first sacrificial layer 41, the method further includes: N-type doping or P-type doping of bit line 1 to reduce the resistance of bit line 1.

[0122] Specifically, bit line 1 is made of silicon. It undergoes N-type or P-type doping to reduce its resistance. This process includes: doping bit line 1 with phosphorus atoms using a thermal diffusion process under phosphorus oxychloride (POCl3) vapor conditions, forming a phosphosilicate glass (PSG) on the surface of bit line 1; then removing the PSG to expose the doped bit line 1. Because the surface of bit line 1 is exposed, especially the two opposing surfaces along the first direction, vapor-phase doping allows for simultaneous doping of both surfaces compared to ion doping or solid-phase doping, resulting in deeper doping and improved doping efficiency and uniformity. The thermal diffusion process is conducted at 800℃-1000℃. After the thermal diffusion process, the surface of bit line 1 is covered with PSG, which can then be removed using hydrofluoric acid etching.

[0123] Step S40: Form a plurality of spaced bit line plugs that extend along a first direction, with one end of each bit line plug corresponding to a groove in a bit line.

[0124] See Figure 14 , Figure 15 , Figure 2 , Figure 3 and Figure 4The bit line plugs 5 include multiple plugs, which extend along a first direction and are spaced apart along a third direction to isolate each plug from the others, thereby preventing interference between bit lines 1. Each bit line plug 5 corresponds one-to-one with and is electrically connected to a plurality of bit lines 1, with one end of each plug 5 disposed within its corresponding groove 23. Specifically, one end of the bit line plug 5 fills the groove 23. This arrangement increases the contact area between the bit line plug 5 and the bit line 1 while maintaining a consistent overall thickness of the bit lines 1, thereby reducing the contact resistance between the bit line plug 5 and the bit line 1 and improving the performance of the semiconductor structure.

[0125] Among some possible implementations, refer to Figure 1 Multiple bit line plugs 5 are arranged in the same row along the third direction, and the space occupied by the multiple bit line plugs 5 along the second direction is small. See also Figure 4 Along the direction close to transistor 2, the length of multiple bit line plugs 5 gradually decreases so that each bit line plug 5 is flush with the surface of substrate 10, thereby connecting to the peripheral circuit.

[0126] In some other possible implementations, multiple bit line plugs 5 are offset along the second direction. See also Figure 5 The line connecting multiple bit line plugs 5 forms an angle with the second direction. With this arrangement, the distance between adjacent bit line plugs 5 is relatively large, and their mutual interference is relatively small.

[0127] In some possible embodiments, a plurality of spaced-apart bit line plugs 5 extending along a first direction are formed, with one end of each bit line plug 5 correspondingly disposed within a groove 23 of a bit line 1, and the method further includes:

[0128] A first insulating layer 33 is formed between the bit lines 1, and a first protective layer 34 is formed covering the bit lines 1 and the first insulating layer 33; a second insulating layer 35 is formed between the bit line plugs 5, and the second insulating layer 35 also covers the first stacked structure; a plurality of spaced word line plugs 6 are formed in the second insulating layer 35, and each word line plug 6 is electrically connected to a word line 4.

[0129] For details, please refer to Figure 4 The first protective layer 34 covers the bit line 1 and the first insulating layer 33, preventing the bit line 1 from being exposed away from the surface of the substrate 10, thus isolating and protecting the bit line 1. The first protective layer 34 is stepped and can be made of silicon nitride or silicon oxynitride. The second insulating layer 35 fills the space between two adjacent bit line plugs 5 to further ensure the insulation performance between the bit line plugs 5. The first insulating layer 33 and the second insulating layer 35 are made of silicon oxide.

[0130] The second insulating layer 35 also includes a plurality of spaced-apart word line plugs 6, each corresponding to and electrically connected to a plurality of word lines 4. The word line plugs 6 extend along a first direction and are used to connect the word lines 4 to peripheral circuitry. Each word line 4 has a first surface and a second surface arranged opposite to each other along the first direction. The first surface is the surface of the word line 4 furthest from the substrate 10, and the second surface is the surface of the word line 4 closest to the substrate 10. Each word line plug 6 contacts the first surface of its corresponding word line 4, thereby leading out each word line 4 through different word line plugs 6.

[0131] In summary, the semiconductor structure fabrication method provided in this disclosure increases the contact area between the bit line 1 and the bit line plug 5 by forming a groove 23 on the surface of the bit line 1 and correspondingly placing one end of the formed bit line plug 5 within the groove 23 of one bit line 1, while maintaining a consistent overall thickness of the bit line 1. This reduces the contact resistance between the bit line 1 and the bit line plug 5, thereby improving the performance of the semiconductor structure. Furthermore, subsequent vapor-phase doping of the bit line 1 effectively reduces the on-resistance of the bit line 1, further improving the performance of the semiconductor structure.

[0132] The embodiments or implementation methods described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, wherein a first stacked structure is disposed on the substrate, the first stacked structure including a memory cell array; Multiple word lines are spaced apart and extend along a first direction, the word lines passing through the first stacked structure and electrically connected to the memory cell array; Multiple spaced bit lines extending along a second direction are provided, the bit lines being disposed on the side of the first stacked structure and electrically connected to the memory cell array; One end of each of the bit lines away from the memory cell array forms a step in the first direction, and each bit line has a groove on the surface of the step; the second direction intersects the first direction. Multiple bit line plugs are spaced apart and extend along the first direction, with one end of each bit line plug correspondingly disposed in the groove of a bit line; The memory cell array includes multiple transistors, each transistor including a source; The drain, one of the source and the drain, is electrically connected to the bit line; The plurality of transistors are arranged at intervals along the first direction and at intervals along the second direction, and each transistor extends along a third direction; The third direction is perpendicular to both the first direction and the second direction; Multiple support layers are disposed between two adjacent rows of transistors along the first direction; The bit line and one of the source and drain electrodes connected to it are integrally formed.

2. The semiconductor structure according to claim 1, characterized in that, At least one of the multiple bit lines is N-type doped or P-type doped.

3. The semiconductor structure according to claim 1, characterized in that, The plurality of bit line plugs are staggered along the second direction.

4. The semiconductor structure according to claim 1, characterized in that, The transistor also includes: The source, the channel, and the drain are arranged sequentially along the third direction; The word line surrounds the channel to form the gate of the transistor; A dielectric layer disposed between the gate and the channel.

5. The semiconductor structure according to claim 4, characterized in that, Each of the word lines surrounds a plurality of the channels located in the same column along the first direction; Multiple bit lines are stacked along the first direction and adjacent bit lines are electrically isolated from each other. Each bit line connects to multiple drains located in the same row along the second direction.

6. The semiconductor structure according to claim 4, characterized in that, The memory cell array also includes a plurality of capacitors, each of which corresponds to and is electrically connected to the other of the source and drain terminals of the plurality of transistors.

7. The semiconductor structure according to any one of claims 4-6, characterized in that, The first stacked structure further includes: An isolation layer that fills the remaining space in the first stacked structure.

8. The semiconductor structure according to claim 7, characterized in that, The support layer is disposed between the sources of two adjacent rows of transistors and between the drains of two adjacent rows of transistors.

9. The semiconductor structure according to any one of claims 1-6, characterized in that, The semiconductor structure further includes: a first insulating layer filled between two adjacent bit lines, a first protective layer covering the bit lines and the first insulating layer, and a second insulating layer filled between two adjacent bit line plugs and covering the first stacked structure. The second insulating layer is provided with a plurality of spaced word line plugs, and the plurality of word line plugs correspond one-to-one with the plurality of word lines and are electrically connected.

10. A method for fabricating a semiconductor structure, characterized in that, include: A first stacked structure is formed on a substrate, the first stacked structure including a memory cell array; Multiple word lines are formed on the substrate at intervals and extending along a first direction. The word lines pass through the first stacked structure and are electrically connected to the memory cell array. Multiple bit lines are formed on the substrate at intervals and extending along a second direction. The bit lines are disposed on the side of the first stacked structure and electrically connected to the memory cell array. One end of the multiple bit lines away from the memory cell array forms a step in the first direction, and each bit line has a groove on the surface of the step. The first direction and the second direction intersect each other. Multiple bit line plugs are formed at intervals and extend along the first direction, with one end of each bit line plug correspondingly disposed in the groove of a bit line; The method includes forming multiple spaced bit lines extending along a second direction on the substrate. These bit lines are disposed beside the first stacked structure and electrically connected to the memory cell array, including: A second stacked structure is formed on the substrate, the second stacked structure being located beside the first stacked structure; the second stacked structure includes a first sacrificial layer and a first active layer alternately disposed in sequence; The portion of the first sacrificial layer and the portion of the first active layer that are far from the first stacked structure are removed, and the remaining first active layer forms a step in the first direction to form the bit line; Remove the remaining first sacrificial layer; The memory cell array includes multiple transistors, each transistor including a source. The drain, one of the source and the drain, is electrically connected to the bit line; the first stacked structure further includes a plurality of support layers formed between two adjacent rows of transistors along the first direction; The bit line and one of the source and drain electrodes connected to it are integrally formed.

11. The manufacturing method according to claim 10, characterized in that, After removing the remaining first sacrificial layer, the process further includes: The bit line is doped with N-type or P-type doping to reduce its resistance.

12. The manufacturing method according to claim 11, characterized in that, The bit line is made of silicon; Performing N-type or P-type doping on the bit line to reduce its resistance includes: Under the gas phase conditions of phosphorus oxychloride, phosphorus atoms are doped into the bit line using a thermal diffusion process, and phosphosilicate glass is formed on the surface of the bit line. Remove the phosphosilicate glass to expose the doped bit lines.

13. The manufacturing method according to claim 12, characterized in that, The temperature of the thermal diffusion process is 800℃-1000℃; The phosphosilicate glass was removed by etching with hydrofluoric acid.

14. The manufacturing method according to claim 10, characterized in that, After forming a plurality of spaced bit line plugs extending along the first direction, with one end of each bit line plug correspondingly disposed in a groove of a bit line, the method further includes: A first insulating layer is formed to fill the space between the bit lines, and a first protective layer is formed to cover the bit lines and the first insulating layer. A second insulating layer is formed to fill the space between the bit line plugs, and the second insulating layer also covers the first stacked structure; A plurality of spaced word line plugs are formed in the second insulating layer, each word line plug being electrically connected to one word line.

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