Semiconductor structure and fabrication method therefor, and electronic device
By employing a word line structure with alternating conductive patterns of different resistivity in DRAM, the problem of high word line resistance in vertical transistor structures is solved, thus improving device performance.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- RUILI INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2025-08-15
- Publication Date
- 2026-05-15
AI Technical Summary
In existing dynamic random access memory (DRAM), the word line resistance of the vertical transistor structure is relatively large, which affects the device performance.
The word lines are formed by alternating first conductive patterns with relatively high resistivity and second conductive patterns with relatively low resistivity, thereby reducing the resistance of the word lines.
By using conductive materials with different resistivity to form word lines, the resistance of the word lines is reduced, thus improving device performance.
Smart Images
Figure CN2025114925_15052026_PF_FP_ABST
Abstract
Description
Semiconductor structure and its manufacturing method, electronic equipment
[0001] This application claims priority to Chinese Patent Application No. 202411596586.2, filed on November 8, 2024, entitled "Semiconductor Structure and Manufacturing Method Thereof, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field
[0002] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure, a method for manufacturing the same, and an electronic device. Background Technology
[0003] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared to static memory (SRAM), DRAM has advantages such as simpler structure, lower manufacturing cost, and higher storage density. With technological advancements, DRAM applications are becoming increasingly widespread. DRAM consists of multiple memory cells, each including a transistor and a capacitor coupled to the transistor. One of the transistor's source and drain is connected to a bit line, the other is connected to a capacitor, and the transistor's gate is connected to a word line. Under the control of the word line, the transistor writes data to or reads data from the capacitor via the bit line.
[0004] With the development of semiconductor technology, an architectural scheme has been proposed to replace planar transistors or buried transistors in DRAM with vertical transistors (whose channels extend at least partially in a vertical direction). In this architecture, vertically extending active pillars are formed on the substrate, and gates are formed on the sidewalls of the active pillars. Summary of the Invention
[0005] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: an active pillar extending in a vertical direction; a word line extending in a first horizontal direction and coupled to the active pillar to form a transistor; and a bit line extending in a second horizontal direction and coupled to the active pillar, wherein the second horizontal direction intersects the first horizontal direction; wherein the word line includes a first conductive pattern and a second conductive pattern interconnected thereto, the first conductive pattern having a first hole and a second hole alternately arranged in the first horizontal direction, the active pillar being located in the first hole, the second conductive pattern being located in the second hole, and the resistivity of the second conductive pattern being less than the resistivity of the first conductive pattern.
[0006] In some embodiments, the first hole is surrounded by a first extension and a second extension of the first conductive pattern, the first extension extending along the first horizontal direction, the second extension extending along the second horizontal direction, and the width of the second extension being greater than 1 / 2 of the width of the first extension.
[0007] In some embodiments, the width of the second extension is smaller than the width of the first extension.
[0008] In some embodiments, the second hole is formed by a third extension of the first conductive pattern and the second extension, the third extension extending along the first horizontal direction, and the width of the third extension being equal to the width of the second extension.
[0009] In some embodiments, the first hole is a through hole, and the second hole is a through hole.
[0010] In some embodiments, the first hole is a through hole and the second hole is a blind hole.
[0011] In some embodiments, the gap-filling ability of the material of the first conductive pattern is stronger than that of the material of the second conductive pattern.
[0012] In some embodiments, the material of the first conductive pattern includes titanium nitride, and the material of the second conductive pattern includes molybdenum or tungsten.
[0013] In some embodiments, the semiconductor structure further includes a data storage element coupled to a transistor.
[0014] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing a semiconductor substrate; etching the semiconductor substrate to form active pillars extending in a vertical direction; forming word lines, wherein the word lines extend in a first horizontal direction and are coupled to the active pillars; forming bit lines, wherein the bit lines extend in a second horizontal direction and are coupled to the active pillars, the second horizontal direction intersecting the first horizontal direction; wherein the word lines include a first conductive pattern and a second conductive pattern, the first conductive pattern having first holes and second holes alternately arranged in the first horizontal direction, the active pillars being located in the first holes, the second conductive pattern being located in the second holes, and the resistivity of the second conductive pattern being less than the resistivity of the first conductive pattern.
[0015] In some embodiments, the first hole is surrounded by a first extension and a second extension of the first conductive pattern, the first extension extending along the first horizontal direction, the second extension extending along the second horizontal direction, and the width of the second extension being greater than 1 / 2 of the width of the first extension.
[0016] In some embodiments, the width of the second extension is smaller than the width of the first extension.
[0017] In some embodiments, the second hole is formed by a third extension of the first conductive pattern and the second extension, the third extension extending along the first horizontal direction, and the width of the third extension being equal to the width of the second extension.
[0018] In some embodiments, the first hole is a through hole, and the second hole is a through hole.
[0019] In some embodiments, the first hole is a through hole and the second hole is a blind hole.
[0020] In some embodiments, the gap-filling ability of the material of the first conductive pattern is stronger than that of the material of the second conductive pattern.
[0021] In some embodiments, the material of the first conductive pattern includes titanium nitride, and the material of the second conductive pattern includes molybdenum or tungsten.
[0022] In some embodiments, the manufacturing method further includes forming a data storage element, wherein the data storage element is coupled to the active pillar.
[0023] According to a third aspect of the present disclosure, an electronic device is provided, including a processor and a memory provided in any embodiment of the present disclosure. The memory is coupled to the processor.
[0024] In the semiconductor structure provided in the embodiments of this disclosure, the word line is composed of a first conductive pattern with relatively high resistivity and a second conductive pattern with relatively low resistivity, which helps to reduce word line resistance and improve device performance. Attached Figure Description
[0025] Figure 1A is a partial planar structural schematic diagram of a semiconductor structure provided in some embodiments of this disclosure;
[0026] Figure 1B is a planar structural schematic diagram of the first conductive pattern in the word line of a semiconductor structure provided in some embodiments of this disclosure;
[0027] Figure 1C is a schematic diagram of a partial cross-sectional structure taken along line A1-A2 in Figure 1A, according to some embodiments of the present disclosure;
[0028] Figure 1D is a schematic diagram of a partial cross-sectional structure taken along line A1-A2 in Figure 1A, according to some embodiments of the present disclosure;
[0029] Figure 1E is a schematic diagram of a partial cross-sectional structure taken along line B1-B2 in Figure 1A according to some embodiments of the present disclosure;
[0030] Figure 2 is a schematic flowchart of a semiconductor structure manufacturing method provided in some embodiments of this disclosure;
[0031] Figures 3A-3D are schematic cross-sectional views of certain stages of a semiconductor structure manufacturing method according to some embodiments of this disclosure;
[0032] Figure 4 is a schematic block diagram of the structure of an electronic device provided in some embodiments of this disclosure. Detailed Implementation
[0033] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.
[0034] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0035] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0036] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0037] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.
[0038] In embodiments of this disclosure, the term "coupling" refers to the operative connection of two (or more) conductive structures to each other. Depending on actual needs, this may include, but is not limited to, the following: 1) two conductive structures are directly electrically connected; 2) two conductive structures are indirectly electrically connected (through other conductive structures); 3) although two conductive structures are not electrically connected (e.g., an insulating layer is provided between them), one of the two conductive structures can control the electrical performance of the other two conductive structures in response to an electrical signal, for example, a gate (or word line) is coupled to an active region (or channel region).
[0039] It should be noted that the technical solutions and technical features described in the embodiments of this disclosure can be combined arbitrarily without conflict.
[0040] This disclosure provides at least some embodiments of a semiconductor structure comprising: an active pillar extending in a vertical direction; a word line extending in a first horizontal direction and coupled to the active pillar to form a transistor; and a bit line extending in a second horizontal direction and coupled to the active pillar, wherein the second horizontal direction intersects the first horizontal direction; wherein the word line includes a first conductive pattern and a second conductive pattern, the first conductive pattern having a first hole and a second hole alternately arranged in the first horizontal direction, the active pillar being located in the first hole, the second conductive pattern being located in the second hole, and the resistivity of the second conductive pattern being less than the resistivity of the first conductive pattern.
[0041] In the semiconductor structure provided in the embodiments of this disclosure, the word line is composed of a first conductive pattern with relatively high resistivity and a second conductive pattern with relatively low resistivity, which helps to reduce word line resistance and improve device performance.
[0042] The semiconductor structure provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0043] Figure 1A is a partial planar structural schematic diagram of a semiconductor structure according to some embodiments of the present disclosure; Figure 1B is a planar structural schematic diagram of the first conductive pattern in the word line of a semiconductor structure according to some embodiments of the present disclosure; Figure 1C is a partial cross-sectional structural schematic diagram taken along line A1-A2 in Figure 1A according to some embodiments of the present disclosure; Figure 1D is another partial cross-sectional structural schematic diagram taken along line A1-A2 in Figure 1A according to some embodiments of the present disclosure; and Figure 1E is a partial cross-sectional structural schematic diagram taken along line B1-B2 in Figure 1A according to some embodiments of the present disclosure. It should be noted that, for clarity and brevity, some insulating layers and / or dielectric layers are omitted in Figures 1A, 1C, to 1E.
[0044] As shown in Figures 1A to 1E, the semiconductor structure includes an active pillar 110, a word line 120, and a bit line 140. The active pillar 110 extends along a vertical direction Z; the word line 120 extends along a first horizontal direction X and is coupled to the active pillar 120 to form a transistor; the bit line 140 extends along a second horizontal direction Y and is coupled to the active pillar 120. The second horizontal direction Y intersects the first horizontal direction X. For example, in some examples, the second horizontal direction Y may be perpendicular to the first horizontal direction X.
[0045] As shown in Figures 1A to 1E, the word line 120 includes interconnected first conductive patterns 121 and second conductive patterns 122. The first conductive pattern 121 has a first hole H1 and a second hole H2 arranged alternately along a first horizontal direction X. The active post 110 is located in the first hole H1, and the second conductive pattern 122 is located in the second hole H2. For example, as shown in Figure 1B, each word line 120 may include one first conductive pattern 121 and multiple second conductive patterns 122.
[0046] The resistivity of the second conductive pattern 122 is less than that of the first conductive pattern 121. Compared to the case where word lines are made of the same material with relatively high resistivity, the semiconductor structure provided in the embodiments of this disclosure uses two materials with different resistivities to form the word lines 120, thereby reducing the resistance of the word lines 120.
[0047] For example, as shown in Figures 1A to 1E, the first hole H1 can be formed by the first extension E1 and the second extension E2 of the first conductive pattern 121, and the second hole H2 can be formed by the third extension E3 and the second extension E2 of the first conductive pattern 121. The first extension E1 extends along the first horizontal direction X, the second extension E2 extends along the second horizontal direction Y, and the third extension E3 extends along the first horizontal direction X.
[0048] For example, as shown in Figures 1A to 1E, the width W2 of the second extension E2 can be greater than 1 / 2 of the width W1 of the first extension E1.
[0049] For example, as shown in Figures 1A to 1E, the width W3 of the third extension E3 can be equal to the width W2 of the second extension E2.
[0050] In the embodiments of this disclosure, the width W1 of the first extension E1 refers to the dimension of the first extension E1 in the horizontal direction perpendicular to the second horizontal direction Y; the width W2 of the second extension E2 refers to the dimension of the second extension E2 in the horizontal direction perpendicular to the first horizontal direction X; and the width W3 of the third extension E3 refers to the dimension of the third extension E3 in the horizontal direction perpendicular to the second horizontal direction Y. When the second horizontal direction Y is perpendicular to the first horizontal direction X, the horizontal direction perpendicular to the first horizontal direction X is the second horizontal direction Y, and the horizontal direction perpendicular to the second horizontal direction Y is the first horizontal direction X.
[0051] For example, in some examples, as shown in Figures 1A to 1E, the width W2 of the second extension E2 may be smaller than the width W1 of the first extension E1, thereby helping to increase the proportion of the second conductive pattern 122 with relatively low resistivity in the word line 120, which helps to further reduce the resistance of the word line 120. For example, in other examples, the width W2 of the second extension E2 may also be greater than or equal to the width W1 of the first extension E1.
[0052] It should be noted that the embodiments of this disclosure do not limit the height of the first extension E1, the second extension E2, and the third extension E3. In the embodiments of this disclosure, the height of the first extension E1 refers to its dimension in the vertical direction Z, the height of the second extension E2 refers to its dimension in the vertical direction Z, and the height of the third extension E3 refers to its dimension in the vertical direction Z.
[0053] For example, as shown in Figures 1A to 1E, the first hole H1 is a through hole, and the active post 110 extends through the first hole H1 in the vertical direction Z.
[0054] For example, in some examples, as shown in Figures 1A to 1C, the second hole H2 can be a blind hole. For example, referring to Figure 1C, the first conductive pattern 121 further includes a fourth extension E4 located at the bottom of the second conductive pattern 122. The fourth extension E4, the third extension E3, and the second extension E2 form a groove in which the second conductive pattern 122 is located. That is, the first conductive pattern 121 surrounds the bottom surface and sidewalls of the second conductive pattern 122, but exposes the top surface of the second conductive pattern 122. Alternatively, the first conductive pattern 121 can surround the bottom surface and the lower sidewall near the bottom surface of the second conductive pattern 122, but expose the top surface and the upper sidewall near the top surface of the second conductive pattern 122.
[0055] For example, in other examples, as shown in Figures 1A, 1B, and 1D, the second hole can also be a through hole. For example, referring to Figure 1D, the third extension E3 and the second extension E2 of the first conductive pattern 121 surround the sidewall of the second conductive pattern 122, but expose the top and bottom surfaces of the second conductive pattern 122.
[0056] For example, as shown in Figures 1A to 1E, the semiconductor structure may further include a gate dielectric layer 130, which is disposed in the first hole H1 and located between the active pillar 110 and the first conductive pattern 121.
[0057] For example, as shown in Figures 1C to 1E, the semiconductor structure may further include a data storage element 150 coupled to a transistor. For example, in some examples, the data storage element 150 may be a capacitor, which may include a first electrode, a second electrode, and a capacitor dielectric layer (not shown) disposed between the first and second electrodes. For example, the first electrode may be coupled to an active post 110, and the second electrodes of multiple capacitors may be formed as a common electrode. For example, in other examples, the data storage element 150 may also be a FeRAM memory element (such as a ferroelectric capacitor), a PCM memory element, an MRAM memory element, etc. That is, the semiconductor structure provided in the embodiments of this disclosure can be formed as DRAM, FeRAM (ferroelectric random access memory), PCM (phase-change memory), MRAM (magnetic random access memory), etc.
[0058] For example, in some examples, as shown in Figures 1C to 1E, the semiconductor structure may also include contact pads 115 through which the data storage element 150 can be coupled to a corresponding active post 110. For example, in other examples, the contact pads 115 may be omitted from the semiconductor structure.
[0059] For example, in some examples, as shown in Figures 1C to 1E, the semiconductor structure may also include bit line contact plugs 135, through which bit lines 140 can be coupled to corresponding active pillars 110. For example, in other examples, bit line contact plugs 135 may be omitted from the semiconductor structure.
[0060] For example, the material of the active pillar 110 can include any suitable semiconductor material, such as silicon, germanium, gallium arsenide, etc. For example, the material of the gate dielectric layer 130 can include any suitable dielectric material, such as silicon dioxide, silicon nitride, high-k dielectric materials, or any combination thereof; for example, high-k dielectric materials can include, but are not limited to, hafnium oxide (HfO2), zirconium oxide (ZrO2), etc. For example, the materials of the bit line 140, contact pad 115, bit line contact plug 135, first electrode 150, and second electrode 160 can each include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicides, doped polysilicon, or any combination thereof.
[0061] For example, the word line 120 may include any suitable combination of conductive materials, as long as the resistivity of the material of the second conductive pattern 122 is less than that of the material of the first conductive pattern 121. For example, in some examples, the material of the first conductive pattern 121 includes titanium nitride or tantalum nitride, and the material of the second conductive pattern 122 includes molybdenum or tungsten.
[0062] For example, in some examples, the gap-filling ability of the material of the first conductive pattern 121 is stronger than that of the material of the second conductive pattern 122 (refer to the relevant description of embodiments of the manufacturing method below). Thus, the manufacturing feasibility of the word line 120 can be provided while reducing its resistance.
[0063] It should be noted that details not described in the embodiments of the semiconductor structure disclosed herein can be found in the relevant descriptions of the embodiments of the manufacturing method below, and will not be repeated here.
[0064] In the semiconductor structure provided in the embodiments of this disclosure, the word line is composed of a first conductive pattern with relatively high resistivity and a second conductive pattern with relatively low resistivity, which helps to reduce word line resistance and improve device performance.
[0065] At least some embodiments of this disclosure also provide a method for manufacturing a semiconductor structure, which can be used to manufacture the semiconductor structure provided in the foregoing embodiments. Figure 2 is a schematic flowchart of a method for manufacturing a semiconductor structure provided in some embodiments of this disclosure. For example, as shown in Figure 2, the manufacturing method may include the following steps S100 to S400.
[0066] S100: Provides a semiconductor substrate;
[0067] S200: Etching the semiconductor substrate to form active pillars extending in the vertical direction;
[0068] S300: Forming a word line, wherein the word line extends along a first horizontal direction and is coupled to an active post, the word line includes a first conductive pattern and a second conductive pattern, the first conductive pattern has a first hole and a second hole arranged alternately along the first horizontal direction, the active post is located in the first hole, the second conductive pattern is located in the second hole, and the resistivity of the second conductive pattern is less than the resistivity of the first conductive pattern.
[0069] S400: Form a bit line, wherein the bit line extends along a second horizontal direction and is coupled to an active post, and the second horizontal direction intersects with the first horizontal direction.
[0070] For example, in step S100, the material of the semiconductor substrate may include any suitable semiconductor material, such as silicon, germanium, gallium arsenide, etc.
[0071] Figures 3A-3D are schematic cross-sectional views of certain stages of a semiconductor structure manufacturing method according to some embodiments of the present disclosure. In Figures 3A-3D, the left sub-figure corresponds to a cross-section taken along line A1-A2 in Figure 1A, and the right sub-figure corresponds to a cross-section taken along line B1-B2 in Figure 1A. Hereinafter, steps S200 to S300 of a semiconductor structure manufacturing method according to some embodiments of the present disclosure will be described with reference to Figures 3A-3D.
[0072] Referring to Figure 3A, the semiconductor substrate 100 can be etched first to form a first trench T1 extending along the second horizontal direction Y, and a first isolation layer 101 can be formed in the first trench T1. Then, a patterned hard mask layer 201 is formed on the semiconductor substrate 100, and the patterned hard mask layer 201 is used as a mask to etch the semiconductor substrate 100 and the first isolation layer 101 to form a second trench T2 extending along the first horizontal direction X, thereby defining the active pillar 110. For example, a first isolation material layer filling the first trench T1 can be formed first using a deposition process, and then a chemical mechanical polishing (CMP) process or an etch-back process can be used to remove the portion of the first isolation material layer outside the first trench T1, leaving the remaining first isolation material layer in the first trench T1 as the first isolation layer 101, with the top surface of the first isolation layer 101 flush with the top surface of the semiconductor substrate 100. For example, the material of the first isolation layer 101 can be an oxide (such as silicon dioxide). For example, the depth of the second trench T2 is less than the depth of the first trench T1.
[0073] Next, referring to FIG3B, a second isolation layer 102 and a third isolation layer 103 can be formed sequentially stacked on the sidewall of the second trench T2. For example, an atomic layer deposition process can be used to form a conformal second isolation material layer covering the second trench T2, and then a back etch process can be used to remove part of the second isolation material layer, leaving the remaining second isolation material layer on the sidewall of the second trench T2 as the second isolation layer 102, with the top surface of the second isolation layer 102 lower than the top surface of the active pillar 110. Then, an atomic layer deposition process can be used to form a conformal third isolation material layer covering the second trench T2 and the second isolation layer 102, and then a back etch process can be used to remove part of the third isolation material layer, leaving the remaining third isolation material layer on the sidewall of the second trench T2 as the third isolation layer 103, with the third isolation layer 103 located on top of the second isolation layer 102, and the top surface of the third isolation layer 103 lower than the top surface of the active pillar 110. For example, the thickness of the third isolation material layer is substantially equal to the thickness of the second isolation layer, but is not limited to this. For example, the material of the second isolation layer 102 is different from the material of the first isolation layer 101, and the material of the second isolation layer 102 has a higher etching selectivity than the material of the first isolation layer 101. For example, the material of the second isolation layer 102 can be a nitride (such as silicon nitride). For example, the material of the third isolation layer 103 is the same as the material of the first isolation layer 101.
[0074] Next, referring to FIG. 3C, the hard mask layer 201 can be removed to form a fourth isolation layer 104 filling the second trench T2. For example, a deposition process can be used to form the fourth isolation material layer filling the second trench T2, and then a chemical mechanical polishing (CMP) process or an etch-back process can be used to remove the portion of the fourth isolation material layer outside the second trench T2, leaving the remaining fourth isolation material layer in the second trench T2 as the fourth isolation layer 104. The top surface of the fourth isolation layer 104 is flush with the top surface of the semiconductor substrate 100. For example, the material of the fourth isolation layer 104 is the same as the material of the second isolation layer 102.
[0075] Next, referring to FIG3D, a selective wet etching process can be used to remove a portion of the first isolation layer 101 and the third isolation layer 103, thereby forming receiving grooves 106 on opposite sides of the active pillar 110 in the first horizontal direction X. These receiving grooves 106 are used to accommodate the first extension E1 of the subsequently formed first conductive pattern 121. For example, as shown in FIG3D, the top surface of the remaining first isolation layer 101 may be lower than the bottom surface of the receiving groove 106.
[0076] Next, in some examples, referring to Figures 1A to 1C and Figure 1E, a gate dielectric layer 130 can be formed first using a thermal oxidation process and / or an atomic layer deposition process; then, a first conductive material layer can be formed using an atomic layer deposition process, with the first conductive material filling the receiving trench 106; subsequently, a second conductive material layer can be formed using a deposition process; finally, a portion of the first conductive material layer and a portion of the second conductive material layer are removed using an etch-back process, with the remaining first conductive material layer serving as the first conductive pattern 121 and the remaining second conductive material layer serving as the second conductive pattern 122, thereby obtaining the word line 120. At this time, referring to Figure 1B, the first conductive pattern 121 is formed with alternating first holes H1 and second holes H2 arranged along a first horizontal direction X, with the active pillar 110 located in the first hole H1 and the second conductive pattern 122 located in the second hole H2. The first hole H1 is a through hole (refer to Figure 1E), and the second hole H2 is a blind hole (refer to Figure 1C).
[0077] Alternatively, in other examples, referring to Figures 1A, 1B, 1D, and 1E, a gate dielectric layer 130 can be formed first using a thermal oxidation process and / or an atomic layer deposition process; then, an atomic layer deposition process can be used to form a first conductive material layer, which fills the receiving trench 106; subsequently, a portion of the first conductive material layer can be etched back to remove it, leaving the remaining first conductive material layer as the first conductive pattern 121; then, a second conductive material layer can be formed using a deposition process; finally, a portion of the second conductive material layer can be etched back to remove it, leaving the remaining second conductive material layer as the second conductive pattern 122, thereby obtaining the word line 120. In this case, referring to Figure 1B, the first conductive pattern 121 is formed with a first hole H1 and a second hole H2 alternately arranged along a first horizontal direction X, with the active post 110 located in the first hole H1 and the second conductive pattern 122 located in the second hole H2, wherein the first hole H1 is a through hole (refer to Figure 1E), and the second hole H2 is also a through hole (refer to Figure 1D).
[0078] For example, to better fill the aforementioned receiving groove 106, the first conductive material layer (corresponding to the first conductive pattern 121) can be selected from conductive materials with relatively strong gap-fill ability; to reduce the resistance of the word line 120, the second conductive material layer (corresponding to the second conductive pattern 122) can be selected from conductive materials with relatively low resistivity. For example, in some examples, the material of the first conductive pattern 121 includes titanium nitride or tantalum nitride, and the material of the second conductive pattern 122 includes molybdenum or tungsten. Compared with the case where the word line is composed of the same material with relatively strong gap-fill ability and relatively high resistivity, the semiconductor structure provided by the embodiments of this disclosure uses a material with relatively strong gap-fill ability (which may have relatively high resistivity) and another material with relatively low resistivity (which may have relatively weak gap-fill ability) to form the word line 120, thereby reducing the resistance of the word line 120 and increasing the range of materials that can be selected for the word line 120.
[0079] For example, as shown in Figures 1A to 1E, the first hole H1 can be formed by the first extension E1 and the second extension E2 of the first conductive pattern 121, and the second hole H2 can be formed by the third extension E3 and the second extension E2 of the first conductive pattern 121. The first extension E1 extends along the first horizontal direction X, the second extension E2 extends along the second horizontal direction Y, and the third extension E3 extends along the first horizontal direction X. It is understood that, since the first conductive material layer (corresponding to the first conductive pattern 121) is formed using an atomic layer deposition process, the width W3 of the third extension E3 is usually equal to the width W2 of the second extension E2. In addition, since the actual deposition rate of the second extension E2 in the receiving tank 106 is about twice the deposition rate of the first conductive material layer, in order to ensure that the receiving tank 106 is filled with the first conductive material layer, the width W2 of the second extension E2 is usually greater than 1 / 2 of the width W1 of the first extension E1.
[0080] In the embodiments of this disclosure, the width W1 of the first extension E1 refers to the dimension of the first extension E1 in the horizontal direction perpendicular to the second horizontal direction Y; the width W2 of the second extension E2 refers to the dimension of the second extension E2 in the horizontal direction perpendicular to the first horizontal direction X; and the width W3 of the third extension E3 refers to the dimension of the third extension E3 in the horizontal direction perpendicular to the second horizontal direction Y. When the second horizontal direction Y is perpendicular to the first horizontal direction X, the horizontal direction perpendicular to the first horizontal direction X is the second horizontal direction Y, and the horizontal direction perpendicular to the second horizontal direction Y is the first horizontal direction X.
[0081] For example, the material of the gate dielectric layer 130 includes any suitable dielectric material, such as silicon dioxide, silicon nitride, high-k dielectric material, or any combination thereof.
[0082] For example, in some examples, in step S400, the semiconductor substrate 100 can be thinned from the back side until one end of the active pillar 110 near the back side of the semiconductor substrate 100 is exposed, and then a bit line 140 coupled to the active pillar 110 is formed on the back side of the semiconductor substrate 100. For example, in other examples, in step S400, a portion of the semiconductor substrate 100 below the plurality of active pillars 110 arranged along the second horizontal direction can be heavily doped from the front side to form the bit line 140. It should be noted that the embodiments of this disclosure do not limit the method of forming the bit line in step S400, and can refer to commonly used methods in the prior art.
[0083] For example, in some embodiments, based on steps S100 to S400, the above manufacturing method may further include the following step S500.
[0084] S500: Forms a data storage element, wherein the data storage element is coupled to an active column.
[0085] For example, referring to Figures 1C to 1E, a data storage element 150 can be formed coupled to the active post 110. For example, in some examples, the data storage element 150 can be a capacitor, which may include a first electrode, a second electrode, and a capacitor dielectric layer (not shown) disposed between the first and second electrodes. For example, the first electrode can be coupled to the active post 110, and the second electrodes of multiple capacitors can be formed as a common electrode. For example, in other examples, the data storage element 150 can also be a FeRAM memory element (such as a ferroelectric capacitor), a PCM memory element, an MRAM memory element, etc. That is, the semiconductor structure provided by the embodiments of this disclosure can be formed as DRAM, FeRAM (ferroelectric random access memory), PCM (phase-change memory), MRAM (magnetic random access memory), etc. It should be noted that the embodiments of this disclosure do not limit the method of forming the data storage element in step S500, and can refer to commonly used methods in the prior art.
[0086] For example, in some embodiments, referring to Figures 1C to 1E, the manufacturing method described above may further include: forming contact pads 115, wherein the contact pads 115 are used for electrically connecting the active post 110 and the data storage element 150. For example, the contact pads 115 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicides, doped polysilicon, or any combination thereof.
[0087] For example, in some embodiments, referring to Figures 1C to 1E, the above manufacturing method may further include: forming a bit line contact plug 135, wherein the bit line contact plug 135 is used for electrically connecting the active post 110 and the bit line 140. For example, the bit line contact plug 135 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof.
[0088] For example, the manufacturing method described above may also include steps such as forming source and drain regions in the active pillar 110; the implementation of these steps can refer to commonly used methods in the prior art, and is not limited here.
[0089] It should be noted that details not described in the embodiments of the manufacturing method disclosed herein can be referred to the relevant descriptions of the foregoing embodiments of the semiconductor structure, and will not be repeated here.
[0090] The technical effects and other details of the manufacturing method provided in the embodiments of this disclosure can be found in the relevant descriptions of the foregoing embodiments of the semiconductor structure, and will not be repeated here.
[0091] At least some embodiments of this disclosure also provide an electronic device. FIG4 is a schematic block diagram of an electronic device provided in some embodiments of this disclosure. As shown in FIG4, the electronic device 1 includes a processor 20 and a memory 10 coupled to each other, wherein the memory 10 includes the semiconductor structure provided in any of the foregoing embodiments.
[0092] For example, processor 20 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), etc. Memory 10 may be configured to store data to be processed by processor 20 and / or data processed by the processor.
[0093] For example, electronic device 1 includes, but is not limited to, mobile phones, tablets, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, in-vehicle devices, servers, workstations, etc.
[0094] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A semiconductor structure, comprising: An active column (110) extends in the vertical direction (Z); A word line (120) extends along a first horizontal direction (X) and is coupled to the active pillar to form a transistor; Bit line (140) extends along a second horizontal direction (Y) and is coupled to the active post, wherein the second horizontal direction intersects the first horizontal direction; The word line includes a first conductive pattern (121) and a second conductive pattern (122) that are connected to each other. The first conductive pattern has a first hole (H1) and a second hole (H2) that are alternately arranged along the first horizontal direction. The active post is located in the first hole, and the second conductive pattern is located in the second hole. The resistivity of the second conductive pattern is less than that of the first conductive pattern.
2. The semiconductor structure according to claim 1, wherein, The first hole is surrounded by a first extension (E1) and a second extension (E2) of the first conductive pattern. The first extension extends along the first horizontal direction, and the second extension extends along the second horizontal direction. The width (W2) of the second extension is greater than 1 / 2 of the width (W1) of the first extension.
3. The semiconductor structure according to claim 2, wherein, The width of the second extension is smaller than the width of the first extension.
4. The semiconductor structure according to claim 2 or 3, wherein, The second hole is formed by the third extension (E3) of the first conductive pattern and the second extension, the third extension extending along the first horizontal direction, and the width (W3) of the third extension being equal to the width of the second extension.
5. The semiconductor structure according to any one of claims 1-4, wherein, The first hole is a through hole, and the second hole is a through hole.
6. The semiconductor structure according to any one of claims 1-4, wherein, The first hole is a through hole, and the second hole is a blind hole.
7. The semiconductor structure according to any one of claims 1-6, wherein, The gap-filling ability of the material of the first conductive pattern is stronger than that of the material of the second conductive pattern.
8. The semiconductor structure according to any one of claims 1-7, wherein, The material of the first conductive pattern includes titanium nitride or tantalum nitride, and the material of the second conductive pattern includes molybdenum or tungsten.
9. The semiconductor structure according to any one of claims 1-8, further comprising: A data storage element is coupled to the transistor.
10. A method for manufacturing a semiconductor structure, comprising: Provides a semiconductor substrate (100); The semiconductor substrate is etched to form an active pillar (110) extending in the vertical direction (Z); A word line (120) is formed, wherein the word line extends along a first horizontal direction (X) and is coupled to the active pillar; A bit line (140) is formed, wherein the bit line extends along a second horizontal direction (Y) and is coupled to the active post, the second horizontal direction intersecting the first horizontal direction; The word line includes a first conductive pattern (121) and a second conductive pattern (122). The first conductive pattern has a first hole (H1) and a second hole (H2) arranged alternately along the first horizontal direction. The active post is located in the first hole, and the second conductive pattern is located in the second hole. The resistivity of the second conductive pattern is less than that of the first conductive pattern.
11. The manufacturing method according to claim 10, wherein, The first hole is surrounded by a first extension (E1) and a second extension (E2) of the first conductive pattern. The first extension extends along the first horizontal direction, and the second extension extends along the second horizontal direction. The width (W2) of the second extension is greater than 1 / 2 of the width (W1) of the first extension.
12. The manufacturing method according to claim 11, wherein, The width of the second extension is smaller than the width of the first extension.
13. The manufacturing method according to claim 11 or 12, wherein, The second hole is formed by the third extension (E3) of the first conductive pattern and the second extension, the third extension extending along the first horizontal direction, and the width (W3) of the third extension being equal to the width of the second extension.
14. The manufacturing method according to any one of claims 10-13, wherein, The first hole is a through hole, and the second hole is a through hole.
15. The manufacturing method according to any one of claims 10-13, wherein, The first hole is a through hole, and the second hole is a blind hole.
16. The manufacturing method according to any one of claims 10-15, wherein, The gap-filling ability of the material of the first conductive pattern is stronger than that of the material of the second conductive pattern.
17. The manufacturing method according to any one of claims 10-16, wherein, The material of the first conductive pattern includes titanium nitride or tantalum nitride, and the material of the second conductive pattern includes molybdenum or tungsten.
18. The manufacturing method according to any one of claims 10-17, further comprising: A data storage element is formed, wherein the data storage element is coupled to the active column.
19. An electronic device (1), comprising: Processor (20); as well as A memory (10), wherein the memory is coupled to the processor, the memory comprising a semiconductor structure according to any one of claims 1-9.