On-chip network delay prediction method based on artificial neural network

Abstract

The present invention discloses an on-chip network delay prediction method based on an artificial neural network, comprising collecting random hardware mappings and corresponding network feature values, and forming a data set from the hardware mappings and network feature values; setting the network structure and training parameters of the on-chip network delay prediction model according to the data set; training the on-chip network delay prediction model using a K-fold cross-validation method to obtain the model's optimal hyperparameters; retraining the on-chip network delay prediction model on all training data using the optimal hyperparameters to obtain a final on-chip network delay prediction model; and evaluating the generalization ability of the final on-chip network delay prediction model on a test set. The present invention can replace an on-chip network simulator when using exhaustive, heuristic, or iterative algorithms to explore the optimal mapping, quickly obtaining the delay times required for different input hardware mappings, assisting in the exploration of the optimal mapping, with low computational cost, good generalization ability, and strong robustness.

Description

Technical Field

[0001] The present invention belongs to the field of Network on Chip (NoC), and relates to a method for predicting Network on Chip delay based on an artificial neural network. Background Art

[0002] Currently, many brain-inspired computing platforms based on multi-core interconnects achieve higher levels of intelligent computing by simply expanding the number of neurons, without further exploring the utilization of hardware mapping. In fact, the mapping method has a crucial impact on the energy efficiency of the hardware platform. The energy efficiency of the best and worst random mappings differ by a factor of 17. To search for the optimal mapping in the vast and extremely complex hardware mapping exploration space, it is necessary to repeatedly call the brain-inspired computing platform or its corresponding on-chip network simulator to simulate real-world computing and communication transmission conditions to obtain the mapping with the shortest total runtime.

[0003] However, the computing time of a brain-like computing platform is too long. Even for its corresponding on-chip network simulator, according to experiments, it takes 5 minutes to completely calculate a small convolutional neural network (such as LeNet). This is very unfavorable for the process of exhaustive, heuristic, and iterative algorithms to explore the optimal mapping, resulting in the algorithm taking a longer time to converge. Summary of the Invention

[0004] Purpose of the invention: The present invention proposes an on-chip network delay prediction method based on artificial neural network to solve the above-mentioned problems existing in the prior art.

[0005] Technical solution: A method for predicting network-on-chip delay based on an artificial neural network, comprising the following steps:

[0006] Step 1: Collect random hardware mappings and their corresponding network feature values, and combine the hardware mappings and network feature values ​​into a dataset, which includes a training set and a test set.

[0007] Step 2: Setting the network structure and training parameters of the on-chip network delay prediction model according to the data set;

[0008] The prediction model includes an input layer, several fully connected hidden layers, and an output layer. The number of neurons in the input layer is the number of eigenvalues ​​of the input hardware mapping. The output layer has only one neuron, representing the predicted simulation time required for the on-chip network. Each fully connected hidden layer is followed by an activation function.

[0009] Step 3: Use the optimizer to train the NOC delay prediction model using the K-fold cross-validation method to obtain the optimal hyperparameters of the model.

[0010] The K-fold cross-validation method uses a predetermined value of fold cross-validation, which divides the available data into a predetermined value of partitions, instantiates a predetermined value of identical models, trains each model on the predetermined value minus one partition, and evaluates it on the remaining partition. The validation score of the model is the average of the predetermined value of validation scores;

[0011] Step 4: Retrain the NOC delay prediction model on all training data using the optimal hyperparameters to obtain the final NOC delay prediction model.

[0012] Step 5: Evaluate the generalization ability of the final on-chip network delay prediction model on the test set. If it meets the requirements, save the model; otherwise, adjust the model network structure and retrain;

[0013] Step 6: Load the saved on-chip network delay prediction model and combine it with the exhaustive, heuristic, and iterative algorithm platform to obtain the optimal hardware mapping solution.

[0014] According to one aspect of the present application, the data of the data set in step 1 specifically includes: input mapping of the on-chip network, total computing delay, layered computing delay, spatial network delay, total time domain network delay, total number of hops in the on-chip network, number of inter-layer hops, time domain network delay in the X and Y directions, inter-layer congestion characteristic values, and allocation of computing units in the on-chip network.

[0015] According to one aspect of the present application, the input mapping of the on-chip network is specifically as follows: the computing power of a single computing unit of the on-chip network platform is set to M neurons, the convolutional neural network is converted into a quasi-artificial neural network, and M neurons are grouped as a group. The grouped neuron groups are assigned to different on-chip network computing units for calculation, and the on-chip network computing unit serial numbers are obtained. The array consisting of the on-chip network computing unit serial numbers corresponding to the neuron group serial numbers is the input mapping of the on-chip network.

[0016] According to one aspect of the present application, the total computational delay is the sum of the computational unit delays of all neural network layers; the layered computational delay is the sum of the computational unit delays assigned to computational tasks in different neural network layers, where the computational unit delay characteristics are determined by the number of input neurons and the number of output neurons, and the estimation formula is as follows:

[0017] T com =n in ×[(n out +n mac -1) / n mac ]+{(n out +n mac -1)}mod n mac +1;

[0018] Where [] is the floor operator, mod is the modulus operator, n in is the number of neurons input into a single computational unit node, n out is the number of neurons output in a single computational unit node, n mac The number of built-in multiplier-accumulators for the processing unit.

[0019] According to one aspect of the present application, the inter-layer hop count is the sum of the network hop counts of different neural network layers; the total on-chip network hop count is the sum of the inter-layer hop counts of different neural network layers, where the network hop count is determined by the connection relationship between the computing units, specifically:

[0020] After determining a mapping, the connection relationship between each computing unit on the chip network can be determined. If the routing method is XY routing, the number of links from the source node to the destination node is the network hop count between the two nodes. The sequence number of the two connected computing units can be used to know the row and column information of the computing unit in the two-dimensional mesh architecture of the on-chip network. The network hop count calculation formula is as follows:

[0021] hops i →j=|row(PE i )-row(PE j )|+|col(PE i )-col(PE j )|;

[0022] Among them, PE i and PE j are the numbers of the two connected computing units, row(PE) and col(PE) represent the row number and column number of the current PE in the two-dimensional grid architecture of the on-chip network, respectively.

[0023] According to one aspect of the present application, the airspace network delay calculation formula is as follows:

[0024] T spa_delay =h(m)*(T router_pipline +T link )+T size-1 +T NI ;

[0025] Where m is the mapping, h(m) is the total number of hops determined by the mapping, and T router_pipline is the routing delay, T link is the link delay, T size-1 T is the value related to the number of flow control units in the communication transmission packet, NI The corresponding delay for network interface input and output.

[0026] According to one aspect of the present application, the total time domain network delay and inter-layer congestion characteristic value are calculated as follows:

[0027] The links connecting all computing units are set as set {L}, where the horizontal links are denoted as {L Xij}, the vertical direction is recorded as {L Yij For any two adjacent layers, there are N paths, and the amount of data on the nth path is flits. n , let the bandwidth be b, and the time domain network delay in the X direction is the link L Xij The excess data volume that exceeds the bandwidth is calculated using the following formula:

[0028] congestion Xij =∑ n∈{n}Xij flits n -b;

[0029] where {n} Xij For L Xij The set of all data packet transmission path numbers;

[0030] The calculation formula for the time domain network delay in the Y direction is as follows:

[0031] Congestion Yij =∑ n∈{n}Yij flits n -b;

[0032] The total time domain network delay is calculated as follows:

[0033] Congestion total =∑ i ∑ j congestion Xij +∑ i ∑ j Congestion Yij ;

[0034] The inter-layer congestion characteristic value is the total excess data volume between layers, and the total time domain network delay is the sum of the inter-layer congestion characteristic values.

[0035] According to one aspect of the present application, the on-chip network is a two-dimensional mesh network.

[0036] According to one aspect of the present application, the method further includes preprocessing the data set, performing target encoding and deviation normalization on the network feature values ​​and the hardware mapping feature values.

[0037] According to one aspect of the present application, a batch normalization layer is added before each hidden layer in step 2 to speed up the convergence of the model.

[0038] According to one aspect of the present application, the activation function uses a linear correction function to increase the nonlinearity of the network, and the optimizer uses an adaptive moment estimation algorithm for training, at which time the prediction error is the lowest.

[0039] Beneficial effects: First, the present invention provides an on-chip network delay prediction method based on artificial neural network, which is suitable for predicting the completion time of random input mapping system operation.

[0040] Second, the method of the present invention is based on an artificial neural network algorithm, which can more accurately capture the nonlinear relationship between input features and on-chip network delay compared to traditional polynomial models.

[0041] Third, after the weights of the prediction model trained by the present invention are saved, the trained model is called when exploring the optimal mapping using exhaustive, heuristic, and iterative algorithms. This can provide the algorithm with the time required for efficient and fast on-chip network simulation, assist in the optimal mapping exploration, and eliminate the need to call the on-chip network simulator, saving computing costs and the running time required for algorithm convergence, which has good practical application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a training flow chart of the present invention.

[0043] Figure 2 It is a structural diagram of the artificial neural network model of the present invention.

[0044] Figure 3 It is a graph showing the convergence of the loss value of the validation set of the present invention.

[0045] Figure 4 It is a scatter plot comparison diagram of the predicted values ​​and target values ​​in some test sets of the present invention.

[0046] Figure 5 It is the error diagram of the predicted values ​​in the partial test set of the present invention. DETAILED DESCRIPTION

[0047] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] like Figure 1 The figure shows a training flow chart of an on-chip network delay prediction model based on an artificial neural network. The on-chip network described in this embodiment is a two-dimensional mesh on-chip network. First, random hardware mappings and their corresponding network feature values ​​need to be collected as a data set, including a training set and a test set.

[0049] A total of 26,000 random mappings corresponding to the on-chip network delay are collected. The content of the input feature data set includes the input mapping of the on-chip network, total computing delay, layered computing delay, spatial network delay, total temporal network delay, total number of on-chip network hops, number of inter-layer hops, temporal network delay in the X and Y directions, inter-layer congestion characteristic values, and the allocation of on-chip network computing units (PEs).

[0050] The input map of the NoC is an array consisting of the NoC computing unit numbers corresponding to the neuron group numbers. Assuming the computing power of a single NoC computing unit is M neurons, the convolutional neural network to be computed is converted into an artificial neural network-like model. These neurons are then grouped into groups of M neurons, and these groups are then assigned to different NoC computing units for computation.

[0051] The computational latency (in clock cycles) of a single computational unit is characterized by the number of input neurons n in and the number of output neurons n out Determination; layered computational delay is the sum of the computational unit delays assigned to computational tasks in different neural network layers; total computational delay is the sum of the computational unit delays in all neural network layers. The estimation formula is as follows:

[0052] T com =n in ×[(n out +n mac -1) / n mac ]+{(n out +n mac -1)}mod n mac +1;

[0053] Among them, [] is the floor operator. The standard floor operator cannot be displayed normally, so this symbol is used to represent it. mod is the modulus operator, n in is the number of neurons input into a single computational unit node, n out is the number of neurons output in a single computational unit node, n mac The number of built-in multipliers and adders in the processing unit. out +n mac -1) / n mac ] by n mac The output neurons of a single computational unit node are grouped, giving the maximum number of groups required for neuron computation in each computational unit. The computation of neurons within each computational unit node is parallel within the group and serial between groups. After processing in the parallel multiplication and addition units, each group then enters a nonlinear unit serially.

[0054] The number of network hops is determined by the connection relationship between computing units. After a certain mapping is determined, the connection relationship between the computing units in the on-chip network can be determined. If the routing method is XY routing, the number of links from the source node to the destination node is the number of network hops between the two nodes. The number of inter-layer hops is the sum of the number of computing unit connection links assigned to different neural network layers; the total number of hops in the on-chip network is the sum of the number of inter-layer hops in different neural network layers. Let the serial numbers of the two connected computing units be PE i and PE j The serial number can be used to know the row and column information of the computing unit in the on-chip two-dimensional mesh architecture. The network hop count calculation formula is as follows:

[0055] hops i →j=|row(PE i )-row(PE j )|+|col(PE i )-col(PE j )|;

[0056] Where row(PE) and col(PE) represent the row number and column number of the current PE in the two-dimensional grid architecture of the on-chip network, respectively.

[0057] The calculation method of spatial network delay is as follows: let the mapping be m, the total number of hops determined by the mapping be h(m), and the routing delay be T router_pipline , the link delay is T link , T size-1 is the number of flow control units (flits) in the communication transmission packet, and the corresponding delay of the network interface (NI) input and output is T NI , the spatial delay formula is:

[0058] T spa_delay =h(m)*(T router_pipline +T link )+T size-1 +T NI ;

[0059] The total time domain network delay and inter-layer congestion characteristic value are calculated as follows: the links connecting all computing units are set as a set {L}, where the horizontal links are denoted as {L Xij}, the vertical direction is recorded as {L Yij For any two adjacent layers of transmission, there are N paths in total, and the amount of data on the nth path is flits. n Assuming the bandwidth b is 32 bits, the time domain network delay in the X direction is the link L Xij The excess data volume that exceeds the bandwidth is estimated using the following formula:

[0060] congestion Xij =∑ n∈{n}Xij flits n -b;

[0061] where {n} Xij For L Xij The set of all data packet transmission path numbers.

[0062] The calculation formula for the time domain network delay in the Y direction is as follows:

[0063] Congestion Yij =∑ n∈{n}Yij flits n -b;

[0064] The inter-layer congestion characteristic value is the total excess data volume between layers. The total time domain network delay is the sum of the inter-layer congestion characteristic values. The calculation formula for the total time domain network delay is as follows:

[0065] Congestion total =∑ i ∑ j congestion Xij +∑ i ∑ j Congestion Yij ;

[0066] At this point, the data set required for training the prediction model is ready. Next, data preprocessing is required. The data preprocessing of the present invention is divided into two steps: target encoding and deviation normalization.

[0067] Step 1: Target Encoder, also known as mean encoding, is a very effective feature encoding method. This method counts the on-chip network delay value corresponding to each category label. Each category label is replaced by the average on-chip network delay of that category.

[0068] Step 2: Deviation normalization, also known as Min-Max normalization, scales the data to [0,1]. Converts different features to the same order of magnitude for easy comparison. At the same time, it can increase the speed of gradient descent to the optimal solution and improve the calculation accuracy. n} is normalized and converted into a sequence {y1,y2,…,y n The formula is as follows:

[0069] y i =(x i -min 1≤j≤{xj} ) / (max 1≤j≤{xj} -min 1≤j≤{xj} );

[0070] The following shows a comparison of mean absolute error latency clock cycles using target encoding with deviation normalization and without it. A batch size of 16 was used for this comparison. Even though batch normalization is used later to normalize the data, eliminating the need for input normalization, experiments have shown that deviation normalization can still reduce the error to some extent, as shown below:

[0071] When there is no target encoding and deviation standardization, the mean absolute error is 262.50; when there is target encoding and deviation standardization, the mean absolute error is 254.89; when there is no target encoding and no deviation standardization, the mean absolute error is 266.61; when there is target encoding and no deviation standardization, the mean absolute error is 258.69.

[0072] After data preprocessing is completed, the neural network structure is set. Figure 2 As shown in the figure, the prediction model consists of an input layer, several fully connected hidden layers, and an output layer. The number of neurons in the input layer is the number of eigenvalues ​​of the input hardware mapping. The number of neurons in the output layer is 1, which represents the simulation time required for the predicted on-chip network. There is an activation function after each fully connected hidden layer.

[0073] Furthermore, a batch normalization layer is added before each hidden layer to speed up the convergence of the model, avoid the gradient vanishing or exploding problem of deep networks, and reduce the dependence on parameter initialization methods.

[0074] Furthermore, the activation function after each fully connected hidden layer uses the Rectified Linear Unit (ReLU) to delinearize the model. Neurons using ReLU only need to perform addition, multiplication, and comparison operations, making the calculation more efficient. The formula for the ReLU is as follows:

[0075] ReLU(x)=max(0,x)=(x,x>0; 0,x≤0), when x>0, take x; when x≤0, take 0.

[0076] It can be seen that the ReLU function is a left saturation function, and its derivative is 1 when x>0, which alleviates the gradient vanishing problem of the neural network to a certain extent and accelerates the convergence speed of gradient descent.

[0077] Furthermore, a batch normalization (BN) layer is added before each fully connected layer, which is equivalent to performing data preprocessing at each layer, thereby accelerating model convergence. Layer-by-layer normalization not only improves optimization efficiency but also serves as an implicit regularization method. During training, the neural network's prediction for a sample is not only related to the sample itself, but also to other samples in the same batch. Because the batch selection is random, the neural network is prevented from overfitting to a specific sample, thereby improving the network's generalization ability.

[0078] Experiments show that the BN layer does not work when the batch size is too small (less than or equal to 8). In this invention, when the batch size is 24, the mean absolute error of the validation set is the lowest, as shown below:

[0079] When the batch size is 8, the mean absolute error is 65049.15; when the batch size is 16, the mean absolute error is 254.88; when the batch size is 20, the mean absolute error is 249.73; when the batch size is 24, the mean absolute error is 248.69; when the batch size is 32, the mean absolute error is 255.25.

[0080] In summary, there are a total of 1558097 neuron parameters in the model network structure, 1552449 trainable parameters, and 5648 non-trainable parameters, as shown below:

[0081] When the network layer type is batch normalization layer 1, the number of output neurons is 124 and the number of parameters is 496; when the network layer type is fully connected layer 1, the number of output neurons is 1000 and the number of parameters is 125000; when the network layer type is batch normalization layer 2, the number of output neurons is 1000 and the number of parameters is 4000; when the network layer type is fully connected layer 2, the number of output neurons is 1000 and the number of parameters is 1001000; when the network layer type is batch normalization layer 3, the number of output neurons is 1000 and the number of parameters is 4000; when the network layer type is fully connected layer 3, the number of output neurons is 300 and the number of parameters is 300300; when the network layer type is batch normalization layer 4 , the number of output neurons is 300, and the number of parameters is 1200; when the network layer type is fully connected layer 4, the number of output neurons is 300, and the number of parameters is 90300; when the network layer type is batch normalization layer 5, the number of output neurons is 300, and the number of parameters is 1200; when the network layer type is fully connected layer 5, the number of output neurons is 100, and the number of parameters is 30100; when the network layer type is batch normalization layer 6, the number of output neurons is 100, and the number of parameters is 400; when the network layer type is fully connected layer 6, the number of output neurons is 1, and the number of parameters is 101; the total number of parameters is 1558097, the number of trainable parameters is 1552449, and the number of non-trainable parameters is 5648.

[0082] The non-trainable parameters are introduced by the addition of the BN layer. Each BN layer adds four parameters to each input: γ, β, μ, and σ. The last two parameters, μ and σ, are moving averages and are not affected by backpropagation, so they are non-trainable parameters.

[0083] After the model is set up, the artificial neural network training begins. During training, the Adaptive Moment Estimation Algorithm (Adam) optimizer is used. It absorbs the advantages of the adaptive learning rate gradient descent algorithm and the momentum gradient descent algorithm. It can adapt to sparse gradients and alleviate the problem of gradient oscillation. The formula of the Adam optimizer is as follows. The first formula is the first-order moment of the historical gradient, which can be regarded as the mean of the gradient; the second formula is the second-order moment of the historical gradient, which can be regarded as the variance before subtracting the mean, which is used to obtain the learning rate weight parameter of each weight parameter; the third formula is the parameter update value of the Adam algorithm:

[0084] m t =β1*m t-1 +(1-β1)*g t ;

[0085] v t =β2*v t-1 +(1-β2)*g t2 ;

[0086] variable=variable-(lr t *m t ) / ((sqrt(v t ))+ε);

[0087] Wherein, β1 and β2 are the decay rates of two moving averages, which are 0.9 and 0.99 in the present invention; g t is the gradient; lr t is the learning rate, which is set to 0.001 in this invention. The subscript t-1 represents the historical moment, and t represents the current moment.

[0088] The loss function of the model adopts the mean squared error (MSE) function, which is the square of the difference between the predicted value and the target value. Let N be the number of training iterations. The function calculation formula is as follows:

[0089] MSE(y act ,y pre )=∑ i＝1 N (y act -y pre ) 2 / N;

[0090] Among them, y act Represents the target value, y pre Represents the predicted value.

[0091] However, in order to monitor the model more intuitively, all errors in the present invention are expressed as the mean absolute error (MAE) function, which is calculated as follows:

[0092] MSE(y act ,y pre )=∑ i＝1 N |y act -y pre | / N;

[0093] Among them, y act Represents the target value, y pre Represents the predicted value.

[0094] The training method uses 5-fold cross-validation. The available data is divided into five partitions. Five identical models are instantiated, each trained on four partitions and evaluated on the remaining partition. The model's validation score is the average of the five validation scores. K-fold validation fully utilizes all data, helping to promote network generalization and prevent overfitting.

[0095] In the 5-fold validation, the average absolute delay error of each fold validation is as follows:

[0096] When the number of cross-validation folds is 1, the mean absolute error is 254.11; when the number of cross-validation folds is 2, the mean absolute error is 257.10; when the number of cross-validation folds is 3, the mean absolute error is 248.08; when the number of cross-validation folds is 4, the mean absolute error is 246.81; and when the number of cross-validation folds is 5, the mean absolute error is 251.88. The average score of the 5-fold validation is taken as the final mean absolute error value of the model, so the final error value is 251.60 clock cycles.

[0097] After completing the parameter adjustment of the on-chip network delay prediction model, retrain on all training data using the optimal parameters. At this time, 90% of the data is used as the training set and 10% of the data is used as the test set to obtain the final on-chip network delay prediction model. The optimization process of the neural network model can be divided into two stages. In the first stage, the predicted value is calculated by the forward propagation algorithm, and the predicted value is compared with the true value to obtain the difference between the two. Then, in the second stage, the gradient of the loss function for each parameter is calculated by the backpropagation algorithm, and then the gradient descent algorithm is used to update each parameter according to the gradient and learning rate. The convergence of the loss value of the final prediction model is shown in the figure below. Figure 3 shown.

[0098] like Figure 4 As shown, a scatter plot comparison of the predicted values ​​and target values ​​in some test sets is shown.

[0099] like Figure 5 As shown in , the error of the predicted value in part of the test set is shown. Figure 5 It can be seen that the errors of the predicted values ​​are all less than 5%, and the model fit is good.

[0100] Finally, the saved on-chip network delay prediction model is loaded and combined with an exhaustive, heuristic, and iterative algorithm platform to explore the optimal hardware mapping. The above schematically describes the present invention and its implementation methods. This description is not restrictive and the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. The figures shown in the accompanying drawings are only one embodiment of the present invention. The actual structure is not limited to this. Any figure mark in the claims should not limit the claims involved. Therefore, if a person of ordinary skill in the art is inspired by this and, without departing from the purpose of the present invention, designs a structure and embodiment similar to this technical solution without inventiveness, they should fall within the scope of protection of this patent. In addition, the word "comprising" does not exclude other elements or steps, and the word "a" before an element does not exclude the inclusion of "a plurality" of such elements. Multiple elements stated in a product claim can also be implemented by a single element through software or hardware. Terms such as first and second are used to indicate names and do not indicate any specific order.

[0101] The preferred embodiments of the present invention are described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the scope of protection of the present invention.

Claims

1. A method for predicting network-on-chip delay based on artificial neural network, characterized in that: The following steps are involved: Step 1: Collect random hardware mappings and their corresponding network feature values, and combine the hardware mappings and network feature values ​​into a dataset, which includes a training set and a test set. Step 2: Setting the network structure and training parameters of the on-chip network delay prediction model according to the data set; The prediction model includes an input layer, several fully connected hidden layers, and an output layer. The number of neurons in the input layer is the number of eigenvalues ​​of the input hardware mapping. The output layer has only one neuron, representing the predicted simulation time required for the on-chip network. Each fully connected hidden layer is followed by an activation function. Step 3: Use the optimizer to train the NOC delay prediction model using the K-fold cross-validation method to obtain the optimal hyperparameters of the model. The K-fold cross-validation method uses a predetermined value of fold cross-validation, divides the data into a predetermined value of partitions, instantiates a predetermined value of identical models, trains each model on the predetermined value minus one partition, and evaluates it on the remaining partition. The validation score of the model is the average of the predetermined value of validation scores; Step 4: Retrain the NOC delay prediction model on all training data using the optimal hyperparameters to obtain the final NOC delay prediction model. Step 5: Evaluate the generalization ability of the final on-chip network delay prediction model on the test set. If it meets the requirements, save the model; otherwise, adjust the model network structure and retrain; Step 6: Load the saved on-chip network delay prediction model and combine it with the exhaustive, heuristic, and iterative algorithm platform to obtain the optimal hardware mapping solution.

2. The on-chip network delay prediction method based on artificial neural network according to claim 1, characterized in that: The data set in step 1 specifically includes: input mapping of the on-chip network, total computing delay, layered computing delay, spatial network delay, total time domain network delay, total number of hops in the on-chip network, number of inter-layer hops, time domain network delay in the X and Y directions, inter-layer congestion characteristic values, and allocation of computing units in the on-chip network.

3. The on-chip network delay prediction method based on artificial neural network according to claim 2, characterized in that: The input mapping of the on-chip network is specifically as follows: the computing power of a single computing unit of the on-chip network platform is set to M neurons, the convolutional neural network is converted into an artificial neural network-like network, M neurons are grouped into a group, and the grouped neuron groups are assigned to different on-chip network computing units for calculation, and the on-chip network computing unit serial numbers are obtained. The array consisting of the on-chip network computing unit serial numbers corresponding to the neuron group serial numbers is the input mapping of the on-chip network.

4. The on-chip network delay prediction method based on artificial neural network according to claim 2, characterized in that: The total computational delay is the sum of the computational unit delays of all neural network layers; the layered computational delay is the sum of the computational unit delays assigned to computational tasks in different neural network layers, where the computational unit delay characteristics are determined by the number of input neurons and the number of output neurons. The estimation formula is as follows: T com =n in ×[(n out +n mac -1) / n mac ]+{(n out +n mac -1)}mod n mac +1; Where [] is the floor operator, mod is the modulus operator, n in is the number of neurons input into a single computational unit node, n out is the number of neurons output in a single computational unit node, n mac The number of built-in multiplier-accumulators for the processing unit.

5. The method for predicting network-on-chip delay based on artificial neural network according to claim 2, characterized in that: The inter-layer hop count is the sum of the network hop counts of different neural network layers; the total on-chip network hop count is the sum of the inter-layer hop counts of different neural network layers, where the network hop count is determined by the connection relationship between computing units, specifically: After determining a mapping, the connection relationship between each computing unit on the chip network can be determined. If the routing method is XY routing, the number of links from the source node to the destination node is the network hop count between the two nodes. The row and column information of the computing unit in the two-dimensional mesh architecture of the on-chip network is obtained through the serial number of the two connected computing units. The network hop count calculation formula is as follows: hops i→j =|row(PE i )-row (PE j )|+|col(PE i )-col (PE j )|; Among them, PE i and PE j are the numbers of the two connected computing units, row(PE) and col(PE) represent the row number and column number of the current PE in the two-dimensional grid architecture of the on-chip network, respectively.

6. The on-chip network delay prediction method based on artificial neural network according to claim 2, characterized in that: The calculation formula for the airspace network delay is as follows: T spa_delay =h(m)*(T router_pipline + T link )+T size-1 +T NI ; Where m is the mapping, h(m) is the total number of hops determined by the mapping, and T router_pipline is the routing delay, T link is the link delay, T size-1 T is the value related to the number of flow control units in the communication transmission packet, NI The corresponding delay for network interface input and output.

7. The on-chip network delay prediction method based on artificial neural network according to claim 2, characterized in that: The total time domain network delay and inter-layer congestion characteristic value are calculated as follows: The links connecting all computing units are set as set {L}, where the horizontal links are denoted as {L Xij }, the vertical direction is recorded as {L Yij }, for any two adjacent layers of transmission, the total number of N Path, n The amount of data on the path is flits n , let the bandwidth be b , the time domain network delay in the X direction is the link L Xij The excess data volume that exceeds the bandwidth is calculated using the following formula: congestion Xij =∑ n∈{n}Xij flits n -b ; where {n} Xij For L Xij The set of all data packet transmission path numbers; The calculation formula for the time domain network delay in the Y direction is as follows: Congestion Yij =∑ n∈{n}Yij flits n -b ; The total time domain network delay is calculated as follows: Congestion total =∑ i ∑ j congestion Xij +∑ i ∑ j Congestion Yij The inter-layer congestion characteristic value is the total excess data volume between layers, and the total time domain network delay is the sum of the inter-layer congestion characteristic values.

8. The on-chip network delay prediction method based on artificial neural network according to claim 1, characterized in that: The on-chip network is a two-dimensional mesh network.

9. The on-chip network delay prediction method based on artificial neural network according to claim 1, characterized in that: The method also includes preprocessing the data set, performing target encoding and deviation standardization on the network feature values ​​and the hardware mapping feature values.

10. The on-chip network delay prediction method based on artificial neural network according to claim 1, characterized in that: It also includes adding a batch normalization layer before each hidden layer in step 2 to accelerate the convergence of the model; The activation function uses a linear correction function to increase the nonlinearity of the network, and the optimizer uses an adaptive moment estimation algorithm for training, at which time the prediction error is the lowest.

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