Segmentation or cross-section of high aspect ratio structures

Abstract

The invention relates to identifying ring structures in columns of high aspect ratio (HAR) structures. For the segmentation of the rings, a machine learning logic is used. A two-step training method of the machine learning logic is described herein.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to German Patent Application No. DE 102021 110054.2, filed on April 21, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to a three-dimensional circuit pattern inspection and measurement technique using cross-sectional imaging of integrated circuits. More specifically, the invention relates to a method for obtaining 3D volumetric images of channels or high aspect ratio (HAR) structures within an integrated semiconductor sample, and to a corresponding computer program product and a corresponding semiconductor inspection apparatus. This method, computer program product, and apparatus can be used to quantitatively measure, detect defects, review defects, and inspect the shape, cross-section, tilt, or trajectory of channels or HAR structures within an integrated semiconductor sample using a scanning charged particle microscope. Background Technology

[0004] Semiconductor structures are among the most delicate man-made structures, containing only a very small number of imperfections. These rare imperfections are the features that defect detection, defect review, or quantitative metrology devices are looking for.

[0005] The fabricated semiconductor structures are based on prior knowledge. For example, in logic type samples, metal lines are parallel to metal layers or high aspect ratio (HAR) structures, or metal vias are perpendicular to metal layers. The angle between metal lines in different layers is 0° or 90°. On the other hand, for VNAND type structures, it is known that their average cross-section is spherical.

[0006] Integrated semiconductors are fabricated by processing a series of layers on a silicon substrate using planar integration technology. Each layer is first planarized and then patterned within a photolithography process using a projection exposure apparatus. The photolithographic pattern is transferred into the silicon layers using various techniques, including etching, deposition, doping, or implantation. Figure 1 shows a cross-section perpendicular to a set of layers. The integrated semiconductor 50 comprises a set of layers 54.1, 54.2, ... 54.22, which are fabricated using planar integration technology parallel to a top surface 52 extending in the xy direction. Beyond the bottommost layer 54.22 is a bulk silicon substrate 51 of the semiconductor substrate or wafer, the full depth of which is not shown. The bottommost layer 54.22 is a layer in the silicon substrate in which a doped structure 58 is formed, for example, by implantation. On top of this layer, a series of so-called metal layers, consisting of metal conductors such as metal layers 54.1, 54.3, ... 54.17, alternate with a series of isolation layers such as isolation layers 54.2, 54.4, ... The isolation layer includes interconnections to contact two adjacent metal layers, such as a via 55 between a metal structure 56 in metal layer 54.1 and a metal structure in metal layer 54.3. The bottom metal layer includes a series of gates 57 having contacts 59 in the adjacent isolation layer.

[0007] As depth increases in the z-direction, the minimum feature size within the layers becomes smaller. The current minimum feature size, or critical size, of the bottommost, most critical layer is actually below 10 nm, for example, 7 nm or 5 nm, and will approach below 3 nm in the near future. With this slight increase in minimum feature size, the requirements for the lateral alignment of the layers in the x and y directions become increasingly stringent. The lateral stacking precision of two layers is typically on the order of one-third of the minimum feature size of the two layers. Therefore, the lateral alignment of the bottommost layer must be within a few nanometers, and will be even below 1 nm in the near future.

[0008] Figure 2 This illustrates another example of a cross-section through a semiconductor device, such as a NAND memory device. In this example, several pillars (such as the three pillars indicated by reference numeral 60) extend through a large set of metal and insulating layers 54.1, ... 54.k, ... 54.z, establishing conductive connections perpendicular to said layers. Pillar 60 is also called a HAR (High Aspect Ratio) structure, or sometimes a contact channel. Although the metal structure parallel to surface 52 within the metal layer is fabricated in one go using high-precision planar fabrication techniques, pillar 60 is formed in each subsequent layer by a series of large or small metal structures stacked on top of each other. Therefore, pillars may suffer some damage, thus becoming errors in the fabrication of individual planar layers and overlap errors between subsequent planar layers. However, errors or defects within the pillars limit the performance of the semiconductor device or may cause the device to malfunction. One type of pillar is the so-called memory channel in a 3D memory chip.

[0009] Existing techniques for analyzing integrated semiconductor devices currently employ 2D imaging methods. For example, a wafer or thin film is formed from the semiconductor device via ion beam grinding, and a thin sample is extracted using a probe. The thin film can be a so-called "planar view" or "cross-sectional view" sample, which can be parallel or perpendicular to the integrated semiconductor device. The thin film is further analyzed by, for example, scanning electron microscopy (SEM or STEM) or transmission electron microscopy (TEM). This method requires the removal of material before or after channels or pillars, which can lead to inaccurate measurements. Parts of pillars, holes, or channels may have been removed from the wafer and are lost from the imaging film.

[0010] Another approach is to generate a 2D image of a single intersecting plane parallel or perpendicular to the integrated semiconductor device, which is produced by grinding and imaging using intersecting beams or a dual-beam device. However, as mentioned earlier, HAR pillars, holes, or channels are manufactured with shapes that are not always predictable or known. They can be twisted and bent and extend beyond the 2D intersection point of the plane. 2D techniques cannot capture the true path or trajectory of these structures, as well as their shape characteristics, because HAR pillars, holes, or channels are not limited to the intersecting plane. Furthermore, the cross-sectional surface used for 2D imaging can be degraded by an effect called curtaining, causing the cross-sectional surface to display some ripples, and the 2D image may only contain a portion of the semiconductor structure. 2D imaging methods only capture a portion of its shape where that portion intersects with the imaging surface or sheet body.

[0011] Recently, 3D volumetric image generation has been introduced. 3D volumetric images are generated via cross-sectional imaging techniques that utilize a charged particle beam system to slice and image an integrated semiconductor to determine a 3D volumetric image of a predetermined volume within the integrated semiconductor. This cross-sectional imaging technique involves the generation and storage of a large number of 2D cross-sectional images, as well as the registration of these 2D cross-sectional images within the volume to generate a high-precision 3D volumetric image. The charged particle system may include an electron microscope (SEM) for imaging and a focused ion beam (FIB) system for slicing, or an ion beam system for both slicing and imaging.

[0012] Therefore, identifying errors, defects, or structural deviations (including the internal structure of the pillar or hole) is a problem. In particular, memory channels and similar pillars may have internal substructures, such as several concentric rings in cross-section. Automating the identification of such substructures in a manner that allows for the determination of errors or defects is a challenge. Summary of the Invention

[0013] One object of this invention is to provide an improved method for identifying substructures in the cross-section of a HAR (Hybrid Anomaly) structural column, for example, in the context of obtaining a 3D volumetric image of the column or HAR structure. In some specific embodiments, this method allows for accurate 3D reconstruction of the column or HAR structure from a series of cross-sectional images.

[0014] A specific embodiment uses a trained machine learning logic to identify substructures, particularly rings, in the cross-section of a column. The first aspect concerns training this machine learning logic.

[0015] According to a specific embodiment, a method for training machine learning logic to segment the column cross-section ring of a high aspect ratio HAR structure is provided, the method comprising:

[0016] Provides cross-sectional images of multiple columns;

[0017] Binary annotation of rings in cross-sectional images is performed using two alternating labels;

[0018] The first machine learning logic is trained based on the binary annotation;

[0019] The trained first machine learning logic is used to segment the cross-sectional image or a further cross-sectional image to provide a binary segmented image;

[0020] Segmentation loops in multi-level annotated binary segmentation images to provide multi-level annotated images; and

[0021] Based on the multi-level annotated images, a second machine learning logic is trained as a machine learning logic for segmenting loops.

[0022] Training can be improved or facilitated by using this two-step training process with a first machine learning logic and a second machine learning logic. As used herein, machine learning logic refers to an entity that classifies and performs segmentation of objects, in this case, identifying parts of a ring based on machine learning techniques (sometimes also called artificial intelligence (AI)). Machine learning logic is sometimes also referred to as a model. Segmentation typically refers to identifying individual parts of an object (e.g., a ring in this case) so that said parts can be used for further analysis or other processing. Examples of machine learning logic may include, for example, decision trees, vector machines, or various types of neural networks, such as deep neural networks, adversarial networks, etc.

[0023] In some specific embodiments, the first machine learning logic may be a less complex model than the second machine learning logic. For example, the first machine learning logic may include a random forest model, and / or the second machine learning logic may include a neural network.

[0024] In one specific embodiment, the method may further include retraining the first machine learning logic based on the corrected binary segmented image to improve training.

[0025] In one specific embodiment, training the second machine learning logic may be based on a first portion of a multi-level annotated image, and the method further includes testing the trained second machine learning logic based on a second portion of a multi-level annotated image different from the first portion.

[0026] According to the second aspect, a method for analyzing the ring cross-section of a column in a high aspect ratio HAR structure is provided, the method comprising:

[0027] Provide a cross-sectional image of the column;

[0028] The rings are segmented in the cross-section using trained machine learning logic; and

[0029] The parameters of the ring are determined based on the segmented ring.

[0030] In this way, the internal structure of the column can be analyzed, such as memory channels.

[0031] This machine learning logic is a second machine learning logic trained using the first aspect method.

[0032] In one specific embodiment, the method may further include identifying the contour of the ring based on the segmented ring, wherein parameters are determined based on the identified contour.

[0033] In one specific embodiment, the parameters may include parameters selected from a group consisting of the ring radius and the ring diameter.

[0034] In one specific embodiment, the method may further include identifying deviations between parameters and nominal or expected values.

[0035] The techniques discussed in this paper can be specifically implemented or used for high-precision 3D reconstruction of HAR structures using 3D volumetric images or 3D shapes obtained through integrated circuit cross-section methods, and more specifically, methods, computer program products, and apparatus for obtaining 3D volumetric images of HAR structures.

[0036] For example, in one specific embodiment, the method may further include:

[0037] Obtain 3D tomographic images of semiconductor samples;

[0038] Select a subset of 2D cross-sectional image segments from the 3D tomographic image that include cross-sectional images of the column, each segment containing a set of cross-sectional images of the HAR structure;

[0039] Identify the outline of each HAR structure within the set of HAR structures in the subset of 2D cross-sectional images;

[0040] Extract deviation parameters from the HAR structure profile of this set of HAR structures;

[0041] Analyze the aforementioned deviation parameters.

[0042] The deviation parameter includes one or more of the following:

[0043] Displacement from the ideal position;

[0044] Deviation in radius or diameter;

[0045] Deviation from the cross-sectional area;

[0046] Deviation from the cross-sectional shape.

[0047] In one specific embodiment, the step of analyzing the deviation parameters may include performing statistical analysis on at least one deviation parameter of at least one HAR structure in a set of HAR structures.

[0048] This method allows for quantitative measurement of the diameter and shape of the cross-section of a HAR structure, as well as determination of the trajectory of the HAR structure within an integrated circuit. Furthermore, this invention provides a method, computer program product, and apparatus for determining the channel trajectory through an integrated semiconductor device, and for determining the deviation of the channel trajectory from an ideal channel trajectory with an accuracy below a few nanometers.

[0049] In one specific embodiment of the invention, the 3D shape of such pillars within an integrated semiconductor sample is measured via a cross-sectional method that utilizes a charged particle beam system to slice and image the integrated semiconductor to determine a 3D volumetric image of a predetermined volume within the integrated semiconductor. This cross-sectional imaging technique includes the generation and storage of a set of cross-sectional images. The charged particle system may include an electron microscope (SEM) for imaging and a focused ion beam (FIB) system for slicing, or an ion beam system for slicing and imaging.

[0050] 3D memory chips (VNAND or 3D RAM) consist of numerous columnar structures running parallel to each other, sometimes referred to as memory channels or "pillars." According to a specific embodiment or the present invention, samples containing such 3D memory devices can be studied using cross-sectional imaging techniques of a FIB-SEM microscope. A focused ion beam (FIB) is used to remove a thin layer of material from a probe slice by slice. In one example, the FIB is configured such that the slices are oriented perpendicular to the pillar / channel axis, and each newly exposed surface will contain a covered area of ​​pillars that are typically circular and form a hexagonal grid. Each newly exposed surface or slice is imaged one by one by a SEM (scanning electron microscope) or another charged particle imaging microscope as the FIB is removing material from the probe. The 3D shape of the pillars is reconstructed using a stack of 2D slice images. The typical number of pillar-covered areas in a slice can reach hundreds. A typical image slice stack can contain hundreds of images. In most applications, a high degree of automation in reconstructing the pillars in 3D is essential. An automated workflow for this reconstruction is described in one specific embodiment.

[0051] In one specific embodiment of the present invention, at least one cross-sectional image of a HAR structure is determined and extracted through image processing and / or pattern recognition within the intersecting plane of the 3D volumetric image of the integrated circuit. This allows for the precise determination of the exact location of the cross-sectional image of at least one HAR structure within a predetermined volume. By repeatedly determining and extracting subsequent cross-sectional images of at least one HAR structure within subsequent intersecting planes of the 3D volumetric image of the integrated circuit, an isolated 3D volumetric image of the HAR structure within a predetermined volume of the integrated semiconductor is generated.

[0052] In one specific embodiment of the invention, cross-sectional images of at least one HAR structure are automatically evaluated through image processing to extract shape characteristics, such as the lateral dimensions of the cross-section. In one example, an ellipse approximates the cross-section of at least one HAR structure. In another example, shape attributes include the area of ​​the cross-sectional image. In one example, the shape attributes of the HAR structure are used for defect detection or defect review.

[0053] In one specific embodiment, the evaluation further includes extracting the center of a cross-sectional image of at least one HAR structure within the 3D volumetric image with high precision. The center extraction can be accomplished by calculating the centroid of the cross-sectional image of at least one HAR structure.

[0054] A 3D channel trajectory or 3D trajectory is generated by repeatedly evaluating subsequent cross-sectional images of at least one HAR structure within subsequent intersecting planes of a 3D volumetric image of the integrated circuit. In one example, the 3D placement deviation trajectory originates from the deviation of the 3D trajectory from the ideal or design trajectory. Since the coordinate system can be configured such that the design trajectory extends in the z-direction perpendicular to the top surface of the integrated semiconductor, the 3D placement deviation trajectory is evaluated along the 3D trajectory of the channel or in the z-direction. From the 3D placement deviation trajectory, the maximum placement deviation is derived. In one example, the maximum tilt angle of the 3D trajectory relative to the z-direction is derived. In another example, the wobble or twist shape of the 3D trajectory relative to the z-direction is derived.

[0055] In one specific embodiment, shape characteristics are repeatedly generated along a 3D trajectory of the HAR structure within a predetermined volume within the integrated semiconductor in a similar manner. Since the coordinate system can be configured such that the designed trajectory extends in the z-direction, perpendicular to the top surface of the integrated semiconductor, the shape characteristics are evaluated along the 3D trajectory of the channel or in the z-direction.

[0056] In one embodiment, the conductivity of the channel is determined by the minimum cross-sectional area within the channel. In another embodiment, peaks, defects, interruptions, or inclusions within the channel boundary surface are extracted.

[0057] In one specific embodiment, the 3D trajectory and shape characteristics of at least two HAR structures are determined and evaluated. In addition to the 3D trajectory and shape characteristics of individual HAR structures, the relative characteristics of at least two HAR structures are also evaluated. Relative attributes include channel proximity, such as the distance between 3D trajectories, and the minimum distance between the outer boundaries of the at least two HAR channels.

[0058] In one specific embodiment, the method of the present invention includes analyzing a set of HAR structures within an integrated semiconductor device, including obtaining a 3D tomographic image of a semiconductor sample, selecting a subset of 2D cross-sectional image segments from the 3D tomographic image, each of which contains a cross-sectional image of a set of HAR structures, identifying the outline of each HAR structure within the set of HAR structures in the subset of 2D cross-sectional image segments, extracting deviation parameters from the HAR structure outlines of the set of HAR structures, and analyzing the deviation parameters, wherein the deviation parameters include one or more of the following: displacement from an ideal position, deviation from a radius or diameter, deviation from a cross-sectional area, and deviation from a cross-sectional shape.

[0059] In one specific embodiment, the method further includes performing a statistical analysis on at least one deviation parameter of at least one HAR structure in the group of HAR structures. In one example, the deviation parameter from the displacement of the ideal position includes the tilt or sway of the HAR structure.

[0060] In one specific embodiment, the method further includes the step of obtaining a 3D tomographic image, comprising obtaining the 3D tomographic image by means of a charged particle microscope having at least one charged particle optical column.

[0061] In one specific embodiment, the method further utilizes a charged particle microscope comprising a focused ion beam system (FIB) and a scanning electron microscope (SEM) configured at an angle between 45° and 90° relative to each other. In one example, the relative angle is 90°, such that the FIB is oriented parallel to the surface of the semiconductor sample, and the SEM is oriented perpendicular to the surface of the semiconductor sample.

[0062] In one specific embodiment, the method further includes image processing, edge detection, or pattern recognition in the step of identifying at least one contour of each HAR structure.

[0063] In one specific embodiment, the method further includes calculating the minimum or maximum value of at least one deviation parameter of at least one HAR structure in the set of HAR structures.

[0064] In one specific embodiment, the method further includes calculating at least the distance between two adjacent HAR structures and calculating the minimum distance between two adjacent HAR structures.

[0065] In one specific embodiment, the method further includes detecting and locating at least one local defect or inclusion within at least one HAR structure in the set of HAR structures.

[0066] In one specific embodiment, the method further includes acquiring images using a high-resolution scanning electron microscope and identifying and locating the internal structure of at least one HAR structure, the HAR structure comprising a core and at least one layer surrounding the core.

[0067] In one specific embodiment, the method further includes extracting at least one deviation parameter from the internal structural profile of at least one HAR structure and analyzing the deviation parameter.

[0068] In one specific embodiment, the method further includes steps of process characterization, process optimization, and / or process monitoring.

[0069] According to a specific embodiment of the present invention, the apparatus is a semiconductor inspection apparatus comprising: a focused ion beam (FIB) adapted to grind a series of cross sections of an integrated semiconductor sample; a scanning electron microscope (SEM) adapted to image the series of cross sections of the integrated semiconductor sample; and a controller for operating a set of instructions to perform steps according to at least one specific embodiment of the foregoing method, wherein the focused ion beam (FIB) and the electron microscope (SEM) form an angle of approximately 90° with each other.

[0070] In one specific embodiment, the wafer inspection method includes the following steps: obtaining a 3D volumetric image of an inspection volume within the wafer, and selecting a set of templates representing cross-sections of relevant semiconductor features within the inspection volume. The relevant semiconductor features may include one of the following: metal lines, vias, contacts, fins, HAR structures, HAR channels, or gate structures. The method further includes determining the center position of the cross-sections of the relevant semiconductor features within the inspection volume, for example, by associating the templates with a set of 2D cross-sectional images of the 3D volumetric image. The method further includes the step of determining the contour of the relevant semiconductor features within the 3D volumetric image, and the step of determining parameters of at least one representative primitive that matches the contour of the relevant semiconductor feature. The method further includes the step of analyzing the parameters. In one example, the method further includes the step of assigning a subset of multiple cross-sections of the relevant semiconductor feature to a specific relevant semiconductor feature. The method may further include the step of generating a 3D volumetric image from a sample wafer using a slicing and imaging method with a dual-beam system. The dual-beam system may include a FIB beam for slicing and a charged particle imaging microscope, such as SEM or helium ion microscopy (HIM), for imaging. The method may further include the steps of removing a sample wafer from the wafer and securing the sample wafer. This removal step may include attaching the sample wafer to a probe, moving the sample wafer, and attaching the sample wafer to a holder. In one example, the step of removing the sample wafer from the wafer is performed in a dual-beam apparatus. The dual-beam apparatus may further include a laser beam apparatus configured to cut a semiconductor sample from the wafer, and the method may include performing laser cutting in the wafer. The parameter analysis step may include at least one of calculating a statistical average and a statistical deviation, comparing with a reference primitive, or relating to wafer coordinates. Thus, a set of deviation parameters is obtained. According to a specific embodiment, the method includes classifying the deviation parameters into a certain type of defect. Examples of such defects include "alignment error," "distorted shape," "too small distance," "too small diameter," etc.

[0071] According to one aspect of the invention, the invention relates to a computer program product having program code adapted to perform any of the foregoing methods. The program code can be written in any possible programming language and can be executed on a computer control system. Such a computer control system may comprise one or more computers or processing systems. The computer program may be provided on a tangible storage medium.

[0072] According to one aspect of the invention, the invention relates to a semiconductor inspection apparatus adapted to perform any of the methods described according to any of the foregoing specific embodiments; as well as a computer program and a storage medium. Attached Figure Description

[0073] Refer to the following figures for a more comprehensive understanding of the invention:

[0074] Figure 1a , Figure 1b A diagram of a semiconductor device;

[0075] Figure 2 This is a cross-section of a NAND device;

[0076] Figure 3a and Figure 3b For the column and the column cross section;

[0077] Figure 4a and Figure 4b The deviation of the column from its ideal shape and appearance;

[0078] Figure 5 The method steps are as described in a specific embodiment of the present invention;

[0079] Figure 6a and Figure 6b This is for cross-beam microscopy and section imaging.

[0080] Figure 7a and Figure 7b 3D volumetric images and intersection images of NAND structures;

[0081] Figure 8 The result of image processing and contour extraction;

[0082] Figure 9a and Figure 9b This represents the set of outlines of two pillars and the distance between them;

[0083] Figure 10 Let be the displacement vector of a set of cylinders in an intersecting plane;

[0084] Figure 11 Let z be the locus (x-coordinate) of the three pillars passing through z;

[0085] Figure 12 Let z be the radius of the profile of the three pillars passing through z;

[0086] Figure 13 Let z be the eccentricity of the profile of the three pillars passing through z.

[0087] Figure 14 For statistical analysis of the displacement vectors of a set of columns passing through z;

[0088] Figure 15a and Figure 15b These are inclusions or localized defects in the column;

[0089] Figure 16a A high-resolution SEM image of a set of columns;

[0090] Figure 16b , Figure 16c The core of the column and the outline of the layer;

[0091] Figure 17 A simplified diagram of a 2D cross-sectional image slice through the column;

[0092] Figure 18 This is an illustration of a wafer inspection method, including the preparation steps for automated wafer inspection;

[0093] Figure 19 This is a schematic perspective view of a memory channel;

[0094] Figure 20 A diagram illustrating a method used to train machine learning logic;

[0095] Figure 21 Other diagrams illustrating methods used to train machine learning logic;

[0096] Figure 22 A 2D cross-sectional view of a memory channel with annotated substructures. Detailed Implementation

[0097] HAR structures (often also referred to as "pillars," "holes," or "channels") are fine, typically columnar and elongated structures that extend through a significant portion of an integrated semiconductor sample, oriented perpendicular to the metal layer. In this invention, the terms "HAR structure," "channel," or "pillar" will be used synonymously. Typical examples of HAR structures are... Figure 2 The image shows a view through a semiconductor memory device 50 (such as a NAND memory device). A HAR structure, such as a pillar or HAR structure, three of which are indicated by reference numeral 60, is part of a memory cell in which charge is injected, held, measured, and erased within the integrated electronic device. This HAR structure can be a memory channel. The HAR structure is fabricated during the fabrication of the integrated semiconductor in a series of adjacent layers 54.1, ..., 54.k, ..., 54.z, and consists of a series of segments stacked on top of each other. Examples of HAR structures are filled with insulating or conductive or semiconductor material, or a combination of both. Other examples of HAR structures have no material (unfilled holes).

[0098] Figure 3a and Figure 3bExamples of individual HAR structures 60 are illustrated. In this example, a series of segments (three shown as column segments 62) are formed at the top of each segment to form a long and thin column 60. The segments may be separated by small gaps 63. In another example not shown, a series of empty segments may be formed as a long and thin hollow column and then filled. The HAR structure has a high aspect ratio (HAR), where the height H is significantly greater than the diameter D. A typical aspect ratio is H / D > 5, where the height H ranges from a few nanometers to about 10 μm (micrometers), and the diameter D ranges from a few nanometers to about 1 μm (micrometers). In this example, as Figure 3b shown, in a cross-section perpendicular to the z-axis, the shape of the outer contour 66 of the HAR structure 60 is circular. The trajectory 64 of the column 60 is parallel to the z-direction and is located at Figure 3b the centroid of the circular shape of the outer contour 66 of the cross-section shown. For an ideal column 60, at each z-position, the designed area A of the cross-section within the contour 66 is constant. In addition to the diameter D, the radius R (i.e., half of the diameter D) of the ideal circular cross-section through the column is constant.

[0099] The HAR structure is formed, for example, by a large series or small metal structures in each subsequent layer, stacked on top of each other. Therefore, the HAR structure may suffer from several damages or deviations, thus becoming errors in the processing of individual planar layers and overlapping errors between subsequent planar layers. However, errors or defects within the HAR structure limit the performance of the semiconductor device or may cause this device to malfunction. Figure 4a and Figure 4b show examples of such defects in a simplified model. Figure 4a show the effects of placement or overlapping errors. For example, due to the systematic alignment error between the individual layers of the integrated semiconductor, the trajectory 74.1 of the HAR structure 60 is tilted at an angle θ(70) with respect to the z-axis, as shown in the left half of Figure 4a . In the example shown on the right, the non-linear or distorted shape of the trajectory 74.2 is the result of statistical alignment errors. Due to the statistical random alignment errors between the individual layers of the integrated semiconductor, the three column segments shown as 72.1 may be laterally displaced. Therefore, the trajectory passing through the centroid of each cross-section of the column 60 deviates from the designed trajectory and can reach a maximum deviation T max (not shown).

[0100] In addition, column segments (such as segment 72.2 with a larger diameter D1 or segment 72.3 with a smaller diameter D2 < D1) may deviate from the ideal designed dimensions and circular shape, thereby also causing a change in the lateral position of the trajectory 74.2. This deviation in lateral dimensions and shape is as shown in Figure 4bAs shown. The upper half illustrates an elliptical profile 76.1 of the HAR structure 60 with diameters Dx(z) and Dy(z) at the z-position of the cross-section, while the lower half illustrates a general deviation of the circular shape 76.2 of the cross-section from the ideal circular shape 66 of the HAR structure 60. Profile 76.2 shows different diameters in different directions, with a minimum diameter of D3. This error or deviation may be caused by manufacturing errors in planar integration technology, such as due to photolithographic mask or imaging errors. The HAR structure may also be partially filled with material, or there may be material filling errors, or gaps may exist within the HAR structure 60. This defect or inclusion may be widespread across the column or locally confined to a small area along the column direction (z-direction). Therefore, the cross-sectional area A(z) of the HAR structure may deviate from the designed area A and vary along the z-axis, and may have a minimum area A at a specific z-position. min .

[0101] Deviation from ideal or design parameters is important for the process development and characterization of integrated semiconductor devices. Deviation can be an indicator of process yield and process stability, and therefore an indicator of reliability, as well as the reliability and performance of the integrated semiconductor device itself. In one specific embodiment of the invention, the amount of deviation from ideal or design parameters, such as trajectory T(Z) or cross-sectional area A(z), is measured. Figure 5 An example of an implementation of a method for analyzing HAR structures is provided. This method includes analyzing a set of HAR structures within an integrated semiconductor device, comprising obtaining a 3D tomographic image of a semiconductor sample; selecting a subset of 2D cross-sectional image segments from the 3D tomographic image, each segment containing cross-sectional images of a set of HAR structures; identifying the contour of each HAR structure within the set of HAR structures in the subset of 2D cross-sectional image segments; extracting deviation parameters from the contours of the HAR structures in the set of HAR structures; and analyzing the deviation parameters. The deviation parameters include one or more of the following: displacement from an ideal position, deviation from radius or diameter, deviation from cross-sectional area, and deviation from cross-sectional shape. In addition to analyzing the overall characteristics of the pillars, Figure 5 The method further includes steps S5 and S6, which analyze the internal structure of the columnar memory channel according to a specific embodiment of the present invention. Although these steps are combined into... Figure 5 The method provides a comprehensive analysis of the columns, but it can also be combined with... Figure 5 The remaining analytical steps are used separately.

[0102] In step S1, a sample of the semiconductor device is loaded into the microscope chamber. This microscope will be explained in more detail below. First, the integrated semiconductor sample is prepared for the subsequent tomographic imaging method using methods known in the art. The sample can be produced by breaking the semiconductor wafer or by any other method known in the art (such as laser cutting). Alternatively, the sample can be prepared from the semiconductor wafer in the microscope chamber by laser cutting or charged particle beam grinding techniques known in the art. Alternatively, a groove can be milled into the top surface of the integrated semiconductor to access a cross-section approximately perpendicular to the top surface, or the integrated semiconductor sample can be cut from the integrated semiconductor wafer and removed in a blocky form. This processing step is sometimes referred to as “removal”. The sample removed from the wafer for further study preferably has a cuboid or blocky shape with a size of several millimeters, preferably about 100 μm. The sample is then prepared for the subsequent tomographic imaging step S2. Preparation may include alignment and positioning of the sample, initial grinding and polishing of selected surfaces of the sample, deposition of a protective layer, and generation of reference marks on the sample surface. The surface used for reference may be at least one single side or two or more surfaces of the sample.

[0103] In step S2, a 3D volumetric image of the sample is generated using a tomographic imaging method. A common method for generating nanometer (nm)-scale 3D tomographic data from a semiconductor sample is the so-called slicing and imaging method, meticulously fabricated, for example, using a dual-beam or intersecting-beam apparatus. In this semiconductor inspection apparatus, two particle optics systems are configured at an angle. The first particle optics system may be a scanning electron microscope (SEM), adapted to image a series of cross-sections of the integrated semiconductor sample. The second particle optics system may be a focused ion beam optics system (FIB), using, for example, gallium (Ga) ions, and adapted to grind a series of cross-sections of the integrated semiconductor sample. The semiconductor inspection apparatus further includes a controller for operating a set of instructions capable of performing the steps according to at least one specific embodiment of the method.

[0104] A method for generating 3D tomographic data to obtain at least first and second cross-sectional images includes subsequently removing the surface layers of the cross-section of an integrated semiconductor sample using a focused ion beam (FIB) to make a new cross-section available for imaging, and imaging the new cross-section of the integrated semiconductor sample using a charged particle beam. A focused ion beam (FIB) of Ga ions is used to cut layers at the edges of the semiconductor sample layer by layer, and each cross-section is imaged using a high-resolution scanning electron microscope (SEM), for example, with a resolution of several nanometers. The two particle optics systems, FIB and SEM, can be oriented perpendicularly to each other at an angle of approximately 90° or at an angle between 45° and 90°. From the sequence of 2D cross-sectional images, a 3D image of the integrated semiconductor structure is reconstructed. The distance dz of the 2D cross-sectional images can be controlled by FIB grinding or polishing processes and can be between 1 nm and 10 nm, preferably about 3-5 nm. Throughout this invention, "cross-sectional image" and "image slice" will be used as synonyms.

[0105] Figure 6aA schematic diagram illustrating a slicing and imaging method for obtaining a 3D volumetric image of an integrated semiconductor sample using a cross-beam microscope 1. The slicing and imaging method achieves three-dimensional (3D) volumetric image acquisition through a “step-and-repeat” approach. For simplicity, the description is shown with a bulk integrated semiconductor sample 10, but the invention is not limited to bulk sample 10. This sliced ​​material can be removed using several methods known in the art, including grinding or polishing at a grazing angle using a focused ion beam, but occasionally closer to perpendicular incidence is achieved using a focused ion beam (FIB) 5. For example, the ion beam 9 scans along the x-direction to form a new cross-section 2. The new cross-sectional surface 11 can then be imaged using a CPB (not shown) with a scanning electron beam 7. The cross-sectional surface layer 11 is raster-scanned by a charged particle beam (CPB) (e.g., electron beam 7), but a second FIB can also be used for imaging. A simplified raster of scanning imaging lines 8 is illustrated. The optical axis of the imaging system can be configured to be parallel to the z-direction, and therefore perpendicular to the axis of the FIB 5, or tilted at an angle 6 to the FIB axis or the y-direction. The CPB system has been used to image small regions of samples at a high resolution below 2 nm. A detector (not shown) collects secondary and backscattered electrons to reveal material contrasts within the integrated semiconductor sample, and different gray levels are visible in cross-sectional image 18. Metallic structures produce brighter measurements. Surface layer removal and cross-sectional image processing are repeated across cross-sections 3 and 4 and other surfaces at equidistant distances dz, resulting in a series of 2D cross-sectional images 20 of samples at different depths, to construct a three-dimensional 3D dataset. The distance dz between two subsequent image slices can be 1 nm–10 nm. For high-precision reconstruction, image registration is performed, which typically refers to precisely placing the cross-sectional image within the 3D volume. Image registration can be performed, for example, by referencing location markers or so-called feature-based registration. This 3D volumetric image generation is described in German patent application No. DE 10 2019 006 645.6, filed September 20, 2019, which is incorporated herein by reference. Representative cross-sectional image 18 was obtained by measuring a commercially available Intel processor integrated semiconductor wafer with 14nm technology. The crossbeam microscope 1 also includes several other devices and units, such as a stage with several degrees of freedom for sample positioning and movement, a detector, a gas source for deposition, an overview camera for navigation, manipulators for sample manipulation, a housing including a vacuum chamber, valves and interfaces, a power supply, and control devices to control the crossbeam microscope 1.

[0106] Figure 6bThe cross-sectional imaging workflow is further described below. The process begins with site preparation as described above. Then, a stack of 2D cross-sectional images is created by tandem FIB slicing and charged particle beam imaging. During grinding and imaging, the slice thickness is measured, and the focus and stigmation of the charged particle lens and FIB are adjusted to optimize the slicing and imaging results. The stigmation step is well known in the art and means adjusting the focus and spot size, for example, fine-tuning the charged particle beam column, to minimize aberrations such as stigmation. From the stack of 2D cross-sectional images, a 3D dataset can be determined. The cross-sectional images are registered and aligned with high precision, for example, by the method described in the aforementioned German patent application DE 10 2019 006 645.6.

[0107] Figure 17 A simplified example of a cross-sectional imaging method for a pillar or HAR structure is illustrated. A series of two-dimensional cross-sectional images or image slices are generated, including two two-dimensional cross-sectional images 18.3 and 18.4. Each cross-section contains a relevant semiconductor feature, such as cross-sections 78.3 and 78.4, where the relevant semiconductor feature is pillar 60 in this example.

[0108] The described 3D tomography has several advantages: it allows for the overall imaging of 3D structures. These structures can be, but are not limited to, HAR (high aspect ratio) memory channels, FinFETs, metal wires, vias, contacts, fins, or gate structures. Furthermore, the 3D volume can be viewed as a cross-section from any direction to visualize structural placement. In other words, arbitrary virtual cross-sectional images can be generated. 3D models can be determined from 3D datasets, allowing for the visualization and measurement of 3D features within the 3D model from any direction. Additionally, a wealth of dimensional statistics can be provided in both 2D and 3D.

[0109] Figure 7a The image shows a 3D volumetric image of a NAND memory device, comprising several pillars, including pillars 60.1 and 60.2. The NAND structure within the 3D volumetric image of the sample volume comprises pillars or HAR structures of several sets or groups 68.1 or 68.2 separated by structure 69.

[0110] Figure 7b Displaying a 2D cross-section or intersecting image through the intersecting plane 75 of the 3D volumetric image, parallel to the top surface of the NAND device, showing cross-sections of several pillars including cross-sections 78.1 and 78.2. The cross-sections also show cross-sections of pillar groups or HAR structure sets, such as pillar group 79 on the left.

[0111] In step S3, a series of intersecting images of the z-series passing through the 3D volume image are selected. This selection can be made, for example, by user instructions using a graphical user interface (GUI). For example, the user can select six planes forming the boundary of a cube containing pillars. In another example of routine checks, the selection can be performed automatically based on programming instructions combined with registration and image analysis of the 3D volume image. User input may be required to confirm the automatic selection, or the user can fine-tune it via the GUI. Thus, a group of pillars, such as group 68.1 or 79, is selected. A series of intersecting images of the z-series are extracted from the 3D volume image, each image containing several cross-sectional images, such as 78.1 or 78.2 of at least one pillar 60, 60.1, or 60.2. The z-series intersecting images extend parallel to the longitudinal direction of the HAR structure, and therefore parallel to the z-direction. Each intersecting image of the z-series represents the xy cross-section 78.1 or 78.2 of at least one pillar 60, 60.1, or 60.2 at different z-coordinates. Therefore, the z-series contains a set of intersecting images of the HAR structure or pillars.

[0112] In one specific embodiment, a so-called planar view slicing and imaging method is employed to acquire 3D volumetric images, wherein the semiconductor sample is ground and imaged layer by layer, starting from the top layer of the semiconductor sample. Therefore, a subset of 2D images obtained by charged particle microscopy corresponds to a z-series containing cylindrical cross-sections. In another specific embodiment, the planar view slicing and imaging method is selected to include a predetermined set of cylindrical or HAR structures, and the subsequently acquired 3D volumetric images correspond to 2D cross-sectional image segments of the z-series.

[0113] In step S4, the column cross-sections of the HAR structure set in the z-series 2D intersecting images are located through image processing. Image processing methods may include contrast enhancement, filtering, thresholding operations (image clipping), edge detection or pattern recognition through morphological operations, or combinations thereof, or other methods, all of which are well known in the art. The results are as follows... Figure 8 As shown, it displays a series of pillars after image processing. For example, pillar 80 has been identified and its contour 82 has been obtained through edge detection. For other examples of contour extraction, see Li Huanliang's "Computer-Based Image Contour Extraction Methods" at the Fourth National Conference on Electrical, Electronic and Computer Engineering (NCEECE 2015), 1185–1189 (2016). Figure 9a Displays the stacking of the z-series profiles 92 of the two columns 90.1 and 90.2 of the selected column group via z.

[0114] In step S7, deviation parameters such as the trajectory T(z) or area A(z) of the column passing through the cross-section of the z-series are derived. It can be understood that deviation parameters are the differences between the parameters and the design or ideal parameters, or variations in the parameters, for example, through z or for several columns, while the parameters should be constant through z or for several columns.

[0115] First, the number and center of a series of columns are calculated at a z-position in the z-series. The center can be calculated by calculating the centroid of the column's cross-sectional image, or by calculating the profile center using geometry or analytical components known in the art. For example, a best-fit circle or ellipse can be fitted to an outer profile, such as profile 82. Simplifying the fitting of geometry (e.g., circular or elliptical) helps reduce the amount of data used to describe the deviation of the column from the ideal or designed shape. For circular or elliptical shapes, the center is well-known. From the center of each column and at each z-position in the z-scan, the relative lateral displacement vector of the column center is derived. Figure 10 Displayed at magnification Figure 8 The displacement vector of the column shown.

[0116] Displacements can be evaluated relative to ideal column positions, as shown at point 96, where the ideal column position is 96. Ideal column positions can be derived individually from the column position design or CAD data, or through a best fit of a regular grid with an array of column centers passing through all z-planes. CAD data files can be in GDSII (Graphics Design Station / Graphics Data System II) or OASIS (Open Artwork System Exchange Standard) format. For example, a best fit can be achieved by minimizing the norm of the displacement vectors. The remaining displacement vectors of a column (such as displacement vector 97) along the z-series together form the trajectory T(z) of the column through the 3D volume of the sample. Figure 11 This displays the x-component of the displacement vector or trajectory T(z) of the three pillars from the depth of the top layer or in the z-direction.

[0117] In a specific embodiment, the distance Dnm(z) between the two pillars n and m is evaluated. For example... Figure 9a and 9b As shown, the minimum distance vector 94 between the two contours 92 is calculated using geometric or analytical methods as the minimum distance between the two contours of two adjacent pillars 90.1 and 90.2. Based on the minimum distance vector, the distance Dnm(z) of the pillar through the z series can be calculated as a scalar function of z. Figure 9b Examples show the two minimum distance vectors D23(z1) or D34(z2) between pillars p2 and p2 or p3 and p4 at positions z1 and z2, respectively. Adjacent structures with too small a proximity can easily reduce the functionality or reliability of NAND devices.

[0118] In one specific embodiment, step S5 includes performing pixel-based (image element) or voxel-based (volume element) segmentation on different rings and / or layers within the pillar using machine learning logic trained like a neural network. In another specific embodiment, step S6 then includes calculating parameters for the rings and / or layers based on the segmentation results of step S5. Steps S5 and S6 will be described in more detail below. Deviations from nominal or expected parameters can then be identified, for example, if the ring thickness or ring radius is too large or too small.

[0119] In one specific embodiment, step S7 includes calculating the radius R(z) of the best-fit circle that passes through the cylindrical profile z. The calculation of the best-fit circle can be performed by the minimum distance method or other methods known in the art. Figure 12 Show the radius R(z) of the three pillars obtained through z.

[0120] In one specific embodiment, step S7 includes calculating the eccentricity E(z) of the best-fit ellipse with respect to the cylinder profile. The calculation of the best-fit ellipse can be performed by the minimum distance method or other methods known in the art. Figure 13 Show the eccentricity E(z) of the three columns obtained by z.

[0121] In one specific embodiment, method step S7 further includes evaluating the surface area A(z) enclosed by the contours in the stack of 92. The evaluation can be performed from best-fit circle or best-fit ellipse analysis, or via numerical integration of the contour-covered area. In one specific embodiment, the volume V of the cylinder can be calculated from the stack of these contours 92, for example, by integrating the area A(z). In one specific embodiment, the minimum area A of each cylinder is calculated. min Alternatively, calculate the deviation between the measured area A(z) and the designed area, and express it as dA(z).

[0122] In one specific embodiment, the next step is step S8. In this step S8, the data obtained in step 5 is further analyzed, such as statistical characteristics, tilt angles, or maximum or minimum values. This analysis is useful for handling optimization and error tracking in the manufacturing of integrated semiconductor devices. For example, the tilt angle of a column is calculated by evaluating T(z) of a single column, for example, by calculating or deriving T(z) through gradients. Statistical analysis may include analyzing the trajectories T(z) of many columns, showing the deviation T. mean The average value of (z) and the standard deviation T of many columns sigma (z). Figure 14 This shows a set of pillars calculated by the average value of z, and thus, the standard deviation as z increases. Similarly, deviations such as the distance Dnm(z) between adjacent pillars or the area A(z) or dA(z) of the pillars can be analyzed. This example demonstrates the stability of planar integration techniques used in semiconductor circuit manufacturing, including error propagation as the number of planar layers increases with increasing z-position.

[0123] In one specific embodiment, the minimum or maximum value of the deviation is calculated. For example, the minimum area A of the column. min It is evaluated as the minimum value of A(z). Minimum area A min It can be used as an indicator of the column resistance R, where R = ρ·h / A min Here, R is resistance, ρ is resistivity, h is length, and A is length. min Let A be the cross-sectional area. Another specific embodiment includes calculating the minimum global area A of all columns. min,g In another example, the maximum displacement T of the column... max The maximum value of the T(z) norm is evaluated; another specific embodiment includes calculating the global maximum deviation T of all columns. max，g .

[0124] In step S9, the analysis and results of parameters such as the aforementioned deviation parameters are listed or stored in a file or memory. Deviation parameters can be compared to critical values, or a large number of check rounds can be accumulated to generate a database of check results. For example, if the minimum distance D... min Below a critical value, charge leakage may occur in the semiconductor device, and pillar blocks may fail. However, the method according to the invention allows for the inspection of semiconductor wafers with random samples during manufacturing or process development, and can indicate deviations from design or target values, thereby allowing for process control or optimization. According to one embodiment, the method includes classifying deviation parameters into a certain type of defect. Examples of such defects include "alignment error," "distorted shape," "too small distance," "too small diameter," etc.

[0125] In one specific embodiment, local defects in the column are evaluated, such as infill with incorrect material, particulate defects, contamination, or any other defects that cause local deviations in the circumferential cross-section, also referred to hereinafter as inclusions. An example is illustrated in... Figure 15a Inside. The two pillars show inclusions 102.1 and 102.3 in their cross-sections 101.1 and 101.2. The inclusions can extend over several intersecting images in the z-series intersecting images. After contour extraction (e.g.) Figure 15b As shown), the regions of contours 103.1 and 103.2, as well as inclusions 104.1 and 104.2, are extracted. Defective pillars are further identified by the mark "x". The regions of inclusions 104.1 and 104.2 increase the roughness of the outer surface contour of the pillars and may become sources of failure. For example, inclusions 104.1 and 104.2 are compared with reference inclusions to determine whether the device is malfunctioning or functioning properly. In one specific embodiment, the number of inclusions or marks in a set of pillars is evaluated to derive the processing error rate, and this is monitored, for example, on a set of fabricated semiconductor samples.

[0126] As described above, in one specific embodiment, for example in steps S5 and S6, the internal pillar structure is further analyzed. The pillar comprises, for example, an internal channel and several layers surrounding the internal channel, which are made of different conductive or semiconductor materials. For example, the layers surrounding the core channel may include tunnel layers, isolation layers, charge trapping layers, and blocking layers. In each intersecting image, these layers are identified by their material contrast and can be analyzed in the same manner as described above, for example, by external contours or outlines, to derive the trajectory of the annular regions of the layers. Figure 19 A schematic perspective view of memory channel 1900 is shown as an example of a column with such a ring structure, wherein the diameter of one of the rings is denoted as dr. Along its length, memory channel 1900 has word lines 1902 alternating with dielectric material 1901. Figure 16a An example of a high-resolution intersecting image of such an array of columns is shown, obtained by SEM in high-resolution mode. The figure shows a group of columns 109.1, 109.2, and 109.3. In an example of column 109.3, column 105 illustrates a core 106, a first intermediate layer 107, and a second outer layer 108; the second outer layer 108 and the first intermediate layer 107 are separated by an isolation layer 110. Figure 16b Extracted profiles 116, 117, and 118 of the core 106 and layers 107 and 108 in a set of profiles 115 of column 105 are illustrated, as well as profiles of some other columns, such as a set of profiles 111 and 112 of adjacent columns. A typical associated volume (e.g., several micrometers wide and up to 15 micrometers deep) can contain, for example, more than 10 5 The cross-section of each column is such that, in order to analyze the internal structure, a fast and efficient method is needed, for example, to determine the channel properties in process development and monitoring.

[0127] In some specific embodiments, for each set of contours, the trajectories TC(z), TL1(z), TL2(z), ... of the core and layers, and the corresponding regions AC(z), AL1(z), AL2(z), ... of the core and layers of the pillars, can be calculated in the same manner as described above for the outer contours. In the same manner as described above, the ring thickness of the layers, the internal distance between the layers, and the minimum thickness or distance can be derived. Figure 16c Examples illustrate the radii RC(z), RL1(z), and RL2(z) of the trajectories of contours 116, 117, and 118 relative to the core TC(z). As previously mentioned, all generation parameters of a set of pillars can also be analyzed using statistical methods. Furthermore, local defects in the layers that may lead to leakage can be detected and calculated. This allows for detailed statistical analysis of large amounts of data characterizing the internal structure of the pillars, such as local defects or inclusions in the core and layers, or the distance between the core and layers. Additionally, in some specific embodiments, the ring radius and diameter, such as dr, can be determined, thereby allowing for the analysis and inspection of the internal ring structure of memory channels.

[0128] In one specific embodiment, machine learning logic is used to analyze, such as Figure 16a The image shown is a cross-sectional view. As used in this article, machine learning logic refers to an entity that classifies and performs segmentation of objects. In this case, machine learning techniques (sometimes also called artificial intelligence (AI)) are used to identify the various parts of a ring structure, such as... Figure 5 The columns 105 in the model are segments 106, 107, 108, and 110. Machine learning logic is sometimes also called a model. Segmentation typically refers to identifying individual parts of an object (e.g., loops in this case) so that said parts can be used for further analysis or other processing. Examples of machine learning logic can include, for example, decision trees, vector machines, or various types of neural networks, such as deep neural networks, adversarial networks, etc. Machine learning logic is typically trained using training data, such as images annotated by a user. Annotation refers to the user marking regions in a certain way, in this case, loops, for example, using a graphical user interface (GUI). The annotated images are then used for training. For example, once trained, the machine learning logic can... Figure 5 Step S5 is used to perform pixel- or voxel-based segmentation, such as inner rings or other layers.

[0129] Providing accurate annotations for sufficient training samples to train machine learning logic is a challenge. Both a sufficient number of annotations (i.e., a large cross-section of annotations) and the quality of the annotations (i.e., their correctness) are necessary for training machine learning logic to automatically identify various loop segments with high reliability. For example, in the case of large 3D data volumes, insufficient annotations for training can lead to so-called overfitting and confusion between different loops, resulting in incorrect identification.

[0130] In the current situation, such as Figure 16a As shown, the ring structure (e.g., in the SEM image shown) consists of rings with alternating brightness. A brighter central circle is surrounded by a darker ring, which in turn is surrounded by a brighter ring, and so on. This can lead to confusion between labels of rings with similar brightness during a single annotation process.

[0131] Therefore, in one specific embodiment, a two-step annotation process is used, which will be referred to below. Figure 20 and Figure 21 Let me explain.

[0132] As a preparatory step, such as Figure 21 As shown, a complete input volume 2100 of a cross-sectional image is provided, from which annotable crops 2101 are extracted. Annotable crops are portions of the input volume with reduced cross-sections or areas, allowing, for example, human users to annotate them via a corresponding interface.

[0133] Then, Figure 20 The method begins with the binary annotation in step D1. In the binary annotation, as previously mentioned, rings with alternating brightness are annotated with two alternating labels. This... Figure 21 The rings are represented by two alternating shading lines. Only certain portions of each ring can be annotated; this is known as sparse scribbles.

[0134] Using the binary annotation thus established, step D2 involves training a first machine learning logic. The first machine learning logic can be a relatively simple model, such as a random forest model. In other words, the binary annotation ring from step D1 is provided to the first machine learning logic for training.

[0135] Then, Figure 20 Step D3 involves using the trained first machine learning logic to analyze a larger volume of data, such as Figure 21 The full input volume is 2100 or most of the image. This is in Figure 21 The representation is achieved by providing multiple rings with corresponding shades, using a first machine learning logic that has been trained. Figure 21 This is also known as computationally intensive prediction. An image analyzed by a trained first machine learning logic can be called a binary segmentation image because it uses segmentation loops with two alternating labels.

[0136] Next, in Figure 20 In the method, step D4 includes correcting the analytical data from step D3, which in Figure 21 This can also be referred to as cleaning. Here, the user detects misclassifications (shadows of errors) provided by the machine learning logic. This can then be used for retraining through one or more iterations. Figure 21 The circular arrow 2102 in the diagram indicates this. Step D4 can be repeated multiple times to generate segments of sufficient quality.

[0137] Once the desired segmentation quality is achieved, in step D5, the method includes multi-level annotation on the images segmented by the trained first machine learning logic. In other words, the images segmented using the trained first machine learning logic are now annotated to further distinguish different rings. This is in Figure 21 This is represented by using multiple different shades for different rings instead of two different shades for binary annotations. In the user interface, this is done by coloring the ring or a portion of the ring.

[0138] Since the rings themselves have already been identified by the first machine learning logic, for example, clicking on a single ring can easily provide a label (e.g., shade or color) for the entire ring. Therefore, a crop 2101 with multi-level annotations is provided in step D6, which is then used to train the second machine learning logic. In some implementations, the second machine learning logic can be a deep learning neural network. For this training, in some implementations, such as... Figure 21 As shown, the multi-level annotated crops can be divided into a training set 2103 and a test set 2104. For example, the training set may include approximately 80% of the multi-level annotated crops from step D5, and the test set 2104 may include approximately 20% of the annotated crops. The training set is then used for training, while the test set is used to check the training quality. For example, the output of the test set is fed into the trained second machine learning logic without annotations, and the results are compared with the annotations.

[0139] Based on the quality of the annotations, similar to step D4 of the first machine learning logic, correction and retraining can also be performed in step D7 after analysis until the results have sufficient quality.

[0140] Then, as Figure 21 As shown, the trained neural network can be transformed and encrypted for deployment, resulting in a trained model 2105. This trained model (trained machine learning logic) can then be used in... Figure 5 In step S5, pixel / voxel-based segmentation is performed.

[0141] Therefore, as Figure 22 As shown, the ring thickness dr and ring radius 2200 can be determined based on the segmentation using the trained second machine learning logic.

[0142] like Figure 22 As shown, the calculation of this quantitative parameter based on the segmentation results may include an intermediate contour extraction step, as will be referred to below. Figure 18Further explanation. In this contour extraction step, contours can be extracted at the boundaries of the loops / layers determined by segmentation. Contours can initially be placed at the boundaries of the segmented regions (loops) generated by segmentation using a trained second machine learning logic. For example, the active contour algorithm (Snake algorithm) described by Kass, M. et al. in “Snakes: Active Contour Model” in Computer Vision International Journal 1(4):321 can then be used to refine / adjust the contours. Specifically, the contour vertices can be attracted to the maximum pixel grayscale gradient of the original image near the initial contour. Thus, the generated contours will mark the transitions between image regions characterized by different pixel grayscale values, such as the transitions between different “loops” of memory channels. The active contour algorithm can also be applied to fill the image with the probability of each pixel belonging to its respective category (the probability map generated in the segmentation step). In this case, the contours will also mark the transitions between different image regions, but based on the classification confidence / probability provided by the trained model, rather than the original pixel grayscale values. In some implementations, the “subpixel resolution” of the contour can be used, allowing the image coordinates of the adjusted contour vortices to have floating-point precision.

[0143] The generated segments or the contours extracted based on those segments can be used to search for defects, such as significant deviations in ring shape, broken rings, or substantial deviations from the nominal ring thickness or nominal ring radius.

[0144] The aforementioned method can be executed by a dedicated computing system capable of processing large datasets of graphics. The method of the present invention is implemented as a computer program product and stored in the internal memory of the dedicated computing system. A controller controls the operation of a microscope, such as a cross-beam microscope 1, and transmits image data generated by the microscope to a processing unit such as a graphics processing unit (GPU). The controller further controls the processing of the image data according to method steps S2 to S8, and further controls the generation and storage of results in a memory device (e.g., flash memory, random access memory (RAM), read-only memory (ROM), or other suitable variants). The controller is configured to operate automatically according to computer program code. The computer program code is implemented in a non-transitory computer-readable medium and is programmed to perform any number of functions or algorithms as described above. The computer program code is further configured such that the controller notifies the user of the need for user input over time via a graphical user interface (GUI). The controller sets the system to a waiting state until user input is executed. This user input may, for example, be a region selection of a z-series 2D cross-sectional image, or confirmation of a region selection of a z-series 2D cross-sectional image executed by an image processor. In step S9, the results, such as deviation parameters stored in the memory device, are further output in a standard output file format or via a graphical user interface.

[0145] In inspection or review applications, a high degree of automation is required during the analysis of 3D data stacks formed by multiple cross-sectional image slices. In one specific embodiment of the invention, an automated workflow is provided for 3D inspection of semiconductor wafers, such as semiconductor wafers, during the production of devices such as 3D memory chips (VNAND or 3D RAM). For example, 3D memory chips consist of numerous columnar structures extending parallel to each other, sometimes referred to as memory channels or “pillars.” Samples containing such 3D memory devices can be studied using cross-sectional imaging techniques of FIB-SEM microscopy. The typical number of pillars occupying a slice can reach hundreds to 1000 or more. A typical image slice stack can contain hundreds of images. In most applications, a high degree of automation in reconstructing the pillars in 3D is indispensable.

[0146] The typical number of pillars or other semiconductor structures occupying a single image slice can reach hundreds to 1,000 or more. A typical 3D data stack can contain hundreds of cross-sectional image slices. Therefore, a 3D stack of 2D cross-sectional images can contain more than 100,000 pillar cross-sections. On the other hand, each 10μm x 10μm 2nm image slice with a resolution of less than 2nm can easily contain more than 5 gigapixels, or even more than 10 gigapixels. From this large amount of 3D volumetric image data, a small number of parameters such as the center position, radius, and ellipticity of approximately 100,000 pillar cross-sections are derived, and approximately 500,000 values ​​are extracted. By analyzing the values ​​using, for example, fitting algorithms and statistical methods, further reduction is achieved and important performance metrics are provided. Examples of performance metrics include the maximum value of deviation parameters, such as cross-sectional area deviation, minimum distance between two pillars, maximum tilt of one of multiple pillars, and maximum wobble parameters of multiple pillars, as well as descriptive codes for any variations of these parameters (such as statistical variance). According to specific embodiments of automated workflows, up to thousands of image cross-sections of pillars or general semiconductor structures can be analyzed in high throughput. The method details according to a specific embodiment will be described in the example of a pillar or HAR structure in a 3D memory chip, but the method is generally applicable to any type of semiconductor and wafer.

[0147] The method according to a specific embodiment includes several steps to reduce the amount of data within a 3D volumetric image. In the first step, which automatically detects column occupancy in each slice and automatically generates several descriptive parameters (such as center position, best-fit radius, ellipticity), a large number of approximately M = 10 gigapixels or more is reduced to approximately N² = 500,000 first values. For example, an enumeration of the X and Y coordinates of the center coordinates at the column intersections within the image slice is extracted. The first values ​​are analyzed and derived from the center position, such as a single tilt angle of each column, and a reduction to approximately N³ = 10,000 second values ​​is achieved. The second values ​​are further processed using statistical methods and further reduced to, for example, less than 10 performance metrics. The first paradigm uses classical image processing techniques, while the second paradigm uses machine learning (ML) methods. The method according to the specific embodiment requires preparation steps for automated inspection of semiconductor devices.

[0148] An example of a wafer inspection workflow includes the reconstruction of semiconductor features, which can be applied to 3D volumetric images obtained using the aforementioned FIB-SEM microscope. One example includes preparation steps for automated inspection using classical image processing techniques, such as... Figure 18As shown. In the first step C1, representative 3D volumetric image data is generated, for example, by means of steps S1 and S2 as described above. During the image acquisition step C1, 2D cross-sectional image slices are aligned relative to each other, for example, at an alignment reference or other image alignment method. The remaining alignment error or offset between adjacent 2D cross-sectional images is small and does not exceed a predetermined alignment threshold. Prior to step C1, a method may include additional steps such as loading a wafer onto a wafer stage, wafer alignment and registration, forming a reference feature on the wafer surface, generating grooves using, for example, a FIB or laser beam, and removing at least one sample from the wafer using, for example, a probe with a sample attached. It may further include the step of positioning the sample on a holder movable and positioned at the intersection of the FIB and the charged particle imaging apparatus of the dual-beam inspection device.

[0149] In preparation step C2, which involves annotating 2D cross-sectional image segments or occupants, for example, relevant column occupants are annotated by the operator. One or more occupants are annotated by the operator to generate interrelated templates or train a machine learning ("ML") object detector. During the annotation step, the user interactively annotates one or more occupants in one or more slices. In one example, annotation is assisted by a graphical user interface configured to, for example, display rectangles or circles at locations selected by the operator using a computer mouse or other input device on a display of the 2D cross-sectional image. In one example, annotation is assisted by an image processing algorithm for occupancy detection. This algorithm may include filtering operations, edge detection, or contour extraction or morphological operations. In one example, the algorithm for occupancy detection performs interrelated operations or a machine learning ("ML") object detector using previously obtained templates stored in a database to help the operator select relevant cross-sectional image segments.

[0150] In step C3 or the template generation step, a template representing cross-sectional image features of the relevant semiconductor structure is generated. For example, the template is an idealized cross-sectional image feature constructed for mutual correlation. In one example, the template or idealized cross-sectional image feature is derived from the coverage area of ​​the annotation in step C2. For example, the coverage area of ​​the annotation in step C2 is automatically aligned and averaged. Furthermore, image processing techniques such as noise reduction or sharpening may be applied. Therefore, the template is an image of a "typical" or averaged coverage area of ​​the relevant semiconductor structure (e.g., a HAR structure or pillar). When generating the template, a representative center position of the template is determined, and the template image is adjusted relative to the representative center position. In one example, several relevant semiconductor structures are considered, and steps C2 and C3 are performed on several relevant semiconductor structures to generate a first template representing at least a relevant first semiconductor structure and a second template representing the relevant semiconductor structure.

[0151] In step C4, a series of cross-correlation operations are performed. Cross-correlation is performed between 2D cross-sectional image slices and the templates generated in step C3. Each peak in the generated 2D cross-correlation image (one for each matching location of the template in each 2D cross-sectional image slice) represents a coverage area or cross section of the detected relevant semiconductor structure. To improve the sensitivity and / or robustness of coverage area detection, cross-correlation can be performed multiple times using different templates representing the relevant first semiconductor structure. For example, a series of scaling factors can be used before each cross-correlation operation to scale the variations in the templates representing the relevant first semiconductor structure. Furthermore, different templates can be used for different cross-sectional image slices, or, for example, different z-positions in a 3D volumetric image.

[0152] In step C5, a list of channel coverage areas corresponding to the coverage areas detected in each 2D image cross-sectional slice in step C4 is generated, using coverage area coordinates or center coordinates. The lateral coordinates originate from the lateral or xy position in the 2D image cross-sectional slice, and the z-coordinate in the 3D volumetric image originates from the z-position of the 2D image cross-sectional slice within the 3D volume. The center position of the 2D cross-sectional image feature of the relevant semiconductor structure detected in the 2D cross-sectional image slice in step C4 corresponds to the representative center position of the template determined in step C3.

[0153] In step C6, the 2D cross-sectional image features representing the coverage area are segmented, i.e., the boundaries of the coverage area are determined. This is done "locally" for each coverage area, i.e., using multiple 2D sub-images, each containing only one coverage area at the center location determined in step C5. The boundaries are calculated using known contour extraction algorithms, such as edge detection, morphological operations, threshold processing, or equivalent methods.

[0154] In step C7, the contours or boundaries determined in step C6 are assigned to the relevant semiconductor structures, such as individual HAR structures or pillars. The boundaries or contours belonging to the same pillar / channel in adjacent 2D cross-sectional image slices, calculated in step C6, are determined, for example, based on their lateral center coordinates. Therefore, for each relevant semiconductor structure, an enumeration of contours / boundaries belonging to relevant semiconductor structures in different 2D cross-sectional image slices is generated.

[0155] The predetermined alignment threshold in step C1 could be, for example, half the distance between two adjacent coverage areas. In this case, any ambiguity in assigning contours to the corresponding related semiconductor structures is avoided. However, in this example, the identification and assignment of contours belonging to the same semiconductor structure of interest is not always possible. In this example, contours that cannot be clearly assigned to 2D cross-sectional image features of the semiconductor structure of interest are marked as ambiguous.

[0156] In step C8, the coverage areas belonging to the same associated semiconductor structures identified in different 2D cross-sectional image slices in step C7 are analyzed, and the lateral alignment of the 2D cross-sectional image slices relative to each other can be selectively improved. For this purpose, for all pairs of adjacent 2D cross-sectional image slices, the average or average offset of all coverage areas in one 2D cross-sectional image slice relative to corresponding coverage areas on adjacent 2D cross-sectional image slices is calculated. The calculated offset is then applied to the center coordinates of the corresponding coverage area. The result of step C8 is a set of enumerations, each containing the corrected center position and contour / boundary belonging to a specific associated semiconductor structure, such as a HAR channel or pillar.

[0157] In one example, displacement is taken into account in the precise alignment of the 2D cross-sectional image slices, and step C7 is reassigned for contours that have been marked as ambiguous in step C7.

[0158] In step C9 (3D surface generation), for each channel, the contour coordinates are extracted as XY- and Z-coordinates, representing surface points located on the surface of the relevant specific semiconductor structure. Surface points can also be combined into primitive forms, such as triangular meshes or 3D polygonal contours for visualization or further analysis. A large number of surface or contour coordinates are thus simplified to a predetermined primitive or primitive form described by a set of parameters representing the relevant semiconductor structure and its predetermined typical deviation from the ideal shape. The primitives can tilt or twist cylinders, with tilt angles and wobbles described by a few parameters.

[0159] In step C10, the semiconductor structure of interest is quantitatively characterized. For each semiconductor structure of interest, a set of parameters characterizing the geometry of the entire semiconductor structure of interest (e.g., a HAR structure or pillar) is extracted or derived. Examples of such parameters are the average radius and ellipticity of the pillar, and the correlation between the parameters and the Z-coordinate, the tilt and curvature of the pillar axis, and the proximity or nearest distance between adjacent semiconductor structures of interest. Statistical properties of a large number of pillars (e.g., all pillars in a dataset) can be calculated. Examples of such properties are the average radius of a set of pillars and its standard deviation, the average tilt of the pillar, the average proximity of adjacent pillars, or the maximum and minimum values ​​of parameters on multiple pillars. Those skilled in the art can define multiple other statistical information representing performance metrics, for example, for monitoring specific process steps or for determining the representative performance of a manufactured semiconductor device. The results of step C10 can also be correlated with other inspection measurements of other samples extracted from the same or a second wafer, or with the location of the sample on the wafer. Examples are, for example, the variation of the pillar cross-section with depth, the tilt of the pillar, especially the tilt towards the outer circumference of the wafer edge, and the variation of the tilt angle on the wafer. Other examples are the shape of the pillars, such as the average number of barrels. Therefore, representative primitives can be compared with reference primitives, for example, obtained from CAD data of semiconductor device design.

[0160] In an example of a specific embodiment, a machine learning (“ML”) type object detector is applied. Instead of the generation template described in step C3, in the modified step C3M, the machine learning algorithm is trained using the annotated cross-sectional image features identified during step C2. The machine learning algorithm is then applied in the modified step C4M to automatically detect cross-sectional image features of the semiconductor structure of interest. This can be performed as described above, and then the trained second machine learning logic can be used to detect the cross-section of the pillar in the 2D cross-section and its internal structure, i.e., segmentation into rings.

[0161] The inspection method may further include a modified step C6M utilizing machine learning (ML)-based local segmentation. After determining the coordinates of the covered area in the previous step, the boundary or contour of the covered area is determined, and the covered area is segmented and separated from the background. This segmentation can be accomplished using the second machine learning logic trained above to perform loop segmentation. The boundary or contour can also be calculated using an ML-type segmentation algorithm.

[0162] As can be clearly seen from the foregoing, steps C2 and C3 are preparatory steps performed in preparation for the routine inspection task. In the routine inspection task, steps C2 and C3 are omitted; instead, a set of pre-selected templates, identified during the preparation workflow and stored, for example, in a database, are used for steps C4 and further steps. It is also understood that these steps may overlap during the routine inspection. For example, step C4 may overlap with step C1, and the identification of the coverage area using the relevant templates may begin, for example, from the first 2D cross-sectional image obtained during step C1. Certain processing steps may also be performed in a different order. For example, step C9, the 3D surface generation step, may be performed, for example, before the fine alignment step C8, on a set of representative related semiconductor structures, and the fine alignment execution according to step C8 may be influenced by the results of representative 3D surface analysis. Alternatively, step C8, the fine alignment step, may be performed directly after step C5.

[0163] Methods containing any of steps C4 through C10, or those containing modified steps C4M or C6M, benefit from faster computation time. In this method, in a first step, the volumetric data of the 3D volumetric image is reduced by more than 10,000 times to a first value. The first value contains an enumeration of the center location and contour coordinates of the semiconductor structure of interest, such as those obtained in steps C5 through C7. During step C9, the first value is further simplified to parameters in the form of representative primitives. Therefore, the number of first values ​​is further reduced to approximately 50 times that of a second value. This method further benefits from statistical averaging, including the statistical averaging in step C9 during the generation of representative primitives.

[0164] The aforementioned examples are illustrated using HAR channels or pillars as examples of semiconductor structures of interest. Other semiconductor structures of interest could be vias in logic probes. A via is a vertical contact structure between adjacent horizontal layers of a logic chip containing various IC components. Such vias are treated in the same way as HAR channels or pillars in 3D memory probes. Other examples are metal lines or connections in logic chips. A series of such metal lines, known (e.g., based on available design information) to be parallel to each other, can be treated in the same way as memory channels in 3D memory chips.

[0165] The method according to the present invention can be applied to process characterization, process optimization and / or process monitoring in the process development or manufacturing of semiconductor devices.

[0166] The foregoing specific embodiments can be combined completely or partially with each other. Furthermore, modifications or methods, derived parameters, or statistical values ​​known to those skilled in the art are within the scope of this invention. Although according to Figure 5 The method is explained in sequence S1 to S7, but the order of at least two method steps can be interchanged, such as the order of method steps S2 and S3.

[0167] List of reference numerals

[0168] Numbered Items

[0169] 1. Cross-beam microscope

[0170] 2. Cross-sectional surface

[0171] 3. Cross-sectional surface

[0172] 4. Cross-sectional surface

[0173] 5. Focused Ion Beam (FIB)

[0174] 6. Angle between CPB and FIB

[0175] 7. Charged Particle Beam (CPB)

[0176] 8. Scanning imaging lines of raster scanning

[0177] 9 Ion beams

[0178] 10 block samples

[0179] 11 Cross-sectional surface

[0180] 18 2D cross-sectional images

[0181] 20 Stacked 2D cross-sectional images at a distance dz

[0182] 50 Integrated Semiconductors

[0183] 51 Silicon substrate

[0184] 52 Top surface

[0185] 54.1, 54.2, ... 54.22, ... 54.k ... 54.z: Planar layers of semiconductor devices.

[0186] 55 through hole

[0187] 56 Metal Structure

[0188] 57 gate

[0189] 58 Doped Structure

[0190] 59 contacts

[0191] 60-column or HAR structure

[0192] 62 column section

[0193] 63 Thin gap

[0194] The trajectory of 64 columns

[0195] 66 HAR structure outer circumference

[0196] Column groups 68.1 and 68.2

[0197] 69. Separation Structure

[0198] 70° tilt angle θ

[0199] 72.1 Column Section

[0200] 72.2 Column sections with larger diameters

[0201] 72.3 Column sections with smaller diameters

[0202] 74.1 Inclined Trajectory

[0203] 74.2 Nonlinear Trajectory

[0204] 75 Intersecting planes

[0205] 76.1 Elliptical circumference

[0206] 76.2 Circumference of General Shapes

[0207] Cross sections of columns 78.1 and 78.2

[0208] Cross section of the 79 column group

[0209] 80 Examples of identified columns

[0210] 82 Columns with a circumference of 80

[0211] 90.1, 90.2 Columns described by circumferential stacking

[0212] 92 Circular stacking 94. Minimum distance vector between two circles 96 The center of a column 97. The displacement vector of a column, or T(z).

[0213] Cross sections 101.1 and 101.2

[0214] 102.1, 102.2 Inclusions or defects

[0215] 103.1, 103.2 Inclusions or defects around the circumference of 101.1, 101.2

[0216] Areas of inclusions 102.1 and 102.2, 104.1 and 104.2 respectively.

[0217] 105 One column

[0218] The core of the 106 pillars

[0219] 107 First Intermediate Layer

[0220] 108 Second outer layer

[0221] Columns 109.1, 109.2, and 109.3

[0222] 110 Isolation Layer

[0223] 111 Column Profile Set

[0224] 112 Column Profile Set

[0225] The set of contours of column 105.

[0226] 116 Core 106 contour extraction

[0227] 117 Extraction of the contour from the first intermediate layer 107

[0228] 118 Extracted contour of the second outer layer 108

[0229] 1900 memory channel

[0230] 1901 Dielectric

[0231] 1902 line

[0232] 2100 Full Input Volume

[0233] 2101 Annotable Crops

[0234] 2102 Arrow

[0235] 2103 training set

[0236] Test set 2104

[0237] S1-S8 Method Steps

[0238] C1-C10 Method Steps

[0239] Methods and steps for D1-D7

Claims

1. A method of training machine learning logic to segment a column cross-section annulus in a high aspect ratio (HAR) structure, the method comprising: providing cross-section images of a plurality of columns; binary annotating the annulus in the cross-section images with two alternating labels; training a first machine learning logic based on the binary annotated annulus; segmenting the cross-section images or further cross-section images using the trained first machine learning logic to provide binary segmented images; multi-level annotating the segmented annulus in the binary segmented images to provide multi-level annotated images; and training a second machine learning logic based on the multi-level annotated images as machine learning logic for segmenting the annulus.

2. The method of claim 1, wherein the first machine learning logic comprises a random forest model.

3. The method of claim 1, wherein the second machine learning logic comprises a neural network.

4. The method of claim 1, further comprising retraining the first machine learning logic based on the corrected binary segmented images.

5. The method of claim 4, wherein the multi-level annotating is performed after the retraining.

6. The method of any one of claims 1-5, wherein training the second machine learning logic is based on a first portion of the multi-level annotated images, and wherein the method further comprises testing the trained second machine learning logic based on a second portion of the multi-level annotated images different from the first portion.

7. The method of any one of claims 1-5, wherein the binary annotating is performed for a portion of each of the annulus.

8. A method of analyzing a column cross-section annulus in a high aspect ratio (HAR) structure, the method comprising: providing a cross-section image of a column; segmenting the annulus in the cross-section using trained machine learning logic; and determining parameters of the annulus based on the segmented annulus, wherein the machine learning logic is a second machine learning logic trained using a training method of training machine learning logic to segment a column cross-section annulus in a high aspect ratio (HAR) structure, the training method comprising: providing cross-section images of a plurality of columns; binary annotating the annulus in the cross-section images with two alternating labels; training a first machine learning logic based on the binary annotated annulus; segmenting the cross-section images or further cross-section images using the trained first machine learning logic to provide binary segmented images; multi-level annotating the segmented annulus in the binary segmented images to provide multi-level annotated images; and training a second machine learning logic based on the multi-level annotated images as machine learning logic for segmenting the annulus.

9. The method of claim 8, further comprising identifying a profile of the annulus based on the segmented annulus, wherein the parameters are determined based on the identified profile.

10. The method of claim 8, wherein the parameters comprise parameters selected from the group consisting of an annulus radius and an annulus diameter.

11. The method of claim 8, further comprising identifying deviations of the parameters from nominal or expected values.

12. The method of claim 8, further comprising: obtaining a 3D tomographic image of a semiconductor sample; selecting a subset of 2D cross-sectional image segments comprising cross-sectional images of the pillars from the 3D tomographic image, each segment containing a set of cross-sectional images of HAR structures; identifying a contour of each HAR structure within the set of HAR structures in the subset of 2D cross-sectional images; extracting a deviation parameter from the contour of a HAR structure of the set of HAR structures; analyzing the deviation parameter, wherein the deviation parameter comprises one or more of: a displacement from an ideal position; a deviation of a radius or diameter; a deviation from a cross-sectional area; a deviation from a cross-sectional shape.

13. The method of claim 12, wherein the step of analyzing the deviation parameter comprises performing a statistical analysis of at least one deviation parameter of at least one HAR structure of the set of HAR structures.

14. The method of claim 8, wherein the training method further comprises retraining the first machine learning logic based on the corrected binary segmentation images.

15. The method of claim 8, wherein training the second machine learning logic is based on a first portion of the multi-level annotated images, and wherein the method further comprises testing the trained second machine learning logic based on a second portion of the multi-level annotated images different from the first portion.

16. A semiconductor inspection apparatus comprising: a focused ion beam device (FIB) adapted to mill a series of cross-sections of an integrated semiconductor sample; a scanning electron beam microscope (SEM) adapted to image the series of cross-sections of the integrated semiconductor sample; a controller for operating a set of instructions capable of performing a method of analyzing a pillar cross-sectional ring in a high aspect ratio (HAR) structure in the integrated semiconductor sample, the method of analyzing the ring comprising: providing a cross-sectional image of a pillar; segmenting the ring in the cross-sectional image using a trained machine learning logic; and determining parameters of the ring based on the segmented ring, wherein the machine learning logic is a second machine learning logic trained using a training method of training a machine learning logic to segment a pillar cross-sectional ring in a high aspect ratio (HAR) structure, the training method comprising: providing a plurality of cross-sectional images of pillars; binary annotating rings in the cross-sectional images with two alternative labels; training a first machine learning logic based on the binary annotated rings; segmenting the cross-sectional images or further cross-sectional images using the trained first machine learning logic to provide binary segmentation images; multi-level annotating the segmented rings in the binary segmentation images to provide multi-level annotated images; and training a second machine learning logic as the machine learning logic for segmenting rings based on the multi-level annotated images.

17. The semiconductor inspection apparatus of claim 16, wherein the focused ion beam (FIB) and the electron beam microscope (SEM) form a 90° angle with each other.

18. The semiconductor inspection apparatus of claim 16, further comprising a laser beam device for dicing the integrated semiconductor sample from a wafer.

19. The semiconductor inspection apparatus of claim 16, wherein the training method further comprises retraining the first machine learning logic based on the corrected binary segmentation images.

20. The semiconductor inspection apparatus of claim 16, wherein training the second machine learning logic is based on a first portion of the multi-level annotated images, and wherein the method further comprises testing the trained second machine learning logic based on a second portion of the multi-level annotated images that is different than the first portion.

21. A tangible storage medium containing instructions that, when executed on a processor, cause performance of a method of training machine learning logic to segment pillar cross-section rings in high aspect ratio (HAR) structures, the method comprising: providing cross-section images of a plurality of pillars; binary annotating rings in the cross-section images with two alternating labels; training a first machine learning logic based on the binary annotated rings; segmenting the cross-section images or further cross-section images using the trained first machine learning logic to provide binary segmented images; multi-level annotating the segmented rings in the binary segmented images to provide multi-level annotated images; and training a second machine learning logic based on the multi-level annotated images as machine learning logic for segmenting rings.

22. A tangible storage medium containing instructions that, when executed on a processor, cause performance of a method of analyzing pillar cross-section rings in high aspect ratio (HAR) structures, the method comprising: providing a cross-section image of a pillar; segmenting rings in the cross-section using a trained machine learning logic; and determining parameters of the rings based on the segmented rings, wherein the machine learning logic is a second machine learning logic trained using a training method of training machine learning logic to segment pillar cross-section rings in high aspect ratio (HAR) structures, the training method comprising: providing cross-section images of a plurality of pillars; binary annotating rings in the cross-section images with two alternating labels; training a first machine learning logic based on the binary annotated rings; segmenting the cross-section images or further cross-section images using the trained first machine learning logic to provide binary segmented images; multi-level annotating the segmented rings in the binary segmented images to provide multi-level annotated images; and training a second machine learning logic based on the multi-level annotated images as machine learning logic for segmenting rings.

Images