Vapor deposition apparatus and vapor deposition method

Abstract

This invention relates to a vapor deposition apparatus and a vapor deposition method. According to one embodiment, the vapor deposition apparatus includes: a first chamber group having a plurality of vapor deposition chambers arranged in a row along a first conveying direction; a second chamber group having a plurality of vapor deposition chambers arranged in a row along a second conveying direction; a first rotating chamber connected to the upstream first vapor deposition chamber in the first conveying direction and the downstream second vapor deposition chamber in the second conveying direction, and for rotating the processed substrate; and a second rotating chamber connected to the downstream third vapor deposition chamber in the first conveying direction and the upstream fourth vapor deposition chamber in the second conveying direction, and for rotating the processed substrate.

Description

[0001] Cross-referencing of related applications

[0002] This application claims priority based on Japanese Patent Application No. 2022-099797, filed on June 21, 2022, and incorporates all the contents of that Japanese application. Technical Field

[0003] The embodiments of the present invention relate to vapor deposition apparatus and vapor deposition method. Background Technology

[0004] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put into practical use. These display elements include pixel circuits containing thin-film transistors, a lower electrode connected to the pixel circuits, an organic layer covering the lower electrode, and a top electrode covering the organic layer. In addition to the light-emitting layer, the organic layer also includes functional layers such as a hole transport layer and an electron transport layer.

[0005] In manufacturing apparatuses used to form such organic layers containing multiple functional layers, there is a need to reduce costs and minimize setup space. Summary of the Invention

[0006] The purpose of this implementation is to provide a vapor deposition apparatus and method that can reduce costs and minimize setup space.

[0007] According to one embodiment, the vapor deposition apparatus includes:

[0008] A first chamber group having a plurality of vapor deposition chambers arranged in a row along a first transport direction for transporting a processed substrate; a second chamber group having a plurality of vapor deposition chambers arranged in a row along a second transport direction opposite to the first transport direction; a first rotating chamber connected to the first vapor deposition chamber located upstream in the first transport direction in the first chamber group and the second vapor deposition chamber located downstream in the second transport direction in the second chamber group, and rotating the processed substrate in such a way that the processed substrate being transported from the second vapor deposition chamber is moved into the first vapor deposition chamber; and a second rotating chamber connected to the third vapor deposition chamber located downstream in the first transport direction in the first chamber group and the fourth vapor deposition chamber located upstream in the second transport direction in the second chamber group, and rotating the processed substrate in such a way that the processed substrate being transported from the third vapor deposition chamber is moved into the fourth vapor deposition chamber.

[0009] According to one embodiment, the vapor deposition method, wherein...

[0010] A processing substrate is prepared, having a lower electrode formed on its upper surface and a rib having an opening overlapping the lower electrode. The substrate also has a partition wall comprising a lower portion above the rib and an upper portion above the lower portion and protruding from the side of the lower portion. The processing substrate is moved into a vapor deposition apparatus without a mask to form an organic layer. An upper electrode is formed on the organic layer. The processing substrate with the upper electrode formed is then removed from the vapor deposition apparatus. Within the vapor deposition apparatus, the moved-in processing substrate passes through a first rotating cavity and through a plurality of vapor deposition cavities arranged in a row along a first conveying direction. The first chamber group of the chamber rotates 180° in the second rotating chamber, passes through the second chamber group having a plurality of vapor deposition chambers arranged in a row along the second transport direction opposite to the first transport direction, rotates 180° in the first rotating chamber, passes through the first chamber group, rotates 180° in the second rotating chamber, passes through the second chamber group, passes through the first rotating chamber and is removed from the vapor deposition apparatus. In the processed substrate removed from the vapor deposition apparatus, the organic layer and the upper electrode formed on the partition wall are separated from the organic layer and the upper electrode formed on the lower electrode in the opening.

[0011] According to the embodiments, it is possible to provide vapor deposition apparatus and vapor deposition method that can reduce costs and shrink installation space. Attached Figure Description

[0012] Figure 1 This is a diagram illustrating an example of the configuration of a display device DSP.

[0013] Figure 2 This is a diagram showing an example of the layout of sub-pixels SP1, SP2, and SP3.

[0014] Figure 3 It is along Figure 2 A schematic cross-sectional view of the DSP display device for the AB lines.

[0015] Figure 4 This is a flowchart illustrating an example of a manufacturing method for a display device DSP.

[0016] Figure 5 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0017] Figure 6 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0018] Figure 7 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0019] Figure 8 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0020] Figure 9 This is a diagram used to illustrate the manufacturing method of a display device DSP.

[0021] Figure 10 This is a diagram showing an example of the configuration of display elements 201 to 203.

[0022] Figure 11 This is another example of the configuration of display elements 201 to 203.

[0023] Figure 12 This is a diagram illustrating one configuration example of the vapor deposition apparatus 100.

[0024] Figure 13 It is used for explanation Figure 12 The diagram shows the transport room 120.

[0025] Figure 14 It is used for explanation Figure 12 The figure shows the substrate loading and unloading chamber 130 and the first rotating cavity 140.

[0026] Figure 15 It is used for explanation Figure 12 The figure shows the vapor deposition section 150.

[0027] Figure 16 It is used to illustrate the use Figure 12 The vapor deposition apparatus 100 shown in the figure is formed Figure 10 The diagram shows the process of the organic layer OR1 and the upper electrode UE1 of the display element 201.

[0028] Figure 17 It is used to illustrate the use Figure 12 The vapor deposition apparatus 100 shown in the figure is formed Figure 11 The diagram shows the process of the organic layer OR1 and the upper electrode UE1 of the display element 201.

[0029] Figure 18 It is used to illustrate the use Figure 12 The vapor deposition apparatus 100 shown in the figure is formed Figure 11 The diagram shows the process of the organic layer OR1 and the upper electrode UE1 of the display element 201.

[0030] Figure 19 This is a diagram illustrating another configuration example of the vapor deposition apparatus 100.

[0031] Figure 20 It is used to illustrate the use Figure 19 The vapor deposition apparatus 100 shown in the figure is formed Figure 10 The diagram shows the process flow of the organic layer OR1, the upper electrode UE1, and the capping layer CP1 of the display element 201.

[0032] Figure 21 It is used to illustrate the use Figure 19 The vapor deposition apparatus 100 shown in the figure is formed Figure 11 The diagram shows the process flow of the organic layer OR1, the upper electrode UE1, and the capping layer CP1 of the display element 201.

[0033] Figure 22 It is used to illustrate the use Figure 19 The vapor deposition apparatus 100 shown in the figure is formed Figure 11 The diagram shows the process flow of the organic layer OR1, the upper electrode UE1, and the capping layer CP1 of the display element 201. Detailed Implementation

[0034] One embodiment is described with reference to the accompanying drawings.

[0035] The disclosed content is merely an example, and appropriate modifications that can be readily conceived by those skilled in the art without departing from the spirit of the invention are naturally included within the scope of this invention. Furthermore, regarding the accompanying drawings, to make the description clearer, the width, thickness, shape, etc., of various parts are sometimes schematically shown compared to the actual form, but this is merely an example and not a limitation on the interpretation of the invention. Additionally, in this specification and the various figures, for constituent elements that perform the same or similar functions as those described with respect to the already presented figures, there are instances where the same reference numerals are used and repeated detailed descriptions are appropriately omitted.

[0036] It should be noted that, for ease of understanding, mutually orthogonal X-axis, Y-axis, and Z-axis are shown in the accompanying drawings. The direction along the X-axis is referred to as the first direction, the direction along the Y-axis as the second direction, and the direction along the Z-axis as the third direction. The observation of various elements parallel to the third direction Z is called a top-down view. Here, the positive direction of the Z-axis is referred to as "up" or "above." Furthermore, the terms "up," "above," and "relative," which indicate the positional relationship between two or more constituent elements, not only refer to cases where two or more constituent elements of an object are adjacent to each other, but also include cases where they are separated by gaps or other constituent elements.

[0037] The display device involved in this embodiment is an organic electroluminescent display device that has an organic light-emitting diode (OLED) as a display element, and can be mounted on televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, etc.

[0038] Figure 1 This is a diagram illustrating an example of the configuration of a display device DSP.

[0039] The display device DSP has a display area DA for displaying images and a peripheral area SA surrounding the display area DA on an insulating substrate 10. The substrate 10 can be glass or a flexible resin film.

[0040] In this embodiment, the substrate 10 viewed from above has a rectangular shape. However, the shape of the substrate 10 viewed from above is not limited to a rectangle; it can also be other shapes such as a square, a circle, or an ellipse.

[0041] The display area DA has multiple pixels PX arranged in a matrix along the first direction X and the second direction Y. Pixel PX contains multiple sub-pixels SP. In one example, pixel PX contains a sub-pixel SP1 of color 1, a sub-pixel SP2 of color 2, and a sub-pixel SP3 of color 3. Color 1, color 2, and color 3 are different colors from each other. It should be noted that pixel PX may also contain sub-pixels SP of other colors such as white, either together with or replacing any of sub-pixels SP1, SP2, and SP3. It should also be noted that the combination of sub-pixels may not be a combination of three elements but may consist of two elements, or may consist of four or more elements such as sub-pixels SP1 to SP3 plus sub-pixel SP4, etc.

[0042] The sub-pixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements, for example, made of thin-film transistors.

[0043] The gate electrode of pixel switch 2 is connected to scan line GL. One of the source electrode and drain electrode of pixel switch 2 is connected to signal line SL, and the other is connected to the gate electrode of driving transistor 3 and capacitor 4. In driving transistor 3, one of the source electrode and drain electrode is connected to power line PL and capacitor 4, and the other is connected to the anode of display element 20.

[0044] It should be noted that the configuration of pixel circuit 1 is not limited to the example shown in the figure. For example, pixel circuit 1 may also have more thin-film transistors and capacitors.

[0045] Display element 20 is an organic light-emitting diode (OLED), sometimes referred to as an organic EL element, which serves as a light-emitting element.

[0046] Figure 2 This is a diagram showing an example of the layout of sub-pixels SP1, SP2, and SP3.

[0047] exist Figure 2 In the example, sub-pixels SP2 and SP3 are arranged in the second direction Y. Furthermore, sub-pixels SP2 and SP3 are arranged with sub-pixel SP1 in the first direction X.

[0048] With sub-pixels SP1, SP2, and SP3 arranged in this layout, the display area DA contains columns of sub-pixels SP2 and SP3 alternately arranged in the second direction Y, and columns of multiple sub-pixels SP1 repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0049] It should be noted that the layout of sub-pixels SP1, SP2, and SP3 is not limited to... Figure 2 For example, the sub-pixels SP1, SP2, and SP3 in each pixel PX can also be arranged sequentially in the first direction X.

[0050] Ribs 5 and partitions 6 are configured in the display area DA. Ribs 5 have openings AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively.

[0051] When viewed from above, the partition 6 overlaps with the rib 5. The partition 6 has a plurality of first partitions 6x extending along a first direction X and a plurality of second partitions 6y extending along a second direction Y. The plurality of first partitions 6x are respectively disposed between adjacent openings AP2 and AP3 in the second direction Y and between two adjacent openings AP1 in the second direction Y. The second partitions 6y are respectively disposed between adjacent openings AP1 and AP2 in the first direction X and between adjacent openings AP1 and AP3 in the first direction X.

[0052] exist Figure 2 In the example, the first partition 6x and the second partition 6y are interconnected. Thus, the partition 6 as a whole is formed as a lattice surrounding the openings AP1, AP2, and AP3. The partition 6 can also have openings in the sub-pixels SP1, SP2, and SP3, just like the ribs 5.

[0053] Subpixels SP1, SP2, and SP3 each have display elements 201, 202, and 203 as display elements 20, respectively.

[0054] Sub-pixel SP1 has a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with opening AP1. Sub-pixel SP2 has a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with opening AP2. Sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with opening AP3.

[0055] exist Figure 2In the example, the outlines of the lower electrodes LE1, LE2, and LE3 are represented by dashed lines, while the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are represented by single-dotted lines. The periphery of each of the lower electrodes LE1, LE2, and LE3 overlaps with the rib 5. It should be noted that the outlines of the lower electrodes, organic layers, and upper electrodes shown in the illustration are not limited to reflecting their exact shapes.

[0056] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 constitute the display element 201 of sub-pixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 constitute the display element 202 of sub-pixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 constitute the display element 203 of sub-pixel SP3.

[0057] The lower electrodes LE1, LE2, and LE3 correspond to the anode of the display element, for example. The upper electrodes UE1, UE2, and UE3 correspond to the cathode or common electrode of the display element.

[0058] The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 via the contact hole CH1 (see [link]). Figure 1 The lower electrode LE2 is connected to the pixel circuit 1 of sub-pixel SP2 through contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of sub-pixel SP3 through contact hole CH3.

[0059] exist Figure 2 In the example, the area of ​​opening AP1 is larger than the area of ​​opening AP2, and the area of ​​opening AP2 is larger than the area of ​​opening AP3. In other words, the area of ​​the lower electrode LE1 exposed through opening AP1 is larger than the area of ​​the lower electrode LE2 exposed through opening AP2, and the area of ​​the lower electrode LE2 exposed through opening AP2 is larger than the area of ​​the lower electrode LE3 exposed through opening AP3.

[0060] For example, the display element 201 of sub-pixel SP1 is configured to emit light in the blue wavelength region. In addition, the display element 202 of sub-pixel SP2 is configured to emit light in the green wavelength region, and the display element 203 of sub-pixel SP3 is configured to emit light in the red wavelength region.

[0061] Figure 3 It is along Figure 2 A schematic cross-sectional view of the DSP display device for the AB lines.

[0062] A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes... Figure 1 The diagram shows various circuits and wiring, including pixel circuit 1, scan line GL, signal line SL, and power line PL. Circuit layer 11 is covered by insulating layer 12. Insulating layer 12 functions as a planarization film to flatten the unevenness created by circuit layer 11.

[0063] Lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12. Ribs 5 are disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the ribs 5. That is, the ends of the lower electrodes LE1, LE2, and LE3 are disposed between the insulating layer 12 and the ribs 5. Between adjacent lower electrodes among the lower electrodes LE1, LE2, and LE3, the insulating layer 12 is covered by the ribs 5.

[0064] The partition 6 includes a lower part (stem part) 61 disposed above the rib 5 and an upper part (umbrella part) 62 disposed above the lower part 61. The lower part 61 of the partition 6 shown on the left is located between openings AP1 and AP2. The lower part 61 of the partition 6 shown on the right is located between openings AP2 and AP3. The upper part 62 has a wider width than the lower part 61. Therefore, both ends of the upper part 62 protrude beyond the sides of the lower part 61. This shape of the partition 6 can also be described as cantilevered. The portion of the upper part 62 that protrudes towards opening AP1 compared to the lower part 61 is called protrusion 621, the portion that protrudes towards opening AP2 compared to the lower part 61 is called protrusion 622, and the portion that protrudes towards opening AP3 compared to the lower part 61 is called protrusion 623.

[0065] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1, and overlaps a portion of the rib 5. The upper electrode UE1 is opposite to the lower electrode LE1 and is disposed on top of the organic layer OR1. Furthermore, the upper electrode UE1 contacts the side of the lower portion 61. The organic layer OR1 and the upper electrode UE1 are located below the upper portion 62.

[0066] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2, and overlaps a portion of the rib 5. The upper electrode UE2 is opposite to the lower electrode LE2 and is disposed on top of the organic layer OR2. Furthermore, the upper electrode UE2 contacts the side of the lower portion 61. The organic layer OR2 and the upper electrode UE2 are located below the upper portion 62.

[0067] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3, and overlaps a portion of the rib 5. The upper electrode UE3 is opposite to the lower electrode LE3 and is disposed on top of the organic layer OR3. Furthermore, the upper electrode UE3 contacts the side of the lower portion 61. The organic layer OR3 and the upper electrode UE3 are located below the upper portion 62.

[0068] In the illustrated example, subpixels SP1, SP2, and SP3 include capping layers (optical adjustment layers) CP1, CP2, and CP3 for adjusting the optical properties of the light emitted by the light-emitting layers of organic layers OR1, OR2, and OR3. It should be noted that at least one of the capping layers CP1 to CP3 may be omitted.

[0069] Cap layer CP1 is located below opening AP1, relative to upper part 62, and disposed above upper electrode UE1. Cap layer CP2 is located below opening AP2, relative to upper part 62, and disposed above upper electrode UE2. Cap layer CP3 is located below opening AP3, relative to upper part 62, and disposed above upper electrode UE3.

[0070] Subpixels SP1, SP2, and SP3 are respectively equipped with sealing layers SE1, SE2, and SE3.

[0071] The sealing layer SE1 is in contact with the capping layer CP1 and the lower part 61 and upper part 62 of the partition 6, continuously covering all components of the sub-pixel SP1. There is no gap in the sealing layer SE1 below the protrusion 621 of the partition 6.

[0072] The sealing layer SE2 is in contact with the capping layer CP2 and the lower part 61 and upper part 62 of the partition 6, continuously covering all components of the sub-pixel SP2. There is no gap in the sealing layer SE2 below the protrusion 622 of the partition 6.

[0073] The sealing layer SE3 is in contact with the capping layer CP3 and the lower part 61 and upper part 62 of the partition 6, continuously covering all components of the sub-pixel SP3. There is no gap in the sealing layer SE3 below the protrusion 623 of the partition 6.

[0074] Sealing layers SE1, SE2, and SE3 are covered by protective layer 13.

[0075] In the illustrated example, a portion of the organic layer OR1, a portion of the upper electrode UE1, and a portion of the capping layer CP1 are located between the partition 6 and the sealing layer SE1, positioned above the upper portion 62, and separated from the portion located below the upper portion 62.

[0076] In addition, a portion of the organic layer OR2, a portion of the upper electrode UE2, and a portion of the capping layer CP2 are located between the partition wall 6 and the sealing layer SE2, disposed above the upper part 62, and separated from the portion located below the upper part 62.

[0077] In addition, a portion of the organic layer OR3, a portion of the upper electrode UE3, and a portion of the capping layer CP3 are located between the partition wall 6 and the sealing layer SE3, disposed above the upper part 62, and separated from the portion located below the upper part 62.

[0078] Insulation layer 12 is an organic insulation layer. Ribs 5 and sealing layers SE1, SE2, and SE3 are inorganic insulation layers.

[0079] Rib 5 is formed of silicon nitride (SiNx), an example of an inorganic insulating material. It should be noted that rib 5 can also be formed as a monolayer of any of the following inorganic insulating materials: silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Alternatively, rib 5 can also be formed as a laminate consisting of at least two layers selected from silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide layers.

[0080] Sealing layers SE1, SE2, and SE3 are formed, for example, from the same inorganic insulating material.

[0081] Sealing layers SE1, SE2, and SE3 are formed from silicon nitride (SiNx), an example of an inorganic insulating material. It should be noted that sealing layers SE1, SE2, and SE3 can also be formed as a monolayer of any of the following inorganic insulating materials: silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Alternatively, sealing layers SE1, SE2, and SE3 can be formed as a laminate consisting of at least two layers selected from silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. Therefore, sealing layers SE1, SE2, and SE3 may be formed from the same material as rib 5.

[0082] The lower part 61 of the partition 6 is formed of a conductive material and is electrically connected to each of the upper electrodes UE1, UE2, and UE3. The lower part 61 and the upper part 62 of the partition 6 may also both be formed of a conductive material.

[0083] The thickness of rib 5 is sufficiently small compared to the thickness of partition 6 and insulating layer 12. In one example, the thickness of rib 5 is greater than 200 nm and less than 400 nm.

[0084] The thickness of the lower part 61 of the partition 6 (from the upper surface of the rib 5 to the lower surface of the upper part 62) is greater than the thickness of the rib 5.

[0085] The thicknesses of sealing layer SE1, sealing layer SE2, and sealing layer SE3 are approximately the same, for example, around 1 μm.

[0086] The lower electrodes LE1, LE2, and LE3 can also be formed of transparent conductive materials such as ITO, or have a layered structure of metallic materials such as silver (Ag) and transparent conductive materials. The upper electrodes UE1, UE2, and UE3 are formed of metallic materials such as magnesium and silver alloys (MgAg). The upper electrodes UE1, UE2, and UE3 are formed of transparent conductive materials such as ITO.

[0087] Organic layers OR1, OR2, and OR3 each contain multiple functional layers, including a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer. Additionally, organic layer OR1 contains a light-emitting layer EM1. Organic layer OR2 contains a light-emitting layer EM2. The light-emitting layer EM2 is formed of a different material than the light-emitting layer EM1. Organic layer OR3 contains a light-emitting layer EM3. The light-emitting layer EM3 is formed of a different material than both the light-emitting layers EM1 and EM2.

[0088] The materials forming the light-emitting layer EM1, the light-emitting layer EM2, and the light-emitting layer EM3 are materials that emit light in different wavelength regions.

[0089] In one example, the emitting layer EM1 is formed of a material that emits light in the blue wavelength region, the emitting layer EM2 is formed of a material that emits light in the green wavelength region, and the emitting layer EM3 is formed of a material that emits light in the red wavelength region.

[0090] The capping layers CP1, CP2, and CP3 are formed, for example, from a multilayer of transparent thin films. The multilayer, as a thin film, may include both thin films formed of inorganic materials and thin films formed of organic materials. Furthermore, these multiple thin films have different refractive indices. The materials constituting the multilayer are different from the materials of the upper electrodes UE1, UE2, and UE3, and also different from the materials of the sealing layers SE1, SE2, and SE3. It should be noted that the capping layers CP1, CP2, and CP3 can also be omitted.

[0091] The protective layer 13 is formed of a multilayer of transparent films, for example, including films formed of inorganic materials and films formed of organic materials.

[0092] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 that are in contact with the side of the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages via the pixel circuits 1 of each of the sub-pixels SP1, SP2, and SP3.

[0093] If a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EM1 in the organic layer OR1 emits light in the blue wavelength region. If a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EM2 in the organic layer OR2 emits light in the green wavelength region. If a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EM3 in the organic layer OR3 emits light in the red wavelength region.

[0094] Next, an example of a manufacturing method for a display device DSP will be described.

[0095] Figure 4This is a flowchart illustrating an example of a manufacturing method for a display device DSP.

[0096] The manufacturing method shown here generally includes: a process of preparing a processing substrate SUB having sub-pixels SP1, SP2 and SP3 (step ST1); a process of forming a display element 201 of sub-pixels SP1 (step ST2); a process of forming a display element 202 of sub-pixels SP2 (step ST3); and a process of forming a display element 203 of sub-pixels SP3 (step ST4).

[0097] In step ST1, firstly, a processing substrate SUB is prepared on the substrate 10 to form the lower electrode LE1 of sub-pixel SP1, the lower electrode LE2 of sub-pixel SP2, the lower electrode LE3 of sub-pixel SP3, the rib 5, and the partition wall 6. For example... Figure 3 As shown, a circuit layer 11 and an insulating layer 12 are also formed between the substrate 10 and the lower electrodes LE1, LE2, and LE3.

[0098] In step ST2, firstly, a first thin film 31 containing the light-emitting layer EM1 is formed within the areas of sub-pixels SP1, SP2, and SP3 (step ST21). The first thin film 31 is... Figure 3 The image shows a stack of organic layer OR1, upper electrode UE1, capping layer CP1, and sealing layer SE1. Then, a first resist 41 patterned in a predetermined shape is formed on the first thin film 31 (step ST22). Then, a portion of the first thin film 31 is removed by etching using the first resist 41 as a mask (step ST23). At this time, the first thin film 31 disposed in, for example, sub-pixels SP2 and SP3, is removed. Then, the first resist 41 is removed (step ST24). Sub-pixel SP1 is thus formed. Sub-pixel SP1 includes a display element 201 having a first thin film 31 with a predetermined shape.

[0099] In step ST3, firstly, a second thin film 32 containing the light-emitting layer EM2 is formed within the area of ​​sub-pixels SP1, SP2, and SP3 (step ST31). The second thin film 32 is Figure 3 The image shows a stack of organic layer OR2, upper electrode UE2, capping layer CP2, and sealing layer SE2. Then, a second resist 42 patterned into a predetermined shape is formed on the second thin film 32 (step ST32). Next, a portion of the second thin film 32 is removed by etching using the second resist 42 as a mask (step ST33). At this time, the second thin film 32 disposed in, for example, sub-pixels SP1 and SP3, is removed. Then, the second resist 42 is removed (step ST34). This forms sub-pixel SP2. Sub-pixel SP2 includes a display element 202 having a second thin film 32 with a predetermined shape.

[0100] In step ST4, firstly, a third thin film 33 containing the light-emitting layer EM3 is formed within the area of ​​sub-pixels SP1, SP2, and SP3 (step ST41). The third thin film 33 is... Figure 3 The image shows a stack of organic layer OR3, upper electrode UE3, capping layer CP3, and sealing layer SE3. Then, a third resist 43 patterned into a predetermined shape is formed on the third thin film 33 (step ST42). Then, a portion of the third thin film 33 is removed by etching using the third resist 43 as a mask (step ST43). At this time, for example, the third thin film 33 disposed in sub-pixels SP1 and SP2 is removed. Then, the third resist 43 is removed (step ST44). Sub-pixel SP3 is thus formed. Sub-pixel SP3 includes a display element 203 having a third thin film 33 with a predetermined shape.

[0101] It should be noted that detailed illustrations of the second film 32, the second resist 42, the third film 33, and the third resist 43 are omitted.

[0102] The following is for reference Figures 5 to 9 Let's explain steps ST1 and ST2. It should be noted that... Figures 5 to 9 The cross-sections shown in the figure are, for example, along... Figure 2 The cross-section of line AB in the diagram is equivalent.

[0103] First, in step ST1, as follows Figure 5 As shown, a substrate SUB is prepared for processing. The process for preparing the substrate SUB includes: forming a circuit layer 11 on a substrate 10; forming an insulating layer 12 on the circuit layer 11; forming a lower electrode LE1 of sub-pixel SP1, a lower electrode LE2 of sub-pixel SP2, and a lower electrode LE3 of sub-pixel SP3 on the insulating layer 12; forming ribs 5 having openings AP1, AP2, and AP3 respectively overlapping with the lower electrodes LE1, LE2, and LE3; and forming a partition wall 6 including a lower portion 61 disposed on the ribs 5 and an upper portion 62 disposed on the lower portion 61 and protruding from the side of the lower portion 61. The ribs 5 are formed, for example, of silicon nitride. At least the lower portion 61 of the partition wall 6 is formed of a conductive material. It should be noted that... Figures 6 to 9 In the figures, the substrate 10 and circuit layer 11, which are located below the insulating layer 12, are omitted.

[0104] Next, in step ST21, as follows Figure 6As shown, a first thin film 31 is formed within the areas of sub-pixels SP1, SP2, and SP3. The process of forming the first thin film 31 includes: forming an organic layer OR1 containing a light-emitting layer EM1 on a processing substrate SUB; forming an upper electrode UE1 on the organic layer OR1; forming a capping layer CP1 on the upper electrode UE1; and forming a sealing layer SE1 on the capping layer CP1. In other words, in the illustrated example, the first thin film 31 includes the organic layer OR1, the upper electrode UE1, the capping layer CP1, and the sealing layer SE1.

[0105] Organic layer OR1 is formed on lower electrodes LE1, LE2, and LE3, and also on partition 6. The portion of organic layer OR1 formed on the upper part 62 is separate from the portions formed on each lower electrode. The various functional layers and light-emitting layer EM1 of organic layer OR1 are formed by vapor deposition.

[0106] Above the lower electrodes LE1, LE2, and LE3, the upper electrode UE1 is formed on the organic layer OR1, covering the rib 5 and connecting to the lower part 61 of the partition wall 6. Additionally, the upper electrode UE1 is also formed on the organic layer OR1 directly above the upper part 62. The portion of the upper electrode UE1 formed directly above the upper part 62 is separate from the portions formed directly above each of the lower electrodes. The upper electrode UE1 is formed by vapor deposition.

[0107] Above the lower electrodes LE1, LE2, and LE3, capping layers CP1 are formed on the upper electrode UE1, and also directly above the upper portion 62. The portion of capping layer CP1 formed directly above the upper portion 62 is separate from the portion formed directly above each of the lower electrodes. The first transparent layer and the second transparent layer included in capping layer CP1 are formed by vapor deposition.

[0108] The sealing layer SE1 is formed to cover the capping layer CP1 and the partition wall 6. That is, the sealing layer SE1 is formed directly above the capping layer CP1, directly above the lower electrodes LE1, LE2, and LE3, and also directly above the upper portion 62. The portion of the sealing layer SE1 directly above the upper portion 62 is connected to the portion directly above each lower electrode. The sealing layer SE1 is formed by CVD. The upper electrode UE1 is located between the rib 5 and the sealing layer SE1, and the sealing layer SE1 is separate from the rib 5.

[0109] Next, in step ST22, as follows Figure 7As shown, a patterned first resist 41 is formed on top of the sealing layer SE1. The first resist 41 covers the first thin film 31 of sub-pixel SP1, exposing the first thin film 31 of sub-pixels SP2 and SP3. That is, the first resist 41 overlaps with the sealing layer SE1 located directly above the lower electrode LE1. Furthermore, the first resist 41 extends from sub-pixel SP1 upwards towards the partition wall 6. On the partition wall 6 between sub-pixels SP1 and SP2, the first resist 41 is disposed on the sub-pixel SP1 side (left side of the figure), and on the sub-pixel SP2 side (right side of the figure), exposing the sealing layer SE1. Additionally, in sub-pixels SP2 and SP3, the first resist 41 exposes the sealing layer SE1.

[0110] Then, in step ST23, as Figure 8 As shown, etching is performed using the first resist 41 as a mask to remove the first film 31 of sub-pixels SP2 and SP3 exposed by the first resist 41, while the first film 31 remains in sub-pixel SP1.

[0111] The process of removing the first film 31 is as follows, for example.

[0112] First, dry etching is performed using the first resist 41 as a mask to remove the sealing layer SE1 exposed by the first resist 41.

[0113] Then, wet etching is performed using the first resist 41 as a mask to remove the second transparent layer of the capping layer CP1 exposed from the sealing layer SE1.

[0114] Then, using the first resist 41 as a mask, dry etching is performed to remove the first transparent layer of the capping layer CP1 exposed from the second transparent layer.

[0115] Then, wet etching is performed using the first resist 41 as a mask to remove the upper electrode UE1 exposed from the first transparent layer.

[0116] Then, dry etching is performed using the first resist 41 as a mask to remove the organic layer OR1 exposed from the upper electrode UE1.

[0117] Therefore, in sub-pixel SP2, the lower electrode LE2 is exposed, and the rib 5 surrounding the lower electrode LE2 is also exposed. Similarly, in sub-pixel SP3, the lower electrode LE3 is exposed, and the rib 5 surrounding the lower electrode LE3 is also exposed. Furthermore, in the partition 6 between sub-pixel SP1 and sub-pixel SP2, the sub-pixel SP2 side is exposed. Additionally, the partition 6 between sub-pixel SP2 and sub-pixel SP3 is exposed.

[0118] Then, in step ST24, as Figure 9As shown, the first resist 41 is removed. This exposes the sealing layer SE1 of the sub-pixel SP1. Through these steps ST21 to ST24, a display element 201 is formed in the sub-pixel SP1. The display element 201 consists of a lower electrode LE1, an organic layer OR1 containing a light-emitting layer EM1, an upper electrode UE1, and a capping layer CP1. Furthermore, the display element 201 is covered by the sealing layer SE1.

[0119] An organic layer OR1 containing a light-emitting layer EM1, an upper electrode UE1, a capping layer CP1, and a sealing layer SE1 are formed on the partition 6 between sub-pixels SP1 and SP2. Furthermore, the portion of partition 6 on the sub-pixel SP1 side is covered by the sealing layer SE1. It should be noted that there may be... Figure 9 The case shown is where the laminate on partition 6 has been completely removed.

[0120] Figure 4 Steps ST31 to ST34 shown herein are the same as steps ST21 to ST24 described above. After these steps ST31 to ST34, in... Figure 3 A display element 202 is formed in the sub-pixel SP2 shown. The display element 202 is composed of a lower electrode LE2, an organic layer OR2 containing a light-emitting layer EM2, an upper electrode UE2, and a capping layer CP2. In addition, the display element 202 is covered by a sealing layer SE2.

[0121] in addition, Figure 4 Steps ST41 to ST44 shown are the same as steps ST21 to ST24 described above. After these steps ST41 to ST44, in... Figure 3 A display element 203 is formed in the sub-pixel SP3 shown. The display element 203 is composed of a lower electrode LE3, an organic layer OR3 containing a light-emitting layer EM3, an upper electrode UE3, and a capping layer CP3. In addition, the display element 203 is covered by a sealing layer SE3.

[0122] Figure 10 This is a diagram showing an example of the configuration of display elements 201 to 203.

[0123] It should be noted that the following example illustrates the situation where the lower electrode is equivalent to the anode and the upper electrode is equivalent to the cathode.

[0124] The display element 201 includes an organic layer OR1 between the lower electrode LE1 and the upper electrode UE1.

[0125] In the organic layer OR1, the hole injection layer HIL1, the hole transport layer HTL1, the electron blocking layer EBL1, the light emitting layer EM1, the hole blocking layer HBL1, the electron transport layer ETL1, and the electron injection layer EIL1 are stacked sequentially.

[0126] The capping layer CP1 includes a first transparent layer TL11 and a second transparent layer TL12. The first transparent layer TL11 is disposed on the upper electrode UE1. The second transparent layer TL12 is disposed on the first transparent layer TL11. The sealing layer SE1 is disposed on the second transparent layer TL12.

[0127] The display element 202 includes an organic layer OR2 between the lower electrode LE2 and the upper electrode UE2.

[0128] In the organic layer OR2, the hole injection layer HIL2, the hole transport layer HTL2, the electron blocking layer EBL2, the light-emitting layer EM2, the hole blocking layer HBL2, the electron transport layer ETL2, and the electron injection layer EIL2 are stacked sequentially. In one example, the thickness T2 of the hole transport layer HTL2 is greater than the thickness T1 of the hole transport layer HTL1.

[0129] The capping layer CP2 includes a first transparent layer TL21 and a second transparent layer TL22. The first transparent layer TL21 is disposed on the upper electrode UE2. The second transparent layer TL22 is disposed on the first transparent layer TL21. The sealing layer SE2 is disposed on the second transparent layer TL22.

[0130] The display element 203 includes an organic layer OR3 between the lower electrode LE3 and the upper electrode UE3.

[0131] In the organic layer OR3, the hole injection layer HIL3, the hole transport layer HTL3, the electron blocking layer EBL3, the light-emitting layer EM3, the hole blocking layer HBL3, the electron transport layer ETL3, and the electron injection layer EIL3 are stacked sequentially. In one example, the thickness T3 of the hole transport layer HTL3 is greater than the thickness T2 of the hole transport layer HTL2.

[0132] The capping layer CP3 comprises a first transparent layer TL31 and a second transparent layer TL32. The first transparent layer TL31 is disposed on the upper electrode UE3. The second transparent layer TL32 is disposed on the first transparent layer TL31. The sealing layer SE3 is disposed on the second transparent layer TL32.

[0133] The first transparent layers TL11, TL21, and TL31 are organic layers formed of, for example, organic materials, and are also high refractive index layers having a larger refractive index than the upper electrodes UE1, UE2, and UE3.

[0134] The second transparent layers TL12, TL22, and TL32 are inorganic layers formed from inorganic materials such as lithium fluoride (LiF), and are low-refractive-index layers with a smaller refractive index than the first transparent layers TL11, TL21, and TL31.

[0135] It should be noted that the capping layers CP1, CP2, and CP3 can also be stacked in three or more layers.

[0136] In this instruction manual, Figure 10 The configuration of the display elements 201 to 203 shown is called a single structure.

[0137] Figure 11 This is another example of the configuration of display elements 201 to 203.

[0138] It should be noted that the following example illustrates the situation where the lower electrode is equivalent to the anode and the upper electrode is equivalent to the cathode.

[0139] The display element 201 includes an organic layer OR1 between the lower electrode LE1 and the upper electrode UE1.

[0140] In the organic layer OR1, the hole injection layer HIL1, the hole transport layer HTL11, the electron blocking layer EBL11, the light-emitting layer EM11, the hole blocking layer HBL11, the n-type charge generation layer nCGL1, the p-type charge generation layer pCGL1, the hole transport layer HTL12, the electron blocking layer EBL12, the light-emitting layer EM12, the hole blocking layer HBL12, the electron transport layer ETL1, and the electron injection layer EIL1 are stacked sequentially.

[0141] Hole transport layers HTL11 and HTL12 are formed from the same material.

[0142] Electron blocking layers EBL11 and EBL12 are formed from the same material.

[0143] The light-emitting layers EM11 and EM12 are formed from the same material.

[0144] Hole blocking layers HBL11 and HBL12 are formed from the same material.

[0145] The n-type charge generation layer nCGL1 is a functional layer that supplies electrons to the light-emitting layer EM11.

[0146] The p-type charge generation layer pCGL1 is a functional layer that supplies holes to the light-emitting layer EM12.

[0147] A capping layer CP1, comprising a first transparent layer TL11 and a second transparent layer TL12, is disposed on the upper electrode UE1. A sealing layer SE1 is disposed on the second transparent layer TL12.

[0148] The display element 202 includes an organic layer OR2 between the lower electrode LE2 and the upper electrode UE2.

[0149] In the organic layer OR2, the hole injection layer HIL2, the hole transport layer HTL21, the electron blocking layer EBL21, the light-emitting layer EM21, the hole blocking layer HBL21, the n-type charge generation layer nCGL2, the p-type charge generation layer pCGL2, the hole transport layer HTL22, the electron blocking layer EBL22, the light-emitting layer EM22, the hole blocking layer HBL22, the electron transport layer ETL2, and the electron injection layer EIL2 are stacked sequentially.

[0150] Hole transport layers HTL21 and HTL22 are formed of the same material. In one example, the thickness T21 of hole transport layer HTL21 is greater than the thickness T11 of hole transport layer HTL11, and the thickness T22 of hole transport layer HTL22 is greater than the thickness T12 of hole transport layer HTL12.

[0151] Electron blocking layers EBL21 and EBL22 are formed from the same material.

[0152] The light-emitting layers EM21 and EM22 are formed from the same material. The materials of the light-emitting layers EM21 and EM22 are different from those of the light-emitting layers EM11 and EM12.

[0153] Hole blocking layers HBL21 and HBL22 are formed from the same material.

[0154] The n-type charge generation layer nCGL2 is a functional layer that supplies electrons to the light-emitting layer EM21.

[0155] The p-type charge generation layer pCGL2 is a functional layer that supplies holes to the light-emitting layer EM22.

[0156] A capping layer CP2, comprising a first transparent layer TL21 and a second transparent layer TL22, is disposed on the upper electrode UE2. A sealing layer SE2 is disposed on the second transparent layer TL22.

[0157] The display element 203 includes an organic layer OR3 between the lower electrode LE3 and the upper electrode UE3.

[0158] In the organic layer OR3, the hole injection layer HIL3, the hole transport layer HTL31, the electron blocking layer EBL31, the light-emitting layer EM31, the hole blocking layer HBL31, the n-type charge generation layer nCGL3, the p-type charge generation layer pCGL3, the hole transport layer HTL32, the electron blocking layer EBL32, the light-emitting layer EM32, the hole blocking layer HBL32, the electron transport layer ETL3, and the electron injection layer EIL3 are stacked sequentially.

[0159] Hole transport layers HTL31 and HTL32 are formed of the same material. In one example, the thickness T31 of hole transport layer HTL31 is greater than the thickness T21 of hole transport layer HTL21, and the thickness T32 of hole transport layer HTL32 is greater than the thickness T22 of hole transport layer HTL22.

[0160] Electron blocking layers EBL31 and EBL32 are formed from the same material.

[0161] The light-emitting layers EM31 and EM32 are formed of the same material. The materials of the light-emitting layers EM31 and EM32 are different from those of the light-emitting layers EM11 and EM12, and also different from those of the light-emitting layers EM21 and EM22.

[0162] Hole-blocking layers HBL31 and HBL32 are formed from the same material.

[0163] The n-type charge generation layer nCGL3 is a functional layer that supplies electrons to the light-emitting layer EM31.

[0164] The p-type charge generation layer pCGL3 is a functional layer that supplies holes to the light-emitting layer EM32.

[0165] A capping layer CP3, comprising a first transparent layer TL31 and a second transparent layer TL32, is disposed on the upper electrode UE3. A sealing layer SE3 is disposed on the second transparent layer TL32.

[0166] In this instruction manual, Figure 11 The configuration of the display elements 201 to 203 shown is called a tandem structure.

[0167] Next, the vapor deposition apparatus for forming the organic layer and the upper electrode of the display element will be described. Here, as an example, the vapor deposition apparatus 100 for forming the organic layer OR1 and the upper electrode UE1 of the display element 201 will be described. It should be noted that the vapor deposition apparatus for forming the organic layer OR2 and the upper electrode UE2 of the display element 202 and the vapor deposition apparatus for forming the organic layer OR3 and the upper electrode UE3 of the display element 203 can also be configured in the same way as the vapor deposition apparatus 100 described here.

[0168] Figure 12 This is a diagram illustrating one configuration example of a vapor deposition apparatus 100. This vapor deposition apparatus 100 is applicable to reference... Figure 4 and Figure 6 The process of forming the organic layer OR1 and the upper electrode UE1 in the process of forming the first thin film 31 is described.

[0169] The vapor deposition apparatus 100 includes a load locking chamber 110, a transport chamber 120, a substrate loading and unloading chamber 130, a first rotating chamber 140, a vapor deposition section 150, and a second rotating chamber 170.

[0170] In the load-locking chamber 110, when input, for example, reference Figure 5 After processing the substrate SUB as described, a vacuum pump is used to depressurize it. The specified depressurization state is maintained in the transport chamber 120, the substrate loading and unloading chamber 130, the first rotating chamber 140, the vapor deposition section 150, and the second rotating chamber 170.

[0171] The transfer chamber 120 is connected to the load locking chamber 110. As described below, the transfer chamber 120 is equipped with a substrate transfer robot that transfers the processing substrate SUB placed in the load locking chamber 110 to the substrate loading and unloading chamber 130.

[0172] The substrate loading and unloading chamber 130 is connected to the first rotating cavity 140. As described later, the substrate loading and unloading chamber 130 is equipped with a mechanism for mounting the loaded processing substrate SUB onto a dedicated carrier and moving the carrier out to the first rotating cavity 140, or for unloading the processing substrate SUB from the carrier that has been moved out of the first rotating cavity 140.

[0173] The vapor deposition unit 150 includes a first chamber group 150A and a second chamber group 150B. The first chamber group 150A has a plurality of vapor deposition chambers 151 to 155 arranged in a row along a first transport direction TA of the transported substrate SUB. These vapor deposition chambers 151 to 155 are interconnected. The second chamber group 150B has a plurality of vapor deposition chambers 156 to 160 arranged in a row along a second transport direction TB opposite to the first transport direction TA. These vapor deposition chambers 156 to 160 are interconnected.

[0174] In the illustrated example, the vapor deposition unit 150 has 10 vapor deposition chambers 151 to 160. These 10 vapor deposition chambers 151 to 160 are arranged in a 5*2 matrix.

[0175] The vapor deposition chamber 151 is configured to form a hole injection layer HIL1.

[0176] The vapor deposition chamber 152 is configured to form a hole transport layer HTL1.

[0177] The vapor deposition chamber 153 is configured to form an electron blocking layer EBL1.

[0178] The vapor deposition chamber 154 is configured to form the light-emitting layer EM1.

[0179] The vapor deposition chamber 155 is configured to form a hole-blocking layer HBL1.

[0180] The vapor deposition chamber 156 is configured to form an n-type charge generation layer nCGL1.

[0181] The vapor deposition chamber 157 is configured to form a p-type charge generation layer pCGL1.

[0182] The vapor deposition chamber 158 is configured to form an electron transport layer ETL1.

[0183] The vapor deposition chamber 159 is configured to form an electron injection layer EIL1.

[0184] The vapor deposition chamber 160 is configured to form the upper electrode UE1.

[0185] The first rotating cavity 140 is connected to the upstream vapor deposition chamber 151 in the first chamber group 150A located in the first transport direction TA and the downstream vapor deposition chamber 160 in the second chamber group 150B located in the second transport direction TB. The first rotating cavity 140 is equipped with a mechanism for rotating the processing substrate SUB to move the processing substrate SUB that has been moved out of the vapor deposition chamber 160 into the vapor deposition chamber 151.

[0186] The second rotating cavity 170 is connected to the downstream vapor deposition chamber 155 in the first chamber group 150A located in the first transport direction TA and the upstream vapor deposition chamber 156 in the second chamber group 150B located in the second transport direction TB. The second rotating cavity 170 is equipped with a mechanism for rotating the processing substrate SUB to move the processing substrate SUB that has been moved out of the vapor deposition chamber 155 into the vapor deposition chamber 156.

[0187] exist Figure 12 In the configuration example shown, for example, vapor deposition chamber 151 corresponds to the first vapor deposition chamber, vapor deposition chamber 160 corresponds to the second vapor deposition chamber, vapor deposition chamber 155 corresponds to the third vapor deposition chamber, and vapor deposition chamber 156 corresponds to the fourth vapor deposition chamber.

[0188] Figure 13 It is used for explanation Figure 12 The diagram shows the transport room 120.

[0189] The transfer chamber 120 is equipped with a substrate transfer robot 121. The substrate transfer robot 121 is configured to rotate about a rotation axis AX120. The rotation axis AX120 is, for example, parallel to a normal relative to the horizontal plane. The arm 122 of the substrate transfer robot 121 is retractable and configured to support the substrate SUB at its front end.

[0190] The substrate transport robot 121, configured in this manner, first inserts the front end of its arm 122 into the load locking chamber 110 to support the processed substrate SUB and pulls the processed substrate SUB into the transport chamber 120. Then, the substrate transport robot 121 rotates 180° horizontally around the rotation axis AX 120, inserts the front end of its arm 122 into the substrate loading / unloading chamber 130, positions the processed substrate SUB on the carrier CR, and pulls the arm 122 back. Thus, the processed substrate SUB is placed on the carrier CR. The processed substrate SUB is fixed to the carrier CR by an electrostatic chuck. At this time, the processed substrate SUB and the carrier CR are parallel to the horizontal plane.

[0191] Figure 14 It is used for explanation Figure 12 The figure shows the substrate loading and unloading chamber 130 and the first rotating cavity 140.

[0192] The transport rail R0 is configured to extend within the area of ​​the substrate loading and unloading chamber 130 and the first rotating cavity 140, and to transport the carrier CR between the substrate loading and unloading chamber 130 and the first rotating cavity 140.

[0193] The substrate loading and unloading chamber 130 is equipped with a longitudinal lifting mechanism 131. The longitudinal lifting mechanism 131 is configured to rotate about a rotation axis AX130. The rotation axis AX130 is parallel to the horizontal plane.

[0194] The longitudinal erection mechanism 131 rotates 90° around the rotation axis AX130, causing the processing substrate SUB fixed to the carrier CR to stand upright. Then, the longitudinal erection mechanism 131 positions the carrier CR on the transport guide rail R0. Then, the carrier CR and the processing substrate SUB are transported along the transport guide rail R0 to the first rotating cavity 140.

[0195] Additionally, the longitudinal erecting mechanism 131 receives the carrier CR transported from the first rotating cavity 140 and rotates it 90° around the rotation axis AX130, making the processing substrate SUB fixed to the carrier CR parallel to the horizontal plane. Then, the processing substrate SUB is released from its electrostatic chuck fixation and is moved out of the substrate loading and unloading chamber 130 by the substrate transport robot 121.

[0196] The first rotating cavity 140 includes a rotating mechanism 141. The rotating mechanism 141 is configured to rotate about a rotation axis AX140. The rotation axis AX140 is parallel to the normal to the horizontal plane.

[0197] When the processing substrate SUB and the carrier CR are removed from the vapor deposition chamber 160, the rotating mechanism 141 rotates 180° in the horizontal plane around the rotation axis AX140. Then, the processing substrate SUB and the carrier CR are moved out toward the vapor deposition chamber 151. Alternatively, the processing substrate SUB and the carrier CR are moved out toward the substrate loading and unloading chamber 130.

[0198] It should be noted that the second rotating cavity 170 also has the same rotating mechanism as the first rotating cavity 140.

[0199] Figure 15 It is used for explanation Figure 12 The figure shows the vapor deposition section 150.

[0200] The first transport guide rail R1 is configured to extend from the vapor deposition chamber 151 to the vapor deposition chamber 155 to transport the carrier CR on which the processing substrate SUB is mounted.

[0201] The second transport guide rail R2 is configured to extend from the vapor deposition chamber 156 to the vapor deposition chamber 160 to transport the carrier CR on which the processing substrate SUB is mounted.

[0202] Each of the vapor deposition chambers 151 to 160 has a vapor deposition source and a partition plate.

[0203] Specifically, the vapor deposition chamber 151 includes a vapor deposition source S1 and a partition plate P1. The partition plate P1 separates the vapor deposition chamber 151 into a first space 151A and a second space 151B. The vapor deposition source S1 is housed in the first space 151A. The second space 151B is a space for transporting the processing substrate SUB and the carrier CR together, and is provided with a first transport guide rail R1. The vapor deposition source S1 is configured to irradiate material used to form the hole injection layer HIL1.

[0204] The vapor deposition chamber 152 includes a vapor deposition source S2 and a partition plate P2. The vapor deposition source S2 is housed in the first space 152A and is configured to radiate material for forming the hole transport layer HTL1.

[0205] The vapor deposition chamber 153 includes a vapor deposition source S3 and a partition plate P3. The vapor deposition source S3 is housed in the first space 153A and is configured to radiate material used to form the electron blocking layer EBL1.

[0206] The vapor deposition chamber 154 includes a vapor deposition source S4 and a partition plate P4. The vapor deposition source S4 is housed in the first space 154A and is configured to radiate material used to form the light-emitting layer EM1.

[0207] The vapor deposition chamber 155 includes a vapor deposition source S5 and a partition plate P5. The vapor deposition source S5 is housed in the first space 155A and is configured to radiate material for forming the hole blocking layer HBL1.

[0208] The first transport guide rail R1 is provided in the second spaces 151B to 155B of each of the vapor deposition chambers 151 to 155. As a result, the carrier CR is continuously transported within the range from the vapor deposition chamber 151 to the vapor deposition chamber 155.

[0209] The vapor deposition chamber 156 includes a vapor deposition source S6 and a partition plate P6. The vapor deposition source S6 is housed in the first space 156A and is configured to radiate material for forming the n-type charge generation layer nCGL1.

[0210] The vapor deposition chamber 157 includes a vapor deposition source S7 and a partition plate P7. The vapor deposition source S7 is housed in the first space 157A and is configured to radiate material for forming the p-type charge generation layer pCGL1.

[0211] The vapor deposition chamber 158 includes a vapor deposition source S8 and a partition plate P8. The vapor deposition source S8 is housed in the first space 158A and is configured to radiate material for forming the electron transport layer ETL1.

[0212] The vapor deposition chamber 159 includes a vapor deposition source S9 and a partition plate P9. The vapor deposition source S9 is housed in the first space 159A and is configured to radiate material used to form the electron injection layer EIL1.

[0213] The vapor deposition chamber 160 includes a vapor deposition source S10 and a partition plate P10. The vapor deposition source S10 is housed in the first space 160A and is configured to radiate a material (e.g., a mixture of magnesium and silver) for forming the upper electrode UE1.

[0214] The second transport guide rail R2 is provided in the second space 156B to 160B of each of the vapor deposition chambers 156 to 160. Thus, the carrier CR is continuously transported within the range from the vapor deposition chamber 156 to the vapor deposition chamber 160.

[0215] Each of the vapor deposition sources S1 to S10 is configured to heat, vaporize, and continuously emit material during operation of the vapor deposition unit 150. The materials emitted from each of the vapor deposition sources S1 to S10 are different. In a mode where the emitted material is not deposited onto the processing substrate SUB, the outlet of the vapor deposition source faces the first space. Conversely, in a mode where the emitted material is deposited onto the processing substrate SUB, the outlet of the vapor deposition source faces the second space.

[0216] For example, in the vapor deposition chamber 151, the vapor deposition source S1 is configured to rotate about the rotation axis AX1. The vapor deposition source S1 extends along the rotation axis AX1. The partition plate P1 has an opening OP1, indicated by a dashed line. The opening OP1 is opposite to the vapor deposition source S1.

[0217] In the illustrated example, the vapor deposition source S1 is configured to deposit emitted material onto the processing substrate SUB, and the discharge port SA1 faces the second space 151B. Thus, the material emitted from the vapor deposition source S1 is deposited onto the processing substrate SUB, which is transported together with the carrier CR.

[0218] For example, in the vapor deposition chamber 160, the vapor deposition source S10 is configured to rotate about the rotation axis AX10. The vapor deposition source S10 extends along the rotation axis AX10. The partition plate P10 has an opening OP10, indicated by a dashed line. The opening OP10 is opposite to the vapor deposition source S10.

[0219] In the illustrated example, the vapor deposition source S10 is set to a mode in which it does not deposit the emitted material onto the processing substrate SUB, and the discharge port SA10 faces the first space 160A. As a result, the material emitted from the vapor deposition source S10 is not deposited onto the processing substrate SUB, which is transported together with the carrier CR.

[0220] Next, refer to Figure 16 Explanation of the use Figure 12 The vapor deposition apparatus 100 shown in the figure is formed Figure 10 The process of the organic layer OR1 and the upper electrode UE1 of the display element 201 shown in the figure.

[0221] First, prepare references Figure 5 The processing substrate SUB is then placed into the load locking chamber 110 of the vapor deposition apparatus 100 without a fine mask.

[0222] The processing substrate SUB passes through the transport chamber 120 and the substrate loading and unloading chamber 130, and then through the first rotating cavity 140. Then, the processing substrate SUB passes through the first chamber group 150A, rotates 180° in the second rotating cavity 170, and passes through the second chamber group 150B.

[0223] When the substrate SUB passes through the first chamber group 150A, a hole injection layer HIL1 is formed on the lower electrode LE1 in the evaporation chamber 151, a hole transport layer HTL1 is formed on the hole injection layer HIL1 in the evaporation chamber 152, an electron blocking layer EBL1 is formed on the hole transport layer HTL1 in the evaporation chamber 153, a light-emitting layer EM1 is formed on the electron blocking layer EBL1 in the evaporation chamber 154, and a hole blocking layer HBL1 is formed on the light-emitting layer EM1 in the evaporation chamber 155.

[0224] When the processing substrate SUB passes through the second chamber group 150B, the evaporation chambers 156 and 157 are set to a mode in which material emitted from the evaporation source is not deposited onto the processing substrate SUB. Therefore, the processing substrate SUB passes through the evaporation chambers 156 and 157 without being deposited with material.

[0225] Then, in the vapor deposition chamber 158, an electron transport layer ETL1 is formed on top of the hole blocking layer HBL1; in the vapor deposition chamber 159, an electron injection layer EIL1 is formed on top of the electron transport layer ETL1; and in the vapor deposition chamber 160, an upper electrode UE1 is formed on top of the electron injection layer EIL1.

[0226] Then, the processed substrate SUB passes through the first rotating cavity 140, through the substrate loading and unloading chamber 130 and the transport chamber 120, and returns to the load locking chamber 110, and is removed from the vapor deposition apparatus 100.

[0227] In the processed substrate SUB that is removed from the vapor deposition apparatus 100, as shown in reference Figure 6 As explained, the organic layer OR1 formed on the partition wall 6 is separate from the organic layer OR1 formed on the lower electrode LE1 in the opening AP1. The upper electrode UE1 formed on the partition wall 6 is separate from the upper electrode UE1 formed directly above the lower electrode LE1.

[0228] Next, refer to Figure 17 and Figure 18 Explanation of the use Figure 12 The vapor deposition apparatus 100 shown in the figure is formed Figure 11 The process of the organic layer OR1 and the upper electrode UE1 of the display element 201 shown in the figure.

[0229] First, such as Figure 17 As shown, the processing substrate SUB is placed into the load locking chamber 110 of the vapor deposition apparatus 100 without a fine mask.

[0230] The processing substrate SUB passes through the transport chamber 120 and the substrate loading and unloading chamber 130, and then through the first rotating cavity 140. Then, the processing substrate SUB passes through the first chamber group 150A, rotates 180° in the second rotating cavity 170, and passes through the second chamber group 150B.

[0231] When the substrate SUB passes through the first chamber group 150A, a hole injection layer HIL1 is formed on the lower electrode LE1 in the evaporation chamber 151, a hole transport layer HTL11 is formed on the hole injection layer HIL1 in the evaporation chamber 152, an electron blocking layer EBL11 is formed on the hole transport layer HTL11 in the evaporation chamber 153, a light-emitting layer EM11 is formed on the electron blocking layer EBL11 in the evaporation chamber 154, and a hole blocking layer HBL11 is formed on the light-emitting layer EM11 in the evaporation chamber 155.

[0232] When the processing substrate SUB passes through the second chamber group 150B, an n-type charge generation layer nCGL1 is formed on the hole blocking layer HBL11 in the evaporation chamber 156, and a p-type charge generation layer pCGL1 is formed on the n-type charge generation layer nCGL1 in the evaporation chamber 157.

[0233] In the vapor deposition chambers 158 to 160, a mode is set in which material emitted from the vapor deposition source is not deposited onto the processing substrate SUB. Therefore, the processing substrate SUB passes through the vapor deposition chambers 158 to 160 without being deposited with material.

[0234] Then, as Figure 18 As shown, the processing substrate SUB rotates 180° in the first rotating cavity 140 and passes through the first chamber group 150A, and rotates 180° in the second rotating cavity 170 and passes through the second chamber group 150B.

[0235] When the processing substrate SUB passes through the first chamber group 150A, the vapor deposition chamber 151 is set to a mode in which material emitted from the vapor deposition source is not deposited onto the processing substrate SUB. Therefore, the processing substrate SUB passes through the vapor deposition chamber 151 without being deposited with material.

[0236] Then, in the evaporation chamber 152, a hole transport layer HTL12 is formed on the p-type charge generation layer pCGL1; in the evaporation chamber 153, an electron blocking layer EBL12 is formed on the hole transport layer HTL12; in the evaporation chamber 154, a light-emitting layer EM12 is formed on the electron blocking layer EBL12; and in the evaporation chamber 155, a hole blocking layer HBL12 is formed on the light-emitting layer EM12.

[0237] When the processing substrate SUB passes through the second chamber group 150B, the evaporation chambers 156 and 157 are set to a mode in which material emitted from the evaporation source is not deposited onto the processing substrate SUB. Therefore, the processing substrate SUB passes through the evaporation chambers 156 and 157 without being deposited with material.

[0238] Then, in the vapor deposition chamber 158, an electron transport layer ETL1 is formed on top of the hole blocking layer HBL12; in the vapor deposition chamber 159, an electron injection layer EIL1 is formed on top of the electron transport layer ETL1; and in the vapor deposition chamber 160, an upper electrode UE1 is formed on top of the electron injection layer EIL1.

[0239] Then, the processed substrate SUB passes through the first rotating cavity 140, through the substrate loading and unloading chamber 130 and the transport chamber 120, and returns to the load locking chamber 110, and is removed from the vapor deposition apparatus 100.

[0240] In the processed substrate SUB that is removed from the vapor deposition apparatus 100, as shown in reference Figure 6As explained, the organic layer OR1 formed on the partition wall 6 is separate from the organic layer OR1 formed on the lower electrode LE1 in the opening AP1. In addition, the upper electrode UE1 formed on the partition wall 6 is separate from the upper electrode UE1 formed in the opening AP1 directly above the lower electrode LE1.

[0241] In the illustrated example, hole transport layer HTL11 is equivalent to the first hole transport layer, and hole transport layer HTL12 is equivalent to the second hole transport layer. Hole transport layers HTL11 and HTL12 are formed from the same material in the same vapor deposition chamber 152.

[0242] Electron blocking layer EBL11 is equivalent to the first electron blocking layer, and electron blocking layer EBL12 is equivalent to the second electron blocking layer. Electron blocking layers EBL11 and EBL12 are formed from the same material in the same vapor deposition chamber 153.

[0243] The light-emitting layer EM11 is equivalent to the first light-emitting layer, and the light-emitting layer EM12 is equivalent to the second light-emitting layer. The light-emitting layers EM11 and EM12 are formed from the same material in the same vapor deposition chamber 154.

[0244] Hole blocking layer HBL11 is equivalent to the first hole blocking layer, and hole blocking layer HBL12 is equivalent to the second hole blocking layer. Hole blocking layers HBL11 and HBL12 are formed from the same material in the same vapor deposition chamber 154.

[0245] It should be noted that, in reference Figures 16 to 18 In the process of forming the organic layer OR1 and the upper electrode UE1, the transport speed of the processing substrate SUB when passing through the first chamber group 150A and the second chamber group 150B is constant.

[0246] As explained above, according to this embodiment, either a single-structure display element or a series-structure display element can be easily formed in a vapor deposition apparatus 100. Therefore, even if there is a large difference in the manufacturing ratio between series-structure and single-structure products, the reduction in the operating efficiency of the vapor deposition apparatus 100 can be suppressed.

[0247] Furthermore, the vapor deposition apparatus 100 can achieve various series structures by having both the function of vapor deposition material while surrounding the vapor deposition section more than 150 times and the mode setting function of selecting whether or not to vapor deposit radioactive materials.

[0248] Furthermore, in the case of display elements forming a series structure, multiple identical functional layers can be formed in a single vapor deposition chamber. Therefore, compared to vapor deposition apparatuses equipped with vapor deposition chambers for forming each layer, the number of vapor deposition chambers is reduced. Consequently, equipment costs are reduced, and the installation space or equipment size is minimized.

[0249] Next, other vapor deposition apparatuses for forming the organic layer and upper electrode of the display element will be described. Here, as an example, a vapor deposition apparatus 100 for forming the organic layer OR1 and upper electrode UE1 of the display element 201 will be described. It should be noted that the vapor deposition apparatuses for forming the organic layer OR2 and upper electrode UE2 of the display element 202 and the organic layer OR3 and upper electrode UE3 of the display element 203 can also be configured in the same way as the vapor deposition apparatus 100 described here.

[0250] Figure 19 This is a diagram illustrating another configuration example of the vapor deposition apparatus 100. This vapor deposition apparatus 100 is used in reference... Figure 4 and Figure 6 The process of forming the organic layer OR1 and the upper electrode UE1 in the process of forming the first thin film 31 described herein.

[0251] and Figure 12 Compared to the examples shown, Figure 19 The example shown differs in that the vapor deposition unit 150 further includes a vapor deposition chamber 161 for forming the first transparent layer TL1 and a vapor deposition chamber 162 for forming the second transparent layer TL2. Other configurations of the vapor deposition apparatus 100 are similar to... Figure 12 The examples shown are the same, marked with the same reference numerals and detailed descriptions omitted.

[0252] The vapor deposition unit 150 includes a first chamber group 150A and a second chamber group 150B. The first chamber group 150A has a plurality of vapor deposition chambers 151 to 156 arranged in a row along a first transport direction TA of the transport processing substrate SUB. These vapor deposition chambers 151 to 156 are interconnected. The second chamber group 150B has a plurality of vapor deposition chambers 157 to 162 arranged in a row along a second transport direction TB opposite to the first transport direction TA. These vapor deposition chambers 157 to 162 are interconnected.

[0253] In the illustrated example, the vapor deposition unit 150 has 12 vapor deposition chambers 151 to 162. These 12 vapor deposition chambers 151 to 162 are arranged in a 6*2 matrix.

[0254] The vapor deposition chamber 151 is configured to form a hole injection layer HIL1.

[0255] The vapor deposition chamber 152 is configured to form a hole transport layer HTL1.

[0256] The vapor deposition chamber 153 is configured to form an electron blocking layer EBL1.

[0257] The vapor deposition chamber 154 is configured to form the light-emitting layer EM1.

[0258] The vapor deposition chamber 155 is configured to form a hole-blocking layer HBL1.

[0259] The vapor deposition chamber 156 is configured to form an n-type charge generation layer nCGL1.

[0260] The vapor deposition chamber 157 is configured to form a p-type charge generation layer pCGL1.

[0261] The vapor deposition chamber 158 is configured to form an electron transport layer ETL1.

[0262] The vapor deposition chamber 159 is configured to form an electron injection layer EIL1.

[0263] The vapor deposition chamber 160 is configured to form the upper electrode UE1.

[0264] The vapor deposition chamber 161 is configured to form the first transparent layer TL1.

[0265] The vapor deposition chamber 162 is configured to form the second transparent layer TL2. For example, the vapor deposition chamber 162 is configured to use radioactive lithium fluoride as the material for forming the second transparent layer TL2.

[0266] The first rotating cavity 140 is connected to the upstream vapor deposition chamber 151 in the first chamber group 150A located in the first transport direction TA and the downstream vapor deposition chamber 162 in the second chamber group 150B located in the second transport direction TB. The first rotating cavity 140 is equipped with a mechanism for rotating the processing substrate SUB to move the processing substrate SUB that has been moved out of the vapor deposition chamber 162 into the vapor deposition chamber 151.

[0267] The second rotating cavity 170 is connected to the downstream vapor deposition chamber 156 in the first chamber group 150A located in the first transport direction TA and the upstream vapor deposition chamber 157 in the second chamber group 150B located in the second transport direction TB. The second rotating cavity 170 is equipped with a mechanism for rotating the processing substrate SUB to move the processing substrate SUB that has been moved out of the vapor deposition chamber 156 into the vapor deposition chamber 157.

[0268] exist Figure 19 In the configuration example shown, for example, vapor deposition chamber 151 corresponds to the first vapor deposition chamber, vapor deposition chamber 162 corresponds to the second vapor deposition chamber, vapor deposition chamber 156 corresponds to the third vapor deposition chamber, and vapor deposition chamber 157 corresponds to the fourth vapor deposition chamber.

[0269] Next, refer to Figure 20 Explanation of the use Figure 19 The vapor deposition apparatus 100 shown in the figure is used to form Figure 10 The process of organic layer OR1, upper electrode UE1 and capping layer CP1 of display element 201 shown in the figure.

[0270] First, prepare references Figure 5 The processing substrate SUB is then placed into the load locking chamber 110 of the vapor deposition apparatus 100 without a fine mask.

[0271] The processing substrate SUB passes through the transport chamber 120 and the substrate loading and unloading chamber 130, and then through the first rotating cavity 140. Then, the processing substrate SUB passes through the first chamber group 150A, rotates 180° in the second rotating cavity 170, and passes through the second chamber group 150B.

[0272] When the substrate SUB passes through the first chamber group 150A, a hole injection layer HIL1 is formed on the lower electrode LE1 in the evaporation chamber 151, a hole transport layer HTL1 is formed on the hole injection layer HIL1 in the evaporation chamber 152, an electron blocking layer EBL1 is formed on the hole transport layer HTL1 in the evaporation chamber 153, a light-emitting layer EM1 is formed on the electron blocking layer EBL1 in the evaporation chamber 154, and a hole blocking layer HBL1 is formed on the light-emitting layer EM1 in the evaporation chamber 155.

[0273] The vapor deposition chamber 156 is configured to prevent material emitted from the vapor deposition source from being deposited onto the processing substrate SUB. Therefore, the processing substrate SUB passes through the vapor deposition chamber 156 without being deposited with material.

[0274] When the processing substrate SUB passes through the second chamber group 150B, the evaporation chamber 157 is set to a mode in which material emitted from the evaporation source is not deposited onto the processing substrate SUB. Therefore, the processing substrate SUB passes through the evaporation chamber 157 without being deposited with material.

[0275] Then, in the evaporation chamber 158, an electron transport layer ETL1 is formed on top of the hole blocking layer HBL1; in the evaporation chamber 159, an electron injection layer EIL1 is formed on top of the electron transport layer ETL1; in the evaporation chamber 160, an upper electrode UE1 is formed on top of the electron injection layer EIL1; in the evaporation chamber 161, a first transparent layer TL1 is formed on top of the upper electrode UE1; and in the evaporation chamber 162, a second transparent layer TL2 is formed on top of the first transparent layer TL1.

[0276] Then, the processed substrate SUB passes through the first rotating cavity 140, through the substrate loading and unloading chamber 130 and the transport chamber 120, and returns to the load locking chamber 110, and is removed from the vapor deposition apparatus 100.

[0277] In the processed substrate SUB that is removed from the vapor deposition apparatus 100, as shown in reference Figure 6As explained, the organic layer OR1 formed on the partition wall 6 is separated from the organic layer OR1 formed on the lower electrode LE1 in the opening AP1. The upper electrode UE1 formed on the partition wall 6 is separated from the upper electrode UE1 formed directly above the lower electrode LE1. The first transparent layer TL1 and the second transparent layer TL2 formed on the partition wall 6 are separated from the first transparent layer TL1 and the second transparent layer TL2 formed directly above the lower electrode LE1.

[0278] Next, refer to Figure 21 and Figure 22 Explanation of the use Figure 19 The vapor deposition apparatus 100 shown in the figure is formed Figure 11 The process of organic layer OR1, upper electrode UE1 and capping layer CP1 of display element 201 shown in the figure.

[0279] First, such as Figure 21 As shown, the processing substrate SUB is placed into the load locking chamber 110 of the vapor deposition apparatus 100 without a fine mask.

[0280] The processing substrate SUB passes through the transport chamber 120 and the substrate loading and unloading chamber 130, and then through the first rotating cavity 140. Then, the processing substrate SUB passes through the first chamber group 150A, rotates 180° in the second rotating cavity 170, and passes through the second chamber group 150B.

[0281] When the processing substrate SUB passes through the first chamber group 150A, a hole injection layer HIL1 is formed on the lower electrode LE1 in the evaporation chamber 151, a hole transport layer HTL11 is formed on the hole injection layer HIL1 in the evaporation chamber 152, an electron blocking layer EBL11 is formed on the hole transport layer HTL11 in the evaporation chamber 153, a light-emitting layer EM11 is formed on the electron blocking layer EBL11 in the evaporation chamber 154, a hole blocking layer HBL11 is formed on the light-emitting layer EM11 in the evaporation chamber 155, and an n-type charge generation layer nCGL1 is formed on the hole blocking layer HBL11 in the evaporation chamber 156.

[0282] When the processing substrate SUB passes through the second chamber group 150B, a p-type charge generation layer pCGL1 is formed on the n-type charge generation layer nCGL1 in the vapor deposition chamber 157.

[0283] The vapor deposition chambers 158 to 162 are configured to prevent the material emitted from the vapor deposition source from being deposited onto the processing substrate SUB. Therefore, the processing substrate SUB passes through the vapor deposition chambers 158 to 162 without being deposited with material.

[0284] Then, as Figure 22As shown, the processing substrate SUB rotates 180° in the first rotating cavity 140 and passes through the first chamber group 150A, and rotates 180° in the second rotating cavity 170 and passes through the second chamber group 150B.

[0285] When the processing substrate SUB passes through the first chamber group 150A, the vapor deposition chamber 151 is set to a mode in which material emitted from the vapor deposition source is not deposited onto the processing substrate SUB. Therefore, the processing substrate SUB passes through the vapor deposition chamber 151 without being deposited with material.

[0286] Then, in the evaporation chamber 152, a hole transport layer HTL12 is formed on the p-type charge generation layer pCGL1; in the evaporation chamber 153, an electron blocking layer EBL12 is formed on the hole transport layer HTL12; in the evaporation chamber 154, a light-emitting layer EM12 is formed on the electron blocking layer EBL12; and in the evaporation chamber 155, a hole blocking layer HBL12 is formed on the light-emitting layer EM12.

[0287] The vapor deposition chamber 156 is configured to prevent material emitted from the vapor deposition source from being deposited onto the processing substrate SUB. Therefore, the processing substrate SUB passes through the vapor deposition chamber 156 without being deposited with material.

[0288] When the processing substrate SUB passes through the second chamber group 150B, the evaporation chamber 157 is set to a mode in which material emitted from the evaporation source is not deposited onto the processing substrate SUB. Therefore, the processing substrate SUB passes through the evaporation chamber 157 without being deposited with material.

[0289] Then, in the evaporation chamber 158, an electron transport layer ETL1 is formed on top of the hole blocking layer HBL12; in the evaporation chamber 159, an electron injection layer EIL1 is formed on top of the electron transport layer ETL1; in the evaporation chamber 160, an upper electrode UE1 is formed on top of the electron injection layer EIL1; in the evaporation chamber 161, a first transparent layer TL1 is formed on top of the upper electrode UE1; and in the evaporation chamber 162, a second transparent layer TL2 is formed on top of the first transparent layer TL1.

[0290] Then, the processed substrate SUB passes through the first rotating cavity 140, through the substrate loading and unloading chamber 130 and the transport chamber 120, and returns to the load locking chamber 110, and is removed from the vapor deposition apparatus 100.

[0291] In the processed substrate SUB removed from the vapor deposition apparatus 100, as shown in the reference Figure 6As explained, the organic layer OR1 formed on the partition wall 6 is separate from the organic layer OR1 formed on the lower electrode LE1 in the opening AP1. The upper electrode UE1 formed on the partition wall 6 is separate from the upper electrode UE1 formed directly above the lower electrode LE1. The first transparent layer TL1 and the second transparent layer TL2 formed on the partition wall 6 are separate from the first transparent layer TL1 and the second transparent layer TL2 formed directly above the lower electrode LE1.

[0292] In the illustrated example, hole transport layer HTL11 is equivalent to the first hole transport layer, and hole transport layer HTL12 is equivalent to the second hole transport layer. Hole transport layers HTL11 and HTL12 are formed from the same material in the same vapor deposition chamber 152.

[0293] Electron blocking layer EBL11 is equivalent to the first electron blocking layer, and electron blocking layer EBL12 is equivalent to the second electron blocking layer. Electron blocking layers EBL11 and EBL12 are formed from the same material in the same vapor deposition chamber 153.

[0294] The light-emitting layer EM11 is equivalent to the first light-emitting layer, and the light-emitting layer EM12 is equivalent to the second light-emitting layer. The light-emitting layers EM11 and EM12 are formed from the same material in the same vapor deposition chamber 154.

[0295] Hole blocking layer HBL11 is equivalent to the first hole blocking layer, and hole blocking layer HBL12 is equivalent to the second hole blocking layer. Hole blocking layers HBL11 and HBL12 are formed from the same material in the same vapor deposition chamber 154.

[0296] It should be noted that, in reference Figures 20 to 22 In the process of forming the organic layer OR1, the upper electrode UE1 and the capping layer CP1, the transport speed of the processing substrate SUB when passing through the first chamber group 150A and the second chamber group 150B is constant.

[0297] With this vapor deposition apparatus, the same effect as the vapor deposition apparatus described above can be achieved. Moreover, it is possible to continuously vapor deposit organic layers, upper electrodes, and capping layers.

[0298] As explained above, this embodiment can provide a vapor deposition apparatus and method that can reduce costs and minimize installation space.

[0299] Any vapor deposition apparatus and method that can be appropriately designed, modified, and implemented by those skilled in the art based on the above description of the vapor deposition apparatus and method as embodiments of the present invention, as long as they contain the essence of the present invention, also falls within the scope of the present invention.

[0300] It should be understood that various modifications and variations that can be conceived by those skilled in the art within the scope of the present invention also fall within the scope of the present invention. For example, as long as the essence of the present invention is present, technical solutions obtained by those skilled in the art through appropriate addition, deletion, or design changes to the above-described embodiments, or through the addition, omission, or modification of processes or conditions, are also included within the scope of the present invention.

[0301] Furthermore, regarding other effects resulting from the methods described in the above embodiments, any effects that are clear from the description in this specification or that can be reasonably conceived by those skilled in the art should naturally be considered as effects resulting from the present invention.

Claims

1. A vapor deposition apparatus configured to perform vapor deposition on a substrate being processed, without separately setting a mask on the substrate being processed. The processing substrate includes: The lower electrode is located above the substrate; The rib has an opening that overlaps with the lower electrode; The partition includes a lower portion located above the rib and an upper portion located above the lower portion and projecting from the side of the lower portion; The vapor deposition apparatus includes: The first chamber group has a plurality of vapor deposition chambers arranged in a row along a first conveying direction of the conveying processing substrate; The second chamber group has a plurality of vapor deposition chambers arranged in a row along a second conveying direction opposite to the first conveying direction; The first rotating cavity is connected to the first vapor deposition chamber located at the upstream end of the first conveying direction in the first chamber group and the second vapor deposition chamber located at the downstream end of the second conveying direction in the second chamber group. A second rotating cavity is connected to a third vapor deposition chamber in the first chamber group located downstream in the first conveying direction and a fourth vapor deposition chamber in the second chamber group located upstream in the second conveying direction. The processing substrate is rotated such that it is moved from the third vapor deposition chamber into the fourth vapor deposition chamber. The first chamber group, the second chamber group, the first rotating cavity, and the second rotating cavity are configured to form a loop path, such that the processing substrate passes through at least one vapor deposition chamber more than once along the loop path. The substrate loading and unloading chamber is connected to the first rotating cavity. The substrate loading and unloading chamber is configured to mount the processed substrate to be loaded into a carrier, move the carrier out to the first rotating cavity, and remove the processed substrate from the carrier that has been moved out of the first rotating cavity. The first and second vapor deposition chambers are configured to be arranged in a direction orthogonal to the first transport direction and to radiate different materials toward the processed substrate. The vapor deposition apparatus is configured to switch between a first mode and a second mode. The first mode is a mode in which the processed substrate, removed from the second evaporation chamber, is moved into the substrate loading and unloading chamber via the first rotating chamber. The second mode is a mode in which the processed substrate, after being moved out of the second vapor deposition chamber, is rotated 180° in the first rotating chamber and then moved into the first vapor deposition chamber.

2. The vapor deposition apparatus according to claim 1, further comprising: A first conveying guide rail, configured to extend within the range from the first to the third vapor deposition chambers, conveys the carrier; and The second conveying guide rail is configured to extend within the range from the second vapor deposition chamber to the fourth vapor deposition chamber to convey the carrier.

3. The vapor deposition apparatus according to claim 2, wherein, Each of the plurality of vapor deposition chambers includes: a vapor deposition source configured to emit material from an outlet; and a partition plate separating a first space containing the vapor deposition source from a second space for transporting the processing substrate. The first conveying guide rail is installed in the second space of each vapor deposition chamber from the first vapor deposition chamber to the third vapor deposition chamber. The second conveying guide rail is installed in the second space of each vapor deposition chamber from the second vapor deposition chamber to the fourth vapor deposition chamber. The partition plate has an opening opposite to the vapor deposition source. The vapor deposition source is configured such that, in a mode where the emitted material is not deposited onto the processing substrate, the outlet faces the first space, and in a mode where the emitted material is deposited onto the processing substrate, the outlet faces the second space.

4. The vapor deposition apparatus according to claim 3, wherein, The vapor deposition sources located in each of the plurality of vapor deposition chambers are configured to radiate different materials from each other.

5. The vapor deposition apparatus according to claim 4, wherein, The material emitted from the vapor deposition source in the first vapor deposition chamber is a material used to form a hole injection layer.

6. The vapor deposition apparatus according to claim 5, wherein, The material emitted from the vapor deposition source in the second vapor deposition chamber is a mixture of magnesium and silver.

7. The vapor deposition apparatus according to claim 5, wherein, The material emitted from the vapor deposition source in the second vapor deposition chamber is lithium fluoride.

8. The vapor deposition apparatus according to claim 1, wherein, The first chamber group includes: a first evaporation chamber for forming a hole injection layer; an evaporation chamber for forming a hole transport layer; an evaporation chamber for forming an electron blocking layer; an evaporation chamber for forming a light-emitting layer; and a third evaporation chamber for forming a hole blocking layer. The second chamber group includes: the fourth vapor deposition chamber for forming an n-type charge generation layer; the vapor deposition chamber for forming a p-type charge generation layer; the vapor deposition chamber for forming an electron transport layer; the vapor deposition chamber for forming an electron injection layer; and the second vapor deposition chamber for forming an upper electrode.

9. The vapor deposition apparatus according to claim 1, wherein, The first chamber group includes: a first evaporation chamber for forming a hole injection layer; an evaporation chamber for forming a hole transport layer; an evaporation chamber for forming an electron blocking layer; an evaporation chamber for forming a light-emitting layer; an evaporation chamber for forming a hole blocking layer; and a third evaporation chamber for forming an n-type charge generation layer. The second chamber group includes: the fourth vapor deposition chamber for forming a p-type charge generation layer; the vapor deposition chamber for forming an electron transport layer; the vapor deposition chamber for forming an electron injection layer; the vapor deposition chamber for forming an upper electrode; the vapor deposition chamber for forming a first transparent layer; and the second vapor deposition chamber for forming a second transparent layer.

10. Evaporation deposition method, wherein, A processing substrate is prepared, wherein a lower electrode is formed on the upper part of the substrate, and a rib having an opening overlapping the lower electrode is formed, and a partition wall is formed including a lower portion located above the rib and an upper portion located above the lower portion and protruding from the side of the lower portion. The processing substrate is moved into a vapor deposition apparatus without a mask to form an organic layer, an upper electrode is formed on the organic layer, and the processing substrate with the upper electrode formed is removed from the vapor deposition apparatus. The processing substrate is transported into the vapor deposition apparatus. It is mounted on a carrier in the substrate loading and unloading chamber. Together with the carrier, it passes through the first rotating cavity, Passing through the first chamber group, which has multiple vapor deposition chambers arranged in a row along the first conveying direction, Rotate 180° in the second rotating cavity The processed substrate passes through a second chamber group having a plurality of vapor deposition chambers arranged in a row along a second transport direction opposite to the first transport direction, wherein the processed substrate circulates through the first chamber group and the second chamber group such that the processed substrate passes through at least one vapor deposition chamber more than once. In the first mode, the substrate is moved into the substrate loading and unloading chamber via the first rotating cavity, unloaded from the carrier, and then removed from the vapor deposition apparatus. In the second mode, the substrate is rotated 180° within the first rotating cavity. After passing through the first chamber group, Rotate 180° in the second rotating cavity After passing through the second chamber group, The substrate is moved into the substrate loading and unloading chamber via the first rotating cavity, unloaded from the carrier, and then removed from the vapor deposition apparatus. In the processed substrate removed from the vapor deposition apparatus, the organic layer and the upper electrode formed on the partition wall are separated from the organic layer and the upper electrode formed on the lower electrode in the opening.

11. The vapor deposition method according to claim 10, wherein, When passing through the first chamber group and the second chamber group, A hole injection layer is formed on the lower electrode. A first hole transport layer is formed on top of the hole injection layer. A first electron blocking layer is formed on top of the first hole transport layer. A first light-emitting layer is formed on top of the first electron-blocking layer. A first hole-blocking layer is formed on top of the first light-emitting layer. An n-type charge generation layer is formed on top of the first hole-blocking layer. A p-type charge generation layer is formed on top of the n-type charge generation layer. A second hole transport layer is formed on top of the p-type charge generation layer. A second electron blocking layer is formed on top of the second hole transport layer. A second light-emitting layer is formed on top of the second electron-blocking layer. A second hole-blocking layer is formed on top of the second light-emitting layer. An electron transport layer is formed on top of the second hole-blocking layer. An electron injection layer is formed on top of the electron transport layer. The upper electrode is formed on the electron injection layer.

12. The vapor deposition method according to claim 11, wherein, The first hole transport layer and the second hole transport layer are formed from the same material in the same vapor deposition chamber. The first electron blocking layer and the second electron blocking layer are formed from the same material in the same vapor deposition chamber. The first light-emitting layer and the second light-emitting layer are formed from the same material in the same vapor deposition chamber. The first hole-blocking layer and the second hole-blocking layer are formed from the same material in the same vapor deposition chamber.

13. The vapor deposition method according to claim 11, wherein, Upon passing through the second chamber group, further, A first transparent layer is formed on the upper electrode. A second transparent layer is formed on top of the first transparent layer.

14. The vapor deposition method according to claim 10, wherein, The conveying speed of the processing substrate is constant when passing through the first chamber group and the second chamber group.

15. The vapor deposition method according to claim 10, wherein, As the processing substrate passes through the second chamber group, in at least one vapor deposition chamber, material emitted from the vapor deposition source is not vapor deposited onto the processing substrate.

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