Array substrate, touch display panel and display device

Abstract

The present invention discloses an array substrate, a touch display panel, and a display device. The array substrate includes common electrodes, compensation traces, and a compensation control module. The common electrodes are multiplexed into touch electrodes. Multiple common electrodes located in the same row along a first direction constitute a common electrode group. Along a second direction, a common electrode group overlaps with multiple scan lines, and these multiple scan lines constitute a scan line group. The scan line group includes a center scan group and an edge scan group. The extension direction of the compensation traces is parallel to the extension direction of the scan lines. The compensation control module is electrically connected to the compensation traces and the scan lines in the edge scan group. The compensation control module is configured to respond to scan signals from each scan line in the edge scan group and control the generation of compensation signals on the compensation traces. The compensation signals and the scan signals from each scan line in the edge scan group have potential changes in opposite directions at each target time. The technical solution of the present invention can improve the appearance of horizontal streaks.

Description

Technical Field

[0001] The present invention relates to the technical field of liquid crystal display panels, and in particular to an array substrate, a touch display panel and a display device. Background Art

[0002] In the field of liquid crystal displays, TDDI (Touch and Display Driver Integration) display panels divide the common electrode layer into multiple sensor blocks. Through time-sharing multiplexing technology, the sensor blocks act as common electrodes during the display period, providing common voltage signals to display the image, and act as touch electrodes during the touch period, providing touch signals, thereby achieving the effect of both touch and display.

[0003] However, TDDI display panels often have a problem of display stripes due to their special structural design, which needs to be solved urgently. Summary of the Invention

[0004] The present invention provides an array substrate, a touch display panel and a display device to improve the horizontal stripe defect of a TDDI display panel.

[0005] In a first aspect, the present invention provides an array substrate, comprising:

[0006] substrate;

[0007] a plurality of scan lines located on one side of the substrate;

[0008] Multiple common electrodes are located on a side of the film layer where the scan lines are located away from the substrate; the common electrodes are reused as touch electrodes; along a first direction, multiple common electrodes located in the same row constitute a common electrode group; along a second direction, a common electrode group overlaps with multiple scan lines, and the multiple scan lines constitute a scan line group; wherein the first direction is parallel to the extension direction of the scan lines, and the second direction is perpendicular to the plane where the substrate is located;

[0009] The array substrate further includes: compensation wiring and a compensation control module;

[0010] The extension direction of the compensation line is parallel to the extension direction of the scan line; along the second direction, one common electrode group overlaps with at least one compensation line;

[0011] The scanning line group includes a central scanning group and an edge scanning group; along the third direction, the edge scanning group is located on a side of the edge of the central scanning group close to the common electrode; the edge scanning group includes at least two scanning lines; the third direction is parallel to the arrangement direction of the scanning lines;

[0012] The compensation control module is electrically connected to the compensation trace and the scan lines in the edge scan group respectively; the compensation control module is used to respond to the scan signals of each scan line in the edge scan group and control the generation of the compensation signal on the compensation trace; the compensation signal and the scan signals of each scan line in the edge scan group have potential changes in opposite directions at each target moment; the target moment is the rising edge moment or the falling edge moment of the scan signal, and the time sequence of the target moments corresponding to each scan line in the edge scan group is consistent with its scanning sequence.

[0013] In a second aspect, the present invention provides a touch display panel, comprising an opposing substrate, a liquid crystal layer, and an array substrate provided by any embodiment of the present invention, wherein the liquid crystal layer is located between the opposing substrate and the array substrate.

[0014] In a third aspect, the present invention provides a display device comprising a backlight module and a touch display panel provided by any embodiment of the present invention, wherein the backlight module is located on a side of an array substrate away from an opposing substrate.

[0015] The technical solution of an embodiment of the present invention is to set an array substrate including a compensation line and a compensation control module, and set the compensation control module to be electrically connected to the compensation line and the scanning lines in the edge scanning group respectively. The compensation control module responds to the scanning signal of each scanning line in the edge scanning group, and controls the generation of the compensation signal on the compensation line, so that the compensation signal and the scanning signal of each scanning line in the edge scanning group have potential changes in opposite directions at each target moment, so that the potential change of the compensation signal on the compensation line at each target moment can be used to compensate for or even offset the coupling effect of the potential change of each scanning line in the edge scanning group on the common electrode potential, thereby improving the horizontal stripe defect.

[0016] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 It is a schematic diagram of the structure of an existing TDDI display panel;

[0019] Figure 2 This is a schematic diagram showing the principle of the horizontal stripe problem in existing TDDI display panels;

[0020] Figure 3 is a schematic top view of the structure of an array substrate provided by an embodiment of the present invention;

[0021] Figure 4 It is along Figure 3 A schematic diagram of the cross-sectional structure of the array substrate taken along line BB';

[0022] Figure 5 It is along Figure 3 A schematic cross-sectional structural diagram of the array substrate taken along line CC';

[0023] Figure 6 Schematic diagram of the working principle of the array substrate provided by an embodiment of the present invention;

[0024] Figure 7 yes Figure 3 A schematic diagram of an enlarged structure of the Q1 region;

[0025] Figure 8 is with Figure 7 A corresponding circuit diagram of a first compensation unit;

[0026] Figure 9 is with Figure 8 The timing diagram corresponding to the circuit shown;

[0027] Figure 10 yes Figure 3 A schematic diagram of an enlarged structure of the middle Q2 region;

[0028] Figure 11 is with Figure 10 A corresponding circuit diagram of a second compensation unit;

[0029] Figure 12 is with Figure 11 The timing diagram corresponding to the circuit shown;

[0030] Figure 13 is with Figure 10 A corresponding circuit diagram of another second compensation unit;

[0031] Figure 14 is a schematic top view of another array substrate provided by an embodiment of the present invention;

[0032] Figure 15 1 is a schematic structural diagram of a touch display panel provided by an embodiment of the present invention;

[0033] Figure 16 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0035] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application can be combined with each other without contradiction.

[0036] First of all, it should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should have the ordinary meaning understood by people with ordinary skills in the field to which the present invention belongs. The terms "first", "second" and similar terms used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. The terms "include" or "comprising" and similar terms mean that the elements or objects preceding the term include the elements or objects listed after the term and their equivalents, without excluding other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left" and "right" are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In addition, the shapes and sizes of the components in the drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present invention.

[0037] Figure 1 This is a schematic diagram of the structure of an existing TDDI display panel. Figure 2 This is a schematic diagram of the principle of the horizontal stripe problem of the existing TDDI display panel, such as Figure 1 and Figure 2 As shown in FIG, for a TDDI display panel, the common electrode layer is divided into multiple sensor blocks Z. A row of sensor blocks Z overlaps with multiple scan lines G. A scan line G can be electrically connected to sub-pixels P in the same row. In the display phase, each scan line G transmits a scan enable signal ( Figure 2Only a high level is used as an example for the scan enable signal), to achieve row-by-row scanning of the sub-pixels, so that the driver chip IC can transmit the pixel voltage to the pixel electrode corresponding to each sub-pixel through the data line (not shown). At the same time, in the display stage, the sensor block Z serves as a common electrode, and the driver chip can transmit the common voltage (Vcom) to each common electrode (Z) through the touch line. In this way, the deflection angle of the liquid crystal molecules can be controlled under the action of the electric field of the pixel voltage and the common voltage, thereby controlling the light output of each sub-pixel and realizing display.

[0038] However, because the scan lines G overlap with the sensor blocks Z, parasitic capacitance exists between them. This means that during the display phase, voltage jumps on the scan lines G will affect the potential of the common electrode (Z). For TDDI display panels, since the common electrodes (Z) are discontinuous along the arrangement direction of the scan lines G (the column direction shown in the figure), the coupling of the voltage jumps on the scan lines to the common electrode potential is discontinuous at the edges of the common electrodes, resulting in abnormal common electrode potential. This, in turn, leads to a difference between the electric field corresponding to the edge regions of the common electrodes along the column direction within the liquid crystal cell and the electric field corresponding to the center region of the common electrodes, resulting in horizontal streaks near the edges of the common electrodes.

[0039] For example, Figure 1 Two rows of sensor blocks are shown, Figure 2 Where Gn-3, Gn-2, and Gn-1 respectively represent scan signals corresponding to a number of scan lines overlapping with the common electrode (Zx-1), and Gn, Gn+1, and Gn+2 respectively represent scan signals corresponding to a number of scan lines overlapping with the common electrode (Zx) (for ease of understanding, the scan lines and their corresponding scan signals are labeled the same); Figure 2 Where Zx-1 and Zx represent Figure 1 The potential of the corresponding common electrode in (for ease of understanding, the common electrode and its potential are marked with the same symbol). Figure 1 and Figure 2As shown, along the scanning direction, when a scanning line is far away from the disconnection point of the common electrode, there will always be a voltage jump of another scanning line that can compensate for the coupling effect of the voltage jump of the scanning line on the potential of the common electrode. For example, the falling edge potential jump of the scanning signal Gn-3 produces a pull-down coupling on the potential of the common electrode (Zx-1), and this pull-down coupling can be offset by the pull-up coupling of the rising edge potential jump of the scanning signal Gn-1 on the potential of the common electrode (Zx-1); for another example, the rising edge potential jump of the scanning signal Gn+2 produces a pull-up coupling on the potential of the common electrode (Zx), and this pull-up coupling can be offset by the pull-down coupling of the falling edge potential jump of the scanning signal Gn on the potential of the common electrode (Zx). However, for the scanning line close to the disconnection point of the common electrode, its coupling effect on the potential of the common electrode cannot be offset, resulting in abnormal potential of the common electrode. For example, the falling edge potential jumps of the scanning signals Gn-2 and Gn-1 both produce a pull-down coupling on the potential of the common electrode (Zx-1) (indicated by a downward solid arrow), but the pull-down coupling cannot be offset by the coupling influence of other scanning lines overlapping with the common electrode (Zx-1), while the rising edge potential jumps of the scanning signals Gn and Gn+1 both produce a pull-up coupling on the potential of the common electrode (Zx) (indicated by an upward solid arrow), but the pull-up coupling cannot be offset by the coupling influence of other scanning lines overlapping with the common electrode (Zx).

[0040] Based on the above analysis, it is understandable that for traditional solutions with a single common electrode layer, since the coupling of voltage jumps on the scan lines to the potential of the common electrode layer is continuous, horizontal streaks may only occur at the upper and lower edges of the display area, and the impact on the display effect is almost negligible. However, for TDDI display panels, due to the special structural design of its common electrode layer, the coupling of voltage jumps on the scan lines to the potential of the common electrode is discontinuous at the edges of the common electrode. This, in turn, causes a difference between the electric field corresponding to the edge area of ​​the common electrode along the column direction in the liquid crystal cell and the electric field corresponding to the center area of ​​the common electrode, resulting in the problem of horizontal display streaks.

[0041] To solve the above problems, an embodiment of the present invention provides an array substrate, which includes a substrate, a plurality of scan lines, a plurality of common electrodes, a compensation wiring, and a compensation control module; the plurality of scan lines are located on one side of the substrate; the plurality of common electrodes are located on a side of the film layer where the scan lines are located away from the substrate; the common electrodes are reused as touch electrodes; along a first direction, a plurality of common electrodes located in the same row constitute a common electrode group; along a second direction, a common electrode group overlaps with a plurality of scan lines, and the plurality of scan lines constitute a scan line group; the extension direction of the compensation wiring is parallel to the extension direction of the scan lines; along the second direction, a common electrode group overlaps with at least one compensation wiring; the scan line group includes a center scan line group and a bottom scan line group; The central scanning group and the edge scanning group are configured such that: the edge scanning group is located on the side of the central scanning group near the edge of the common electrode along the third direction; the edge scanning group includes at least two scanning lines; the compensation control module is electrically connected to the compensation traces and the scanning lines in the edge scanning group; the compensation control module is configured to respond to the scanning signals of each scanning line in the edge scanning group and control the generation of the compensation signal on the compensation trace; the compensation signal and the scanning signal of each scanning line in the edge scanning group have potential changes in opposite directions at each target moment; the target moment is the rising edge moment or the falling edge moment of the scanning signal, and the time sequence of the target moments corresponding to the scanning lines in the edge scanning group is consistent with the scanning sequence thereof. The first direction is parallel to the extension direction of the scanning lines, the second direction is perpendicular to the plane of the substrate, and the third direction is parallel to the arrangement direction of the scanning lines.

[0042] By adopting the above method, the potential change of the compensation signal on the compensation line at each target moment can be used to compensate or even offset the coupling effect of the potential change of each scanning line in the edge scanning group on the common electrode potential, thereby improving the horizontal stripe defect.

[0043] The above is the core concept of this application. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application. The following will clearly and completely describe the technical solutions in the embodiments of this application in conjunction with the accompanying drawings.

[0044] Figure 3 is a schematic top view of the structure of an array substrate provided by an embodiment of the present invention. Figure 4 It is along Figure 3 The cross-sectional structure diagram of the array substrate taken at BB' is as follows: Figure 3 and Figure 4As shown, the array substrate 100 provided by the embodiment of the present invention includes a substrate 1, multiple scan lines 2, multiple common electrodes 3, compensation wiring 4 and a compensation control module 5; the scan line 2 is located on one side of the substrate 1; the common electrode 3 is located on the side of the film layer where the scan line 2 is located away from the substrate 1; the common electrode 3 is reused as a touch electrode; along the first direction D1, multiple common electrodes 3 located in the same row constitute a common electrode group 30; along the second direction D2, a common electrode group 30 overlaps with multiple scan lines 2, and the multiple scan lines 2 constitute a scan line group 20; the scan line group 20 includes a central scan group 21 and an edge scan group 22; along the third direction D3, the edge scan group 22 is located on the side of the central scan group 21 close to the edge of the common electrode 3; the edge scan group 22 includes at least two scan lines 2; wherein, the first direction D1 is parallel to the extension direction of the scan line 2, the second direction D2 is perpendicular to the plane where the substrate 1 is located; the third direction D3 is parallel to the arrangement direction of the scan line 2.

[0045] For example, Figure 5 It is along Figure 3 The cross-sectional structure diagram of the array substrate taken at CC' is as follows: Figure 4 and Figure 5 As shown, the array substrate 100 further includes a thin film transistor 61 and a pixel electrode 62, and the thin film transistor 61 is electrically connected to the pixel electrode 62 in a one-to-one correspondence. The scan line 2 and the gate electrode 611 of the thin film transistor 61 can be optionally provided in the same layer. In this way, the scan line 2 is electrically connected to the gate electrode of the thin film transistor 61, and the scan enable signal is transmitted sequentially through each scan line to select the thin film transistor row by row, so that the pixel voltage can be written to the pixel electrode 62 corresponding to the thin film transistor 61 in the selected state through the data line. Figure 5 As shown, the film layer where the common electrode 3 is located can be located between the film layer where the thin film transistor 61 is located and the film layer where the pixel electrode 62 is located, so that the common electrode can avoid shielding the electric field.

[0046] like Figure 3 As shown, in this embodiment, the array substrate 100 includes a plurality of common electrodes 3, and the common electrodes 3 can be reused as touch electrodes. Thus, the display panel including the array substrate is a TDDI display panel. For the specific working principle of the TDDI display panel, please refer to the above description and will not be repeated here.

[0047] Reference Figure 3 and Figure 4In this embodiment, along the first direction D1, multiple common electrodes 3 located in the same row constitute a common electrode group 30. Along the second direction D2, one common electrode group 30 overlaps with multiple scan lines 2, and these multiple scan lines 2 constitute a scan line group 20. In other words, one common electrode group 30 corresponds to one scan line group 20, and multiple common electrodes 3 in one common electrode group 30 simultaneously overlap with multiple scan lines 2 in one scan line group 20.

[0048] Reference Figure 3 In this embodiment, the scanning line group 20 includes a central scanning group 21 and an edge scanning group 22. Along the third direction D3, the edge scanning group 22 is located on the side of the central scanning group 21 close to the edge of the common electrode 3. In other words, along the third direction D3, the scanning lines 2 in the edge scanning group 22 are closer to the edge of the common electrode 3 than the scanning lines 2 in the central scanning group 21. Specifically, along the third direction D3, a common electrode 3 includes two edges, such as Figure 3 The upper edge and the lower edge are shown. Accordingly, a scanning line group 20 may include two edge scanning groups 22, and the center scanning group 21 is located between the two edge scanning groups 22. Wherein, an edge scanning group 22 includes at least two scanning lines 2, Figure 3 An example is given in which an edge scanning group 22 includes three scanning lines.

[0049] According to the above explanation, in this embodiment, the scan line 2 in the center scan group 21 can be understood as a scan line in which the potential effect of a potential jump in any direction on the common electrode 3 can be offset by the potential jump of other scan lines in the same scan line group 20, and the scan line 2 in the edge scan group 22 can be understood as a scan line in which the potential effect of a potential jump in at least one direction on the common electrode 3 cannot be offset by the potential jump of other scan lines in the same scan line group 20.

[0050] Further, such as Figure 3 As shown, to compensate for / offset the coupling effect of the scan lines in the edge scanning group 22 on the common electrode potential, the array substrate 100 provided in this embodiment further includes compensation traces 4 and a compensation control module 5. The compensation traces 4 extend parallel to the direction of the scan lines 2. Along the second direction D2, one common electrode group 30 overlaps with at least one compensation trace 4. The compensation control module 5 is electrically connected to the compensation traces 4 and the scan lines 2 in the edge scanning group 22, respectively.

[0051] As described above, one scan line group 20 includes two edge scan groups 22. The common electrode group 30 overlaps with at least one compensation line 4, and the compensation control module 5 is electrically connected to the compensation line 4 and the scan lines 2 in the edge scan group 22. Specifically, it can be understood that for at least one of the two edge scan groups 22, a compensation line 4 and a compensation control module 5 can be correspondingly provided in the array substrate, and the compensation control module 5 can be electrically connected to the corresponding compensation line 4 and the scan lines 2 in the edge scan group 22 to compensate for the coupling effect of the scan lines in the edge scan group 22 on the common electrode potential.

[0052] For example, Figure 3 In the example, corresponding to one common electrode group 30, the scan lines 2 in the upper edge scanning group 22 are electrically connected to a compensation trace 4 via a compensation control module 5. Simultaneously, the scan lines 2 in the lower edge scanning group 22 are also electrically connected to a compensation trace 4 via a compensation control module 5. In this case, one common electrode group 30 overlaps with two compensation traces 4, compensating for both the coupling effects of the scan lines in the upper edge scanning group 22 on the common electrode potential and the coupling effects of the scan lines in the lower edge scanning group 22 on the common electrode potential. It should be noted that this configuration is for illustration only and is not intended to be limiting.

[0053] In other embodiments, as needed, compensation traces 4 and compensation control modules 5 may be provided for only one of the two edge scanning groups 22, and the compensation control module 5 may be electrically connected to the compensation traces 4 and the scan lines 2 in the edge scanning group 22, respectively. In this case, one common electrode group 30 overlaps with one compensation trace 4. For example, for the two common electrode groups closest to the edge of the display area along the third direction D3 in the array substrate, although the scan lines in the edge scanning line group adjacent to the edge of the display area may have a coupling effect on the potential of the common electrodes, resulting in horizontal streaks, the sub-pixels connected to these scan lines are very close to the edge of the entire display area, and the user's perception of the horizontal streaks in this area is relatively weak compared to the horizontal streaks in the inner area. Therefore, for the two common electrode groups closest to the edge of the display area along the third direction D3, compensation traces 4 and compensation control modules 5 may be provided only for the one edge scanning group 22 in the scan line group corresponding to the common electrode group that is away from the edge of the display area, and compensation traces and compensation control modules may not be provided for the edge scanning group 22 adjacent to the edge of the display area. In addition, for other common electrode groups 30 within the display area, one common electrode group 30 may also overlap with only one compensation trace 4 , which is not limited in the embodiment of the present invention.

[0054] Further, Figure 6 This is a schematic diagram of the working principle of the array substrate provided by an embodiment of the present invention, referring to Figure 3 and Figure 6 As shown, in this embodiment, the compensation control module 5 is used to respond to the scanning signal of each scanning line 2 in the edge scanning group 22 ( Figure 6 The "G" represents the scanning signal, and the number after "G" only represents the number), which controls the compensation line 4 to generate the compensation signal Sx; the compensation signal Sx and the scanning signal of each scanning line 2 in the edge scanning group 22 are respectively at each target time (such as Figure 6 The target time is the rising or falling edge of the scan signal, and the temporal sequence of the target times corresponding to the scan lines 2 in the edge scan group 22 is consistent with their scanning order. This arrangement allows the potential change of the compensation signal on the compensation trace 4 at each target time to compensate for or even offset the coupling effect of the potential change of each scan line 2 in the edge scan group 22 on the common electrode potential, thereby improving the horizontal streak defect.

[0055] Specifically, each scan line in an edge scan group 22 has a target time, and the time sequence of the target times corresponding to the scan lines in the edge scan group 22 is consistent with the scan order of the scan line. That is, the target time corresponding to the scan line scanned earlier is earlier, and the target time corresponding to the scan line scanned later is later. Furthermore, for each scan line, its corresponding target time can specifically be the time when a potential jump occurs, at which the coupling effect cannot be offset by other scan lines in the same scan line group, such as a rising edge time or a falling edge time. It will be understood that for the same edge scan group 22, the target time corresponding to each scan line is either the rising edge time or the falling edge time of the respective scan signal. In this embodiment, when the scan signals of each scan line 2 in an edge scan group 22 sequentially undergo potential jumps at their corresponding target times, the compensation control module 5 can respond to the potential jumps of the scan signals of each scan line and control the compensation signal Sx of the compensation trace 4 to undergo opposite potential changes at the target times corresponding to each scan line, thereby compensating for or even canceling the coupling effect of the scan lines 2 in the edge scan group 22 on the common electrode potential.

[0056] For example, Figure 6The figure shows the scanning timing of the scan lines in a scan line group 20. For example, a scan line group 20 includes m+4 scan lines. The scan signals of each scan line are G1, G2, G3, G4, ..., and Gm+4, and each scan line sequentially transmits a high-level enable signal. G1, G2, and G3 are the scan signals corresponding to the three scan lines in one edge scan group 22 (e.g., the upper edge scan group), Gm+2, Gm+3, and Gm+4 are the scan signals corresponding to the three scan lines in another edge scan group 22 (e.g., the lower edge scan group), and G4, G5, ..., Gm, and Gm+1 are the scan signals corresponding to the scan lines in the center scan group 21.

[0057] Reference Figure 6 For the scan lines in the center scan group 21 (corresponding to the scan signals G4, G5, ..., Gm, Gm+1), the pull-up coupling of the common electrode potential caused by the rising-edge potential jump and the pull-down coupling of the common electrode potential caused by the falling-edge potential jump can be offset by the potential jumps of other scan lines in the same scan line group 20. However, for the scan lines in the edge scan group 22 (corresponding to the scan signals G1, G2, G3), the pull-up coupling of the common electrode potential caused by the rising-edge potential jump cannot be offset by the pull-down coupling (falling-edge potential jump) of other scan lines in the same scan line group 20. For the scan lines in the edge scan group (corresponding to the scan signals Gm+2, Gm+3, Gm+4), the pull-down coupling of the common electrode potential caused by the falling-edge potential jump cannot be offset by the pull-up coupling (rising-edge potential jump) of other scan lines in the same scan line group 20.

[0058] Furthermore, for the scan lines in the edge scan group 22 scanned previously (the corresponding scan signals are G1, G2, and G3, respectively), since the pull-up coupling of the common electrode potential caused by the rising edge potential jump cannot be offset by other scan lines in the same scan line group 20, the target moments corresponding to the scan lines in the edge scan group 22 are the rising edge moments of their respective scan signals, such as the target moment corresponding to the scan signal G1 is T1, the target moment corresponding to the scan signal G2 is T2, and the target moment corresponding to the scan signal G3 is T3. The compensation signal (Sx1) of the corresponding compensation trace 4 has a falling edge at T1, T2, and T3, respectively, thereby compensating for or even offsetting the pull-up coupling of the common electrode potential caused by the rising edge potential jump of each scan line, thereby improving the horizontal stripes in this area.

[0059] Similarly, for the scan lines in the edge scan group 22 scanned later (the corresponding scan signals are Gm+2, Gm+3, and Gm+4, respectively), the pull-down coupling of the common electrode potential caused by the falling edge potential jump cannot be offset by other scan lines in the same scan line group 20. Therefore, the target moments corresponding to the scan lines in the edge scan group 22 are the falling edge moments of their respective scan signals, such as the target moment corresponding to the scan signal Gm+2 is Tm+2, the target moment corresponding to the scan signal Gm+3 is Tm+3, and the target moment corresponding to the scan signal Gm+4 is Tm+4. The compensation signal (Sx2) of the corresponding compensation trace 4 has rising edges at Tm+2, Tm+3, and Tm+4, respectively, thereby compensating for or even offsetting the pull-down coupling of the common electrode potential caused by the falling edge potential jump of each scan line, thereby improving the horizontal stripes in this area.

[0060] In summary, the technical solution of the embodiment of the present invention is to set an array substrate including a compensation line and a compensation control module, and set the compensation control module to be electrically connected to the compensation line and the scanning line in the edge scanning group respectively. The compensation control module responds to the scanning signal of each scanning line in the edge scanning group, and controls the generation of the compensation signal on the compensation line, so that the compensation signal and the scanning signal of each scanning line in the edge scanning group have potential changes in opposite directions at each target moment, so that the potential change of the compensation signal on the compensation line at each target moment can be used to compensate for or even offset the coupling effect of the potential change of each scanning line in the edge scanning group on the common electrode potential, thereby improving the horizontal stripe defect.

[0061] Based on the above embodiments, Figure 3 and Figure 6As shown, optionally, the edge scanning group 22 includes a first edge scanning group 221 and a second edge scanning group 222. Along the third direction D3, the first edge scanning group 221 and the second edge scanning group 222 are located on opposite sides of the center scanning group 21; the scanning direction Y of the multiple scanning lines 2 is the direction from the first edge scanning group 221 to the second edge scanning group 222; the scanning line in the first edge scanning group 221 is the first scanning line 201; the scanning line in the second edge scanning group 222 is the second scanning line 202. Further optionally, the compensation trace 4 includes a first compensation trace 41, and the compensation control module 5 includes a first compensation control module 51, which is electrically connected to the first compensation trace 41 and the first scan line 201, respectively; the first compensation control module 51 is used to respond to the scan signal of each first scan line 201 and control the generation of a first compensation signal Sx1 on the first compensation trace 41; the first compensation signal Sx1 and the scan signal of each first scan line 201 (such as G1, G2 and G3) have potential changes in opposite directions at each first target time (such as T1, T2 and T3); the first target time is the rising edge time of the scan signal of the first scan line 201; and / or, The compensation line 4 includes a second compensation line 42, and the compensation control module 5 includes a second compensation control module 52, which is electrically connected to the second compensation line 41 and the second scan line 202 respectively; the second compensation control module 52 is used to respond to the scan signal of each second scan line 202 and control the generation of a second compensation signal Sx2 on the second compensation line 42; the second compensation signal Sx2 and the scan signal of each second scan line 202 (such as Gm+2, Gm+3, Gm+4) have potential changes in opposite directions at each second target time (such as Tm+2, Tm+3, Tm+4); the second target time is the falling edge time of the scan signal of the second scan line 202.

[0062] The scanning direction Y of the plurality of scanning lines 2 is determined according to the order in which the plurality of scanning lines 2 arranged along the third direction D3 output the scanning enable signal. The scanning direction Y is parallel to the third direction D3 and is directed from the scanning line that outputs the scanning enable signal first to the scanning line that outputs the scanning enable signal later. For different products, the scanning direction of the scanning line can be forward scanning (such as Figure 3 It can also be reverse scanning (from bottom to top), which is not limited in the embodiment of the present invention.

[0063] Furthermore, in this embodiment, the scanning direction Y signal of the scanning line is the direction from the first edge scanning group 221 to the second edge scanning group 222. In other words, for a scanning line group 20, the scanning time of the first scanning line 201 in the first edge scanning group 221 is before the scanning time of the second scanning line 202 in the second edge scanning group 222.

[0064] Furthermore, according to the above explanation, for the first scan line 201 in the first edge scan group 221 scanned previously, the pull-up coupling of the common electrode potential caused by the rising edge potential jump of the first scan line 201 cannot be offset by other scan lines in the same scan line group 20. Therefore, the first target time corresponding to the first scan line 201 in the first edge scan group 221 is the rising edge time of each scan signal (such as Figure 6 T1, T2 and T3 moments). Figure 3 and Figure 6 In this embodiment, by providing a first compensation line 41 and a first compensation control module 51 corresponding to the first edge scan group 221, the first compensation control module 51 can be used to respond to the scan signal of each first scan line 201 and control the generation of the first compensation signal Sx1 on the first compensation line 41, so that the first compensation signal Sx1 and the scan signal of each first scan line 201 (such as G1, G2 and G3) have potential changes in opposite directions at each first target time (such as T1, T2 and T3), that is, the first compensation signal Sx1 has a compensation falling edge L at the rising edge time corresponding to each first scan line 201, so that the compensation falling edge L can compensate for or even offset the pull-up coupling of the common electrode potential caused by the rising edge potential jump of each first scan line 201, thereby improving the horizontal stripes in this area.

[0065] For the second scan line 202 in the second edge scan group 222 scanned later, the pull-down coupling of the common electrode potential caused by the falling edge potential jump of the second scan line 202 cannot be offset by other scan lines in the same scan line group 20. Therefore, the second target time corresponding to the second scan line 202 in the second edge scan group 222 is the falling edge time of each scan signal (such as Figure 6 (Tm+2, Tm+3, Tm+4 time). Figure 3 and Figure 6 In this embodiment, by providing a second compensation line 42 and a second compensation control module 52 corresponding to the second edge scan group 222, the second compensation control module 52 can be used to respond to the scan signal of each second scan line 202 and control the second compensation line 42 to generate a second compensation signal Sx2, so that the second compensation signal Sx2 and the scan signal of each second scan line 202 (such as Gm+2, Gm+3, and Gm+4) have potential changes in opposite directions at each second target time (such as Tm+2, Tm+3, and Tm+4). That is, the second compensation signal Sx2 has a compensation rising edge J at the falling edge time corresponding to each second scan line 202, so that the compensation rising edge J can compensate for or even offset the pull-down coupling of the common electrode potential caused by the potential jump of the falling edge of each second scan line 202, thereby improving the horizontal stripes in this area.

[0066] It should be noted that Figure 3For illustration, the compensation trace 4 includes both a first compensation trace 41 and a second compensation trace 42, and the compensation control module 52 includes both a first compensation control module 51 and a second compensation control module 52. The first compensation control module 51 is electrically connected to the first compensation trace 41 and each first scan line 201 in the first edge scan group 221, and the second compensation control module 52 is electrically connected to the second compensation trace 41 and each second scan line 202 in the second edge scan group 222. In other embodiments, for a scan line group 20, the first compensation trace 41 and the first compensation control module 51 may be provided only for the first edge scan group 221, such that the first compensation control module 51 is electrically connected to the first compensation trace 41 and each first scan line 201 in the first edge scan group 221; or the second compensation trace 42 and the second compensation control module 52 may be provided only for the second edge scan group 222, such that the second compensation control module 52 is electrically connected to the second compensation trace 41 and each second scan line 202 in the second edge scan group 222.

[0067] It should also be noted that Figure 3 The two scanning line groups 20 corresponding to the two common electrode groups 30 shown are respectively provided with corresponding compensation lines 4 and compensation control modules 5 corresponding to the first edge scanning group 221 and the second edge scanning group 222. This setting method is only for illustration and not for limitation. For each scanning line group 20 corresponding to each common electrode group 30, the setting methods of the corresponding compensation lines 4 and compensation control modules 5 can be the same or different, and the embodiment of the present invention does not limit this.

[0068] Based on the above embodiment, optionally, the compensation signal (first compensation signal Sx1 / second compensation signal Sx2) is a pulse signal. In other words, the compensation signal has a potential change at the target moment (referred to as the first potential change) and also has a potential change between two adjacent target moments (referred to as the second potential change). The potential change directions of the first potential change and the second potential change are opposite. For example, refer to Figure 6 The first compensation signal Sx1 has a compensation falling edge L at the rising edge of the scanning signal (e.g., G1, G2, G3) on the first scanning line 201, and a recovery rising edge H between two adjacent compensation falling edges L. The potential change directions of the compensation falling edge L and the recovery rising edge H are opposite. The second compensation signal Sx2 has a compensation rising edge J at the falling edge of the scanning signal (e.g., Gm+2, Gm+3, Gm+4) on the second scanning line 202, and a recovery falling edge E between two adjacent compensation rising edges J. The potential change directions of the compensation rising edge J and the recovery falling edge E are opposite.

[0069] This embodiment sets the compensation signal as a pulse signal. By generating a pulse compensation signal on the compensation line, the coupling effect of each scanning line in the edge scanning group on the common electrode potential can be compensated or even offset in sequence, thereby improving the horizontal stripes. At the same time, it can also avoid the potential of the compensation signal from continuously changing in one direction (for example, continuously rising or continuously falling).

[0070] Research has found that the more scan lines there are in an edge scan group, the wider the horizontal stripes are, and the more obvious the visual experience is. In this embodiment, for an edge scan group 22 having multiple scan lines 2, only one compensation line 4 is provided. The compensation control module 5 responds to the scan signals of multiple scan lines in the edge scan group 22 respectively, and controls the compensation line 4 to generate a pulsed compensation signal, so that the compensation signal and each scan signal have potential changes in opposite directions at the target time. Although the compensation line 4 also has a coupling effect on the potential of the common electrode that cannot be offset (such as Figure 6 The coupling effect of the recovered rising edge H of the first compensation signal Sx1 cannot be offset, and the coupling effect of the recovered falling edge E of the second compensation signal Sx2 cannot be offset). However, compared with the coupling effect of multiple scan lines in the edge scanning group 22, since one edge scanning group corresponds to only one compensation line, one common electrode group overlaps with two compensation lines at most, which can greatly reduce the horizontal stripe defect and improve the display effect.

[0071] Further optionally, the duration of the second potential change of the compensation signal is greater than or equal to the duration corresponding to the first potential change.

[0072] Reference Figure 6 The compensation falling edge L, the recovery rising edge H, the compensation rising edge J, the recovery falling edge E, and the rising edge and falling edge of the scanning signal all represent a potential change, and the time required to complete the potential change is the corresponding time length.

[0073] Usually, the duration of the rising and falling edges of the scanning signal is very short. Figure 6 Indicated by a vertical line. Accordingly, the duration corresponding to the compensation falling edge L (i.e., the first potential change) of the first compensation signal Sx1 can be equal to the duration corresponding to the rising edge of the scanning signal, and the duration corresponding to the compensation rising edge J (i.e., the first potential change) of the second compensation signal Sx2 can be equal to the duration corresponding to the falling edge of the scanning signal, to ensure the compensation effect.

[0074] Furthermore, the duration corresponding to the restored rising edge H (i.e., the second potential change) of the first compensation signal Sx1 can be greater than or equal to the duration corresponding to the compensated falling edge L (i.e., the first potential change), that is, greater than or equal to the duration corresponding to the rising edge of the scanning signal; the duration corresponding to the restored falling edge E (i.e., the second potential change) of the second compensation signal Sx2 can be greater than or equal to the duration corresponding to the compensated rising edge J (i.e., the first potential change), that is, greater than or equal to the duration corresponding to the falling edge of the scanning signal, and the embodiments of the present invention do not limit this. Figure 6 For example, the duration corresponding to the restored rising edge H of the first compensation signal Sx1 is equal to the duration corresponding to the rising edge of the scanning signal, and the duration corresponding to the restored falling edge E of the second compensation signal Sx2 is equal to the duration corresponding to the falling edge of the scanning signal.

[0075] In other embodiments, optionally, the duration corresponding to the recovery rising edge H (i.e., the second potential change) of the first compensation signal Sx1 is greater than the duration corresponding to the compensation falling edge L (i.e., the first potential change), that is, greater than the duration corresponding to the rising edge of the scanning signal. In this way, the potential rising speed of the recovery rising edge H can be made smaller than the potential rising speed of the rising edge of the scanning signal, compared with the potential sudden change of the recovery rising edge H (refer to Figure 6 ), the coupling effect of the recovery rising edge H in the first compensation signal Sx1 on the common electrode potential can be further reduced. Similarly, the duration corresponding to the recovery falling edge E (i.e., the second potential change) of the second compensation signal Sx2 can be selected to be greater than the duration corresponding to the compensation rising edge J (i.e., the first potential change), that is, greater than the duration corresponding to the falling edge of the scanning signal. In this way, the potential falling speed of the recovery falling edge E can be made smaller than the potential falling speed of the falling edge of the scanning signal, which is different from the sudden change in the potential of the recovery falling edge E (refer to Figure 6 ), the coupling effect of the recovery falling edge E in the second compensation signal Sx2 on the common electrode potential can be further reduced.

[0076] The feasible solutions for the specific structures of the first compensation control module 51 and the second compensation control module 52 are further described in detail below.

[0077] Figure 7 yes Figure 3 A schematic diagram of the enlarged structure of the Q1 region, combined with Figure 3 、 Figure 6 and Figure 7As shown, when the compensation line 4 includes the first compensation line 41 and the compensation control module 5 includes the first compensation control module 51, optionally, along the scanning direction Y, a target first scanning line (such as 201-1) and a secondary scanning line (such as 201-2) constitute a first scanning line unit 2010, wherein the secondary scanning line (such as 201-2) is adjacent to the target first scanning line (such as 201-1), and the scanning time of the secondary scanning line (such as 201-2) is later than that of the target first scanning line (such as 201-1), and the two adjacent first scanning line units 2010 shares a first scan line 201; the first compensation control module 51 includes at least two first compensation units 511; the first compensation units 511 are electrically connected to the first scan line units 2010 in a one-to-one correspondence, and each first compensation unit 511 is electrically connected to the first compensation trace 41; the first compensation unit 511 (such as 511-1) is used to respond to the scan signal (such as G1) of the target first scan line (such as 201-1), and control the first compensation signal Sx1 to have a compensated falling edge L at the rising edge moment (such as T1) of the scan signal (such as G1).

[0078] A target first scan line refers to a first scan line 201 in the first edge scan group 221. A target first scan line can be understood as a scan line in the first scan line unit 2010 whose coupling effect on the common electrode potential needs to be offset. Specifically, the number of first scan line units 2010 is the same as the number of first scan lines 201 in the first edge scan group 22. Each first scan line unit 2010 includes a target first scan line. Along the scanning direction, the target first scan lines in each first scan line unit 2010 correspond to each first scan line 201 in the first edge scan group 221.

[0079] The secondary scan line is a scan line adjacent to the target first scan line and scanned later than the target first scan line. The secondary scan line may be a scan line in the first edge scan group 221 or a scan line in the center scan group 21.

[0080] For example, refer to Figure 3 and Figure 7The first edge scan group 221 includes three first scan lines, namely, a first scan line 201-1, a first scan line 201-2, and a first scan line 201-3 (the number after the "-" only represents the number, the same below). Among them, the first scan line 201-1 is a target first scan line, and its secondary scan line (i.e., the first scan line 201-2) constitutes a first scan line unit 2010-1; the first scan line 201-2 is a target first scan line, and its secondary scan line (i.e., the first scan line 201-3) constitutes a first scan line unit 2010-2; the first scan line 201-3 is a target first scan line, and its secondary scan line (i.e., scan line 2-4) constitutes a first scan line unit 2010-3. The number of the first scan line units 2010 is the same as the number of the first scan lines 201 in the first edge scan group 221 . One first scan line 201 serves as a target first scan line in one first scan line unit 2010 , and two adjacent first scan line units 2010 share one first scan line 201 .

[0081] Furthermore, the first compensation control module 51 includes at least two first compensation units 511, each of which is electrically connected to the first scan line unit 2010 in a one-to-one correspondence, and each of the first compensation units 511 is electrically connected to the first compensation trace 41. Thus, each first compensation unit 511 can respond to the scan signal of the target first scan line in its corresponding first scan line unit 2010 and control the first compensation signal Sx1 to have a compensation falling edge L at the rising edge of the scan signal of the target first scan line. The pull-down coupling of the compensation falling edge L on the common electrode potential offsets the pull-up coupling of the rising edge potential jump of the target first scan signal on the common electrode potential, thereby improving the horizontal streak phenomenon.

[0082] For example, refer to Figure 6 and Figure 7The first compensation control module 51 includes three first compensation units 511. The first compensation unit 511-1 is electrically connected to the two scan lines of the first scan line unit 2010-1, and can respond to the scan signal (G1) of the target first scan line (201-1) to control the first compensation signal Sx1 to have a compensation falling edge L at the rising edge time (T1) of the scan signal (G1); the first compensation unit 511-2 is electrically connected to the two scan lines of the first scan line unit 2010-2, and can respond to the scan signal (G2) of the target first scan line (201-2) to control the first compensation signal Sx1 At the rising edge moment (T2) of the scanning signal (G2), there is a compensation falling edge L; the first compensation unit 511-3 is electrically connected to the two scanning lines of the first scanning line unit 2010-3, and can respond to the scanning signal (G3) of the target first scanning line (201-3), and control the first compensation signal Sx1 to have a compensation falling edge L at the rising edge moment (T3) of the scanning signal (G3); in this way, the first compensation signal Sx1 and the scanning signals of each first scanning line 201 can have potential changes in opposite directions at the rising edge moment (first target moment) of each scanning signal, thereby improving the horizontal stripe phenomenon.

[0083] Figure 8 is with Figure 7 A corresponding circuit diagram of a first compensation unit, Figure 9 is with Figure 8 The timing diagram corresponding to the circuit shown is as follows: Figure 7 、 Figure 8 and Figure 9As shown, optionally, the first compensation unit 511 (such as the first compensation unit 511-1) includes a first storage capacitor C1, a first transistor M1, a second transistor M2 and a third transistor M3; the first transistor M1 and the third transistor M3 are P-type transistors, and the second transistor M2 is an N-type transistor; the first compensation trace 41 is electrically connected to the first level signal terminal V1, and both ends are suspended; the gates of the first transistor M1 and the second transistor M2 are electrically connected to the target first scan line (such as 201-1), and the source of the first transistor M1 is electrically connected to the first level signal terminal V1. In this embodiment, the drain of the first transistor M1 and the source of the second transistor M2 are both electrically connected to the first plate of the first storage capacitor C1, the drain of the second transistor M2 is electrically connected to the second level signal terminal V2, the gate of the third transistor M3 is electrically connected to the secondary scan line (e.g., 201-2), the source of the third transistor M3 is electrically connected to the second plate of the first storage capacitor C1, and the drain of the third transistor M3 is electrically connected to the first compensation trace 41. The potential of the first level signal at the first level signal terminal V1 is greater than the potential of the second level signal at the second level signal terminal V2. Optionally, the absolute value of the potential difference between the first level signal terminal V1 and the second level signal terminal V2 is approximately equal to the potential increase at the rising edge / the potential decrease at the falling edge of the scan signal.

[0084] For example, Figure 8 Only the circuit structure of the first compensation unit 511-1 is shown. Accordingly, the target first scan line is the first scan line 201-1, and the secondary scan line is the first scan line 201-2. The circuit structures of the remaining first compensation units 511 are the same as this, and the only difference is that the corresponding target first scan lines and secondary scan lines are different. For details, please refer to Figure 7 And related descriptions, no longer go into details here. Figure 8 and Figure 9 The working principle of the first compensation unit 511 is described in detail.

[0085] like Figure 8 and Figure 9As shown, when the scanning signal (G1) of the target first scanning line (201-1) and the scanning signal (G2) of the secondary scanning line (201-2) are both at a low level, the first compensation signal Sx1 of the first compensation line 41 is pulled up to a high level by the first level signal of the first level signal terminal V1, and at the same time, the first transistor M1 and the third transistor M3 are turned on, and both ends of the first storage capacitor C1 are at a high level; at the rising edge moment of the target first scanning line (201-1) (i.e., the first target moment T1), the first transistor M1 is turned off, and the second transistor M2 is turned on. Since the scanning signal (G2) of the secondary scanning line (201-2) is still at a low level at this time, the third transistor M3 is turned on, and the potential of the first plate of the first storage capacitor C1 is immediately pulled up by the second level signal terminal V 2 is pulled down to a low level. Since the potential difference across the capacitor cannot change suddenly, the potential of the first compensation signal Sx1 on the first compensation wiring 41 is immediately pulled down to a low level, thereby generating a compensation falling edge L. Afterwards, the first level signal terminal V1 can charge the first storage capacitor C1 when the second transistor M2 and the third transistor M3 are turned on, so that the potential of the first compensation signal Sx1 on the first compensation wiring 41 is gradually pulled up to a high level, generating a recovery rising edge H, until the scanning signal (G2) of the secondary scanning line (201-2) has a rising edge at time T2, causing the third transistor M3 to be turned off. The next first compensation unit (such as the first compensation unit 511-2) repeats this process, so that the first compensation signal Sx1 generates the next compensation falling edge L.

[0086] By adopting the circuit structure of the above-mentioned first compensation unit, the first compensation signal Sx1 can generate a compensation falling edge L in sequence at the rising edge of the scanning signal of each first scanning line 201, and a recovery rising edge H can be provided between two adjacent compensation falling edges L of the first compensation signal Sx1. Moreover, since the recovery rising edge H corresponds to the charging stage of the first storage capacitor C1, which is relatively slow, the duration corresponding to the recovery rising edge H can be made longer than the duration corresponding to the rising edge of the scanning signal. While compensating for the pull-up coupling effect of the rising edge potential jump of the first scanning line 201 on the common electrode potential, the coupling effect of the recovery rising edge H of the first compensation line on the common electrode potential can be greatly reduced, thereby significantly improving the horizontal stripe phenomenon.

[0087] It should be noted that Figure 8 The resistor symbol between the first level signal terminal V1 and the first compensation trace 41 only represents the internal resistance of the circuit therebetween, and is not an actual circuit element. Due to the existence of the internal resistance of the circuit, the first storage capacitor C1 can be slowly charged.

[0088] Figure 10 yes Figure 3 A schematic diagram of an enlarged structure of the Q2 region, combined with Figure 3 、 Figure 6 and Figure 10 As shown, when the compensation trace 4 includes a second compensation trace 42 and the compensation control module 5 includes a second compensation control module 52, the second compensation control module 52 optionally includes at least two second compensation units 521. The second compensation units 521 are electrically connected to the second scan lines 202 in a one-to-one correspondence, and each second compensation unit 521 is electrically connected to the second compensation trace 42. The second compensation units 521 are configured to respond to the scan signal of the second scan line 202 and control the second compensation signal Sx2 to have a compensation rising edge J at the falling edge of the scan signal. With this configuration, each second compensation unit 521 can respond to the scan signal of its corresponding second scan line 202 and control the second compensation signal Sx2 to have a compensation rising edge J at the falling edge of the scan signal of the second scan line 202. The pull-up coupling of the common electrode potential by each compensation rising edge J offsets the pull-down coupling of the common electrode potential caused by the falling edge potential jump of the scan signal of each second scan line 202, thereby improving the horizontal streak phenomenon.

[0089] For example, refer to Figure 6 and Figure 10 The second edge scanning group 222 includes three second scanning lines 202 (the scanning signals are Gm+2, Gm+3, and Gm+4 respectively). Accordingly, the second compensation control module 52 includes three second compensation units, namely, a second compensation unit 521-1, a second compensation unit 521-2, and a second compensation unit 521-3. Among them, the second compensation unit 521-1 is electrically connected to the second scanning line 202 with the scanning signal Gm+2, so that the second compensation signal Sx2 can have a compensated falling edge J at the rising edge of the scanning signal Gm+2; the second compensation unit 521-2 is electrically connected to the second scanning line 202 with the scanning signal Gm+3, so that the second compensation signal Sx2 can have a compensated falling edge J at the rising edge of the scanning signal Gm+3; the second compensation unit 521-3 is electrically connected to the second scanning line 202 with the scanning signal Gm+3, so that the second compensation signal Sx2 can have a compensated falling edge J at the rising edge of the scanning signal Gm+3; in this way, the second compensation signal Sx2 and the scanning signals of each second scanning line 202 can have potential changes in opposite directions at the falling edge of each scanning signal (second target moment), thereby improving the horizontal stripe phenomenon.

[0090] Figure 11 is with Figure 10 A corresponding circuit diagram of a second compensation unit, Figure 12 is with Figure 11 The timing diagram corresponding to the circuit shown is as follows: Figure 10 、 Figure 11 and Figure 12As shown, optionally, the second compensation unit 521 includes a second storage capacitor C2, a fourth transistor M4 and a fifth transistor M5; the fourth transistor M4 is an N-type transistor, and the fifth transistor M5 is a P-type transistor; the gates of the fourth transistor M4 and the fifth transistor M5 are both electrically connected to the second scan line 202, the source of the fourth transistor M4 is electrically connected to the first-level signal terminal V1, the drain of the fourth transistor M4 and the source of the fifth transistor M5 are both electrically connected to the first plate of the second storage capacitor C2, the second plate of the second storage capacitor C2 is electrically connected to the second-level signal terminal V2, the drain of the fifth transistor M5 is coupled to the second compensation trace 42, and one end of the second compensation trace 42 is electrically connected to the second-level signal terminal V2; the potential of the first-level signal at the first-level signal terminal V1 is greater than the potential of the second-level signal at the second-level signal terminal V2.

[0091] The drain of the fifth transistor M5 is coupled to the second compensation trace 42 , which can be understood as the drain of the fifth transistor M5 being directly electrically connected to the second compensation trace 42 , or can be understood as the drain of the fifth transistor M5 being electrically connected to the second compensation trace 42 via other circuit elements, and this is not limited in the embodiment of the present invention. Figure 11 The former is used as an example for illustration.

[0092] like Figure 11 and Figure 12 As shown, the working principle of the second compensation unit (such as the second compensation unit 521-1) is as follows: when the scan signal (such as Gm+2) of the second scan line 202 rises to a high level, the fourth transistor M4 is turned on, and the first level signal of the first level signal terminal V1 charges the second storage capacitor C2. During this stage, the fifth transistor M5 remains off; at the falling edge moment of the scan signal (Gm+2) of the second scan line 202 (i.e., the second target moment Tm+2), the fifth transistor M5 is turned on. Since the second storage capacitor C2 has been charged, the potential of the second compensation signal Sx2 of the second compensation line 42 is immediately increased by the first target moment Tm+2. The second storage capacitor C2 is pulled up to a high level, generating a compensation rising edge J; thereafter, since one end of the second compensation line 42 is electrically connected to the second level signal terminal V2, the second storage capacitor C2 can be gradually discharged through the second compensation line 42, and the fifth transistor M5 is gradually turned off, so that the second compensation signal Sx2 on the second compensation line 42 slowly recovers to a low level, generating a recovery falling edge E; until the next second compensation unit (such as the second compensation unit 521-2) responds to the scanning signal of its corresponding second scanning line (such as Gm+3) and repeats this action, so that the second compensation signal Sx2 generates the next compensation rising edge.

[0093] By adopting the circuit structure of the above-mentioned second compensation unit, the second compensation signal Sx2 can generate a compensation rising edge J in sequence at the falling edge of the scanning signal of each second scanning line 202, and a recovery falling edge E can be provided between two adjacent compensation rising edges J of the second compensation signal Sx2. Moreover, since the recovery falling edge E corresponds to the discharge stage of the second storage capacitor C2, which is relatively slow, the duration corresponding to the recovery falling edge E can be made longer than the duration corresponding to the falling edge of the scanning signal. While compensating for the pull-down coupling effect of the falling edge potential jump of the second scanning line 202 on the common electrode potential, the coupling effect of the recovery falling edge E of the second compensation line on the common electrode potential can be greatly reduced, thereby significantly improving the horizontal stripe phenomenon.

[0094] It should be noted that Figure 11 The resistor symbol between the second level signal terminal V2 and the second compensation trace 42 only represents the internal resistance of the circuit therebetween, and is not an actual circuit element. Due to the existence of the internal resistance of the circuit, the second storage capacitor C2 can be discharged slowly.

[0095] Figure 13 is with Figure 10 The corresponding circuit diagram of another second compensation unit is as follows: Figure 13 As shown, the second compensation unit 521 optionally further includes a sixth transistor M6, which is an N-type transistor; the drain of the fifth transistor M5 is electrically connected to the gate of the sixth transistor M6, the source of the sixth transistor M6 is electrically connected to the first plate of the second storage capacitor C2, and the drain of the sixth transistor M6 is electrically connected to the second compensation trace 42. The on-off state of the sixth transistor M6 is consistent with that of the fifth transistor M5. By adding the sixth transistor M6 between the drain of the fifth transistor M5 and the second compensation trace 42, the channel type of the sixth transistor M6 is different from that of the fifth transistor M5, and the drain of the fifth transistor M5 is electrically connected to the gate of the sixth transistor M6, the source of the sixth transistor M6 is electrically connected to the first plate of the second storage capacitor C2, and the drain of the sixth transistor M6 is electrically connected to the second compensation trace, thereby further ensuring the stability and reliability of the second compensation unit 521.

[0096] In summary, the above embodiments respectively provide detailed descriptions of feasible design schemes for the first compensation unit and the second compensation unit. It should be noted that the above embodiments are only described with the scanning direction being forward scanning as an example. In other embodiments, the scanning direction may also be reverse scanning, and the embodiments of the present invention do not limit this. Regardless of forward scanning or reverse scanning, for any scan line group 20, the edge scanning group formed by the scan lines scanned first is the first edge scanning group 221, and it is possible to choose whether to set the first compensation control module 51 and the first compensation routing 41 accordingly according to actual needs, and the edge scanning group formed by the scan lines scanned later is the second edge scanning group 222, and it is possible to choose whether to set the second compensation control module 52 and the second compensation routing 42 accordingly according to needs.

[0097] Based on any of the above embodiments, see Figure 4 Optionally, the compensation trace 4 and the scan line 2 are insulated in the same layer. The distance between the common electrode 3 and the trace (such as the scan line 2) along the second direction D2 affects the magnitude of the parasitic capacitance between the two. In this embodiment, by insulating the compensation trace 4 and the scan line 2 in the same layer, the distance between the compensation trace 4 and the common electrode 3 can be made the same as the distance between the scan line 2 and the common electrode 3, so that this influencing factor can be ignored. By reasonably controlling the potential jump amplitude and jump direction of the compensation signal Sx on the compensation trace 4, the coupling effect of the scan line on the common electrode potential can be compensated or even offset, resulting in a simpler control method and a better compensation effect.

[0098] like Figure 3 As shown, optionally, along the third direction D3, the compensation trace 4 is located on a side of the scan line 2 close to the edge of the common electrode 3. As can be understood from the above explanation, when the compensation trace 4 also has an irreversible coupling effect on the common electrode 3, by arranging the compensation trace 4 closer to the edge of the common electrode 3 than the scan line 2, the coupling effect of the compensation trace 4 on the common electrode potential can be further reduced, thereby improving the horizontal stripe phenomenon.

[0099] Figure 14 is a schematic diagram of a top view of another array substrate provided by an embodiment of the present invention. Figure 14 As shown, optionally, the array substrate 100 includes a display area AA, a first non-display area NA1, and a second non-display area NA2, wherein the first non-display area NA1 and the second non-display area NA2 are located on opposite sides of the display area AA along the first direction D1; the compensation control module 5 is located in at least one of the first non-display area NA1 and the second non-display area NA2. Exemplarily, Figure 14Taking the example of a compensation control module 5 being provided in both the first non-display area NA1 and the second non-display area NA2 as an example, this arrangement helps to improve the potential uniformity of the compensation signal at different positions along the compensation trace 4 along the first direction D1, further improving the compensation effect. In other embodiments, the compensation control module 5 may be provided only in the first non-display area NA1 or only in the second non-display area NA2.

[0100] Based on the same inventive concept, an embodiment of the present invention further provides a touch display panel. Figure 15 FIG. 1 is a structural diagram of a touch display panel provided by an embodiment of the present invention. Figure 15 As shown, the touch display panel 200 provided in an embodiment of the present invention includes an opposing substrate 2001, a liquid crystal layer 2002, and the array substrate 100 provided in any of the above embodiments. The liquid crystal layer 2002 is located between the opposing substrate 2001 and the array substrate 100. The opposing substrate 2001 can be, for example, a color filter substrate having a color filter layer to enable the touch display panel to achieve color display. Since the touch display panel provided in an embodiment of the present invention includes the array substrate provided in any of the above embodiments, it has the same beneficial effects. For similarities, please refer to the description of the above-mentioned array substrate embodiments and will not be repeated here.

[0101] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Figure 16 is a structural diagram of a display device provided by an embodiment of the present invention, such as Figure 16 As shown, the display device 300 provided in an embodiment of the present invention includes a backlight module 3001 and the touch display panel 200 provided in any embodiment of the present invention. The backlight module 3001 is located on a side of the array substrate 100 away from the opposite substrate 2001. This display device also has the same beneficial effects as the above-mentioned array substrate, which will not be described in detail here.

[0102] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that: include: substrate; a plurality of scanning lines located on one side of the substrate; A plurality of common electrodes are located on a side of the film layer where the scan lines are located away from the substrate; the common electrodes are multiplexed as touch electrodes; along a first direction, the plurality of common electrodes located in the same row constitute a common electrode group; along a second direction, one common electrode group overlaps with a plurality of the scan lines, and the plurality of scan lines constitute a scan line group; wherein the first direction is parallel to an extension direction of the scan lines, and the second direction is perpendicular to the plane where the substrate is located; The array substrate further includes: compensation wiring and a compensation control module; The extension direction of the compensation line is parallel to the extension direction of the scan line; along the second direction, one of the common electrode groups overlaps with at least one of the compensation lines; The scanning line group includes a central scanning group and an edge scanning group; along the third direction, the edge scanning group is located on a side of the central scanning group close to the edge of the common electrode; the edge scanning group includes at least two scanning lines; the third direction is parallel to the arrangement direction of the scanning lines; The compensation control module is electrically connected to the compensation routing and the scan lines in the edge scanning group, respectively; the compensation control module is used to respond to the scanning signals of each of the scan lines in the edge scanning group, and control the generation of compensation signals on the compensation routing; the compensation signal and the scanning signals of each of the scan lines in the edge scanning group have potential changes in opposite directions at each target moment; the target moment is the rising edge moment or the falling edge moment of the scanning signal, and the time sequence of the target moments corresponding to each of the scan lines in the edge scanning group is consistent with its scanning sequence.

2. The array substrate according to claim 1, wherein: The edge scanning group includes a first edge scanning group and a second edge scanning group. Along the third direction, the first edge scanning group and the second edge scanning group are located on opposite sides of the central scanning group. The scanning direction of the plurality of scanning lines is the direction from the first edge scanning group to the second edge scanning group. The scanning lines in the first edge scanning group are first scanning lines; and the scanning lines in the second edge scanning group are second scanning lines. The compensation trace includes a first compensation trace, the compensation control module includes a first compensation control module, and the first compensation control module is electrically connected to the first compensation trace and the first scan line, respectively; the first compensation control module is configured to respond to a scan signal of each of the first scan lines and control the generation of a first compensation signal on the first compensation trace; the first compensation signal and the scan signal of each of the first scan lines have potential changes in opposite directions at each first target moment; the first target moment is a rising edge moment of the scan signal of the first scan line; and / or, The compensation routing includes a second compensation routing, and the compensation control module includes a second compensation control module, and the second compensation control module is electrically connected to the second compensation routing and the second scan line, respectively; the second compensation control module is used to respond to the scan signal of each second scan line and control the generation of a second compensation signal on the second compensation routing; the second compensation signal and the scan signal of each second scan line have potential changes in opposite directions at each second target moment; the second target moment is the falling edge moment of the scan signal of the second scan line.

3. The array substrate according to claim 2, wherein: The compensation line includes a first compensation line, and the compensation control module includes a first compensation control module; Along the scanning direction, a target first scanning line and a secondary scanning line constitute a first scanning line unit, wherein the secondary scanning line is adjacent to the target first scanning line, and the scanning time of the secondary scanning line is later than that of the target first scanning line, and two adjacent first scanning line units share one first scanning line; The first compensation control module includes at least two first compensation units; the first compensation units are electrically connected to the first scan line units in a one-to-one correspondence, and each first compensation unit is electrically connected to the first compensation trace; the first compensation unit is used to respond to the scan signal of the target first scan line and control the first compensation signal to have a compensated falling edge at the rising edge of the scan signal.

4. The array substrate according to claim 3, wherein: There is a recovery rising edge between two adjacent compensation falling edges of the first compensation signal, and a duration corresponding to the recovery rising edge is greater than a duration corresponding to a rising edge of the scanning signal.

5. The array substrate according to claim 3, wherein: The first compensation unit includes a first storage capacitor, a first transistor, a second transistor, and a third transistor; the first transistor and the third transistor are P-type transistors, and the second transistor is an N-type transistor; The first compensation trace is electrically connected to the first level signal terminal, and both ends are suspended; the gates of the first transistor and the second transistor are electrically connected to the target first scan line, the source of the first transistor is electrically connected to the first level signal terminal, the drain of the first transistor and the source of the second transistor are electrically connected to the first plate of the first storage capacitor, the drain of the second transistor is electrically connected to the second level signal terminal, the gate of the third transistor is electrically connected to the secondary scan line, the source of the third transistor is electrically connected to the second plate of the first storage capacitor, and the drain of the third transistor is electrically connected to the first compensation trace; A potential of the first-level signal at the first-level signal terminal is greater than a potential of the second-level signal at the second-level signal terminal.

6. The array substrate according to claim 2, wherein: The compensation wiring includes a second compensation wiring, and the compensation control module includes a second compensation control module; The second compensation control module includes at least two second compensation units; the second compensation units are electrically connected to the second scan lines in a one-to-one correspondence, and each second compensation unit is electrically connected to the second compensation trace; the second compensation unit is used to respond to the scan signal of the second scan line and control the second compensation signal to have a compensated rising edge at the falling edge of the scan signal.

7. The array substrate according to claim 6, wherein: There is a recovery falling edge between two adjacent compensation rising edges of the second compensation signal, and a duration corresponding to the recovery falling edge is greater than a duration corresponding to the falling edge of the scanning signal.

8. The array substrate according to claim 6, wherein: The second compensation unit includes a second storage capacitor, a fourth transistor and a fifth transistor; the fourth transistor is an N-type transistor, and the fifth transistor is a P-type transistor; The gates of the fourth transistor and the fifth transistor are both electrically connected to the second scan line, the source of the fourth transistor is electrically connected to the first level signal terminal, the drain of the fourth transistor and the source of the fifth transistor are both electrically connected to the first plate of the second storage capacitor, the second plate of the second storage capacitor is electrically connected to the second level signal terminal, the drain of the fifth transistor is coupled to the second compensation wiring, and one end of the second compensation wiring is electrically connected to the second level signal terminal; A potential of the first-level signal at the first-level signal terminal is greater than a potential of the second-level signal at the second-level signal terminal.

9. The array substrate according to claim 8, wherein: The second compensation unit further includes a sixth transistor, and the sixth transistor is an N-type transistor; The drain of the fifth transistor is electrically connected to the gate of the sixth transistor, the source of the sixth transistor is electrically connected to the first plate of the second storage capacitor, and the drain of the sixth transistor is electrically connected to the second compensation trace.

10. The array substrate according to claim 1, wherein: The compensation line and the scanning line are insulated and arranged on the same layer.

11. The array substrate according to claim 1, wherein: Along the third direction, the compensation line is located on a side of the scan line close to an edge of the common electrode.

12. The array substrate according to claim 1, wherein: The array substrate comprises a display area, a first non-display area and a second non-display area, wherein the first non-display area and the second non-display area are located on opposite sides of the display area along the first direction; The compensation control module is located in at least one of the first non-display area and the second non-display area.

13. A touch display panel, characterized in that: The invention comprises an opposing substrate, a liquid crystal layer, and the array substrate according to any one of claims 1 to 12, wherein the liquid crystal layer is located between the opposing substrate and the array substrate.

14. A display device, characterized in that: The touch display device comprises a backlight module and the touch display panel according to claim 13, wherein the backlight module is located on a side of the array substrate away from the opposite substrate.

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